T ODUC MENT TE P R E CE L A O L S t OB RE P D E enter a D MMEN al Support C om/tsc O C E Data Sheet NO R rsil.c chnic our Te or www.inte t c a t n co SIL INTER 1-888- CD22204 TM November 2002 FN1696.5 5V Low Power Subscriber DTMF Receiver Features The CD22204 complete dual tone multiple frequency (DTMF) receiver detects a selectable group of 12 or 16 standard digits. No front-end pre-filtering is needed. The only externally required components are an inexpensive 3.579545MHz TV ‘‘colorburst’’ crystal (for frequency reference) and a bias resistor. Extremely high system density is possible through the use of the Alternate Time Base (ATB) output of a crystal connected CD22204 receiver to drive the time bases of up to 10 additional receivers. This is a monolithic integrated circuit fabricated with low power, complementary symmetry CMOS processing. It only requires a single power supply. • No Front End Band Splitting Filters Required The CD22204 employs state-of-the-art ‘‘switched-capacitor’’ filter technology, resulting in approximately 40 poles of filtering and digital circuitry on the same CMOS chip. The analog input is preprocessed by 60Hz reject and bandsplitting filters and then zero-cross detected to provide AGC. Eight bandpass filters detect the individual tones. Digital processing is used to measure the tone and pause durations and provides the correctly coded and timed digital outputs. The outputs interface directly to standard CMOS circuitry and are threestate enabled to facilitate bus oriented architectures. • Excellent Latch-Up Immunity Part Number Information PART NUMBER TEMP. RANGE (oC) CD22204E 0 to 70 PACKAGE 14 Ld PDIP PKG. NO. • Single Low Tolerance 5V Supply • Three-State Outputs for Microprocessor Based Systems • Detects all 16 Standard DTMF Digits • Uses Inexpensive 3.579545MHz Crystal • Excellent Speech Immunity • Output in 4-Bit Hexadecimal Code Pinouts CD22204 (PDIP) TOP VIEW D2 1 14 D4 D1 2 13 D8 EN 3 12 DV VDD 4 11 ATB NC 5 10 XIN XEN 6 ANALOG 7 IN E14.3 9 XOUT 8 VSS Functional Diagram FILTERS DV 2 FILTERS ATB 6 CHIP CLOCKS XEN CLOCK 9 XOUT GENERATOR XIN PROCESSING CIRCUITS D1 HIGH B/P 11 10 12 DETECTORS AND SIGNAL- ANALOG IN NC LOW B/P BANDSPLIT FILTER 7 PREPROCESSOR/ 5 1 D2 14 D4 13 D8 3 EN VOLTAGE REG./REF. 4 VDD 8 VSS NOTE: Pin numbers are for PDIP. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved All other trademarks mentioned are the property of their respective owners. CD22204 Absolute Maximum Ratings (Note 1) Thermal Information DC Supply Voltage (VDD) (Referenced to VSS Terminal) . . . . . . .7V Power Dissipation TA = 25oC (Derate above TA = 25oC at 6.25mW/oC . . . . . . .65mW Input Voltage Range All Inputs Except Analog In . . . . . . . . . . . . . . (VDD 0.5V) to -0.5V Analog in Voltage Range . . . . . . . . . . . . . (VDD 0.5V) to (VDD -10V) DC Current into any Input or Output . . . . . . . . . . . . . . . . . . . . . . ±20mA Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .175oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 0oC ≤ TA ≤ 70oC, VDD = 5V ±10%. Electrical Specifications PARAMETER TEST CONDITIONS Frequency Detect Bandwidth Amplitude for Detection Each Tone Minimum Acceptable Twist MIN TYP MAX UNITS ±(1.5 + 2Hz) ±2.3 ±3.5 -32 (Note 3) - -2 dBm Referenced to 600Ω -8 - +4 dB - - 0.8 VRMS % of fO High Tone Twist = ---------------------------Low Tone 60Hz Tolerance Dial Tone Tolerance “Precise” Dial Tone - - 0 dB Referenced to Lower Amplitude Tone Talk Off Mitel Tape #CM7291 - 2 - Hits Digital Outputs (except XOUT) “0” Level, 400µA Load 0 - 0.5 V “1” Level, 200µA Load VDD -0.5 - VDD V “0” Level 0 - 0.3VDD V “1” Level 0.7VDD - VDD V Digital Inputs Supply Current TA = 25oC - 10 20 mA Noise Tolerance Mitel Tape #CM7291 (Note 2) - - -12 dB Referenced to Lowest Amplitude Tone Input Impedance VDD ≥ VIN ≥ (VDD -10) 100kΩ//15pF 300kΩ - NOTES: 1. Unused inputs must be connected to VDD or VSS as appropriate. 2. Bandwidth limited (3kHz) Gaussian noise. 3. Lower minimum available, please contact sales office. (-32dBm = 19.45mVRMS, -2dBm = 0.615mVRMS) 2 CD22204 Functional Block Diagram BANDPASS FILTERS ANALOG IN BAND SPLIT FILTERS PREPROCESSOR 60Hz REJECT 7 PRE EMP ZERO CROSSING DETECTORS BS1 697 AMPLITUDE DETECTORS 770 852 941 BS2 TIMING CIRCUITRY 1209 1336 ATB 11 1477 XEN DV 12 6 1633 DATA STROBE ÷8 10 CLOCK GENERATOR CHIP CLOCKS XIN 2 D1 1M 1 D2 OUTPUT DECODER XOUT 9 POWER REGULATOR OUTPUT REGISTER 14 D4 VOLTAGE REF 13 D8 DATA CLEAR 4 8 VDD VSS 3 EN NOTE: Pin numbers are for plastic DIP. System Functions Analog In The Analog In pin accepts the analog input. It is internally biased so that the input signal may be either AC or DC coupled, as long as it does not exceed the positive supply voltage. Proper input coupling is illustrated below. CD22204E 0.01µF AUDIO INPUT (+4dBm OR 1.22VRMS MAXIMUM) VDD 270kΩ 7 1500pF 33kΩ 10pF (ON CHIP) ANALOG IN >100kΩ VSS OPTIONAL HIGH FREQUENCY NOISE FILTER (fC = 3.9kHz) FIGURE 1. ANALOG IN 3 The CD22204 is designed to accept sinusoidal input waveforms, but will operate satisfactorily with any input that has the correct fundamental frequency with harmonics that are at least 20dB below the fundamental. Crystal Oscillator The CD22204 contains an on-board inverter with sufficient gain to provide oscillation when connected to a low cost television “color-burst” (3.579545MHz) crystal. The crystal oscillator is enabled by tying XEN high. The crystal is connected between XIN and XOUT. A 1MΩ resistor is also connected between these pins in this mode. ATB is a clock frequency output. Other CD22204 devices may use the same frequency reference by tying their ATB pins to the ATB output of a crystal connected device. XIN and XEN of the auxiliary devices must then be tied high and low, respectively. Up to ten devices may be run from a single crystal connected CD22204 as shown in Figure 2. CD22204 DTMF Dialing Matrix 3.579545MHz COL 0 1209Hz COL 1 1336Hz COL 2 1477Hz COL 3 1633Hz ROW 0 697Hz 1 2 3 A ROW 1 770Hz 4 5 6 B ROW 2 852Hz 7 8 9 C ROW 3 941Hz * 0 # D 1M 10 ATB VDD XOUT XIN 9 6 CD22204 11 XEN XIN CONNECTED TO VDD 10 11 NOTE: Column 3 is for special applications and is not normally used in telephone dialing. XEN CD22204 6 UP TO 10 DEVICES Digital Inputs and Outputs FIGURE 2. CRYSTAL OSCILLATOR Outputs D1, D2, D4, D8 and EN Outputs D1, D2, D4, D8 are CMOS push-pull when enabled (EN high) and open circuited (high impedance) when disabled by pulling EN low. These digital outputs provide the hexadecimal code corresponding to the detected digit. The digital outputs become valid after a tone pair has been detected and they are then cleared when a valid pause is timed. The table below describes the hexadecimal codes. All digital inputs and outputs of the DTMF receivers are represented by the schematic below. Only the “analog in” pin is different, and is described above. Care must be exercised not to exceed the voltage or current ratings on these pins as listed in the “maximum ratings” section. VDD CMOS DIGITAL CIRCUITRY DIGITAL INPUT TABLE 1. OUTPUT CODES DIGIT D8 D4 D2 D1 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 0 1 0 1 0 * 1 0 1 1 # 1 1 0 0 A 1 1 0 1 B 1 1 1 0 C 1 1 1 1 D 0 0 0 0 VSS FIGURE 3. DIGITAL INPUTS AND OUTPUTS Input Filter The CD22204 will tolerate total input noise of a maximum of 12dB below the lowest amplitude tone. For most telephone applications, the combination of the high frequency attenuation of the telephone line and internal band limiting make special circuitry at the input to these receivers unnecessary. However, noise near the 56kHz internal sampling frequency will be aliased (folded back) into the audio spectrum, so if excessive noise is present above 28kHz, the simple RC filter shown below may be used to band limit the incoming signal. The cut off frequency is 3.9kHz. DV DV signals a detection by going high after a valid tone pair is sensed and decoded at the output pins D1, D2, D4, and D8. DV remains high until a valid pause occurs. DIGITAL OUTPUT NOISY SIGNAL 270kΩ 0.0015µF ANALOG IN CD22204 33kΩ N/C Pin This pin has no internal connection and should be left floating. 4 FIGURE 4. FILTER FOR USE IN EXTREME HIGH FREQUENCY INPUT NOISE ENVIRONMENT CD22204 Noise will also be reduced by placing a grounded trace around XIN and XOUT pins on the circuit board layout when using a crystal. It is important to note that XOUT is not intended to drive an additional device. XIN may be driven externally; in this case, leave XOUT floating. Timing Waveforms tON TONE BURST 1 tOFF PAUSE ANALOG INPUT TONE BURST 2 tR tD D1, D2 D4, D8 tSU tH DV FIGURE 5. TABLE 2. PARAMETER SYMBOL MIN TYP MAX UNITS For Detection tON 40 - - ms For Rejection tON - - 20 ms For Detection tOFF 40 - - ms For Rejection tOFF - - 20 ms Detect Time tD 25 - 46 ms Release Time tR 35 50 ms Data Setup Time tSU 7 - - µs Data Hold Time tH 4.2 - 5 ms Output Enable Time CL = 50pF, RL = 1kΩ - - 200 300 ns Output Disable Time CL = 35pF, RL = 500Ω - - 150 200 ns Output Rise Time CL = 50pF - - 200 300 ns Output Fall Time CL = 50pF - - 160 250 ns Tone Time Pause Time All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 5