AD AD8469WBRMZ Fast, rail-to-rail, low power, 2.5 v to 5.5 v Datasheet

Fast, Rail-to-Rail, Low Power, 2.5 V to 5.5 V,
Single-Supply TTL/CMOS Comparator
AD8469
Data Sheet
FEATURES
GENERAL DESCRIPTION
Qualified for automotive applications
Fully specified rail-to-rail at VCC = 2.5 V to 5.5 V
Input common-mode voltage: VEE − 0.2 V to VCC + 0.2 V
Low glitch TTL-/CMOS-compatible output stage
40 ns propagation delay
Low power: 1.4 mW at 2.5 V
Shutdown pin
Programmable hysteresis
Power supply rejection better than −50 dB
−40°C to +125°C operation
The AD8469 is a fast comparator fabricated on XFCB2, an
Analog Devices, Inc., proprietary process. This comparator is
exceptionally versatile and easy to use. Features include an input
range from VEE − 0.2 V to VCC + 0.2 V, low noise, TTL- and
CMOS-compatible output drivers, adjustable hysteresis control,
and a shutdown input. The device offers a 40 ns propagation
delay driving a 15 pF load with 10 mV overdrive on 500 µA
typical supply current.
A flexible power supply scheme allows the device to operate
from a single +2.5 V positive supply with a −0.2 V to +2.7 V
input signal range up to a +5.5 V positive supply with a −0.2 V
to +5.7 V input signal range.
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current/voltage controlled oscillators
The TTL-/CMOS-compatible output stage is designed to drive
up to 15 pF with full rated timing specifications and to degrade
in a graceful and linear fashion as additional capacitance is added.
The input stage of the comparator offers robust protection against
large input overdrive, and the outputs do not phase reverse when
the valid input signal range is exceeded.
The AD8469 is available in an 8-lead MSOP package and features
a shutdown pin and hysteresis control. It is fully specified over
an operating temperature range of −40°C to +125°C.
FUNCTIONAL BLOCK DIAGRAM
VP NONINVERTING
INPUT
Q OUTPUT
AD8469
TTL/CMOS
HYS INPUT
SDN INPUT
10490-001
Q OUTPUT
VN INVERTING
INPUT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
AD8469
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .................................................................8
Applications ....................................................................................... 1
Power/Ground Layout and Bypassing ........................................8
General Description ......................................................................... 1
TTL-/CMOS-Compatible Output Stage ....................................8
Functional Block Diagram .............................................................. 1
Optimizing Performance..............................................................8
Revision History ............................................................................... 2
Comparator Propagation Delay Dispersion ................................8
Specifications..................................................................................... 3
Comparator Hysteresis .................................................................9
Electrical Characteristics ............................................................. 3
Crossover Bias Point .....................................................................9
Absolute Maximum Ratings............................................................ 4
Minimum Input Slew Rate Requirement ................................ 10
Thermal Resistance ...................................................................... 4
Typical Applications Circuits ........................................................ 11
ESD Caution .................................................................................. 4
Outline Dimensions ....................................................................... 12
Pin Configuration and Function Descriptions ............................. 5
Ordering Guide .......................................................................... 12
Typical Performance Characteristics ............................................. 6
Automotive Products ................................................................. 12
REVISION HISTORY
1/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Data Sheet
AD8469
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 2.5 V, TA = −40°C to +125°C, typical values at TA = 25°C, unless otherwise noted.
Table 1.
Parameter
DC INPUT CHARACTERISTICS
Voltage Range
Common-Mode Range
Differential Voltage
Offset Voltage
Bias Current
Offset Current
Capacitance
Differential Mode Resistance
Common-Mode Resistance
Active Gain
Common-Mode Rejection Ratio
Hysteresis
HYSTERESIS MODE AND TIMING
Hysteresis Mode Bias Voltage
Minimum Resistor Value
SHUTDOWN PIN CHARACTERISTICS 1
Input Voltage High
Input Voltage Low
Input Current High
Sleep Time
Wake-Up Time
DC OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
AC PERFORMANCE 2
Rise Time/Fall Time
Propagation Delay
Symbol
Test Conditions/Comments
Min
VP, VN
VCM
VCC = 2.5 V to 5.5 V
VCC = 2.5 V to 5.5 V
VCC = 2.5 V to 5.5 V
−0.2
−0.2
VOS
IP, IN
CP, CN
AV
CMRR
VIH
VIL
IIH
tSD
tH
VOH
VOL
tR/tF
tPD
Propagation Delay Skew
Rising-to-Falling Transition
Q to Q
Overdrive Dispersion
Common-Mode Dispersion
POWER SUPPLY
Supply Voltage Range
Positive Supply Current
1
2
−5.0
−0.4
−1.0
VCC
IVCC
Power Dissipation
PD
Power Supply Rejection Ratio
Shutdown Current
PSRR
ISD
Typ
±3
Max
Unit
VCC + 0.2
VCC + 0.2
VCC
+5.0
+0.4
+1.0
V
V
V
mV
µA
µA
pF
kΩ
kΩ
dB
dB
dB
mV
1
−0.5 V to VCC + 0.5 V
−0.5 V to VCC + 0.5 V
200
100
VCM = −0.2 V to +2.7 V, VCC = 2.5 V
VCM = −0.2 V to +2.7 V, VCC = 5.5 V
RHYS = ∞
50
50
Current = 1 μA
Hysteresis = 120 mV
1.145
30
Comparator is operating
Shutdown guaranteed
VIH = VCC
lCC < 100 µA
VP = 10 mV, output valid
VCC = 2.5 V
IOH = 0.8 mA
IOL = 0.8 mA
2.0
−0.2
−6
7000
4000
80
0.1
1.25
1.35
120
V
kΩ
VCC
+0.4
+6
V
V
µA
ns
ns
300
150
VCC − 0.4
0.4
V
V
10% to 90%, VCC = 2.5 V
10% to 90%, VCC = 5.5 V
VOD = 10 mV, VCC = 2.5 V
VOD = 50 mV, VCC = 5.5 V
25 to 50
45 to 75
30 to 50
35 to 60
ns
ns
ns
ns
VCC = 2.5 V
VCC = 5.5 V
VCC = 2.5 V
VCC = 5.5 V
10 mV < VOD < 125 mV
−0.2 V < VCM < VCC + 0.2 V
4.5
8
3
4
12
1.5
ns
ns
ns
ns
ns
ns
2.5
VCC = 2.5 V
VCC = 5.5 V
VCC = 2.5 V
VCC = 5.5 V
VCC = 2.5 V to 5.5 V
VCC = 2.5 V to 5.5 V
550
800
1.4
4.5
5.5
650
1100
1.7
7
150
260
−50
V
μA
μA
mW
mW
dB
μA
The output is high impedance when the device is in shutdown mode. Note that this feature must be used with care because the enable/disable time is much longer
than with a true tristate output.
VIN = 100 mV square input at 1 MHz, VCM = 0 V, CL = 15 pF, VCC = 2.5 V, unless otherwise noted.
Rev. 0 | Page 3 of 12
AD8469
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Supply Voltages, VCC and VEE
VCC to Ground
Differential Supply Voltage
Analog Inputs, VP and VN
Input Voltage
Differential Input Voltage
Maximum Input/Output Current
Shutdown Pin, SDN
Applied Voltage (SDN to Ground)
Maximum Input/Output Current
Hysteresis Control Pin, HYS
Applied Voltage (HYS to Ground)
Maximum Input/Output Current
Output Current, Q and Q
Operating Temperature
Ambient Temperature Range
Junction Temperature
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Rating
−0.5 V to +6.0 V
−6.0 V to +6.0 V
Table 3.
−0.5 V to VCC + 0.5 V
±(VCC + 0.5 V)
±50 mA
1
Package Type
8-Lead MSOP (RM-8)
Measurement in still air.
ESD CAUTION
−0.5 V to VCC + 0.5 V
±50 mA
−0.5 V to VCC + 0.5 V
±50 mA
±50 mA
−40°C to +125°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 4 of 12
θJA1
130
Unit
°C/W
Data Sheet
AD8469
VCC 1
VP 2
VN 3
SDN 4
AD8469
TOP VIEW
(Not to Scale)
8
Q
7
Q
6
VEE
5
HYS
10490-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
Mnemonic
VCC
VP
VN
SDN
HYS
VEE
Q
8
Q
Description
Positive Supply Voltage.
Noninverting Analog Input.
Inverting Analog Input.
Shutdown. Drive this pin low to shut down the device.
Hysteresis Control. Bias this pin with a resistor or current source for hysteresis.
Negative Supply Voltage.
Noninverting Output. In compare mode, Q is at logic high if the analog voltage at the noninverting input (VP)
is greater than the analog voltage at the inverting input (VN).
Inverting Output. In compare mode, Q is at logic low if the analog voltage at the noninverting input (VP) is
greater than the analog voltage at the inverting input (VN).
Rev. 0 | Page 5 of 12
AD8469
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 2.5 V, TA = 25°C, unless otherwise noted.
200
VCC = 2.5V
VCC = 5.5V
HYSTERESIS (mV)
HYS PIN CURRENT (µA)
300
100
0
–100
160
150
140
130
120
110
100
90
80
70
–200
–400
–1
0
1
2
3
4
5
6
7
HYS PIN VOLTAGE (V)
10490-003
–300
60
50
40
30
20
10
0
VCC = 2.5V
VCC = 5.5V
0
Figure 3. HYS Pin Current vs. Voltage, VCC = 2.5 V and 5.5 V
100 200 300 400 500 600 700 800 900 1000 1100 1200 1300
HYS RESISTOR (kΩ)
10490-006
400
Figure 6. Hysteresis vs. HYS Resistor, VCC = 2.5 V and 5.5 V
1.5
5
VCC = 2.5V
4
SOURCE
3
1.0
LOAD CURRENT (mA)
BIAS CURRENT (µA)
SINK
2
1
0
–1
–2
0.5
0
+125°C
–3
–0.5
+25°C
–4
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
COMMON-MODE VOLTAGE (V)
–1.0
–1.0 –0.5
10490-004
–0.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT VOLTAGE (V)
Figure 4. Input Bias Current vs. Input Common-Mode Voltage, VCC = 2.5 V
Figure 7. Load Current vs. Output Voltage
38.0
60
37.8
PROPAGATION DELAY (ns)
55
50
45
VCC = 5.5V
RISE DELAY
35
VCC = 5.5V
FALL DELAY
30
VCC = 2.5V
FALL DELAY
25
37.4
37.2
37.0
RISE DELAY
36.8
36.6
36.4
VCC = 2.5V
RISE DELAY
36.2
20
0
50
100
OVERDRIVE (mV)
FALL DELAY
37.6
150
36.0
0.5
Figure 5. Propagation Delay vs. Input Overdrive, VCC = 2.5 V and 5.5 V
VCC = 2.5V
1.0
1.5
2.0
COMMON-MODE VOLTAGE (V)
2.5
3.0
10490-008
40
10490-005
PROPAGATION DELAY (ns)
0
10490-007
–40°C
–5
–1.0
Figure 8. Propagation Delay vs. Input Common-Mode Voltage, VCC = 2.5 V
Rev. 0 | Page 6 of 12
Data Sheet
AD8469
Q
Q
Q
10ns/DIV
1V/DIV
Figure 9. 1 MHz Output Voltage Waveform, VCC = 2.5 V
10ns/DIV
Figure 10. 1 MHz Output Voltage Waveform, VCC = 5.5 V
Rev. 0 | Page 7 of 12
10490-010
0.5V/DIV
10490-009
Q
AD8469
Data Sheet
APPLICATIONS INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
VLOGIC
It is also important to adequately bypass the input and output
supplies. Place a 0.1 μF bypass capacitor as close as possible to
each supply pin. The capacitors should be connected to the
ground plane with redundant vias placed to provide a physically
short return path for output currents flowing back from ground
to the VCC pin. Use high frequency bypass capacitors for minimum inductance and effective series resistance (ESR). Parasitic
layout inductance should also be strictly controlled to maximize
the effectiveness of the bypass at high frequencies.
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
To achieve the specified propagation delay performance, keep
the capacitive load at or below the specified maximum value.
The outputs of the AD8469 are designed to directly drive one
Schottky TTL or three low power Schottky TTL loads (or
equivalent). For large fan outputs, buses, or transmission lines,
use an appropriate buffer to maintain the excellent speed and
stability of the comparator.
With the rated 15 pF load capacitance applied, more than half
of the total device propagation delay is output stage slew time.
For this reason, the total propagation delay decreases as VCC
decreases, and instability in the power supply may appear as
excess delay dispersion.
Delay is measured to the 50% point of the supply that is in use;
therefore, the fastest times are observed with the VCC supply at
2.5 V, and larger delay values are observed when driving loads
that switch at other levels.
Overdrive and input slew rate dispersions are not significantly
affected by output loading and VCC variations.
A simplified schematic diagram of the TTL-/CMOS-compatible
output stage is shown in Figure 11. Because of its inherent symmetry and generally good behavior, this output stage is readily
adaptable for driving various filters and other unusual loads.
A1
Q1
OUTPUT
+IN
–IN
AV
A2
GAIN STAGE
Q2
OUTPUT STAGE
10490-011
The AD8469 comparator is a high speed device. Despite the
low noise output stage, it is essential to use proper high speed
design techniques to achieve the specified performance. Because
comparators are uncompensated amplifiers, feedback in any
phase relationship is likely to cause oscillations or undesired
hysteresis. Of critical importance is the use of low impedance
supply planes, particularly the output supply plane (VCC) and
the ground plane. Separate supply planes are recommended
as part of a multilayer board. Providing the lowest inductance
return path for switching currents ensures the best possible
performance in the target application.
Figure 11. Simplified Schematic Diagram of
TTL-/CMOS-Compatible Output Stage
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout
techniques are essential to obtain the specified performance. Stray
capacitance, inductance, common power and ground impedances,
or other layout issues can severely limit performance and often
cause oscillation. Source impedance should be minimized as
much as possible. High source impedance, in combination with
the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, therefore degrading
the overall response. Higher impedances encourage undesired
coupling.
COMPARATOR PROPAGATION DELAY DISPERSION
The AD8469 comparator is designed to reduce propagation delay
dispersion over a wide input overdrive range of 10 mV to VCC − 1 V.
Propagation delay dispersion is the variation in propagation delay
that results from a change in the degree of overdrive or slew rate—
that is, how far or how fast the input signal exceeds the switching
threshold (see Figure 12 and Figure 13).
The propagation delay dispersion specification becomes important
in high speed, time critical applications, such as data communication, automatic test and measurement, and instrumentation. It is
also important in event driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is
the variation in propagation delay as the input overdrive conditions
are changed (see Figure 12).
The propagation delay dispersion of the AD8469 is typically <12 ns
as the overdrive varies from 10 mV to 125 mV. This specification
applies to both positive and negative signals because the device has
very closely matched delays for both positive-going and negativegoing inputs, and very low output skews. Note that for repeatable
dispersion measurements the actual device offset is added to the
overdrive.
Rev. 0 | Page 8 of 12
Data Sheet
AD8469
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. One limitation of this approach is that the amount of
hysteresis varies with the output logic level, resulting in hysteresis
that is not symmetric about the threshold. The external feedback
network can also introduce significant parasitics that reduce high
speed performance and can even induce oscillation in some cases.
500mV OVERDRIVE
INPUT VOLTAGE
10mV OVERDRIVE
VN ± VOS
INPUT VOLTAGE
1V/ns
VN ± VOS
10490-013
10V/ns
DISPERSION
Q/Q OUTPUT
Figure 13. Propagation Delay—Slew Rate Dispersion
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in
noisy environments or when the differential input amplitudes
are relatively small or slow moving. The transfer function for a
comparator with hysteresis is shown in Figure 14.
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
OUTPUT
VCC = 2.5V
VCC = 5.5V
0
100 200 300 400 500 600 700 800 900 1000 1100 1200 1300
HYS RESISTOR (kΩ)
10490-019
Figure 12. Propagation Delay—Overdrive Dispersion
HYSTERESIS (mV)
The AD8469 comparator offers a programmable hysteresis
feature that significantly improves accuracy and stability. By
connecting an external pull-down resistor or current source
from the HYS pin to ground, the user can vary the amount of
hysteresis in a predictable, stable manner. Leaving the HYS pin
disconnected or driving it high removes the hysteresis. The
maximum hysteresis that can be applied using the HYS pin is
approximately 160 mV. Figure 15 illustrates the amount of
hysteresis applied as a function of the external resistor value.
10490-012
DISPERSION
Q/Q OUTPUT
Figure 15. Hysteresis vs. HYS Resistor
VOH
The HYS pin appears as a 1.25 V bias voltage seen through a
series resistance of 7 kΩ ± 20% throughout the hysteresis control
range. The advantages of applying hysteresis in this manner are
improved accuracy, improved stability, reduced component
count, and maximum versatility. An external bypass capacitor is
not recommended on the HYS pin because it impairs the latch
function and often degrades the jitter performance of the device.
–VH
2
0.0V
+VH
2
INPUT
10490-014
VOL
Figure 14. Comparator Hysteresis Transfer Function
As the input voltage approaches the threshold (0.0 V in Figure 14)
from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +VH/2.
The new switching threshold becomes −VH/2. The comparator
remains in the high state until the threshold, −VH/2, is crossed
from below the threshold region in a negative direction. In this
way, noise or feedback output signals centered on the 0.0 V input
cannot cause the comparator to switch states unless they exceed
the region bounded by ±VH/2.
When the HYS pin is driven low, hysteresis may become large,
but in this device, the effect is not reliable or intended as a latch
function.
CROSSOVER BIAS POINT
Rail-to-rail inputs in both op amps and comparators have a dual
front-end design. Certain devices are active near the VCC rail, and
others are active near the VEE rail. At some predetermined point
in the common-mode range, a crossover occurs. At the crossover
point (normally VCC/2), the direction of the bias current is reversed
and there are changes in measured offset voltages and currents.
The AD8469 elaborates slightly on this scheme. The crossover
points are at approximately 0.8 V and 1.6 V.
Rev. 0 | Page 9 of 12
AD8469
Data Sheet
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PCB design
(see the Power/Ground Layout and Bypassing section), the
AD8469 comparator should be stable at any input slew rate with
no hysteresis. Broadband noise from the input stage is observed
in place of the excessive chatter that is seen with most other high
speed comparators.
With additional capacitive loading or poor bypassing, oscillation
may be encountered. These oscillations are due to the high gain
bandwidth of the comparator in combination with feedback
through parasitics in the package and PCB. In many applications,
chatter is not harmful.
Rev. 0 | Page 10 of 12
Data Sheet
AD8469
TYPICAL APPLICATIONS CIRCUITS
5V
10kΩ
82pF
AD8469
OUTPUT
HYS
10490-016
10kΩ
CONTROL
VOLTAGE
0V TO 2.5V
150kΩ
150kΩ
Figure 16. Voltage Controlled Oscillator
5V
10kΩ
INPUT
+
AD8469
VREF
0.02µF
–
10kΩ
0.1µF
OUTPUT
10490-017
HYS
Figure 17. Duty Cycle to Differential Voltage Converter
2.5V
CMOS
PWM
OUTPUT
AD8469
INPUT
1.25V ± 50mV
VREF INPUT
1.25V
10kΩ
10kΩ
ADCMP601
82pF
HYS
100kΩ
Figure 18. Oscillator and Pulse-Width Modulator
Rev. 0 | Page 11 of 12
10490-018
10kΩ
AD8469
Data Sheet
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.09
0.80
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-AA
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
Figure 19. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
AD8469WBRMZ
AD8469WBRMZ-RL
1
2
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
Package Option
RM-8
RM-8
Branding
Y4F
Y4F
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD8469W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10490-0-1/12(0)
Rev. 0 | Page 12 of 12