AD AD8565 16 v rail-to-rail operational amplifier Datasheet

16 V Rail-to-Rail
Operational Amplifiers
AD8565/AD8566/AD8567
APPLICATIONS
LCD reference drivers
Portable electronics
Communications equipment
PIN CONFIGURATIONS
AD8565
OUT 1
5 V–
V+ 2
+IN 3
TOP VIEW
(Not to Scale)
4 –IN
01909-001
Single-supply operation: 4.5 V to 16 V
Input capability beyond the rails
Rail-to-rail output swing
Continuous output current: 35 mA
Peak output current: 250 mA
Offset voltage: 10 mV
Slew rate: 6 V/μs
Unity gain stable with large capacitive loads
Supply current: 700 μA per amplifier
Figure 1. 5-Lead SC70 Pin Configuration
AD8566
OUT A 1
8 V+
–IN A 2
7 OUT B
+IN A 3
6 –IN B
V– 4
TOP VIEW
(Not to Scale)
5 +IN B
01909-002
FEATURES
Figure 2. 8-Lead MSOP Pin Configuration
GENERAL DESCRIPTION
14 OUT D
–IN A 2
+IN A
13 –IN D
3
12 +IN D
AD8567
TOP VIEW
(Not to Scale)
V+ 4
+IN B 5
9 –IN C
6
OUT B 7
01909-003
–IN B
11 V–
10 +IN C
8 OUT C
OUT D
NC
16
15
14
13
12
–IN D
11
+IN D
–IN A
1
+IN A
2
V+
3
TOP VIEW
(Not to Scale) 10
+IN B
4
9
5
6
7
8
OUT C
–IN C
AD8567
NC = NO CONNECT
V–
+IN C
01909-004
OUT A
Figure 3. 14-Lead TSSOP Pin Configuration
NC
The AD8565, AD8566, and AD8567 are specified over the
−40°C to +85°C temperature range. The AD8565 single is
available in a 5-lead SC70 package. The AD8566 dual is
available in an 8-lead MSOP package. The AD8567 quad is
available in a 14-lead TSSOP package and a 16-lead LFCSP
package.
1
–IN B
These LCD op amps have high slew rates, 35 mA continuous
output drive, 250 mA peak output drive, and a high capacitive
load drive capability. They have a wide supply range and offset
voltages below 10 mV. The AD8565, AD8566, and AD8567 are
ideal for LCD grayscale reference buffer and VCOM applications.
OUT A
OUT B
The AD8565, AD8566, and AD8567 are low cost, single-supply,
rail-to-rail input and output operational amplifiers optimized
for LCD monitor applications. They are built on an advanced
high voltage CBCMOS process. The AD8565 contains a single
amplifier, the AD8566 has two amplifiers, and the AD8567 has
four amplifiers.
Figure 4. 16-Lead LFCSP Pin Configuration
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD8565/AD8566/AD8567
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Overvoltage Protection ......................................................9
Applications....................................................................................... 1
Output Phase Reversal............................................................... 10
General Description ......................................................................... 1
Power Dissipation....................................................................... 10
Pin Configurations ........................................................................... 1
Thermal Pad—AD8567............................................................. 10
Revision History ............................................................................... 2
Total Harmonic Distortion + Noise (THD+N)...................... 11
Specifications..................................................................................... 3
Short-Circuit Output Conditions............................................. 11
Electrical Characteristics............................................................. 3
LCD Panel Applications ............................................................ 11
Absolute Maximum Ratings............................................................ 4
Outline Dimensions ....................................................................... 12
ESD Caution.................................................................................. 4
Ordering Guide .......................................................................... 13
Typical Performance Characteristics ............................................. 5
Theory of Operation ........................................................................ 9
REVISION HISTORY
2/06—Rev C to Rev. D
Updated Format..................................................................Universal
Changes to Figure 6 and Figure 8................................................... 5
Added the Thermal Pad—AD8567 Section................................ 10
Changes to Ordering Guide .......................................................... 13
3/04—Rev B to Rev. C
Changes to Specifications ................................................................ 2
Changes to TPC 4 ............................................................................. 4
Changes to TPC 10........................................................................... 5
Changes to TPC 14........................................................................... 6
Changes to TPC 20........................................................................... 7
12/03—Rev. A to Rev. B
Updated Ordering Guide................................................................. 3
Updated Outline Dimensions ....................................................... 11
10/01—Rev. 0 to Rev. A
Edit to 16-Lead CSP and 5-Lead SC70 Pin Configuration ......... 1
Edit to Ordering Guide.................................................................... 3
7/01—Revision 0: Initial Version
Rev. D | Page 2 of 16
AD8565/AD8566/AD8567
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
4.5 V ≤ VS ≤ 16 V, VCM = VS/2, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Drift
Input Bias Current
Symbol
Conditions
VOS
ΔVOS/ΔT
IB
−40°C ≤ TA ≤ +85°C
Min
Typ
Max
Unit
2
5
80
10
mV
μV/°C
nA
nA
nA
nA
V
dB
V/mV
kΩ
pF
−40°C ≤ TA ≤ +85°C
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Input Impedance
Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Continuous Output Current
Peak Output Current
POWER SUPPLY
Supply Voltage
Power Supply Rejection Ratio
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
Channel Separation
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
IOS
CMRR
AVO
ZIN
CIN
VOH
VOL
IOUT
IPK
VS
PSRR
ISY
1
−40°C ≤ TA ≤ +85°C
Common-mode input
VCM = 0 to VS, −40°C ≤ TA ≤ +85°C
RL = 10 kΩ, VO = 0.5 V to (VS − 0.5 V)
IL = 100 μA
VS = 16 V, IL = 5 mA
−40°C ≤ TA ≤ +85°C
VS = 4.5 V, IL = 5 mA
−40°C ≤ TA ≤ +85°C
IL = 100 μA
VS = 16 V, IL = 5 mA
−40°C ≤ TA ≤ +85°C
VS = 4.5 V, IL = 5 mA
−40°C ≤ TA ≤ +85°C
−0.5
54
3
15.85
15.75
4.2
4.1
SR
GBP
Øo
RL = 10 kΩ, CL = 200 pF
RL = 10 kΩ, CL = 10 pF
RL = 10 kΩ, CL = 10 pF
en
en
in
f = 1 kHz
f = 10 kHz
f = 10 kHz
Rev. D | Page 3 of 16
95
10
400
1
VS − 0.005
15.95
4.38
5
42
95
150
250
300
400
35
250
VS = 16 V
VS = 4 V to 17 V, −40°C ≤ TA ≤ +85°C
VO = VS/2, no load
−40°C ≤ TA ≤ +85°C
600
800
80
130
VS + 0.5
4.5
70
4
16
90
700
850
1
V
V
V
V
V
mV
mV
mV
mV
mV
mA
mA
V
dB
μA
mA
6
5
65
75
V/μs
MHz
Degrees
dB
26
25
0.8
nV/√Hz
nV/√Hz
pA/√Hz
AD8565/AD8566/AD8567
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage (VS)
Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
Table 3.
Ratings
18 V
−0.5 V to VS + 0.5 V
VS
−65°C to +150°C
−40°C to +85°C
−65°C to +150°C
300°C
Package Type
5-Lead SC70 (KS-5)
8-Lead MSOP (RM-8)
14-Lead TSSOP (RU-14)
16-Lead LFCSP (CP-16-4)
1
2
θJA 1
376
210
180
38 2
θJC
126
45
35
302
Unit
°C/W
°C/W
°C/W
°C/W
θJA is specified for worst-case conditions, that is, θJA is specified for a device
soldered onto a circuit board for surface-mount packages.
DAP is soldered down to PCB.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 4 of 16
AD8565/AD8566/AD8567
TYPICAL PERFORMANCE CHARACTERISTICS
1000
4.5V ≤ VS ≤ 16V
TA = 25°C
VOLTAGE NOISE DENSITY (nV/√Hz)
–0.25
–0.50
VS = 16V
–0.75
VS = 4.5V
–1.00
–1.25
–40
25
TEMPERATURE (°C)
85
10
1
10
01909-005
–1.50
100
100
10k
Figure 8. Voltage Noise Density vs. Frequency
Figure 5. Input Offset Voltage vs. Temperature
1.0
SUPPLY CURRENT/AMPLIFIER (mA)
4.5V ≤ VS ≤ 16V
TA = 25°C
0.1
10
100
1k
FREQUENCY (Hz)
10k
0.8
0.6
0.4
0.2
0
01909-006
1
VO = VS/2
AV = +1
TA = 25°C
0
2
4
6
8
10
12
SUPPLY VOLTAGE (V)
14
16
18
01909-009
10
CURRENT NOISE DENSITY (pA/√Hz)
1k
FREQUENCY (Hz)
Figure 9. Supply Current/Amplifier vs. Supply Voltage
Figure 6. Current Noise Density vs. Frequency
0.80
VS = 16V
RL = 10kΩ
CL = 100pF
AV = +1
TA = 25°C
FREQUENCY (1µs/DIV)
01909-007
TIME (50mV/DIV)
SUPPLY CURRENT/AMPLIFIER (mA)
VCM = VS/2
0.75
VS = 16V
0.70
0.65
0.60
0.50
Figure 7. Small Signal Transient Response
VS = 4.5V
0.55
–40
25
TEMPERATURE (°C)
85
Figure 10. Supply Current/Amplifier vs. Temperature
Rev. D | Page 5 of 16
01909-010
INPUT OFFSET VOLTAGE (mV)
VCM = VS/2
01909-008
0
AD8565/AD8566/AD8567
VS = 16V
VIN = 100mV p-p
RL = 10kΩ
AV = +1
TA = 25°C
80
OVERSHOOT (%)
70
VS = 16V
RL = 10kΩ
CL = 40pF
TA = 25°C
100
80
60
GAIN (dB)
90
–OS
50
40
0
60
45
40
90
20
135
0
180
+OS
225
30
PHASE SHIFT (Degrees)
100
270
20
100
LOAD CAPACITANCE (pF)
1k
1k
10k
100k
1M
10M
01909-014
0
10
01909-011
10
100M
FREQUENCY (Hz)
Figure 14. Open-Loop Gain and Phase Shift vs. Frequency
Figure 11. Small Signal Overshoot vs. Load Capacitance
1k
18
TA = 25°C
16
10
8
6
VS = 16V
AV = +1
RL = 10kΩ
DISTORTION < 1%
TA = 25°C
4
2
0
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100
135
1
10
100
ISINK = 5mA
OUTPUT VOLTAGE (mV)
120
AVCL = –10
10
0
0.1
150
30
20
0.01
Figure 15. Output Voltage to Supply Rail vs. Load Current
AVCL = +1
VS = 4.5V
105
90
75
60
VS = 16V
45
30
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0
–40
25
85
TEMPERATURE (°C)
Figure 13. Closed-Loop Gain vs. Frequency
Figure 16. Output Voltage Swing to Rail vs. Temperature
Rev. D | Page 6 of 16
01909-016
15
01909-013
CLOSED-LOOP GAIN (dB)
40
AVCL = –100
1
LOAD CURRENT (mA)
4.5V ≤ VS ≤ 16V
RL = 10kΩ
CL = 40pF
TA = 25°C
50
VS = 16V
10
0.1
0.001
Figure 12. Closed-Loop Output Swing vs. Frequency
60
VS = 4.5V
01909-015
∆OUTPUT VOLTAGE (mV)
12
01909-012
OUTPUT SWING (V p-p)
14
AD8565/AD8566/AD8567
150
105
90
75
VS = 16V
60
45
30
0
–40
25
85
TEMPERATURE (°C)
120
100
80
+PSRR
60
40
–PSRR
20
0
–20
–40
100
01909-017
15
VS = 16V
TA = 25°C
140
1k
10k
100k
1M
Figure 17. Output Voltage Swing to Rail vs. Temperature
Figure 20. Power Supply Rejection Ratio vs. Frequency
500
VS = 16V
RL = 10kΩ
AV = +1
TA = 25°C
AV = +1
TA = 25°C
450
400
VOLTAGE (3V/DIV)
350
IMPEDANCE (Ω)
10M
FREQUENCY (Hz)
01909-020
VS = 4.5V
120
OUTPUT VOLTAGE (mV)
POWER SUPPLY REJECTION RATIO (dB)
135
160
ISOURCE = 5mA
VS = 4.5V
300
250
200
150
100
50
10k
100k
1M
10M
FREQUENCY (Hz)
01909-021
1k
01909-018
VS = 16V
0
100
TIME (40µs/DIV)
Figure 21. No Phase Reversal
Figure 18. Closed-Loop Output Impedance vs. Frequency
1.8k
140
VS = 16V
TA = 25°C
1.6k
1.4k
QUANTITY (Amplifiers)
120
100
80
60
40
20
1.2k
1.0k
800
600
400
0
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0
–10
–8
–6
–4
–2
0
2
4
6
INPUT OFFSET VOLTAGE (mV)
Figure 22. Input Offset Voltage Distribution
Figure 19. Common-Mode Rejection Ratio (CMRR) vs. Frequency
Rev. D | Page 7 of 16
8
10
01909-022
200
01909-019
CMRR (dB)
VS = 16V
TA = 25°C
AD8565/AD8566/AD8567
7
5
6
3
1
VS = 4.5V
0
VS = 16V
–1
–2
5
4
3
2
VS = 16V
AV = +1
RL = x
TA = 25°C
–3
1
–4
–40
25
0
01909-023
–5
85
TEMPERATURE (°C)
0
2
4
6
8
10
12
COMMON-MODE VOLTAGE (V)
6
0
VS = 5V
AV = +1
RL = 10kΩ
TA = 25°C
VCM = VS/2
–50
5
VS = 16V
–100
BANDWIDTH (MHz)
–150
VS = 4.5V
–200
4
3
2
–250
1
–300
–40
25
0
01909-024
–350
85
TEMPERATURE (°C)
–20
–40
–60
–80
4.5V
–120
16V
–140
–180
100
1k
FREQUENCY (Hz)
10k
60k
01909-025
–160
50
1
2
3
COMMON-MODE VOLTAGE (V)
4
5
Figure 27. Frequency vs. Common-Mode Voltage (VS = 5 V)
Figure 24. Input Bias Current vs. Temperature
–100
0
Figure 25. Channel A vs. Channel B Crosstalk
Rev. D | Page 8 of 16
01909-027
INPUT BIAS CURRENT (nA)
16
Figure 26. Frequency vs. Common-Mode Voltage (VS = 16 V)
Figure 23. Input Offset Current vs. Temperature
CROSSTALK (dB)
14
01909-026
2
BANDWIDTH (MHz)
INPUT OFFSET CURRENT (nA)
4
AD8565/AD8566/AD8567
THEORY OF OPERATION
VPOS
R1
Q3
D1
D2
R3
R4
Q6
V+
BIAS LINE
Q4
Q4
600
400
200
0
–200
–400
–600
–800
–1000
0
2
4
6
8
10
12
INPUT COMMON-MODE VOLTAGE (V)
14
16
Figure 29. AD856x Input Bias Current vs. Common-Mode Voltage
To achieve rail-to-rail output performance, the AD856x design
uses a complementary common-source (or gmRL) output. This
configuration allows output voltages to approach the power
supply rails, particularly if the output transistors are allowed to
enter the triode region on extremes of signal swing, which are
limited by VGS, the transistor sizes, and output load current. In
addition, this type of output stage exhibits voltage gain in an
open-loop gain configuration. The amount of gain depends on
the total load resistance at the output of the AD856x.
R6
C2
INPUT OVERVOLTAGE PROTECTION
V–
Q5
Q10
As with any semiconductor device, whenever the input exceeds
either supply voltages, attention needs to be paid to the input
overvoltage characteristics. As an overvoltage occurs, the amplifier
could be damaged, depending on the voltage level and the
magnitude of the fault current. When the input voltage exceeds
either supply by more than 0.6 V, internal pn junctions allow
current to flow from the input to the supplies.
D4
Q11
D5
I1
VS = 16V
TA = 25°C
800
Q8
C1
R5
D3
1000
01909-029
Figure 28 illustrates a simplified equivalent circuit for the
AD856x. The rail-to-rail bipolar input stage is composed of two
PNP differential pairs, Q4 to Q5 and Q10 to Q11, operating in
series with diode protection networks, D1 to D2. Diode network
D1 to D2 serves as protection against large transients for Q4 to
Q5 to accommodate rail-to-rail input swing. D5 to D6 protect
Q10 to Q11 against Zenering. In normal operation, Q10 to Q11
are off and their input stage is buffered from the operational
amplifier inputs by Q6 to D3 and Q8 to D4. Operation of the
input stage is best understood as a function of applied
common-mode voltage: when the inputs of the AD856x are
biased midway between the supplies, the differential signal path
gain is controlled by resistive loads (via R9, R10) Q4 to Q5. As
the input common-mode level is reduced toward the negative
supply (VNEG or GND), the input transistor current sources, I1
and I2, are forced into saturation, thereby forcing the Q6 to D3
and Q8 to D4 networks into cutoff. However, Q4 to Q5 remain
active, providing input stage gain. Inversely, when commonmode input voltage is increased toward the positive supply, Q4
to Q5 are driven into cutoff, Q3 is driven into saturation, and
Q4 becomes active, providing bias to the Q10 to Q11 differential
pair. The point at which Q10 to Q11 differential pair becomes
active is approximately equal to (VPOS − 1 V).
The benefit of this type of input stage is low bias current. The
input bias current is the sum of base currents of Q4 to Q5 and
Q6 to Q8 over the range from (VNEG + 1 V) to (VPOS − 1 V).
Outside of this range, input bias current is dominated by the
sum of base currents of Q10 to Q11 for input signals close to
VNEG and of Q6 to Q8 (Q10 to Q11) for signals close to VPOS.
From this type of design, the input bias current of AD856x not
only exhibits different amplitude but also exhibits different
polarities. Figure 29 provides the characteristics of the input
bias current vs. the common-mode voltage. It is important to
keep in mind that the source impedances driving the AD856x
inputs are balanced for optimum dc and ac performance.
INPUT BIAS CURRENT (nA)
The AD856x family is designed to drive large capacitive loads in
LCD applications. It has high output current drive, rail-to-rail
input/output operation, and is powered from a single 16 V
supply. It is also intended for other applications where low
distortion and high output current drive are needed.
I2
D6
FOLDED
CASCADE
R10
VNEG
01909-028
R9
Figure 28. AD856x Equivalent Input Circuit
Rev. D | Page 9 of 16
AD8565/AD8566/AD8567
This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. If a condition exists using
the AD856x where the input exceeds the supply more than
0.6 V, an external series resistor should be added. The size of the
resistor can be calculated by using the maximum overvoltage
divided by 5 mA. This resistance should be placed in series with
either input exposed to an overvoltage.
VOUT is the output voltage.
OUTPUT PHASE REVERSAL
ILOAD is the output load current.
The AD856x family is immune to phase reversal. Although the
device’s output does not change phase, large currents due to
input overvoltage could damage the device. In applications
where the possibility of an input voltage exceeding the supply
voltage exists, overvoltage protection should be used as
described in the Input Overvoltage Protection section.
Figure 30 shows the maximum power dissipation vs.
temperature. To achieve proper operation, use the previous
equation to calculate PDISS for a specific package at any given
temperature or use Figure 30.
The power dissipated by the device can be calculated as
PDISS = (VS − VOUT) × ILOAD
where:
VS is the supply voltage.
1.25
The maximum safe junction temperature, TJMAX, is 150°C. Using
the following formula, the maximum power that an AD856x
device can safely dissipate as a function of temperature can be
obtained:
PDISS = TJMAX − TA/θJA
where:
PDISS is the AD856x power dissipation.
TJMAX is the AD856x maximum allowable junction temperature
(150°C).
TA is the ambient temperature of the circuit.
θJA is the AD856x package thermal resistance, junction-to-ambient.
1.00
0.75
14-LEAD TSSOP
8-LEAD MSOP
0.50
5-LEAD SOT-23
0.25
0
–35
–15
5
25
45
AMBIENT TEMPERATURE (°C)
65
85
01909-030
The maximum allowable internal junction temperature of
150°C limits the AD856x family’s maximum power dissipation
of AD856x devices. As the ambient temperature increases, the
maximum power dissipated by AD856x devices must decrease
linearly to maintain the maximum junction temperature. If this
maximum junction temperature is exceeded momentarily, the
device still operates properly once the junction temperature is
reduced below 150°C. If the maximum junction temperature is
exceeded for an extended period, overheating could lead to
permanent damage of the device.
MAXIMUM POWER DISSIPATION (W)
14-LEAD SOIC
POWER DISSIPATION
Figure 30. Maximum Power Dissipation vs. Temperature
for 5-Lead SC70, 8-Lead MSOP, and 14-Lead TSSOP/SOIC Packages
THERMAL PAD—AD8567
The AD8567 LFCSP comes with a thermal pad that is attached
to the substrate. This substrate is connected to VDD. To be
electrically safe, the thermal pad should be soldered to an area
on the board that is electrically isolated or connected to VDD.
Attaching the thermal pad to ground adversely affects the
performance of the part.
Soldering down this thermal pad dramatically improves the
heat dissipation of the package. It is necessary to attach vias that
connect the soldered thermal pad to another layer on the board.
This provides an avenue to dissipate the heat away from the
part. Without vias, the heat is isolated directly under the part.
Rev. D | Page 10 of 16
AD8565/AD8566/AD8567
TOTAL HARMONIC DISTORTION + NOISE (THD+N)
LCD PANEL APPLICATIONS
The AD856x family features low total harmonic distortion.
Figure 31 shows THD+N vs. frequency. The THD+N for the
AD856x over the entire supply range is below 0.008%. When
the device is powered from a 16 V supply, the THD+N stays
below 0.003%. Figure 31 shows the AD8566 in a unity
noninverting configuration.
The AD856x amplifier is designed for LCD panel applications
or applications where large capacitive load drive is required. It
can instantaneously source/sink greater than 250 mA of current. At
unity gain, it can drive 1 μF without compensation. This makes
the AD856x ideal for LCD VCOM driver applications.
10
Figure 32 shows the test circuit. Series capacitors and resistors
connected to the output of the op amp represent the load of the
LCD panel. The 300 Ω and 3 kΩ feedback resistors are used to
improve settling time. This test circuit simulates the worst-case
scenario for a VCOM. It drives a represented load that is connected to
a signal switched symmetrically around VCOM. Figure 33 shows a
scope photo of the instantaneous output peak current capability
of the AD856x family.
VS = ±2.5V
100
1k
FREQUENCY (Hz)
10k
30k
300Ω
INPUT 0V TO 8V
SQUARE WAVE WITH
15.6µs PULSE WIDTH
Figure 31. THD+N vs. Frequency
8V
3kΩ
SHORT-CIRCUIT OUTPUT CONDITIONS
10Ω
The AD856x family does not have internal short-circuit
protection circuitry. As a precautionary measure, it is
recommended not to short the output directly to the
positive power supply or to ground.
4V
MEASURE
CURRENT
10nF
10Ω
10nF
10Ω
10nF
10Ω
10nF
10Ω TO 20Ω
Figure 32. VCOM Test Circuit with Supply Voltage at 16 V
It is not recommended to operate the AD856x with more than
35 mA of continuous output current. The output current can be
limited by placing a series resistor at the output of the amplifier
whose value can be derived using
100
90
VS
RX ≥
35 mA
CH 2 = 100mA/DIV
For a 5 V single-supply operation, RX should have a minimum
value of 143 Ω.
CH 1 = 5V/DIV
10
0%
TIME (2µs/DIV)
01909-033
0.01
20
01909-031
VS = ±8V
01909-032
THD+N (%)
1
0.1
To evaluate the performance of the AD856x family, a test circuit
was developed to simulate the VCOM driver application for an
LCD panel.
Figure 33. Scope Photo of the VCOM Instantaneous Peak Current
Rev. D | Page 11 of 16
AD8565/AD8566/AD8567
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5
2.20
2.00
1.80
5.15
4.90
4.65
1.35
1.25
1.15
4
5
1
2.40
2.10
1.80
4
2
3
PIN 1
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.80
0.60
0.40
8°
0°
0.23
0.08
0.65 BSC
1.00
0.90
0.70
1.10
0.80
0.30
0.15
0.10 MAX
SEATING
PLANE
SEATING
PLANE
0.40
0.10
0.22
0.08
0.46
0.36
0.26
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-187-AA
COMPLIANT TO JEDEC STANDARDS MO-203-AA
Figure 34. 8-Lead Micro Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Figure 35. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
1.05
1.00
0.80
0.65
BSC
1.20
MAX
0.15
0.05
0.30
0.19
0.20
0.09
SEATING
COPLANARITY
PLANE
0.10
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 36. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Rev. D | Page 12 of 16
0.75
0.60
0.45
AD8565/AD8566/AD8567
4.00
BSC SQ
PIN 1
INDICATOR
0.65 BSC
TOP
VIEW
12° MAX
1.00
0.85
0.80
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
13
12
16
1
EXPOSED
PAD
3.75
BSC SQ
0.75
0.60
0.50
(BOTTOM VIEW)
9
4
8
2.25
2.10 SQ
1.95
5
0.25 MIN
1.95 BSC
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8565AKS-R2
AD8565AKS-REEL7
AD8565AKSZ-REEL7 1
AD8566ARM-R2
AD8566ARM-REEL
AD8566ARMZ-R21
AD8566ARMZ-REEL1
AD8567ARU
AD8567ARU-REEL
AD8567ARUZ1
AD8567ARUZ-REEL1
AD8567ACP-R2
AD8567ACP-REEL
AD8567ACP-REEL7
AD8567ACPZ-R21
AD8567ACPZ-REEL1
AD8567ACPZ-REEL71
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
5-Lead Thin Shrink Small Outline Transistor Package (SC70)
5-Lead Thin Shrink Small Outline Transistor Package (SC70)
5-Lead Thin Shrink Small Outline Transistor Package (SC70)
8-Lead Micro Small Outline Package (MSOP)
8-Lead Micro Small Outline Package (MSOP)
8-Lead Micro Small Outline Package (MSOP)
8-Lead Micro Small Outline Package (MSOP)
14-Lead Thin Shrink Small Outline Package (TSSOP)
14-Lead Thin Shrink Small Outline Package (TSSOP)
14-Lead Thin Shrink Small Outline Package (TSSOP)
14-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Z = Pb-free part, # denotes lead-free product may be top or bottom marked.
Rev. D | Page 13 of 16
Package
Option
KS-5
KS-5
KS-5
RM-8
RM-8
RM-8
RM-8
RU-14
RU-14
RU-14
RU-14
CP-16-4
CP-16-4
CP-16-4
CP-16-4
CP-16-4
CP-16-4
Branding
ASA
ASA
A0N
ATA
ATA
ATA#
ATA#
AD8565/AD8566/AD8567
NOTES
Rev. D | Page 14 of 16
AD8565/AD8566/AD8567
NOTES
Rev. D | Page 15 of 16
AD8565/AD8566/AD8567
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01909-0-2/06(D)
Rev. D | Page 16 of 16