PRELIMINARY CY22E016L 16-Kbit (2K x 8) nvSRAM Features Functional Description • 25 ns, 35 ns and 45 ns Access Times The Cypress CY22E016L is a fast static RAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an infinite number of times, while independent, nonvolatile data resides in Nonvolatile Elements. Data transfers from the SRAM to the Nonvolatile Elements (the STORE operation) can take place automatically on power down. A 68-µF or larger capacitor tied from VCAP to ground guarantees the STORE operation, regardless of power-down slew rate or loss of power from “hot swapping”. Transfers from the Nonvolatile Elements to the SRAM (the RECALL operation) take place automatically on restoration of power. A hardware STORE may be initiated with the HSB pin. • “Hands-off” Automatic STORE on Power Down with external 68µF capacitor • STORE to QuantumTrap® Nonvolatile Elements is initiated by Hardware or Autostore®on Power-down • RECALL to SRAM Initiated on Power-up • Infinite READ, WRITE and RECALL Cycles • 10 mA Typical ICC at 200 ns Cycle Time • 1,000,000 STORE Cycles to QuantumTrap • 100-Year Data Retention to QuantumTrap • Single 5V Operation +10% • Commercial, Industrial Temperature • SOIC Package • RoHS Compliance Logic Block Diagram VCC Quantum Trap 32 X 512 A5 A8 A9 STATIC RAM ARRAY 32 X 512 DQ 0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 RECALL STORE/ RECALL CONTROL HSB COLUMN I/O INPUT BUFFERS DQ 1 POWER CONTROL STORE ROW DECODER A6 A7 VCAP COLUMN DEC A 0 A 1 A 2 A 3 A 4 A 10 DQ 7 OE CE WE Cypress Semiconductor Corporation Document #: 001-06727 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 28, 2006 [+] Feedback PRELIMINARY CY22E016L Pin Configurations V CAP 1 28 V CC NC 2 27 WE A7 3 26 HSB A6 4 25 A8 A5 5 24 A9 A4 6 23 NC A3 7 22 OE A2 Top View 8 (Not To Scale) 21 A 10 A1 9 20 CE A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 V SS 14 15 DQ3 28-SOIC Pin Definitions Pin Name I/O Type A0–A10 Input Description Address Inputs used to select one of the 2,048 bytes of the nvSRAM. DQ0-DQ7 Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation. WE Input Write Enable Input, active LOW. When selected LOW, enables data on the I/O pins to be written to the address location latched by the falling edge of CE. CE Input Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. OE Input Output Enable, active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tri-state. VSS Ground VCC Ground for the device. Should be connected to ground of the system. Power Supply Power Supply inputs to the device. HSB Input/Output Hardware Store Busy. When low this output indicates a Hardware Store is in progress. When pulled low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull-up resistor keeps this pin high if not connected. (Connection Optional) VCAP Power Supply Autostore® Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. NC No Connect No Connects. This pin is not connected to the die Document #: 001-06727 Rev. *C Page 2 of 14 [+] Feedback PRELIMINARY CY22E016L 28 10k Ohm 1 27 0.1U F Bypass 26 68 UF 6v, +20% The CY22E016L nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The CY22E016L supports infinite reads and writes just like a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 1 million STORE operations. 10k Ohm Device Operation SRAM Read The CY22E016L performs a READ cycle whenever CE and OE are low while WE and HSB are high. The address specified on pins A0–10 determines which of the 2,048 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAA (READ cycle #1). If the READ is initiated by CE or OE, the outputs will be valid at tACE or at tDOE, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and will remain valid until another address change or until CE or OE is brought high, or WE or HSB is brought low. 14 28 27 10k Ohm 1 10k Ohm Figure 1. AutoStore® Mode SRAM Write 26 0.1U F Bypass A WRITE cycle is performed whenever CE and WE are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes high at the end of the cycle. The data on the common I/O pins I/O0–7 will be written into the memory if it is valid tSD before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. It is recommended that OE be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If OE is left low, internal circuitry will turn off the output buffers tHZWE after WE goes low. 15 AutoStore Operation During normal AutoStore operation, the CY22E016L will draw current from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. After power up, when the voltage on the VCAP pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCC and initiate a STORE operation. Figure 1 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. A charge storage capacitor having a capacity of between 68 µF and 220 µF (±20%) rated at 6V should be provided.In system power mode both VCC and VCAP are connected to the +5V power supply without the 68-µF capacitor. In this mode the AutoStore function of the CY22E016L will operate on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6V during the Document #: 001-06727 Rev. *C 14 15 Figure 2. System Power Mode If an automatic STORE on power loss is not required, then VCC can be tied to ground and +5V applied to VCAP. This is the AutoStore Inhibit mode, in which the AutoStore function is disabled. If the CY22E016L is operated in this configuration, references to VCC should be changed to VCAP throughout this data sheet. In this mode, STORE operations may be triggered with the HSB pin. It is not permissible to change between these three options “on the fly”. Page 3 of 14 [+] Feedback 28 27 10k Ohm 1 10k Ohm 0.1U F Bypass PRELIMINARY 26 CY22E016L be scaled by the number of devices connected to it. When any one of the CY22E016L detects a power loss and asserts HSB, the common HSB pin will cause all parts to request a STORE cycle (a STORE will take place in those CY22E016L that have been written since the last nonvolatile cycle). During any STORE operation, regardless of how it was initiated, the CY22E016L will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the CY22E016L will remain disabled until the HSB pin returns high. If HSB is not used, it should be left unconnected. Hardware RECALL (Power-up) During power-up, or after any low-power condition (VCC < VSWITCH), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tHRECALL to complete. Data Protection 14 15 Figure 3. AutoStore Inhibit Mode In order to prevent unneeded STORE operations, automatic STOREs as well as those initiated by externally driving HSB low will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. An optional pull-up resistor is shown connected to HSB. This can be used to signal the system that the AutoStore cycle is in progress. Hardware STORE (HSB) Operation The CY22E016L provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the CY22E016L will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the CY22E016L will continue SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. The HSB pin can be used to synchronize multiple CY22E016L while using a single larger capacitor. To operate in this mode the HSB pin should be connected together to the HSB pins from the other CY22E016L. An external pull-up resistor to +5V is required since HSB acts as an open-drain pull-down. The VCAP pins from the other CY22E016L parts can be tied together and share a single capacitor. The capacitor size must Document #: 001-06727 Rev. *C The CY22E016L protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCC < VSWITCH. If the CY22E016L is in a WRITE mode (both CE and WE low) at power-up, after a RECALL, or after a STORE, the WRITE will be inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power-up or brown-out conditions. Noise Considerations The CY22E016L is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 µF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, careful routing of power, ground, and signals will reduce circuit noise. Low Average Active Power CMOS technology provides the CY22E016L the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 4 shows the relationship between ICC and READ/WRITE cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the CY22E016L depends on the following items: 1. The duty cycle of chip enable. 2. The overall cycle rate for accesses. 3. The ratio of READs to WRITEs. 4. CMOS vs. TTL Input Levels. 5. The operating temperature. 6. The VCC level. 7. I/O loading. Page 4 of 14 [+] Feedback PRELIMINARY Preventing STOREs The STORE function can be disabled on the fly by holding HSB high with a driver capable of sourcing 30 mA at a VOH of at least 2.2V, as it will have to overpower the internal pull-down device that drives HSB low for 20 ns at the onset of a STORE. CY22E016L When the CY22E016L is connected for AutoStore operation (system VCC connected to VCC and a 68 µF capacitor on VCAP) and VCC crosses VSWITCH on the way down, the CY22E016L will attempt to pull HSB low; if HSB doesn’t actually get below VIL, the part will stop trying to pull HSB low and abort the STORE attempt. Table 1. Hardware Mode Selection CE WE HSB A10–A0 Mode I/O Power H X H X Not Selected Output High-Z Standby L H H X Read SRAM Output Data Active L L H X Write SRAM Input Data Active X X L X Non-Volatile STORE Output High-Z ICC2 Figure 4. Current vs. Cycle Time (READ) Document #: 001-06727 Rev. *C Figure 5. Current vs. Cycle Time (WRITE) Page 5 of 14 [+] Feedback PRELIMINARY Maximum Ratings CY22E016L Package Power Dissipation Capability (TA = 25°C) ................................................... 1.0W (Above which the useful life may be impaired. For user guidelines, not tested.) Surface Mount Lead Soldering Temperature (3 Seconds) .......................................... +260°C Storage Temperature ................................. –65°C to +150°C Output Short Circuit Current [1] .................................... 15 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Supply Voltage on VCC Relative to GND.......... –0.5V to 7.0V Latch-up Current.................................................... > 200 mA Voltage Applied to Outputs in High-Z State .......................................–0.5V to VCC + 0.5V Operating Range Input Voltage ............................................ –0.5V to Vcc+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential...................–0.5V to VCC + 2.0V Range Commercial Industrial Ambient Temperature VCC 0°C to +70°C 4.5V to 5.5V -40°C to +85°C DC Electrical Characteristics Over the Operating Range (VCC = 4.5V to 5.5V) [2] Parameter ICC1 Description Test Conditions Average VCC Current Min. tRC = 25 ns Commercial tRC = 35 ns tRC = 45 ns Dependent on output loading and cycle rate. Industrial Values obtained without output loads. IOUT = 0mA. Max. Unit 85 75 65 mA mA mA 75 mA ICC2 Average VCC Current during STORE All Inputs Don’t Care, VCC = Max. Average current for duration tSTORE 3 mA ICC3 Average VCC Current at WE > (VCC – 0.2). All other inputs cycling. tAVAV = 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained without output loads. typical 10 mA ICC4 Average VCAP Current All Inputs Don’t Care, VCC = Max. during AutoStore Cycle Average current for duration tSTORE 2 mA ISB VCC Standby Current 2.5 mA CE > (VCC – 0.2). All others VIN < 0.2V or > (VCC – 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0MHz. IILK Input Leakage Current VCC = Max., VSS < VIN < VCC -1 +1 µA IOLK Off-State Output Leakage Current -5 +5 µA VIH Input HIGH Voltage 2.2 VCC + 0.5 V VIL Input LOW Voltage VSS – 0.5 0.8 V VOH Output HIGH Voltage IOUT = –4 mA except HSB VOL Output LOW Voltage IOUT = 8 mA except HSB 0.4 V VBL Logic “0” on HSB IOUT = 3 mA 0.4 V VCC = Max., VSS < VIN < VCC, CE or OE > VIH 2.4 V Capacitance [3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 0 to 3.0 V Max. Unit 8 pF 7 pF Notes: 1. Outputs shorted for no more than one second. No more than one output shorted at a time. 2. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C (room temperature), and VCC = 5V. Not 100% tested. 3. These parameters are guaranteed but not tested. Document #: 001-06727 Rev. *C Page 6 of 14 [+] Feedback PRELIMINARY CY22E016L Thermal Resistance [3] Parameter ΘJA ΘJC 28-SOIC Unit Thermal Resistance Test conditions follow standard test methods and proce(Junction to Ambient) dures for measuring thermal impedance, per EIA / JESD51. Description Test Conditions TBD °C/W Thermal Resistance (Junction to Case) TBD °C/W AC Test Loads R1 480Ω 5.0V OUTPUT 30 pF R2 255Ω AC Test Conditions Input Pulse Levels.................................................. 0 V to 3 V Input Rise and Fall Times (10% - 90%)........................ <5 ns Input and Output Timing Reference Levels....................1.5 V Document #: 001-06727 Rev. *C Page 7 of 14 [+] Feedback PRELIMINARY CY22E016L AC Switching Characteristics Parameter 25ns part Cypress Alt. Parameter Parameter Description Min. Max. 35ns part Min. 45ns part Max. Min. Max. Unit 45 ns SRAM Read Cycle tACS Chip Enable Access Time tRC [4] tRC Read Cycle Time tAA [5] tAA Address Access Time tDOE tOE Output Enable to Data Valid tOHA [5] tOH Output Hold After Address Change 5 5 5 ns tLZCE [6] tLZ Chip Enable to Output Active 5 5 5 ns tHZCE [6] tHZ Chip Disable to Output Inactive tLZOE [6] tOLZ Output Enable to Output Active tHZOE [6] tOHZ Output Disable to Output Inactive tPU [3] tPA Chip Enable to Power Active [ 3] tPS Chip Disable to Power Standby tACE tPD 25 25 35 35 25 35 10 ns 20 13 0 ns 15 ns 15 ns 0 10 0 ns 45 15 10 0 45 13 0 ns 0 25 35 ns 45 ns SRAM Write Cycle tWC tWC Write Cycle Time 25 35 45 ns tPWE tWP Write Pulse Width 20 25 30 ns tSCE tCW Chip Enable To End of Write 20 25 30 ns tSD tDW Data Set-Up to End of Write 10 12 15 ns tHD tDH Data Hold After End of Write 0 0 0 ns tAW tAW Address Set-Up to End of Write 20 25 30 ns tSA tAS Address Set-Up to Start of Write 0 0 0 ns tHA tWR Address Hold After End of Write 0 tHZWE [6,7] tWZ Write Enable to Output Disable tOW Output Active after End of Write tLZWE [6] 0 0 10 5 13 ns 14 5 ns 5 ns AutoStore/Power-Up RECALL CY22E016L Parameter tHRECALL [8] tSTORE [9] Description Min. Power-Up RECALL Duration STORE Cycle Duration tDELAY Time allowed to complete SRAM Cycle VSWITCH Low Voltage Trigger Level VRESET Low Voltage Reset Level Max. Unit 550 µs 10 ms µs 1 4.0 4.5 V 3.6 V Notes: 4. WE must be HIGH during SRAM Read Cycles. 5. Device is continuously selected with CE and OE both Low. 6. Measured ±200 mV from steady state output voltage. 7. If WE is Low when CE goes Low, the outputs remain in the high-impedance state. 8. tHRECALL starts from the time VCC rises above VSWITCH. 9. If an SRAM Write has not taken place since the last non-volatile cycle, no STORE will take place. Document #: 001-06727 Rev. *C Page 8 of 14 [+] Feedback PRELIMINARY CY22E016L Hardware STORE Cycle CY22E016L Parameter tSTORE [6] tDELAY Description Min Max Unit 10 ms STORE Cycle Duration [10] Time allowed to complete SRAM Cycle tRESTORE [11] Hardware STORE High to Inhibit Off tHLHX Hardware STORE Pulse Width tHLBL Hardware STORE Low to STORE Busy µs 1 700 15 ns ns 300 ns Switching Waveforms tRC ADDRESS t AA t OH DQ (DATA OUT) DATA VALID Figure 6. SRAM Read Cycle #1: Address Controlled [4, 5, 12] tRC ADDRESS tLZCE CE tACE tPD tHZCE OE tLZOE DQ (DATA OUT) t PU ICC tHZOE tDOE DATA VALID ACTIVE STANDBY Figure 7. SRAM Read Cycle #2: CE Controlled [4,12] Notes: 10. Read and Write cycles in progress before HSB are given this amount of time to complete. 11. tRESTOREis only applicable after tSTORE is complete. 12. HSB must remain HIGH during READ and WRITE cycles. Document #: 001-06727 Rev. *C Page 9 of 14 [+] Feedback PRELIMINARY CY22E016L Switching Waveforms (continued) tWC ADDRESS tHA tSCE CE tAW tSA tPWE WE tSD tHD DATA VALID DATA IN tHZWE DATA OUT tLZWE HIGH IMPEDANCE PREVIOUS DATA Figure 8. SRAM Write Cycle #1: WE Controlled [12,13] tWC ADDRESS CE tHA tSCE tSA tAW tPWE WE tSD DATA IN tHD DATA VALID HIGH IMPEDANCE DATA OUT Figure 9. SRAM Write Cycle #2: CE Controlled Note: 13. CE or WE must be > VIH during address transitions. Document #: 001-06727 Rev. *C Page 10 of 14 [+] Feedback PRELIMINARY CY22E016L Switching Waveforms (continued) VCC VSWITCH VRESET AutoStore POWER-UP RECALL tRESTORE tVSBL tSTORE HSB tDELAY DQ (DATA OUT) POWER UP RECALL BROWN OUT NO STROKE BROWN OUT AutoStore TM BROWN OUT AutoStore TM NO RECALL (VCC DID NOT GO BELOW VRESET) NO RECALL (VCC DID NOT GO BELOW VRESET) RECALL WHEN VCC RETURNS ABOVE VSWITCH (NO SRAM WRITES) Figure 10. AutoStore/Power-Up RECALL Document #: 001-06727 Rev. *C Page 11 of 14 [+] Feedback PRELIMINARY CY22E016L Switching Waveforms (continued) a a tHLHX HSB (IN) tSTORE HSB (OUT) a a tHLBL HIGH IMPEDANCE HIGH IMPEDANCE a a t DELAY DATA VALID DQ (DATA OUT) DATA VALID Figure 11. Hardware STORE Cycle PART NUMBERING NOMENCLATURE CY 22 E 016 L- SZ 25 X C T Option: T - Tape & Reel Blank - Std. Temperature: C - Commercial (0 to 70°C) I - Industrial (-40°C to 85°C) Speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns Pb-Free Package: SZ - 28 SOIC Data Bus: L - x8 Density: 016 - 16 Kb Voltage: E - 5.0V NVSRAM 22 - AutoStore + Hardware Store Cypress Document #: 001-06727 Rev. *C Page 12 of 14 [+] Feedback PRELIMINARY CY22E016L Ordering Information Speed (ns) Ordering Code Package Name 25 CY22E016L-SZ25XCT 51-85026 35 CY22E016L-SZ35XCT 35 CY22E016L-SZ35XIT 45 CY22E016L-SZ45XCT 51-85026 Operating Range Package Type 28-pin SOIC Commercial 51-85026 28-pin SOIC Commercial 51-85026 28-pin SOIC Industrial 28-pin SOIC Commercial All of the above mentioned parts are of “Lead-Free” type. Package Diagrams 28-pin (300-Mil) Molded SOIC (51-85026) NOTE : PIN 1 ID 1. JEDEC STD REF MO-119 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT 14 DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. 1 MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES 0.291[7.39] MIN. MAX. 4. PACKAGE WEIGHT 0.85gms 0.300[7.62] 0.394[10.01] * 0.419[10.64] 15 28 PART # S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG. 0.026[0.66] 0.032[0.81] SEATING PLANE 0.697[17.70] 0.713[18.11] 0.092[2.33] 0.105[2.67] 0.004[0.10] 0.050[1.27] 0.013[0.33] 0.004[0.10] 0.019[0.48] 0.0118[0.30] * 0.015[0.38] 0.050[1.27] 0.0091[0.23] 0.0125[3.17] * TYP. 51-85026-*D AutoStore and QuantumTrap are registered trademarks of Simtek Corporation.All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 001-06727 Rev. *C Page 13 of 14 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback PRELIMINARY CY22E016L Document History Page Document Title: CY22E016L 16-Kbit (2K x 8) nvSRAM Document Number: 001-06727 REV. ECN NO. Issue Date Orig. of Change ** 427789 See ECN TUP Description of Change New Data Sheet *A 437321 See ECN TUP Show Data Sheet on external Web *B 472053 See ECN TUP Updated Part Numbering Nomenclatue and Ordering Information *C 503290 See ECN PCI Converted from Advance to Preliminary Changed the term “Unlimited” to “Infinite” Removed Industrial Grade mention Corrected VIL min. spec from (VCC - 0.5) to (VSS - 0.5) Updated Part Nomenclature Table and Ordering InformationTable Document #: 001-06727 Rev. *C Page 14 of 14 [+] Feedback