AD AD8011 300 mhz current feedback amplifier Datasheet

300 MHz
Current Feedback Amplifier
AD8011
FEATURES
Easy to Use
Low Power
1 mA Power Supply Current (5 mW on 5 VS)
High Speed and Fast Settling on 5 V
300 MHz, –3 dB Bandwidth (G = +1)
180 MHz, –3 dB Bandwidth (G = +2)
2000 V/␮s Slew Rate
29 ns Settling Time to 0.1%
Good Video Specifications (RL = 1 k⍀, G = +2)
Gain Flatness 0.1 dB to 25 MHz
0.02% Differential Gain Error
0.06ⴗ Differential Phase Error
Low Distortion
–70 dBc Worst Harmonic @ 5 MHz
–62 dBc Worst Harmonic @ 20 MHz
Single Supply Operation
Fully Specified for 5 V Supply
FUNCTIONAL BLOCK DIAGRAM
8-Lead PDIP and SOIC
7
+IN 3
6 OUT
4
AD8011
V+
5 NC
PRODUCT DESCRIPTION
The AD8011 is a very low power, high speed amplifier designed
to operate on +5 V or ± 5 V supplies. With wide bandwidth,
low distortion, and low power, this device is ideal as a generalpurpose amplifier. It also can be used to replace high speed
amplifiers consuming more power. The AD8011 is a current feedback amplifier and features gain flatness of 0.1 dB to 25 MHz
while offering differential gain and phase error of 0.02% and 0.06°
on a single 5 V supply. This makes the AD8011 ideal for professional video electronics such as cameras, video switchers, or any
high speed portable equipment. Additionally, the AD8011’s low
distortion and fast settling make it ideal for buffering high speed
8-, 10-, and 12-bit A-to-D converters.
The AD8011 offers very low power of 1 mA maximum and can
run on single 5 V to 12 V supplies. All this is offered in a small
8-lead PDIP or 8-lead SOIC package. These features fit well with
portable and battery-powered applications where size and power
are critical.
G = +2
RF = 1k⍀
VS = +5V OR ⴞ5V
VOUT = 200mV p-p
The AD8011 is available in the industrial temperature range of
–40°C to +85°C.
2
–40
1
0
G = +2
THIRD
RL = 150⍀
–1
–2
–3
–4
–5
1
10
FREQUENCY (MHz)
100
500
Figure 1. Frequency Response; G = +2, VS = +5 V, or ± 5 V
DISTORTION (dBc)
NORMALIZED GAIN (dB)
–IN 2
NC = NO CONNECT
5
3
8 NC
V–
APPLICATIONS
Power Sensitive, High Speed Systems
Video Switchers
Distribution Amplifiers
A-to-D Driver
Professional Cameras
CCD Imaging Systems
Ultrasound Equipment (Multichannel)
4
NC 1
–60
SECOND
RL = 150⍀
THIRD
RL =1k⍀
–80
SECOND
RL = 1k⍀
–100
10
20
FREQUENCY (MHz)
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
Figure 2. Distortion vs. Frequency; VS = ± 5 V
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
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IMPORTANT LINKS for the AD8011*
Last content update 08/18/2013 06:27 pm
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DOCUMENTATION
AN-692: Universal Precision Op Amp Evaluation Board
AN-649: Using the Analog Devices Active Filter Design Tool
AN-356: User's Guide to Applying and Measuring Operational
Amplifier Specifications
MT-057: High Speed Current Feedback Op Amps
MT-051: Current Feedback Op Amp Noise Considerations
MT-034: Current Feedback (CFB) Op Amps
MT-059: Compensating for the Effects of Input Capacitance on VFB
and CFB Op Amps Used in Current-to-Voltage Converters
A Stress-Free Method for Choosing High-Speed Op Amps
UG-101: Evaluation Board User Guide
Considerations In Designing Single Supply, Low-Power Systems
Part 1: Designs Using Ac Line Power
Considerations In Designing Single Supply, Low-Power Systems
Part 2: Battery Powered Systems
Two-Stage Current-Feedback Amplifier
New High-Speed, Low-Power Data-Acquisition ICs
Application Example--ADC Driver
Single-Supply IF-Strip Digitizes QAM Signals
Choosing High-Speed Signal Processing Components for Ultrasound
Systems
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Quality and Reliability
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AD8011
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AD8011–SPECIFICATIONS
DUAL SUPPLY
(@ TA = 25ⴗC, VS = ⴞ5 V, G = +2, RF = 1 k⍀, RL = 1 k⍀, unless otherwise noted.)
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, VO < 1 V p-p
–3 dB Small Signal Bandwidth, VO < 1 V p-p
–3 dB Large Signal Bandwidth, VO = 5 V p-p
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
Rise and Fall Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Conditions
Min
G = +1
G = +2
G = +10, RF = 500 Ω
G = +2
G = +2, VO = 4 V Step
G = –1, VO = 4 V Step
G = +2, VO = 2 V Step
G = +2, VO = 2 V Step
G = –1, VO = 2 V Step
340
180
20
fC = 5 MHz, VO = 2 V p-p, G = +2
RL = 1 kΩ
RL = 150 Ω
RL = 1 kΩ
RL = 150 Ω
f = 10 kHz
f = 10 kHz, +In
–In
NTSC, G = +2, RL = 1 kΩ
RL = 150 Ω
NTSC, G = +2, RL = 1 kΩ
RL = 150 Ω
DC PERFORMANCE
Input Offset Voltage
AD8011A
Typ
Offset Drift
–Input Bias Current
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
ns
ns
–75
–67
–70
–54
2
5
5
0.02
0.02
0.06
0.3
dB
dB
dB
dB
nV/√Hz
pA/√Hz
pA/√Hz
%
%
Degrees
Degrees
TMIN–TMAX
+Input Bias Current
5
TMIN–TMAX
Open-Loop Transresistance
800
550
TMIN–TMAX
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Offset Voltage
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Resistance
Output Current
Short-Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
+Input
+Input
VCM = ± 2.5 V
TMIN–TMAX
5
6
15
20
15
20
1300
± mV
± mV
µV/°C
±µA
±µA
±µA
±µA
kΩ
kΩ
3.8
450
2.3
4.1
kΩ
pF
±V
–52
–57
dB
3.9
4.1
0.1
30
60
15
± 1.5
TMIN–TMAX
VS = ± 5 V ± 1 V
Unit
400
210
57
25
3500
1100
25
0.4
3.7
2
2
10
5
TMIN–TMAX
Max
55
1.0
58
0.3
± 6.0
1.3
±V
Ω
mA
mA
V
mA
dB
Specifications subject to change without notice.
–2–
REV. C
AD8011
SINGLE SUPPLY
(@ TA = 25ⴗC, VS = 5 V, G = +2, RF = 1 k⍀, VCM = 2.5 V, RL = 1 k⍀, unless otherwise noted.)
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, VO < 0.5 V p-p
–3 dB Small Signal Bandwidth, VO < 0.5 V p-p
–3 dB Large Signal Bandwidth, VO = 2.5 V p-p
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
Rise and Fall Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Conditions
Min
G = +1
G = +2
G = +10, RF = 500 Ω
G = +2
G = +2, VO = 2 V Step
G = –1, VO = 2 V Step
G = +2, VO = 2 V Step
G = +2, VO = 2 V Step
G = –1, VO = 2 V Step
270
150
15
fC = 5 MHz, VO = 2 V p-p, G = +2
RL = 1 kΩ
RL = 150 Ω
RL = 1 kΩ
RL = 150 Ω
f = 10 kHz
f = 10 kHz, +In
–In
NTSC, G = +2, RL = 1 kΩ
RL = 150 Ω
NTSC, G = +2, RL = 1 kΩ
RL = 150 Ω
DC PERFORMANCE
Input Offset Voltage
AD8011A
Typ
Offset Drift
–Input Bias Current
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
ns
ns
–84
–67
–76
–54
2
5
5
0.02
0.6
0.06
0.8
dB
dB
dB
dB
nV/√Hz
pA/√Hz
pA/√Hz
%
%
Degrees
Degrees
TMIN–TMAX
+Input Bias Current
5
TMIN–TMAX
Open-Loop Transresistance
800
550
TMIN–TMAX
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Offset Voltage
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Resistance
Output Current
Short-Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
+Input
+Input
VCM = 1.5 V to 3.5 V
TMIN–TMAX
REV. C
mV
mV
µV/°C
±µA
±µA
±µA
±µA
kΩ
kΩ
1.5 to 3.5
kΩ
pF
V
–52
–57
dB
1.2 to 3.8
0.9 to 4.1
0.1
30
50
55
–3–
15
20
15
20
1300
+3
Specifications subject to change without notice.
5
6
450
2.3
1.2 to 3.8
15
TMIN–TMAX
∆VS = ± 1 V
Unit
328
180
57
20
2000
500
29
0.6
4
2
2
10
5
TMIN–TMAX
Max
0.8
58
0.3
+12
1.15
+V
Ω
mA
mA
V
mA
dB
AD8011
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Internal Power Dissipation2
Plastic DIP Package (N) . . . . . . . Observe Derating Curves
Small Outline Package (R) . . . . . . Observe Derating Curves
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± 2.5 V
Output Short-Circuit Duration
. . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
The maximum power that can be safely dissipated by the AD8011
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Exceeding this limit temporarily
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can result
in device failure.
While the AD8011 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. To ensure proper
operation, it is necessary to observe the maximum power derating
curves (shown in Figure 3).
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead PDIP Package: ␪JA = 90°C/W
8-Lead SOIC Package: ␪JA = 155°C/W
1k⍀
1k⍀
RL
1k⍀
VOUT
VIN
+VS
50⍀
0.01␮F
10␮F
0.01␮F
10␮F
2.0
MAXIMUM POWER DISSIPATION (W)
TJ = 150ⴗC
–VS
8-LEAD PLASTIC DIP PACKAGE
Figure 4. Test Circuit; Gain = +2
1.5
VIN
1.0
1k⍀
1k⍀
RL
1k⍀
52.3⍀
8-LEAD SOIC PACKAGE
+VS
0.5
0
–50 –40 –30 –20 –10
VOUT
0.01␮F
10␮F
0.01␮F
10␮F
–VS
0
10
20 30
40
50
60
70 80
Figure 5. Test Circuit; Gain = –1
90
AMBIENT TEMPERATURE (ⴗC)
Figure 3. Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD8011AN
AD8011AR
AD8011AR-REEL
AD8011AR-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead PDIP
8-Lead SOIC
13" Tape and Reel
7" Tape and Reel
N-8
R-8
R-8
R-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8011 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. C
Typical Performance Characteristics–AD8011
5ns
20mV
5ns
20mV
*TPC 1. 100 mV Step Response; G = +2,
VS = ±2.5 V or ±5 V
*TPC 4. 100 mV Step Response; G = –1,
VS = ± 2.5 V or ± 5 V
4V STEP
4V STEP
2V STEP
2V STEP
10ns
800mV
*TPC 2. Step Response; G = +2, VS = ± 2.5 V
(2 V Step) and ± 5 V (4 V Step)
*TPC 5. Step Response; G = –1, VS = ± 2.5 V
(2 V Step) and ± 5 V (4 V Step)
9
6.5
G = +2
VIN = 100mV p-p
RL = 1k⍀
RF = 1k⍀
6.4
6.3
8
ⴞ5V
VS = +5V
7
SWING (V p-p)
6.2
GAIN (dB)
10ns
800mV
6.1
VS = ⴞ5V
6.0
5.9
6
5
4
+5V
3
5.8
2
5.7
1
5.6
0
10
5.5
1
10
FREQUENCY (MHz)
100
500
TPC 3. Gain Flatness; G = +2
TPC 6. Output Voltage Swing vs. Load
*NOTE: VS = ± 5 V operation is identical to V S = +5 V single-supply operation.
REV. C
100
1000
LOAD RESISTANCE (⍀)
–5–
10000
AD8011
–40
–40
–60
SECOND
RL = 150⍀
THIRD
RL =1k⍀
–80
THIRD
RL = 150⍀
G = +2
THIRD
RL = 150⍀
DISTORTION (dBc)
–60
SECOND
RL = 150⍀
–80
THIRD
RL =1k⍀
SECOND
RL = 1k⍀
SECOND
RL =1k⍀
–100
–100
10
1
20
10
RL = 1k⍀
IRE
VS = ⴞ5V
G = +2
0.08
0.06
0.04
0.02
0.00
–0.02
–0.04
–0.06
–0.08
100
0.4
0.3
0.2
0.1
0.00
–0.1
–0.2
–0.3
–0.4
RL = 150⍀
RL = 1k⍀
0
1k⍀ DIFF GAIN (%)
RL = 150⍀
0.08
0.06
0.04
0.02
0.00
–0.02
–0.04
–0.06
–0.08
1k⍀ DIFF PHASE (Degrees)
VS = ⴞ5V
G = +2
0
0.04
0.03
0.02
0.01
0.00
–0.01
–0.02
–0.03
–0.04
TPC 10. Distortion vs. Frequency; VS = +5 V
IRE
100
VS = +5V
G = +2
RL=1k⍀
RL=150⍀
0
150⍀ DIFF PHASE (Degrees)
1k⍀ DIFF PHASE (Degrees)
DIFF GAIN (%)
TPC 7. Distortion vs. Frequency; VS = ± 5 V
0.04
0.03
0.02
0.01
0.00
–0.01
–0.02
–0.03
–0.04
20
FREQUENCY (MHz)
FREQUENCY (MHz)
IRE
TPC 8. Diff Phase and Diff Gain; VS = ± 5 V
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
100
VS = +5V
G = +2
RL=150⍀
RL=1k⍀
0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
150⍀ DIFF GAIN (%)
1
150⍀ DIFF PHASE (Degrees)
DISTORTION (dBc)
G = +2
100
IRE
TPC 11. Diff Phase and Diff Gain; VS = +5 V
9
3
6
0
1V rms
–3
OUTPUT VOLTAGE (dBV)
OUTPUT VOLTAGE (dBV)
3
1V rms
0
–3
–6
–9
–12
–6
–9
–12
–15
–18
–15
–21
–18
–24
–21
1
10
40
FREQUENCY (MHz)
100
–27
1
500
TPC 9. Large Signal Frequency Response;
VS = ± 5 V, G = +2
10
40
FREQUENCY (MHz)
100
500
TPC 12. Large Signal Frequency Response;
VS = +5 V, G = +2
–6–
REV. C
AD8011
5
VS = +5V OR ⴞ5V
VOUT = 200mV p-p
NORMALIZED GAIN (dB)
3
G = +1
RF = 1k⍀
2
G = +2
RF = 1k⍀
1
0
–1
G = +2
RF = 1K⍀
2V STEP
OUTPUT VOLTAGE (0.1%/DIV)
4
G = +10
RF = 500⍀
–2
–3
–4
5ns
0.1%
–5
1
10
FREQUENCY (MHz)
100
500
t=0
TPC 16. Short-Term Settling Time; VS = +5 V or ± 5 V
TPC 13. Frequency Response; G = +1, +2, +10;
VS = +5 V or ± 5 V
2
VS = +5V OR ⴞ5V
VOUT = 200mV p-p
G = –10
RF = 500⍀
RL = 1k⍀
NORMALIZED GAIN (dB)
0
–1
G = –1
RF = 1k⍀
RL = 1k⍀
–2
G = +2
RF = 1k⍀
2V STEP
OUTPUT VOLTAGE (0.1%/DIV)
1
–3
–4
–5
–6
–7
0.1%
100ns
–8
1
10
FREQUENCY (MHz)
100
500
t=0
TPC 17. Long-Term Settling Time; VS = +5 V or ± 5 V
TPC 14. Frequency Response; G = –1, –10;
VS = +5 V or ± 5 V
–10
–15
–20
10
0
VS = +5V OR ⴞ5V
G = +2
–10
–25
–20
–30
–30
VS = +5V OR ⴞ5V
G = +2
RF = 1k⍀
–PSRR
PSRR (dB)
CMRR (dB)
+PSRR
–35
–40
–40
–50
–45
–60
–50
–70
–55
–80
–60
0.1
1
10
FREQUENCY (MHz)
–90
100
TPC 15. CMRR vs. Frequency; VS = +5 V or ± 5 V
REV. C
100k
1M
10M
FREQUENCY (Hz)
100M
500M
TPC 18. PSRR vs. Frequency; VS = +5 V or ± 5 V
–7–
VS = +5V OR ⴞ5V
G = +2
RF = 1k⍀
INPUT VOLTAGE NOISE (nV/ Hz)
OUTPUT RESISTANCE (⍀)
100
10
1
0.1
12.5
50
10.0
40
7.5
30
5.0
20
2.5
10
INPUT CURRENT NOISE (pA/ Hz)
AD8011
0.01
10k
0.1M
1M
10M
FREQUENCY (Hz)
100M
0
500
500M
0
120
–40
PEAK-TO-PEAK OUTPUT AT 5MHz [ 0.5% THD] (V)
140
–80
80
–120
GAIN
60
–160
40
–200
20
–240
10k
100k
1M
10M
FREQUENCY (Hz)
100M
PHASE (Degrees)
GAIN (dB ⍀)
PHASE
100
1k
0
100k
10k
FREQUENCY (Hz)
TPC 21. Noise vs. Frequency; VS = +5 V or ± 5 V
TPC 19. Output Resistance vs. Frequency;
VS = +5 V or ±5 V
0
1k
–280
1G
TPC 20. Transimpedance Gain and Phase vs. Frequency
9
RL = 1k⍀
8
f = 5MHz
G = +2
RF = 1k⍀
7
6
RL = 150⍀
5
4
3
2
1
0
3
4
5
6
7
8
9
TOTAL SUPPLY VOLTAGE (V)
10
11
TPC 22. Output Swing vs. Supply
–8–
REV. C
AD8011
Overall, when high external load drive and low ac distortion is a
requirement, a twin gain stage integrating amplifier like the AD8011
will provide superior results for lower power over the traditional
single-stage complementary devices. In addition, being a CF
amplifier, closed-loop BW variations versus external gain variations
(varying RN) will be much lower compared to a VF op amp, where
the BW varies inversely with gain. Another key attribute of this
amplifier is its ability to run on a single 5 V supply due in part to
its wide common-mode input and output voltage range capability.
For 5 V supply operation, the device obviously consumes half
the quiescent power (versus 10 V supply) with little degradation
in its ac and dc performance characteristics. See Specifications.
THEORY OF OPERATION
The AD8011 is a revolutionary generic high speed CF amplifier
that attains new levels of BW, power, distortion, and signal swing
capability. If these key parameters were combined as a figure of
ac merit performance or [(frequency ⫻ VSIG)/(distortion ⫻ power)],
no IC amplifier today would come close to the merit value of the
AD8011 for frequencies above a few MHz. Its wide dynamic
performance (including noise) is the result of both a new complementary high speed bipolar process and a new and unique
architectural design. The AD8011 uses basically a two gain stage
complementary design approach versus the traditional “single
stage” complementary mirror structure sometimes referred to as
the Nelson amplifier. Though twin stages have been tried before,
they typically consumed high power since they were of a folded
cascade design much like the AD9617. This design allows for
the standing or quiescent current to add to the high signal or slew
current induced stages much like the Nelson or single-stage design.
Thus, in the time domain, the large signal output rise/fall time
and slew rate is controlled typically by the small signal BW of the
amplifier and the input signal step amplitude respectively, not the
dc quiescent current of the gain stages (with the exception of
input level shift diodes Q1/Q2). Using two stages versus one also
allows for a higher overall gain bandwidth product (GBWP) for
the same power, thus lower signal distortion and the ability to
drive heavier external loads. In addition, the second gain stage
also isolates (divides down) A3’s input reflected load drive and
the nonlinearities created resulting in relatively lower distortion
and higher open-loop gain.
A1
Gain stages A1/A1B and A2/A2B combined provide negative
feedforward transresistance gain (see Figure 6). Stage A3 is a unity
gain buffer that provides external load isolation to A2. Each stage
uses a symmetrical complementary design. (A3 is also complementary though not explicitly shown.) This is done to reduce second
order signal distortion and overall quiescent power as discussed
previously. In the quasi dc to low frequency region, the closedloop gain relationship can be approximated as
G = 1 + RF /RN
G = –RF /RN
noninverting operation
inverting operation
These basic relationships are common to all traditional operational amplifiers. Due to the inverting input error current (IE)
required to servo the output and the inverting IE ⫻ RI drop
CD
Z1 = R1 || C1
Z1
IPN
IPP
DC GAIN CHARACTERISTICS
–VI
A2
CP1
IQ1
Q3
CP2
IR + IFC
ICQ + IO
Q1
VN
VP
VO
ZI
A3
Z2
VO
RL
Q2
RF
IE
RL
IR – IFC
Q4
ICQ – IO
Z1
IQ1
INP
–VI
IPN
A2
CP1
AD8011
A1
CD
Figure 6. Simplified Block Diagram
REV. C
–9–
CL
AD8011
This analysis assumes perfect current sources and infinite transistor
VAs. (Q3, Q4 output conductances are assumed zero.) These
assumptions result in actual versus model open-loop voltage gain
and associated input referred error terms being less accurate for
low gain (G) noninverting operation at the frequencies below the
open-loop pole of the AD8011. This is primarily a result of the
input signal (VP) modulating the output conductances of Q3/Q4,
resulting in RI less negative than derived here. For inverting
operation, the actual versus model dc error terms are relatively
much less.
AV =
G
G
=
G × RI RF
R
G
1+
+
1+
+ F
TO
TO
AO TO
for noninverting (G is positive).
AV =
G
1 – G RF
1+
+
AO
TO
for inverting (G is negative).
–90
–100
–110
60
PHASE
GAIN (dB ⍀)
where G is the ideal gain as previously described. With RI = TO /AO
(open-loop inverting input resistance), the second expression
(positive G) clearly relates to the classical voltage feedback op amp
equation with TO omitted due to its relatively much higher value
and thus insignificant effect. AO and TO are the open-loop dc
voltage and transresistance gains of the amplifier, respectively.
These key transfer variables can be described as
AO =
80
70
mc
–120
40
–130
GAIN
30
× R1)
–140
–150
20
–160
10
AO(s)
0
R1 × gmf × |A2|
(1 – g
50
–170
–10
–180
–20
–190
–30
1E+03
1E+04
1E+05
1E+06
PHASE (Degrees)
(error current times the open-loop inverting input resistance) that
results (see Figure 7), a more exact low frequency closed-loop
transfer function can be described as
1E+07
1E+08
–200
1E+09
FREQUENCY (Hz)
TO =
and
R1 × |A2|
Figure 8. Open-Loop Voltage Gain and Phase
2
1 – gmc × R1
RI =
2× g
Therefore
mf
where gmc is the positive feedback transconductance (not shown)
and 1/gmf is the thermal emitter resistance of devices D1/D2 and
Q3/Q4. The gmc × R1 product has a design value that results in a
negative dc open-loop gain of typically –2500 V/V (see Figure 8).
+VS
LS
LN
RS
TO (s)
AO (s)
IE
VP
ZI
LI
CP
RN
VO
RL
AC TRANSFER CHARACTERISTICS
The ac small signal transfer derivations below are based on a
simplified single-pole model. Though inaccurate at frequencies
approaching the closed-loop BW (CLBW) of the AD8011 at low
noninverting external gains, they still provide a fair approximation and an intuitive understanding of its primary ac small signal
characteristics.
For inverting operation and high noninverting gains, these
transfer equations provide a good approximation to the actual
ac performance of the device.
To accurately quantify the VO versus VP relationship, AO(s)
and TO(s) need to be derived. This can be seen by the following
nonexpanded noninverting gain relationship
CL
VO (s) / VP (s) =
LS
RF
G
R
G
+ F +1
AO [s] TO [s]
–VS
Z I = OPEN LOOP INPUT IMPEDANCE = CI || RL
with
Figure 7. ZI = Open-Loop Input Impedance
Though atypical of conventional CF or VF amps, this negative
open-loop voltage gain results in an input referred error term
(VP–VO/G = G/AO + RF/TO) that will typically be negative for G,
greater than +3/–4. As an example, for G = 10, AO = –2500,
and TO = 1.2 MΩ, results in an error of –3 mV using the AV
derivation above.
AO ( s ) =
R1 × g
× | A2 |
mf
1 – g × R1
mc
Sτ 1
1 – g × R1
mc
where R1 is the input resistance to A2/A2B, and τ1 (equal to
CD ⫻ R1 ⫻ A2) is the open-loop dominate time constant,
and
–10–
TO (s) =
| A2 | ×R1
2
sτ1 + 1
REV. C
AD8011
140
20
400
0
SERIES 1
370
–40
GAIN
60
–160
TO(s)
40
–200
20
–240
RESISTANCE (⍀)
–120
80
PHASE (Degrees)
–80
–20
PHASE
340
PHASE
100
GAIN (dB ⍀)
0
IMPEDANCE
310
–40
280
–60
250
–80
ZI(s)
220
–100
190
–120
–140
160
SERIES 2
–160
130
0
1E+03
1E+04
1E+05
1E+06
1E+07
FREQUENCY (Hz)
1E+08
PHASE (Degrees)
120
–280
1E+09
100
1E+03
1E+04
1E+05
1E+06
1E+07
FREQUENCY (Hz)
–180
1E+09
1E+08
Figure 9. Open-Loop Transimpedance Gain
Figure 10. Open-Loop Inverting Input Impedance
Note that the ac open-loop plots in Figures 8, 9, and 10 are based
on the full SPICE AD8011 simulations and do not include
external parasitics (see equations below). Nevertheless, these ac
loop equations still provide a good approximation to simulated
and actual performance up to the CLBW of the amplifier. Typically, gmc ⫻ R1 is –4, resulting in AO(s) having a right half plane
pole. In the time domain (inverse Laplace of AO), it appears as
unstable, causing VO to exponentially rail out of its linear region.
When the loop is closed however, the BW is greatly extended and
the transimpedance gain, TO (s), overrides and directly controls
the amplifiers stability behavior due to ZI approaching 1/2 gmf
for s>>1/τ1 (see Figure 10). This can be seen by the ZI (s) and
AV (s) noninverting transfer equations below.
ZI (s) goes positive real and approaches 1/2 gmf as ␻ approaches
(gmc 冤 R1 – 1)/τ1. This results in the input resistance for the AV (s)
complex term being 1/2 gmf, the parallel thermal emitter
resistances of Q3/Q4. Using the computed CLBW from AV (s)
and the nominal design values for the other parameters, results in
a closed-loop 3 dB BW equal to the open-loop corner frequency
(1/2 πτ1) × 1/[G/(2 gmf ⫻ TO) + RF/TO]. For a fixed RF, the
3 dB BW is controlled by the RF/TO term for low gains and
G/(2 gmf ⫻ TO) for high gains. For example, using nominal design
parameters and R1 = 1 kΩ (which results in a nominal TO of
1.2 MΩ), the computed BW is 80 MHz for G = 0 (inverting
I-V mode with RN removed) and 40 MHz for G = +10/–9.


Sτ 1
(1 – g × R1) 
+ 1
mc
1 – gmc × R 1 
Z I (s) =
(Sτ 1 + 1)
2× g
mf
AV ( s ) =
G


G
RF  
G
R  
+ F  + 1
1 + A + T  Sτ 1 2 g
T
TO  
O
O 

 
 mf O

DRIVING CAPACITIVE LOADS
The AD8011 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, the best
settling response is obtained by the addition of a small series
resistance as shown in Figure 11. The accompanying graph shows
the optimum value for RSERIES versus capacitive load. It is worth
noting that the frequency response of the circuit when driving
large capacitive loads will be dominated by the passive roll-off
of RSERIES and CL.
1k⍀
1k⍀
RSERIES
AD8011
RL
1k⍀
CL
Figure 11. Driving Capacitive Load
REV. C
–11–
AD8011
40
11
10
VS = ⴞ5V
G = +2
VIN = 200mV
9
8
30
GAIN (dB)
RSERIES (⍀)
RF = 750⍀
7
6
RF = 1k⍀
5
20
4
3
2
10
0
5
10
15
20
1
25
1
CL (pF)
Figure 12. Recommended RSERIES vs. Capacitive
Load for ≤ 30 ns Settling to 0.1%
10
FREQUENCY (MHz)
100
500
Figure 13. Flatness vs. Feedback
OPTIMIZING FLATNESS
As mentioned, the previous ac transfer equations are based on a
simplified single-pole model. Due to the device’s internal parasitics (primarily CP1/CP1B and CP2 in Figure 6) and external
package/board parasites (partially represented in Figure 12) the
computed BW, using the previous VO (s) equation, typically will
be lower than the AD8011’s measured small signal BW. See
data sheet Bode plots.
With only internal parasitics included, the BW is extended due
to the complex pole pairs created primarily by CP1/CP2B and
CP2 versus the single-pole assumption shown above. This
results in a design controlled, closed-loop damping factor (␨) of
nominally 0.6 resulting in the CLBW increasing by approximately 1.3⫻ higher than the computed single-pole value above
for optimized external gains of +2/–1. As external noninverting
gain (G) is increased, the actual closed-loop bandwidth versus
the computed single-pole ac response is in closer agreement.
Inverting pin and external component capacitance (designated CP)
will further extend the CLBW due to the closed-loop zero created
by CP and RN储RF when operating in the noninverting mode. Using
proper RF component and layout techniques (see the Layout
Considerations section), this capacitance should be about 1.5 pF.
This results in a further incremental BW increase of almost 2⫻
(versus the computed value) for G = +1 decreasing and approaching its complex pole pair BW for gains approaching +6 or higher.
As previously discussed, the single-pole response begins to correlate well. Note that a pole is also created by 1/2 gmf and CP, which
prevents the AD8011 from becoming unstable. This parasitic
has the greatest effect on BW and peaking for low positive gains
as the data sheet Bode plots clearly show. For inverting operation,
CP has relatively much less effect on CLBW variation.
Output pin and external component capacitance (designated CL)
will further extend the devices BW and can also cause peaking
below and above the CLBW if too high. In the time domain,
poor step settling characteristics (ringing up to about 2 GHz
and excessive overshoot) can result. For high CL values greater
than about 5 pF, an external series damping resistor is recommended. For light loads, any output capacitance will reflect on
A2’s output (Z2 of buffer A3) as both added capacitance near
the CLBW (CLBW > fT/B) and eventually negative resistance at
much higher frequencies. These added effects are proportional
to the load C. This reflected capacitance and negative resistance
has the effect of both reducing A2’s phase margin and causing
high frequency, L ⫻ C, peaking respectively. Using an external
series resistor (as previously specified) reduces these unwanted
effects by creating a reflected zero to A2’s output, which will
reduce the peaking and eliminate ringing. For heavy resistive
loads, relatively more load C would be required to cause these
same effects.
High inductive parasitics, especially on the supplies and inverting/
noninverting inputs, can cause modulated low level RF ringing on
the output in the transient domain. Proper RF component and
board layout practices need to be observed. Relatively high parasitic lead inductance (roughly L >15 nh) can result in L ⫻ C
underdamped ringing. Here L/C means all associated input pins,
external components, and lead frame strays, including collector
to substrate device capacitance. In the ac domain, this L ⫻ C
resonance effect would typically not appear in the pass band of
the amplifier but would appear in the open-loop response at
frequencies well above the CLBW of the amplifier.
–12–
REV. C
AD8011
INCREASING BW AT HIGH GAINS
As presented previously, for a fixed RF (feedback gain setting
resistor), the AD8011 CLBW will decrease as RN is reduced
(increased G). This effect can be minimized by simply reducing
RF and partially restoring the devices optimized BW for gains
greater than +2/–1. Note that the AD8011 is ac optimized (high
BW and low peaking) for AV = +2/–1 and RF = 1 kΩ. Using this
optimized G as a reference and the previous VO(s) equations,
the following relationships result: R F = 1kΩ + 2 – G/2 gm for
G = 1+ RF/RN (noninverting) or RF = 1kΩ + G + 1/2 gm for
G = –RF/RN (inverting).
Using 1/2 gm equal to 120 Ω results in a RF of 500 Ω for G =
+5/–4 and a corresponding RN of 125 Ω. This will extend the
AD8011’s BW to near its optimum design value of typically
180 MHz at RL = 1 kΩ. In general, for gains greater than +7/–6,
RF should not be reduced to values much below 400 Ω or else ac
peaking can result. Using this RF value as the lower limit will
result in BW restoration near its optimized value to the upper G
values specified. Gains greater than about +7/–6 will result in
CLBW reduction. The derivations above are just approximations.
DRIVING A SINGLE-SUPPLY A/D CONVERTER
New CMOS A/D converters are placing greater demands on the
amplifiers that drive them. Higher re solutions, faster conversion
rates, and input switching irregularities require superior settling
characteristics. In addition, these devices run off a single 5 V supply
and consume little power, so good single-supply operation with
low power consumption are very important. The AD8011 is
well positioned for driving this new class of A/D converters.
Figure 14 shows a circuit that uses an AD8011 to drive an AD876,
a single-supply, 10-bit, 20 MSPS A/D converter that requires
only 140 mW. Using the AD8011 for level shifting and driving,
the A/D exhibits no degradation in performance compared to
when it is driven from a signal generator.
+5V
R3
1.65k⍀
R2
1k⍀
0.1␮F
10␮F
3.6V
0.1␮F
1V
0V
+3.6V
R1
499k⍀
VIN
50⍀
0.1␮F
REFT
100⍀
AD8011
AD876
3.6V
1.6V
REFB
+1.6V
The analog input of the AD876 spans 2 V centered at about
2.6 V. The resistor network and bias voltages provide the level
shifting and gain required to convert the 0 V to 1 V input signal
to a 3.6 V to 1.6 V range that the AD876 wants to see.
Biasing the noninverting input of the AD8011 at 1.6 V dc forces
the inverting input to be at 1.6 V dc for linear operation of the
amplifier. When the input is at 0 V, there is 3.2 mA flowing out of
the summing junction via R1 (1.6 V/499 Ω). R3 has a current of
1.2 mA flowing into the summing junction (3.6 V – 1.6 V)/1.65 kΩ.
The difference of these two currents (2 mA) must flow through
R2. This current flows toward the summing junction and
requires that the output be 2 V higher than the summing junction
or at 3.6 V.
When the input is at 1 V, there is 1.2 mA flowing into the summing junction through R3 and 1.2 mA flowing out through R1.
These currents balance and leave no current to flow through R2.
Thus, the output is at the same potential as the inverting input
or 1.6 V.
The input of the AD876 has a series MOSFET switch that turns
on and off at the sampling rate. This MOSFET is connected to a
hold capacitor, internal to the device. The on impedance of the
MOSFET is about 50 Ω, while the hold capacitor is about 5 pF.
In a worst-case condition, the input voltage to the AD876 will
change by a full-scale value (2 V) in one sampling cycle. When
the input MOSFET turns on, the output of the op amp will be
connected to the charged hold capacitor through the series resistance of the MOSFET. Without any other series resistance, the
instantaneous current that flows would be 40 mA. This would
cause settling problems for the op amp.
The series 100 Ω resistor limits the current that flows instantaneously to about 13 mA after the MOSFET turns on. This resistor
cannot be made too large or the high frequency performance
will be affected.
The sampling MOSFET of the AD876 is closed for only half of
each cycle or for 25 ns. Approximately seven time constants are
required for settling to 10 bits. The series 100 Ω resistor, the
50 Ω on resistance, and the hold capacitor create a 750 ps time
constant. These values leave a comfortable margin for settling.
Obtaining the same results with the op amp A/D combination
as compared to driving with a signal generator indicates that the
op amp is settling fast enough.
Overall, the AD8011 provides adequate buffering for the AD876
A/D converter without introducing distortion greater than that
of the A/D converter by itself.
1.6V
Figure 14. AD8011 Driving the AD876
REV. C
–13–
AD8011
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8011 requires
careful attention to board layout and component selection. Table I
shows the recommended component values for the AD8011.
Proper RF design techniques and low parasitic component selection are mandatory.
Table I. Typical Bandwidth vs. Gain Setting Resistors
Gain
–1
–2
–10
+1
+2
+10
+6
+6
RF (⍀)
1000
1000
499
1000
1000
422
1000
500
RG (⍀)
1000
499
49.9
1000
47.5
200
100
RT (⍀)
52.3
54.9
49.9
49.9
49.9
49.9
49.9
Small Signal
–3 dB BW (MHz),
VS = ⴞ5 V
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance greater than 1.5 pF at the inverting input
will significantly affect high speed performance when operating
at low noninverting gains.
Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with the
proper system characteristic impedance and be properly
terminated at each end.
RG
VIN
RF
RO
VOUT
RT
150
130
140
400
250
100
70
170
C1
0.01␮F
C3
10␮F
C2
0.01␮F
C4
10␮F
–VS
INVERTING CONFIGURATION
RG
RF
RO
VOUT
RT chosen for 50 Ω characteristic input impedance. RO chosen for characteristic
output impedance.
VIN
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
RT
+VS
C1
0.01␮F
C3
10␮F
C2
0.01␮F
C4
10␮F
+VS
–VS
Chip capacitors should be used for supply bypassing (see
Figure 15). One end should be connected to the ground plane
and the other within 1/8 in. of each power pin. An additional tantalum electrolytic capacitor (4.7 µF – 10 µF) should be connected
in parallel.
–14–
NONINVERTING CONFIGURATION
Figure 15. Inverting and Noninverting Configurations
REV. C
AD8011
OUTLINE DIMENSIONS
8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
8
5
1
4
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.015
(0.38)
MIN
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
SEATING
PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MO-095AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Standard Small Outline Package [SOIC]
(R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
SEATING
0.10
PLANE
6.20 (0.2440)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
ⴛ 45ⴗ
0.25 (0.0099)
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. C
–15–
AD8011
Revision History
Location
Page
7/03—Data Sheet changed from REV. B to REV. C.
Format updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Renumbered figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to TPC 9 and 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to TPC 13 and 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Changes to TPC 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
–16–
REV. C
C01048–0–7/03(C)
Deleted all references to evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal