Anpec APL5910 1a, ultra low dropout (0.12v typical) linear regulator Datasheet

APL5910
1A, Ultra Low Dropout (0.12V Typical) Linear Regulator
General Description
Features
•
•
•
•
•
•
Ultra Low Dropout
- 0.12V (Typical) at 1A Output Current
The APL5910 is a 1A ultra low dropout linear regulator.
The IC needs two supply voltages, one is a control volt-
0.8V Reference Voltage
age (VCNTL) for the control circuitry, the other is a main
supply voltage (VIN) for power conversion, to reduce power
High Output Accuracy
- ±1.5% over Line, Load, and Temperature Range
dissipation and provide extremely low dropout voltage.
The APL5910 integrates many functions. A Power-On-
Fast Transient Response
Reset (POR) circuit monitors both supply voltages on
VCNTL and VIN pins to prevent erroneous operations.
Adjustable Output Voltage
The functions of thermal shutdown and current-limit protect the device against thermal and current over-loads. A
Power-On-Reset Monitoring on Both VCNTL and
VIN Pins
•
•
•
•
•
•
•
•
POK indicates that the output voltage status with a delay
time set internally. It can control other converter for power
Internal Soft-Start
Current-Limit and Short Current-Limit Protections
sequence. The APL5910 can be enabled by other power
systems. Pulling and holding the EN voltage below 0.4V
Thermal Shutdown with Hysteresis
Open-Drain VOUT Voltage Indicator (POK)
shuts off the output.
The APL5910 is available in a SOP-8P package which
Low Shutdown Quiescent Current (< 30µA )
features small size as SOP-8 and an Exposed Pad to
reduce the junction-to-case resistance to extend power
Shutdown/Enable Control Function
Simple SOP-8P Package with Exposed Pad
range of applications.
Lead Free and Green Devices Available
(RoHS Compliant)
Simplified Application Circuit
Applications
•
•
•
Motherboards, VGA Cards
VCNTL
Notebook PCs
Add-in Cards
VIN
VCNTL
Pin Configuration
POK
VIN
POK
VOUT
VOUT
APL5910
POK
EN
VIN
VCNTL
8
7
6
5
1
2
3
4
GND
FB
VOUT
NC
EN
Enable
EN
FB
GND
Optional
SOP-8P (Top View)
= Exposed Pad
(connected to ground plane for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2008
1
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APL5910
Ordering and Marking Information
Package Code
KA : SOP-8P
Operating Ambient Temperature Range
I : -40 to 85 °C
Handling Code
TR : Tape & Reel
Assembly Material
L : Lead Free Device G : Halogen and Lead Free Device
APL5910
Assembly Material
Handling Code
Temperature Range
Package Code
APL5910
XXXXX
APL5910 KA :
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
VCNTL
VIN
VOUT
Parameter
Rating
Unit
VCNTL Supply Voltage (VCNTL to GND)
-0.3 ~ 6
V
VIN Supply Voltage (VIN to GND)
-0.3 ~ 6
V
-0.3 ~ VIN+0.3
V
VOUT to GND Voltage
POK to GND Voltage
-0.3 ~ 7
EN, FB to GND Voltage
-0.3 ~ VCNTL+0.3
V
PD
Power Dissipation
Internally Limited
W
TJ
Maximum Junction Temperature
TSTG
Storage Temperature Range
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
150
ο
-65 ~ 150
ο
260
ο
C
C
C
Thermal Characteristics
Symbol
θJA
θJC
Parameter
Typical Value
Junction-to-Ambient Resistance in Free Air (Note 1)
SOP-8P
Junction-to-Case Resistance in Free Air (Note 2)
SOP-8P
Unit
50
o
20
o
C/W
C/W
Note 1: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Note 2: The “Thermal-Pad Temperature” is measured on the PCB copper area connected to the thermal pad of package.
1
8
2
7
3
4
5
6
Measured Point
PCB Copper
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2008
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APL5910
Recommended Operating Conditions
Symbol
VCNTL
Parameter
Range
Unit
3.0 ~ 5.5
V
1.0 ~ 5.5
V
0.8 ~ VIN - VDROP
V
VCNTL Supply Voltage
VIN
VIN Supply Voltage
VOUT
VOUT Output Voltage (when VCNTL-VOUT>1.4V)
IOUT
VOUT Output Current
R2
FB to GND
IOUT=1A at 25% nominal VOUT
COUT
VOUT Output Capacitance
ESRCOUT
TA
TJ
0~1
A
1k ~ 24k
Ω
8 ~ 600
IOUT=0.5A at 25% nominal VOUT
8 ~ 900
IOUT=0.25A at 25% nominal VOUT
8 ~ 1100
µF
ESR of VOUT Output Capacitor
0 ~ 200
Ambient Temperature
-40 ~ 85
ο
-40 ~ 125
ο
Junction Temperature
mΩ
C
C
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VCNTL=5V, VIN=1.5V, VOUT=1.2V, and TA= -40 ~ 85oC, unless
otherwise specified. Typical values are at TJ=25oC.
Symbol
Parameter
APL5910
Test Conditions
Min.
Typ.
Max.
Unit
SUPPLY CURRENT
IVCNTL
ISD
VCNTL Supply Current
EN = VCNTL, IOUT=0A
-
1.0
1.5
mA
VCNTL Supply Current at
Shutdown
EN = GND
-
20
30
µA
VIN Supply Current at
Shutdown
EN = GND, VIN=5.5V
-
-
1
µA
2.5
2.7
2.9
V
-
0.4
-
V
0.8
0.9
1.0
-
0.5
-
V
0.792
0.8
0.808
V
-1.5
-
+1.5
%
-
0.06
0.15
%
POWER-ON-RESET (POR)
Rising VCNTL POR Threshold
VCNTL POR Hysteresis
Rising VIN POR Threshold
VIN POR Hysteresis
OUTPUT VOLTAGE
VREF
Reference Voltage
FB=VOUT, IOUT=10mA,TJ=25oC
o
Output Voltage Accuracy
IOUT= 0~1A, TJ= -40~125 C
Load Regulation
IOUT=0A ~1A
Line Regulation
IOUT=10mA, VCNTL= 3.0 ~ 5.5V
-0.15
-
+0.15
%/V
VOUT Pull-Low Resistance
VCNTL=3.3V,VEN=0V, VOUT<0.8V
-
85
-
Ω
FB Input Current
VFB=0.8V
-100
-
100
nA
TJ=25oC
-
0.13
0.16
TJ=-40~125oC
-
-
0.22
TJ=25 C
-
0.12
0.15
TJ=-40~125oC
-
-
0.20
TJ=25oC
-
0.12
0.14
TJ=-40~125oC
-
-
0.19
DROPOUT VOLTAGES
VOUT=2.5V
VDROP
VIN-to-VOUT Dropout Voltage
VCNTL=4.5V,
IOUT=1A
o
VOUT=1.8V
VOUT=1.2V
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2008
3
V
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APL5910
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VCNTL=5V, VIN=1.5V, VOUT=1.2V, and TA= -40 ~ 85oC, unless
otherwise specified. Typical values are at TJ=25oC.
Symbol
Parameter
APL5910
Test Conditions
Min.
Typ.
Max.
Unit
PROTECTIONS
ILIM
TJ=25οC
1.7
2.1
2.5
1.4
-
-
-
0.4
-
0.6
1.6
-
ms
Thermal Shutdown Temperature TJ rising
-
170
-
o
Thermal Shutdown Hysteresis
-
50
-
o
0.5
0.8
1.1
V
-
80
-
mV
Current-Limit Level
ο
TJ= -40 ~ 125 C
ISHORT
TSD
Short Current-Limit Level
VFB<0.2V
Short Current-Limit Blanking
Time
From beginning of soft-start
A
C
C
ENABLE AND SOFT-START
EN Logic High Threshold Voltage VEN rising
EN Hysteresis
EN Pull-High Current
TSS
EN=GND
Soft-Start Interval
-
5
-
µA
0.3
0.6
1
ms
90
92
94
%
POWER-OK AND DELAY
VTHPOK
Rising POK Threshold Voltage
VFB rising
POK Threshold Hysteresis
-
8
-
%
POK sinks 5mA
-
0.25
0.4
V
POK Debounce Interval
VFB<falling POK voltage threshold
-
10
-
µs
POK Delay Time
From VFB =VTHPOK to rising edge of the
VPOK
1
2
4
ms
POK Pull-Low Voltage
Pin Description
PIN
FUNCTION
NO.
NAME
1
POK
Power-OK signal output pin. This pin is an open-drain output used to indicate the status of output
voltage by sensing FB voltage. This pin is pulled low when output voltage is not within the
Power-OK voltage window.
2
EN
Active-high enable control pin. Applying and holding the voltage on this pin below the enable
voltage threshold shuts down the output. When re-enabled, the IC undergoes a new soft-start
process. When left this pin open, an internal pull-up current (5µA typical) pulls the EN voltage and
enables the regulator.
3
VIN
Main supply input pin for voltage conversions. A decoupling capacitor (≥10µF recommended) is
usually connected near this pin to filter the voltage noise and improve transient response. The
voltage on this pin is monitored for Power-On-Reset purpose
4
VCNTL
Bias voltage input pin for internal control circuitry. Connect this pin to a voltage source (+5V
recommended). A decoupling capacitor (1µF typical) is usually connected near this pin to filter
the voltage noise. The voltage at this pin is monitored for Power-On-Reset purpose.
5
NC
6
VOUT
Output pin of the regulator. Connecting this pin to load and output capacitors (10µF at least) is
required for stability and improving transient response. The output voltage is programmed by the
resistor-divider connected to FB pin. The VOUT can provide 1A (max.) load current to loads.
During shutdown, the output voltage is quickly discharged by an internal pull-low MOSFET.
7
FB
Voltage Feedback Pin. Connecting this pin to an external resistor divider receives the feedback
voltage of the regulator.
No Connection.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2008
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APL5910
Pin Description (Cont.)
PIN
NO.
NAME
8
GND
Exposed Pad
-
FUNCTION
Ground pin of the circuitry. All voltage levels are measured with respect to this pin.
P-Type Substrate connection of the chip. Connect this pad to system ground plane for good
thermal conductivity.
Block Diagram
VCNTL
Thermal
Shutdown
VCNTL
PowerOn-Reset
(POR)
POR
5µA
Enable
EN
0.8V
Control Logic
and
Soft-Start
POR
VIN
VOUT
Error
Amplifier
Dela
y
Current-Limit
and
Short Current-Limit
90%
VREF
ISEN
PWOK
VREF
0.8V
Enabl
e
Soft-Start
POK
GND
FB
Typical Application Circuit
VCNTL
(+5V is preferred)
CCNTL
1µF
VIN
4
R3
5.1kΩ
1
POK
VIN
POK
+1.5V
CIN
10µF
VCNTL
VOUT
3
6
VOUT
+1.2V / 1A
EN
2
Enable
APL5910
EN
FB
7
GND
8
R2
24kΩ
R1
12kΩ
COUT
10µF
(X5R/X7R Recommended)
C1
Optional
(X5R/X7R Recommended)
10µF: GRM31MR60J106KE19 Murata
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2008
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APL5910
Typical Operating Characteristics
Short Current-Limit vs.
Junction Temperature
Current-Limit vs.
Junction Temperature
2.5
600
Current-Limit, ILIM (A)
2.3
Short Current-Limit, ISHORT (mA)
VOUT = 1.2V
2.4
VCNTL = 5V
2.2
2.1
2.0
1.9
VCNTL = 3.3V
1.8
1.7
1.6
1.5
550
500
VCNTL = 3.3V
450
400
350
VCNTL = 5V
300
250
200
1.4
-50
-25
0
25
50
75
100
125
-50
Dropout Voltage vs.
Output Current
25
50
75
100
125
Droput Voltage vs.
Output Current
200
180
VCNTL = 5V
VOUT = 1.2V
160
TJ = 125°
C
140
TJ = 75°
C
120
TJ = 25°
C
100
VCNTL = 3.3V
VOUT = 1.2V
180
Dropout Voltage, VDROP (mV)
Dropout Voltage, VDROP (mV)
0
Junction Temperature (oC)
Junction Temperature (oC)
80
TJ = 0°
C
60
40
TJ = - 40°
C
20
TJ = 125°
C
160
140
TJ = 75°
C
TJ = 25°
C
120
100
80
TJ = 0°
C
60
40
TJ = - 40°
C
20
0
0
0
0.25
0.5
0.75
0
1
0.25
0.5
0.75
Output Current, IOUT (A)
Output Current, IOUT (A)
Dropout Voltage vs.
Output Current
Dropout Voltage vs.
Output Current
200
1
220
VCNTL = 5V
VOUT = 1.8V
TJ = 125°
C
160
TJ = 75°
C
140
TJ = 25°
C
120
VCNTL = 3.3V
VOUT = 1.8V
200
Dropout Voltage, VDROP (mV)
180
Dropout Voltage, VDROP (mV)
-25
100
80
60
TJ = 0°
C
40
TJ = - 40°
C
20
180
TJ = 125°
C
TJ = 75°
C
160
140
TJ = 25°
C
120
100
80
TJ = 0°
C
60
TJ = - 40°
C
40
20
0
0
0
0.25
0.5
0.75
0
1
Output Current, IOUT (A)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2008
0.25
0.5
0.75
1
Output Current, IOUT (A)
6
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APL5910
Typical Operating Characteristics (Cont.)
Dropout Voltage vs.
Output Current
Reference Voltage vs.
Junction Temperature
220
0.808
Dropout Voltage, VDROP (mV)
180
Reference Voltage, VREF (V)
VCNTL = 5V
VOUT = 2.5V
200
TJ = 125°
C
160
TJ = 75°
C
140
TJ = 25°
C
120
100
80
60
TJ = 0°
C
40
0
0
0.5
0.25
0.804
0.802
0.800
0.798
0.796
0.794
TJ = - 40°
C
20
0.806
0.75
0.792
-50
1
-25
VCNTL Power Supply Rejection
Ratio (PSRR)
0
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
VCNTL=4.6~5.4V
VIN=1.5V
VOUT=1.2V
IOUT=1A
CIN=COUT=10µF
-30
-40
-50
-60
-70
-80
1000
10000
100000
75
100
125
-10
-20
VCNTL=5V
VIN=1.55V
VINPK-PK=100mV
VOUT=1.2V
IOUT=1A
COUT=10µF
-30
-40
-50
-60
-70
1000
1000000
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2008
50
VIN Power Supply Rejection
Ratio (PSRR)
0
-20
25
Junction Temperature (oC)
Output Current, IOUT (A)
-10
0
10000
100000
1000000
Frequency (Hz)
7
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APL5910
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25oC unless otherwise specified.
Power Off
Power On
1
VCNTL
VCNTL
1
VIN
VIN
2
2
VOUT
VOUT
3
4
3
VPOK
VPOK
4
COUT=10µF, CIN=10µF, RL=1.2Ω
CH1: VCNTL, 5V/Div, DC
CH2: VIN, 1V/Div, DC
CH3: VOUT, 1V/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 5ms/Div
COUT=10µF, CIN=10µF, RL=1.2Ω
CH1: VCNTL, 5V/Div, DC
CH2: VIN, 1V/Div, DC
CH3: VOUT, 1V/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 10ms/Div
Load Transient Response
Over Current Protection
VOUT
1
VOUT
1
IOUT
IOUT
4
4
IOUT=10mA to 1A to 10mA (rise / fall time = 1µs)
COUT=10µF, CIN=10µF
CH1: VOUT, 20mV/Div, AC
CH4: IOUT, 0.5A/Div, DC
TIME: 20µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2008
COUT=10µF, CIN=10µF, IOUT=1A to 2.3A
CH1: VOUT, 1V/Div, DC
CH4: IOUT, 1A/Div, DC
TIME: 50µs/Div
8
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APL5910
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25oC unless otherwise specified.
Enable
Shutdown
VEN
VEN
1
1
VOUT
VOUT
2
2
VPOK
VPOK
3
3
IOUT
IOUT
4
4
COUT=10µF, CIN=10µF, RL=1.2Ω
CH1: VEN, 5V/Div, DC
CH2: VOUT, 1V/Div, DC
CH3: VPOK, 5V/Div, DC
CH4: IOUT, 1.0A/Div, DC
TIME: 10µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2008
COUT=10µF, CIN=10µF, RL=1.2Ω
CH1: VEN, 5V/Div, DC
CH2: VOUT, 1V/Div, DC
CH3: VPOK, 5V/Div, DC
CH4: IOUT, 1.0A/Div, DC
TIME: 0.5ms/Div
9
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APL5910
Function Description
A Power-On-Reset (POR) circuit monitors both of supply
resulting in a pulsed output during continuous thermal
overload conditions. The thermal shutdown is designed
voltages on VCNTL and VIN pins to prevent wrong logic
controls. The POR function initiates a soft-start process
with a 50oC hysteresis to lower the average junction temperature during continuous thermal overload conditions,
after both of the supply voltages exceed their rising POR
voltage thresholds during powering on. The POR func-
extending lifetime of the device.
For normal operation, the device power dissipation should
tion also pulls low the POK voltage regardless of the
output status when one of the supply voltages falls below
be externally limited so that junction temperatures will
not exceed +125οC.
its falling POR voltage threshold.
Enable Control
Internal Soft-Start
An internal soft-start function controls rise rate of the out-
The APL5910 has a dedicated enable pin (EN). A logic
low signal applied to this pin shuts down the output. Fol-
put voltage to limit the current surge during start-up. The
typical soft-start interval is about 0.6ms.
lowing a shutdown, a logic high signal re-enables the
output through initiation of a new soft-start cycle. When
Output Voltage Regulation
left open, this pin is pulled up by an internal current source
(5µA typical) to enable normal operation. It’s not neces-
An error amplifier working with a temperature-compen-
sary to use an external transistor to save cost.
sated 0.8V reference and an output NMOS regulates output to the preset voltage. The error amplifier is designed
Power-OK and Delay
Power-On-Reset
The APL5910 indicates the status of the output voltage by
with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the
monitoring the feedback voltage (VFB) on FB pin. As the
VFB rises and reaches the rising Power-OK voltage thresh-
reference with the feedback voltage and amplifies the difference to drive the output NMOS which provides load
old (VTHPOK), an internal delay function starts to work. At the
end of the delay time, the IC turns off the internal NMOS of
current from VIN to VOUT.
the POK to indicate that the output is ok. As the VFB falls
and reaches the falling Power-OK voltage threshold, the
Current-Limit Protection
The APL5910 monitors the current flowing through the
IC turns on the NMOS of the POK (after a debounce time
output NMOS and limits the maximum current to prevent
load and APL5910 from damages during current over-
of 10µs typical).
load conditions.
Short Current-Limit Protection
The short current-limit function reduces the current-limit
level down to 0.4A (typical) when the voltage on FB pin
falls below 0.2V (typical) during current overload or shortcircuit conditions.
The short current-limit function is disabled for successful start-up during soft-start interval.
Thermal Shutdown
A thermal shutdown circuit limits the junction temperature of APL5910. When the junction temperature exceeds
+170oC, a thermal sensor turns off the output NMOS, allowing the device to cool down. The regulator regulates
the output again through initiation of a new soft-start process after the junction temperature cools by 50oC,
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2008
10
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APL5910
Application Information
Power Sequencing
More capacitance reduces the variations of the supply
voltage on VIN pin.
The power sequencing of VIN and VCNTL is not necessary to be concerned. However, do not apply a voltage to
VOUT for a long time when the main voltage applied at
Setting The Output Voltage
The output voltage is programmed by the resistor divider
connected to FB pin. The preset output voltage is calcu-
VIN is not present. The reason is the internal parasitic
diode from VOUT to VIN conducts and dissipates power
lated by the following equation :
without protections due to the forward-voltage.
R1 

VOUT = 0.8 ⋅ 1 +

 R2 
Output Capacitor
........... (V)
The APL5910 requires a proper output capacitor to maintain stability and improve transient response. The output
where R1 is the resistor connected from VOUT to FB with
Kelvin sensing connection and R2 is the resistor con-
capacitor selection is dependent upon ESR (equivalent
series resistance) and capacitance of the output capacitor
nected from FB to GND. A bypass capacitor (C1) may be
connected with R1 in parallel to improve load transient
over the operating temperature.
response and stability.
Ultra-low-ESR capacitors (such as ceramic chip
capacitors) and low-ESR bulk capacitors (such as solid
tantalum, POSCap, and Aluminum electrolytic capacitors)
can all be used as output capacitors.
During load transients, the output capacitors which is depending on the stepping amplitude and slew rate of load
current, are used to reduce the slew rate of the current
seen by the APL5910 and help the device to minimize the
variations of output voltage for good transient response.
For the applications with large stepping load current, the
low-ESR bulk capacitors are normally recommended.
Decoupling ceramic capacitors must be placed at the load
and ground pins as close as possible and the impedance of the layout must be minimized.
Input Capacitor
The APL5910 requires proper input capacitors to supply
current surge during stepping load transients to prevent
the input voltage rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN pin limits the slew rate of the surge
currents, more parasitic inductance needs, more input
capacitance.
Ultra-low-ESR capacitors (such as ceramic chip
capacitors) and low-ESR bulk capacitors (such as solid
tantalum, POSCap, and Aluminum electrolytic capacitors
can all be used as an input capacitor of VIN. For most
applications, the recommended input capacitance of VIN
is 10µF at least. However, if the drop of the input voltage
is not cared, the input capacitance can be less than 10µF.
Copyright  ANPEC Electronics Corp.
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APL5910
Layout Consideration (See figure 1)
Thermal Consideration
1. Please solder the Exposed Pad on the system ground
pad on the top-layer of PCBs. The ground pad must
Refer to the figure 2, the SOP-8P is a cost-effective package featuring a small size like a standard SOP-8 and a
have wide size to conduct heat into the ambient air
through the system ground plane and PCB as a heat
bottom exposed pad to minimize the thermal resistance
of the package, being applicable to high current
sink.
2. Please place the input capacitors for VIN and VCNTL
applications. The exposed pad must be soldered to the
top-layer ground plane. It is recommended to connect the
pins near the pins as close as possible for decoupling
high-frequency ripples.
top-layer ground pad to the internal ground plan by using
vias. The copper of the ground plane on the top-layer con-
3. Ceramic decoupling capacitors for load must be
placed near the load as close as possible for
ducts heat into the PCB and ambient air. Please enlarge
the area of the top-layer pad and the ground plane to
decoupling high-frequency ripples.
4. To place APL5910 and output capacitors near the load
reduce the case-to-ambient resistance (θCA).
reduces parasitic resistance and inductance for excellent load transient reponse.
5. The negative pins of the input and output capacitors
and the GND pin must be connected to the ground
plane of the load.
6. Large current paths, shown by bold lines on the figure 1, must have wide tracks.
7. Place the R1, R2, and C1 near the APL5910 as close
as possible to avoid noise coupling.
8. Connect the ground of the R2 to the GND pin by using
1
8
2
7
SOP-8P
3
6
4
5
Internal
ground
plane
a dedicated track.
9. Connect the one pin of the R1 to the load for Kelvin
Die
Exposed
Pad
Top
ground
plane
Ambient
Air
sensing.
10. Connect one pin of the C1 to the VOUT pin for reliable
PCB
feedback compensation.
Figure 2
VCNTL
Recommanded Minimum Footprint
CIN
0.024
VCNTL
VIN
VIN
APL5910
8
7
6
5
0.072
CCNTL
VOUT
VOUT
C1
COUT
(Optional)
0.138
R2
0.118
R1
Load
0.212
FB
GND
Figure 1
1
2
0.050
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Rev. A.2 - Aug., 2008
12
3
4
Unit : Inch
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APL5910
Package Information
SOP-8P
D
SEE VIEW
A
E
E2
THERMAL
PAD
E1
D1
h X 45
°
c
A
0.25
b
L
0
GAUGE PLANE
SEATING PLANE
A1
A2
e
VIEW A
S
Y
M
B
O
L
SOP-8P
MILLIMETERS
MIN.
MAX.
A
A1
INCHES
MAX.
MIN.
0.063
1.60
0.006
0.000
0.15
0.00
0.049
A2
1.25
b
0.31
0.51
0.012
0.020
c
0.17
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
D1
2.25
3.50
0.098
0.138
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
E2
2.00
3.00
0.079
0.118
e
h
1.27 BSC
0.25
0.050 BSC
0.50
0.010
0.020
0.050
8o
L
0.40
1.27
0.016
0
0o
8o
0o
Note : 1. Follow JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
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Rev. A.2 - Aug., 2008
13
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APL5910
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
SOP- 8P
A
H
T1
C
d
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN.
1.5 MIN.
-0.00
-0.20
P0
P1
P2
D0
D1
1.5+0.10
4.0±0.10 8.0±0.10 2.0±0.05
1.5 MIN.
-0.00
D
W
E1
20.2 MIN. 12.0±0.30 1.75±0.10
F
5.5±0.05
T
A0
B0
K0
0.6+0.00
6.40±0.20 5.20±0.20 2.10±
0.20
-0.40
(mm)
Devices Per Unit
Package Type
Unit
Quantity
SOP- 8P
Tape & Reel
2500
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Rev. A.2 - Aug., 2008
14
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APL5910
Taping Direction Information
SOP-8P
USER DIRECTION OF FEED
Reflow Condition (IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Temperature
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25°C to Peak
Time
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
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Rev. A.2 - Aug., 2008
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Description
245°C, 5 sec
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
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APL5910
Classification Reflow Profiles
Profile Feature
Average ramp-up rate (TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classification Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Sn-Pb Eutectic Assembly
3°C/second max.
Pb-Free Assembly
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package. Measured on the body surface.
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
3
3
Package Thickness
Volume mm
Volume mm
<350
≥350
<2.5 mm
240 +0/-5°C
225 +0/-5°C
≥2.5 mm
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
3
3
3
Package Thickness
Volume mm
Volume mm
Volume mm
<350
350-2000
>2000
<1.6 mm
260 +0°C*
260 +0°C*
260 +0°C*
1.6 mm – 2.5 mm
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 mm
250 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the
stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C)
at the rated MSL level.
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2008
16
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