P3P623S05A/B and P3P623S09A/B Timing-Safe™ Peak EMI Reduction IC General Features the CLKIN pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad, internal to the device. • Clock distribution with Timing-Safe™ Peak EMI Reduction Multiple P3P623S05 / P3P623S09 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of the two devices is guaranteed to be less than 700pS. • Input frequency range: 20MHz - 50MHz • Multiple low skew Timing-safe™ Outputs: P3P623S05: 5 Outputs P3P623S09: 9 Outputs • Supply Voltage: 3.3V±0.3V All outputs have less than 200pS of cycle-to-cycle jitter. • Packaging Information: The input and output propagation delay is guaranteed to P3P623S05: 8 pin TSSOP be less than ±350pS, and the output-to-output skew is P3P623S09:16 pin TSSOP guaranteed to be less than 250pS. • True Drop-in Solution for Zero Delay Buffer Refer “Spread Spectrum Control and Input-Output Skew Table” for deviations and Input-Output Skew for P3P623S05A/B and P3P623S09A/B devices. Functional Description P3P623S05/09 is a versatile, 3.3V Zero-delay buffer designed to distribute Timing-Safe™ clocks with Peak EMI reduction. P3P623S05 is an eight-pin version, accepts one reference input and drives out five low-skew Timing-Safe™ clocks. P3P623S09 accepts one reference input and drives out nine low-skew Timing-Safe™ clocks. All parts have on-chip PLLs that lock to an input clock on P3P623S05/09 operates from a 3.3V supply and is available in TSSOP package, as shown in the ordering information table. Application P3P623S05/09 is targeted for use in Displays and memory interface systems. General Block Diagram PLL CLKOUT PLL MUX CLKOUT CLKIN CLK1 CLKA1 CLKIN CLKA2 CLK2 CLKA3 CLK3 P3P623S05A/B CLKA4 CLK4 S2 S1 CLKB1 Select Input Decoding CLKB2 CLKB3 P3P623S09A/B ©2010 SCILLC. All rights reserved. July 2010 – Rev. 1 CLKB4 Publication Order Number: P3P623S05/D P3P623S05A/B and P3P623S09A/B Spread Spectrum Frequency Generation The clocks in digital systems are typically square waves PCBs, etc. These methods are expensive. Spread with a 50% duty cycle and as frequencies increase the spectrum clocking reduces the peak energy by reducing edge rates also get faster. Analysis shows that a square the Q factor of the clock. This is done by slowly wave is composed of fundamental frequency and modulating the clock frequency. The P3P623S05/09 uses harmonics. The fundamental frequency and harmonics the center modulation spread spectrum technique in generate the energy peaks that become the source of which the modulated output frequency varies above and EMI. Regulatory agencies test electronic equipment by below measuring the amount of peak energy radiated from the modulation rate. With center modulation, the average equipment. In fact, the peak level allowed decreases as frequency is the same as the unmodulated frequency and the frequency increases. The standard methods of there is no performance degradation. the reducing EMI are to use shielding, filtering, multi-layer Timing-Safe™ technology Timing-Safe™ technology is the ability to modulate a clock source with Spread Spectrum technology and maintain synchronization with any associated data path. Rev. 1 | Page 2 of 11 | www.onsemi.com reference frequency with a specified P3P623S05A/B and P3P623S09A/B Pin Configuration for P3P623S05A/B CLKIN 1 8 CLKOUT 7 CLK4 CLK2 3 6 VDD GND 4 5 CLK3 CLK1 2 P3P623S05A/B Pin Description for P3P623S05A/B Pin # Notes: Pin Name 1 Type Description 1 CLKIN I External reference Clock input, 5V tolerant input 2 CLK1 2 O Buffered clock output 3 CLK2 2 O Buffered clock output 4 GND P Ground O Buffered clock output P 3.3V supply O Buffered clock output O Buffered clock output.Internal feedback on this pin. 5 CLK3 6 VDD 2 2 7 CLK4 8 CLKOUT 4 4 4 4 4 1. Weak pull down 2. Weak pull-down on all outputs 3. Weak pull-up on these Inputs 4. Buffered clock output is Timing-Safe™ Rev. 1 | Page 3 of 11 | www.onsemi.com P3P623S05A/B and P3P623S09A/B Pin Configuration for P3P623S09A/B CLKIN 1 16 CLKOUT CLKA1 2 15 CLKA4 CLKA2 3 14 CLKA3 13 VDD 12 GND CLKB1 6 11 CLKB4 7 10 CLKB3 S2 8 9 S1 VDD 4 GND 5 CLKB2 P3P623S09A/B Pin Description for P3P623S09A/B Pin # 1 Pin Name External reference Clock input, 5V tolerant input O Buffered clock Bank A output 4 O Buffered clock Bank A output 4 P 3.3V supply 2 CLKA1 3 CLKA2 2 4 VDD 5 GND 6 CLKB1 2 7 CLKB2 2 9 S2 3 Ground O Buffered clock Bank B output 4 O Buffered clock Bank B output 4 Select input, bit 2. See Select Input Decoding table for P3P623S09A/B for more details S1 3 I Select input, bit 1. See Select Input Decoding table for P3P623S09A/B for more details 10 CLKB3 11 CLKB4 2 12 GND 13 VDD 14 CLKA3 2 15 CLKA4 2 16 P I 2 Notes: Description I CLKIN 2 8 Pin Type 1 2 CLKOUT O Buffered clock Bank B output 4 O Buffered clock Bank B output 4 P Ground P 3.3V supply O Buffered clock Bank A output 4 O Buffered clock Bank A output 4 O Buffered clock output.Internal feedback on this pin. 1. Weak pull down 2. Weak pull-down on all outputs 3. Weak pull-up on these Inputs 4. Buffered clock output is Timing-Safe™ Rev. 1 | Page 4 of 11 | www.onsemi.com P3P623S05A/B and P3P623S09A/B Select Input Decoding table for P3P623S09A/B 1 PLL S2 S1 CLK A1 - A4 CLK B1 - B4 CLKOUT Output Source 0 0 Three-state Three-state Driven PLL N 0 1 Driven Three-state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N Shut-Down Note1: This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the Output Spread Spectrum Control and Input-Output Skew Table Frequency (MHz) Device Deviation (±%) Input-Output Skew (±TSKEW) P3P623S05A / 09A 0.25 0.125 P3P623S05B / 09B 0.5 0.25 32 Note: TSKEW is measured in units of the Clock Period Absolute Maximum Ratings Symbol Parameter VDD Supply Voltage to Ground Potential VIN DC Input Voltage (CLKIN) TSTG Storage temperature Rating Unit -0.5 to +4.6 V -0.5 to +7 -65 to +125 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C TDV Static Discharge Voltage (As per JEDEC STD22- A114-B) 2 KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Operating Conditions Parameter Min Max Unit Supply Voltage 3.0 3.6 V TA Operating Temperature (Ambient Temperature) -40 +85 °C CL Load Capacitance 30 pF CIN Input Capacitance 7 pF VDD Description Rev. 1 | Page 5 of 11 | www.onsemi.com P3P623S05A/B and P3P623S09A/B Electrical Characteristics Parameter Description VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current IIH Input HIGH Current VOL Notes: Test Conditions Min Typ 5 5 Output LOW Voltage Max Unit 0.8 V 2.0 6 VOH Output HIGH Voltage IDD Supply Current Zo Output Impedance 6 V VIN = 0V 50 µA VIN = VDD 100 µA IOL = 8mA 0.4 V IOH = -8mA 2.4 V Unloaded outputs 15 mA 23 Ω 5. CLKIN input has a threshold voltage of VDD/2 6. Parameter is guaranteed by design and characterization. Not 100% tested in production. Switching Characteristics Parameter Test Conditions Max Unit 20 50 MHz 30pF load 20 50 MHz Measured at VDD/2 40 60 % Measured between 0.8V and 2.0V 2.5 nS Measured between 2.0V and 0.8V 2.5 nS All outputs equally loaded 250 pS Measured at VDD /2 ±350 pS 700 pS ±200 pS 1.0 mS Input Frequency Output Frequency Duty Cycle 7,8 = (t2 / t1) * 100 Output Rise Time Output Fall Time 7, 8 7, 8 Output-to-output skew 7, 8 Delay, CLKIN Rising Edge to CLKOUT Rising Edge 8 Device-to-Device Skew Cycle-to-Cycle Jitter PLL Lock Time Notes: 8 7, 8 8 Measured at VDD/2 on the CLKOUT pins of the device Loaded outputs Stable power supply, valid clock presented on CLKIN pin 7. All parameters specified with 30pF loaded outputs. 8. Parameter is guaranteed by design and characterization. Not 100% tested in production. Rev. 1 | Page 6 of 11 | www.onsemi.com Min Typ 50 P3P623S05A/B and P3P623S09A/B Switching Waveforms Duty Cycle Timing t1 t2 VDD/2 VDD/2 VDD/2 OUTPUT All Outputs Rise/Fall Time 2V 2V 0.8V 0.8V OUTPUT t3 t4 Output - Output Skew VDD/2 OUTPUT VDD/2 OUTPUT t5 Input - Output Propagation Delay VDD/2 INPUT VDD/2 OUTPUT t6 Rev. 1 | Page 7 of 11 | www.onsemi.com P3P623S05A/B and P3P623S09A/B Device - Device Skew VDD/2 CLKOUT, Device 1 VDD/2 CLKOUT, Device 2 t7 Input - Output Skew Input Test Circuit Timing-Safe™ Output +3.3V VDD 0.1uF TSKEW - TSKEW+ OUTPUT +3.3V LOAD VDD GND One clock cycle N=1 0.1uF TSKEW represents input-output skew when spread spectrum is ON For example, TSKEW = ± 0.125 for an Input clock12MHz, translates in to (1/12MHz) * 0.125=10.41nS Typical example of Timing-Safe™ waveform Input Input Timing-Safe™ CLKOUT CLKOUT with SSOFF Rev. 1 | Page 8 of 11 | www.onsemi.com CLK P3P623S05A/B and P3P623S09A/B Package Information 8-lead TSSOP (4.40-MM Body) H E D A2 A e θ C A1 L B Dimensions Symbol Inches Min Millimeters Max A Min Max 0.043 1.10 A1 0.002 0.006 0.05 0.15 A2 0.033 0.037 0.85 0.95 B 0.008 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 D 0.114 0.122 2.90 3.10 E 0.169 0.177 4.30 4.50 e 0.026 BSC 0.65 BSC H 0.252 BSC 6.40 BSC L 0.020 0.028 θ 0° 8° 0.50 0.70 0° 8° Rev. 1 | Page 9 of 11 | www.onsemi.com P3P623S05A/B and P3P623S09A/B 16-lead TSSOP (4.40-MM Body) 1 8 PIN 1 ID E 16 A A2 e A1 Seating Plane C θ D 9 H B L D Dimensions Symbol Inches Min Millimeters Max A Min Max 0.043 1.20 A1 0.002 0.006 0.05 0.15 A2 0.031 0.041 0.80 1.05 B 0.007 0.012 0.19 0.30 C 0.004 0.008 0.09 0.20 D 0.193 0.201 4.90 5.10 E 0.169 0.177 4.30 4.50 e 0.026 BSC 0.65 BSC H 0.252 BSC 6.40 BSC L 0.020 0.030 θ 0° 8° Rev. 1 | Page 10 of 11 | www.onsemi.com 0.50 0.75 0° 8° P3P623S05A/B and P3P623S09A/B Ordering Code Ordering Code P3P623S05BG-08TR Marking ADQ Package Type Temperature 8-pin 4.4-mm TSSOP – Tape & Reel, Green 0°C to +70° A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb-free ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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