385 MHz BW IF Diversity Receiver AD6674 Data Sheet FEATURES APPLICATIONS JESD204B (Subclass 1) coded serial digital outputs In band SFDR = 83 dBFS at 340 MHz (750 MSPS) In band SNR = 66.7 dBFS at 340 MHz (750 MSPS) 1.4 W total power per channel at 750 MSPS (default settings) Noise density = −153 dBFS/Hz at 750 MSPS 1.25 V, 2.5 V, and 3.3 V dc supply operation Flexible input range AD6674-750 and AD6674-1000 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal) AD6674-500 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) 95 dB channel isolation/crosstalk Amplitude detect bits for efficient automatic gain control (AGC) implementation Noise shaping requantizer (NSR) option for main receiver function Variable dynamic range (VDR) option for digital predistortion (DPD) function 2 integrated wideband digital processors per channel 12-bit numerically controlled oscillator (NCO), up to 4 cascaded half-band filters Differential clock inputs Integer clock divide by 1, 2, 4, or 8 Energy saving power-down modes Flexible JESD204B lane configurations Small signal dither Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers GENERAL DESCRIPTION The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. FUNCTIONAL BLOCK DIAGRAM AVDD1 (1.25V) AVDD2 (2.5V) AVDD3 (3.3V) AVDD1_SR (1.25V) DVDD (1.25V) DRVDD (1.25V) SPIVDD (1.8V TO 3.3V) VIN+B VIN–B ADC DIGITALDOWN DOWNCONVERSION CONVERSION DIGITAL DIGITAL DOWN CONVERSION DIGITAL DOWNCONVERSION (×4) (×4) (×4) (×4) NOISESHAPING SHAPINGREQUANTIZER REQUANTIZER NOISE (×2) (×2) VARIABLEDYNAMIC DYNAMICRANGE RANGE VARIABLE (×2) (×2) TX OUTPUTS SIGNAL MONITOR DATA ROUTER MUX FD_B FAST DETECT FD_A SIGNAL PROCESSING ADC JESD204B HIGH SPEED SERIALIZER BUFFER VIN+A VIN–A 4 SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± BUFFER CLK+ CLK– CLOCK GENERATION FAST DETECT JESD204B SUBCLASS 1 CONTROL SIGNAL MONITOR PDWN/ STBY SPI CONTROL ÷2 ÷4 ÷8 AD6674 AGND SYSREF± SYNCINB± SDIO SCLK CSB DGND DRGND 12400-001 V_1P0 Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD6674 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Numerically Controlled Oscillator .......................................... 44 Applications ....................................................................................... 1 FIR Filters ........................................................................................ 46 General Description ......................................................................... 1 General Description ................................................................... 46 Functional Block Diagram .............................................................. 1 Half-Band Filters ........................................................................ 47 Revision History ............................................................................... 3 DDC Gain Stage ......................................................................... 48 Product Highlights ........................................................................... 4 DDC Complex to Real Conversion ......................................... 48 Specifications..................................................................................... 5 DDC Example Configurations ................................................. 49 DC Specifications ......................................................................... 5 Noise Shaping Requantizer (NSR) ............................................... 53 AC Specifications.......................................................................... 6 Decimating Half-Band Filter .................................................... 53 Digital Specifications ................................................................... 8 NSR Overview ............................................................................ 53 Switching Specifications .............................................................. 9 Variable Dynamic Range (VDR) .................................................. 56 Timing Specifications .................................................................. 9 VDR Real Mode.......................................................................... 57 Absolute Maximum Ratings .......................................................... 11 VDR Complex Mode ................................................................. 57 Thermal Characteristics ............................................................ 11 Digital Outputs ............................................................................... 59 ESD Caution ................................................................................ 11 Introduction to JESD204B Interface ........................................ 59 Pin Configuration and Function Descriptions ........................... 12 JESD204B Overview .................................................................. 59 Typical Performance Characteristics ........................................... 14 Functional Overview ................................................................. 60 AD6674-1000 .............................................................................. 14 JESD204B Link Establishment ................................................. 60 AD6674-750 ................................................................................ 17 Physical Layer (Driver) Outputs .............................................. 62 AD6674-500 ................................................................................ 20 JESD204B Tx Converter Mapping ........................................... 64 Equivalent Circuits ......................................................................... 23 Configuring the JESD204B Link .............................................. 64 Theory of Operation ...................................................................... 25 Multichip Synchronization............................................................ 68 ADC Architecture ...................................................................... 25 SYSREF± Setup/Hold Window Monitor ................................. 70 Analog Input Considerations.................................................... 25 Test Modes ....................................................................................... 72 Voltage Reference ....................................................................... 30 ADC Test Modes ........................................................................ 72 Clock Input Considerations ...................................................... 31 JESD204B Block Test Modes .................................................... 72 Power-Down/Standby Mode..................................................... 32 Serial Port Interface (SPI) .............................................................. 75 Temperature Diode .................................................................... 32 Configuration Using the SPI ..................................................... 75 ADC Overrange and Fast Detect .................................................. 33 Hardware Interface ..................................................................... 75 ADC Overrange (OR) ................................................................ 33 SPI Accessible Features .............................................................. 75 Fast Threshold Detection (FD_A and FD_B) ........................ 33 Memory Map .................................................................................. 76 Signal Monitor ................................................................................ 34 Reading the Memory Map Register Table............................... 76 SPORT over JESD204B .............................................................. 34 Memory Map Register Table ..................................................... 77 Digital Downconverter (DDC) ..................................................... 37 Applications Information .............................................................. 90 DDC I/Q Input Selection .......................................................... 37 Power Supply Recommendations............................................. 90 DDC I/Q Output Selection ....................................................... 37 Exposed Pad Thermal Heat Slug Recommendations ............ 90 DDC General Description ........................................................ 37 AVDD1_SR (Pin 57) and AGND (Pin 56, Pin 60) ................ 90 Frequency Translation ................................................................... 43 Outline Dimensions ....................................................................... 91 General Description ................................................................... 43 Ordering Guide .......................................................................... 91 DDC NCO + Mixer Loss and SFDR ........................................ 44 Rev. B | Page 2 of 91 Data Sheet AD6674 REVISION HISTORY 4/15—Rev. A to Rev. B Changed SPIVDD Range from 1.8 V to 3.3 V to 1.8 V to 3.4 V ................................................................. Throughout Changes to General Description Section ....................................... 4 Changes to Table 1 ............................................................................ 5 Changes to Table 3 ............................................................................ 8 Changes to Figure 14 ......................................................................15 Change to Figure 78 Caption .........................................................27 Changes to Table 10 ........................................................................29 Changes to Clock Jitter Considerations Section .........................32 Added Figure 92; Renumbered Sequentially ...............................32 Changes to Digital Downconverter (DDC) Section ...................37 Changes to Table 17 ........................................................................46 Changes to Table 23 ........................................................................49 Changes to Figure 108 ....................................................................53 Changes to Figure 116 ....................................................................56 Changes to Figure 117 and VDR Complex Mode Section ........57 Changes to Table 45 ........................................................................79 12/14—Revision A: Initial Version Rev. B | Page 3 of 91 AD6674 Data Sheet The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and up to four half-band decimation filters. Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6674 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining a 9-bit output resolution. NSR is enabled by default on the AD6674. Each ADC output is also connected internally to a VDR block. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask (based on DPD applications) are passed unaltered. Inputs that violate this defined mask result in the reduction of the output resolution. indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. Besides the fast detect outputs, the AD6674 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC. Users can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of two-lane and four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins. The AD6674 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V capable 3-wire serial port interface (SPI). The AD6674 is available in a Pb-free, 64-lead LFCSP, specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent. With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed. For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. This mask is based on DPD applications and supports tunable real IF sampling, and zero IF or complex IF receive architectures. PRODUCT HIGHLIGHTS Operation of the AD6674 between the DDC, NSR, and VDR modes is selectable via SPI-programmable profiles. 4. In addition to the DDC blocks, the AD6674 has several functions that simplify the AGC function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect 5. 1. 2. 3. 6. 7. Rev. B | Page 4 of 91 Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible SPI controls various product features and functions to meet specific system requirements. Programmable fast overrange detection and signal monitoring. Programmable fast overrange detection. 9 mm × 9 mm 64-lead LFCSP. Data Sheet AD6674 SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, 1.0 V internal reference (VREF), AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Voltage INPUT REFERRED NOISE VREF = 1.0 V ANALOG INPUTS Differential Input Voltage Range (Internal VREF = 1.0 V) Common-Mode Voltage (VCM) Differential Input Capacitance 1 Analog Full Power Bandwidth POWER SUPPLY AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD IAVDD1 2 IAVDD22 IAVDD32 IAVDD1_SR2 IDVDD2 IDRVDD2, 3 L = 2 Mode 4 ISPIVDD Temp Full Full Full Full Full Full Full Min 14 AD6674-1000 Typ Max Guaranteed 0 +0.31 0 +0.23 −6 0 +6 1 +4.5 −0.7 ±0.5 +0.8 −5.7 ±2.5 +6.9 −0.31 Min AD6674-750 Typ Max Guaranteed 0 +0.42 0 +0.41 −6 0 +6 1 +5.2 −0.6 ±0.5 +0.8 −3.4 ±2.5 +5.0 −0.51 AD6674-500 Min Typ Max 14 Unit Bits Guaranteed 0 +0.3 0 +0.3 −6 0 +6 1 +5.1 −0.6 ±0.5 +0.7 −4.5 ±2.5 +5.0 % FSR % FSR % FSR % FSR LSB LSB −0.3 Full Full −14 ±13.8 −9 −57 −3 ±25 ppm/°C ppm/°C Full 1.0 1.0 1.0 V 25°C 2.63 2.48 2.06 LSB rms Full 1.46 Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25°C Full 1.70 1.94 1.46 2.05 1.5 2 1.22 2.44 3.2 1.22 1.22 1.22 1.8 1.25 2.50 3.3 1.25 1.25 1.25 685 595 125 16 263 200 N/A 5 5 1.70 1.94 1.46 2.05 1.5 2 1.28 2.56 3.4 1.28 1.28 1.28 3.4 721 677 142 18 292 225 6 Rev. B | Page 5 of 91 1.22 2.44 3.2 1.22 1.22 1.22 1.8 1.25 2.50 3.3 1.25 1.25 1.25 545 460 125 10 165 190 N/A5 5 2.06 2.06 2.05 1.5 2 1.28 2.56 3.4 1.28 1.28 1.28 3.4 623 572 142 17 217 258 7.0 1.22 2.44 3.2 1.22 1.22 1.22 1.8 1.25 2.50 3.3 1.25 1.25 1.25 427 398 89 10 139 182 140 5 V p-p V pF GHz 1.28 2.56 3.4 1.28 1.28 1.28 3.4 466 463 100 18 183 237 7 V V V V V V V mA mA mA mA mA mA mA mA AD6674 Parameter POWER CONSUMPTION Total Power Dissipation2 Power-Down Dissipation Standby 6 Data Sheet Temp Min AD6674-1000 Typ Max Full Full Full 3.3 835 1.4 Min 3.6 AD6674-750 Typ Max 2.8 835 1.4 AD6674-500 Min Typ Max 3.1 2.24 710 1.2 2.5 Unit W mW W Differential capacitance is measured between the VIN+x and VIN−x pins (x = A, B). Measured with a low input frequency, full-scale sine wave. All lanes running. Power dissipation on DRVDD changes with lane rate and number of lanes used. 4 L is the number of lanes per converter device (lanes per link). 5 N/A means not applicable. At the maximum sample rate, it is not applicable to use L = 2 mode on the JESD204B output interface because this exceeds the maximum lane rate of 12.5 Gbps. L = 2 mode is supported when the equation ((M × N΄ × (10/8) × fOUT)/L) results in a lane rate that is ≤12.5 Gbps. fOUT is the output sample rate and is denoted by fS/DCM, where DCM = decimation ratio. 6 Can be controlled by the SPI. 1 2 3 AC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, 1.0 V internal reference, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 2. Parameter 1 ANALOG INPUT FULL SCALE NOISE DENSITY 2 SIGNAL-TO-NOISE RATIO (SNR) 3 VDR Mode (Input Mask Not Triggered) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz NSR Enabled (21% BW Mode) 4 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz NSR Enabled (28% BW Mode)4 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz Temp Full Full 25°C Full 25°C 25°C 25°C 25°C 25°C AD6674-1000 Min Typ Max 1.7 −154 65.1 67.2 66.6 65.3 64.0 62.4 61.4 57.0 AD6674-750 Min Typ Max 1.7 −153 65.8 67.3 67.1 66.7 66.2 64.3 63.6 59.9 AD6674-500 Min 67.8 2.06 −153 Unit V p-p dBFS/Hz 69.2 69.0 68.6 68.0 64.4 63.8 60.5 dBFS dBFS dBFS dBFS dBFS dBFS dBFS Typ Max 25°C 25°C 25°C 25°C 25°C 25°C 25°C 73.8 73.6 73.5 71.9 69.0 68.2 63.6 74.0 73.8 73.7 72.2 71.4 71.0 66.6 75.2 75.2 74.8 74.2 70.3 69.3 65.3 dBFS dBFS dBFS dBFS dBFS dBFS dBFS 25°C 25°C 25°C 25°C 25°C 25°C 25°C 72.4 72.2 72.1 70.5 67.0 66.3 61.9 72.8 72.6 72.5 71.0 70.0 68.9 65.1 72.4 72.4 72.1 71.9 68.3 67.7 64.1 dBFS dBFS dBFS dBFS dBFS dBFS dBFS Rev. B | Page 6 of 91 Data Sheet Parameter 1 SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)3 VDR Mode (Input Mask Not Triggered) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz EFFECTIVE NUMBER OF BITS (ENOB)3 VDR Mode (Input Mask Not Triggered) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz SPURIOUS FREE DYNAMIC RANGE (SFDR), SECOND OR THIRD HARMONIC3 VDR Mode (Input Mask Not Triggered) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz WORST OTHER (EXCLUDING SECOND OR THIRD HARMONIC)3 VDR Mode (Input Mask Not Triggered) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)3 AIN1 AND AIN2 = −7.0 dBFS fIN1 = 185 MHz, fIN2 = 188 MHz fIN1 = 338 MHz, fIN2 = 341 MHz CROSSTALK 5 FULL POWER BANDWIDTH AD6674 Temp 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C AD6674-1000 Min Typ Max 65.0 10.5 75 −81 67.1 66.4 65.2 63.8 62.1 61.1 56.0 10.8 10.7 10.5 10.3 10.0 9.8 9.0 88 85 85 82 82 80 68 −95 −94 −88 −86 −81 −82 −75 −87 −88 95 2 AD6674-750 Min Typ Max 65.6 10.4 75 −81 67.1 67.0 66.5 66.1 64.1 63.1 59.0 10.8 10.8 10.7 10.5 10.4 10.2 9.5 85 86 83 82 80 76 68 −95 −89 −83 −82 −85 −83 −80 −85 −83 95 2 AD6674-500 Min 67.6 10.8 80 −82 Typ Max 69.0 68.8 68.4 67.9 64.2 63.6 60.3 dBFS dBFS dBFS dBFS dBFS dBFS dBFS 11.2 11.1 11.1 11.0 10.4 10.3 9.7 Bits Bits Bits Bits Bits Bits Bits 83 88 83 81 80 75 70 dBFS dBFS dBFS dBFS dBFS dBFS dBFS −95 −95 −93 −93 −88 −89 −84 dBFS dBFS dBFS dBFS dBFS dBFS dBFS −88 −88 95 2 dBFS dBFS dB GHz See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Noise density is measured at low analog input frequency (30 MHz). See Table 10 for recommended device settings to achieve stated typical performance. 4 When NSR is activated on the AD6674-750 and AD6674-1000, the decimating half-band filter is also enabled. 5 Crosstalk is measured at 185 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. 1 2 3 Rev. B | Page 7 of 91 Unit AD6674 Data Sheet DIGITAL SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, 1.0 V internal reference, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 3. Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance SYSTEM REFERENCE INPUTS (SYSREF+, SYSREF−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Differential) LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance LOGIC OUTPUT (SDIO) Logic Compliance Logic 1 Voltage (IOH = 800 µA) Logic 0 Voltage (IOL = 50 µA) SYNC INPUTS (SYNCINB+, SYNCINB–) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC OUTPUTS (FD_A, FD_B) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 3) Logic Compliance Differential Output Voltage Output Common-Mode Voltage (VCM) AC-Coupled Short-Circuit Current (IDSHORT) Differential Return Loss (RLDIFF) 1 Common-Mode Return Loss (RLCM)1 Differential Termination Impedance 1 Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Min 600 Typ LVDS/LVPECL 1200 0.85 35 Max Unit 1800 mV p-p V kΩ pF 2.5 400 0.6 LVDS/LVPECL 1200 0.85 35 1800 2.0 2.5 mV p-p V kΩ pF CMOS 0.8 × SPIVDD 0 V V kΩ 30 CMOS 0.8 × SPIVDD 0 400 0.6 V V LVDS/LVPECL/CMOS 1200 0.85 35 1800 2.0 2.5 mV p-p V kΩ pF CMOS 0.8 × SPIVDD 0 V V kΩ 30 Full Full 360 CML 770 mV p-p 25°C 25°C 25°C 25°C Full 0 −100 8 6 80 1.8 +100 V mA dB dB Ω Differential and common-mode return loss is measured from 100 MHz to 0.75 × baud rate. Rev. B | Page 8 of 91 100 120 Data Sheet AD6674 SWITCHING SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, 1.0 V internal reference, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 4. Parameter CLOCK Clock Rate (at CLK+/CLK− Pins) Maximum Sample Rate 1 Minimum Sample Rate 2 Clock Pulse Width High Clock Pulse Width Low OUTPUT PARAMETERS Unit Interval (UI) 3 Rise Time (tR) (20% to 80% into 100 Ω Load) Fall Time (tF) (20% to 80% into 100 Ω Load) PLL Lock Time Data Rate per Channel (NRZ) 4 LATENCY Pipeline Latency Fast Detect Latency Wake-Up Time (Standby) 5 Wake-Up Time (Power-Down)5 APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Out-of-Range Recovery Time Temp AD6674-1000 Min Typ Max Min Full Full Full Full Full 0.3 1000 300 500 500 0.3 750 300 666.67 666.67 4 AD6674-750 Typ Max 4 AD6674-500 Min Typ Max Unit 0.3 500 300 1000 1000 GHz MSPS MSPS ps ps 4 Full 25°C 100 32 133.33 32 200 32 ps ps 25°C 32 32 32 ps 25°C 25°C 3.125 2 10 Full Full 25°C 25°C 75 Full Full Full 530 55 1 12.5 3.125 2 7.5 12.5 3.125 75 28 1 2 5 75 28 1 4 12.5 28 1 4 530 55 1 4 530 55 1 ms Gbps Clock cycles Clock cycles ms ms ps fs rms Clock cycles The maximum sample rate is the clock rate after the divider. The minimum sample rate operates at 300 MSPS with L = 2 or L = 1. 3 Baud rate = 1/UI. A subset of this range can be supported. 4 At full baud rate (12.5 Gbps), each ADC outputs data on two differential pair lanes. 5 Wake-up time is defined as the time required to return to normal operation from power-down mode or standby mode. 1 2 TIMING SPECIFICATIONS Table 5. Parameter CLK± to SYSREF± TIMING REQUIREMENTS tSU_SR tH_SR SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Test Conditions/Comments Device clock to SYSREF± setup time Device clock to SYSREF± hold time See Figure 4 Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK is in a logic high state Minimum period that SCLK is in a logic low state Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 4) Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 4) Rev. B | Page 9 of 91 Min Typ 117 −96 Max Unit ps ps 2 2 40 2 2 10 10 10 ns ns ns ns ns ns ns ns 10 ns AD6674 Data Sheet Timing Diagrams APERTURE DELAY ANALOG INPUT SIGNAL SAMPLE N N – 54 N+1 N – 55 N – 53 N – 52 N–1 N – 51 CLK– CLK+ CLK– CLK+ SERDOUT0– A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 MSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 LSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 MSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 LSB SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SAMPLE N – 55 ENCODED INTO 1 8-BIT/10-BIT SYMBOL SAMPLE N – 54 ENCODED INTO 1 8-BIT/10-BIT SYMBOL 12400-002 SERDOUT3+ SAMPLE N – 53 ENCODED INTO 1 8-BIT/10-BIT SYMBOL Figure 2. Data Output Timing (VDR Mode; L = 4; M = 2; F = 1) CLK– CLK+ tSU_SR tH_SR 12400-003 SYSREF– SYSREF+ Figure 3. SYSREF± Setup and Hold Timing tHIGH tDS tS tCLK tDH tH tLOW CSB SDIO DON’T CARE DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 D5 Figure 4. Serial Port Interface Timing Diagram Rev. B | Page 10 of 91 D4 D3 D2 D1 D0 DON’T CARE 12400-004 SCLK DON’T CARE Data Sheet AD6674 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Electrical AVDD1 to AGND AVDD1_SR to AGND AVDD2 to AGND AVDD3 to AGND DVDD to DGND DRVDD to DRGND SPIVDD to AGND AGND to DRGND VIN±x to AGND SCLK, SDIO, CSB to AGND PDWN/STBY to AGND Operating Temperature Range Junction Temperature Range Storage Temperature Range (Ambient) Rating 1.32 V 1.32 V 2.75 V 3.63 V 1.32 V 1.32 V 3.63 V −0.3 V to +0.3 V 3.2 V −0.3 V to SPIVDD + 0.3 V −0.3 V to SPIVDD + 0.3 V −40°C to +85°C −40°C to +115°C −60°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Typical θJA, ΨJB, and θJC are specified vs. the number of printed circuit board (PCB) layers in different airflow velocities (in m/sec). Airflow increases heat dissipation, effectively reducing θJA and ΨJB. In addition, metal in direct contact with the package leads and exposed pad from metal traces, through holes, ground, and power planes reduces the θJA. Thermal performance for actual applications requires careful inspection of the conditions in an application. The use of appropriate thermal management techniques is recommended to ensure that the maximum junction temperature does not exceed the limits shown in Table 6. Table 7. Thermal Resistance Values PCB Type JEDEC 2s2p Board Airflow Velocity (m/sec) 0.0 1.0 2.5 θJA 17.81, 2 15.61, 2 15.01, 2 ΨJB 6.31, 3 5.91, 3 5.71, 3 θJC_TOP 4.71, 5 N/A4 N/A4 θJC_BOT 1.21, 5 Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per JEDEC JESD51-8 (still air). 4 N/A means not applicable. 5 Per MIL-STD 883, Method 1012.1. 1 2 ESD CAUTION Rev. B | Page 11 of 91 Unit °C/W °C/W °C/W AD6674 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD1 AVDD2 AVDD2 AVDD1 AGND SYSREF– SYSREF+ AVDD1_SR AGND AVDD1 CLK– CLK+ AVDD1 AVDD2 AVDD2 AVDD1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD6674 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVDD1 AVDD1 AVDD2 AVDD3 VIN–B VIN+B AVDD3 AVDD2 AVDD2 AVDD2 SPIVDD CSB SCLK SDIO DVDD DGND NOTES 1. EXPOSED PAD. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE GROUND REFENCE FOR AVDDx. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 12400-005 FD_A DRGND DRVDD SYNCINB– SYNCINB+ SERDOUT0– SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SERDOUT3+ DRVDD DRGND FD_B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD1 AVDD1 AVDD2 AVDD3 VIN–A VIN+A AVDD3 AVDD2 AVDD2 AVDD2 AVDD2 V_1P0 SPIVDD PDWN/STBY DVDD DGND Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. Power Supplies 0 Mnemonic Type Description EPAD Ground 1, 2, 47, 48, 49, 52, 55, 61, 64 3, 8, 9, 10, 11, 39, 40, 41, 46, 50, 51, 62, 63 4, 7, 42, 45 13, 38 15, 34 16, 33 18, 31 19, 30 56, 60 57 Analog 5, 6 12 AVDD1 Supply Exposed Pad. The exposed thermal pad on the bottom of the package provides the ground reference for AVDDx. This exposed pad must be connected to ground for proper operation. See the Applications Information section for more details. Analog Power Supply (1.25 V Nominal). AVDD2 Supply Analog Power Supply (2.5 V Nominal). AVDD3 SPIVDD DVDD DGND DRGND DRVDD AGND 1 AVDD1_SR1 Supply Supply Supply Ground Ground Supply Ground Supply Analog Power Supply (3.3 V Nominal). Digital Power Supply for SPI (1.8 V to 3.4 V). Digital Power Supply (1.25 V Nominal). Ground Reference for DVDD. Ground Reference for DRVDD. Digital Driver Power Supply (1.25 V Nominal). Ground Reference for SYSREF±. Analog Power Supply for SYSREF± (1.25 V Nominal). VIN−A, VIN+A V_1P0 Input Input/DNC VIN+B, VIN−B CLK+, CLK− Input Input ADC A Analog Input Complement/True. 1.0 V Reference Voltage Input/Do Not Connect. This pin is configurable through the SPI as a no connect or an input. Do not connect this pin if using the internal reference. This pin requires a 1.0 V reference voltage input if using an external voltage reference source. ADC B Analog Input True/Complement. Clock Input True/Complement. 43, 44 53, 54 Rev. B | Page 12 of 91 Data Sheet Pin No. CMOS Outputs 17, 32 Digital Inputs 20, 21 58, 59 Data Outputs 22, 23 24, 25 26, 27 28, 29 Device Under Test (DUT) Controls 14 35 36 37 1 AD6674 Mnemonic Type Description FD_A, FD_B Output Fast Detect Outputs for Channel A and Channel B. SYNCINB−, SYNCINB+ SYSREF+, SYSREF− Input Active Low JESD204B LVDS Sync Input True/Complement. Input Active Low JESD204B LVDS System Reference Input True/Complement. Output Lane 0 Output Data Complement/True. Output Lane 1 Output Data Complement/True. Output Lane 2 Output Data Complement/True. Output Lane 3 Output Data Complement/True. PDWN/STBY Input SDIO SCLK CSB Input/Output Input Input Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby. SPI Serial Data Input/Output. SPI Serial Clock. SPI Chip Select (Active Low). SERDOUT0−, SERDOUT0+ SERDOUT1−, SERDOUT1+ SERDOUT2−, SERDOUT2+ SERDOUT3−, SERDOUT3+ To ensure proper ADC operation, connect AVDD1_SR and AGND separately from the AVDD1 and EPAD connection. For more information, see the Applications Information section. Rev. B | Page 13 of 91 AD6674 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AD6674-1000 AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, AIN = −1.0 dBFS, VDR mode (no violation of VDR mask), clock divider = 2, otherwise default SPI settings, TA = 25°C, 128k FFT sample, unless otherwise noted. See Table 10 for recommended settings. AIN = –1dBFS SNR = 67.2dBFS ENOB = 10.8 BITS SFDR = 88dBFS BUFFER CONTROL 1 = 1.5× –10 –30 AMPLITUDE (dBFS) –50 –70 –90 –110 –50 –70 –90 –110 0 100 200 300 400 500 FREQUENCY (MHz) –130 12400-100 –130 0 100 200 300 400 500 FREQUENCY (MHz) Figure 6. Single Tone FFT with fIN = 10.3 MHz 12400-103 AMPLITUDE (dBFS) –30 AIN = –1dBFS SNR = 64.0dBFS ENOB = 10.3 BITS SFDR = 82dBFS BUFFER CONTROL 1 = 3.0× –10 Figure 9. Single Tone FFT with fIN = 450.3 MHz 0 AIN = –1dBFS SNR = 66.6dBFS ENOB = 10.7 BITS SFDR = 85dBFS BUFFER CONTROL 1 = 3.0× –10 –20 AMPLITUDE (dBFS) –50 –70 –90 –40 –60 –80 0 100 200 300 400 500 FREQUENCY (MHz) –120 12400-101 –130 0 100 200 0 AIN = –1dBFS SNR = 65.3dBFS ENOB = 10.5 BITS SFDR = 85dBFS BUFFER CONTROL 1 = 3.0× 500 AIN = –1dBFS SNR = 60.5dBFS ENOB = 9.9 BITS SFDR = 80dBFS BUFFER CONTROL 1 = 6.0× AMPLITUDE (dBFS) –20 –50 –70 –90 –40 –60 –80 –100 –110 –130 0 100 200 300 400 FREQUENCY (MHz) 500 12400-102 AMPLITUDE (dBFS) –30 400 Figure 10. Single Tone FFT with fIN = 765.3 MHz Figure 7. Single Tone FFT with fIN = 170.3 MHz –10 300 FREQUENCY (MHz) 12400-104 –100 –110 –120 0 100 200 300 400 FREQUENCY (MHz) Figure 11. Single Tone FFT with fIN = 985.3 MHz Figure 8. Single Tone FFT with fIN = 340.3 MHz Rev. B | Page 14 of 91 500 12400-105 AMPLITUDE (dBFS) –30 AIN = –1dBFS SNR = 61.5dBFS ENOB = 10.1 BITS SFDR = 82dBFS BUFFER CONTROL 1 = 6.0× Data Sheet 90 0 AIN = –1dBFS SNR = 59.8BFS ENOB = 9.6 BITS SFDR = 79dBFS BUFFER CONTROL 1 = 8.0× –20 85 SFDR (dBFS) –40 SNR/SFDR (dBFS) AMPLITUDE (dBFS) AD6674 –60 –80 80 75 70 SNR (dBFS) –100 0 100 200 300 400 500 FREQUENCY (MHz) 60 700 12400-107 –120 900 950 1000 1050 1100 90 1.5×, SFDR 80 3.0×, SFDR 70 –40 SNR/SFDR (dBFS) AMPLITUDE (dBFS) 850 Figure 15. SNR/SFDR vs. Sample Rate (fS), fIN = 170.3 MHz; Buffer Control 1 = 3.0× AIN = –1dBFS SNR = 57.7dBFS ENOB = 9.2 BITS SFDR = 70dBFS BUFFER CONTROL 1 = 8.0× –20 800 SAMPLE RATE (MHz) Figure 12. Single Tone FFT with fIN = 1293.3 MHz 0 750 12400-201 65 –60 –80 60 50 3.0×, SNR 40 30 1.5×, SNR 20 –100 100 200 300 400 500 FREQUENCY (MHz) 0 10.3 12400-108 0 100.3 170.3 225.3 302.3 341.3 403.3 453.3 502.3 ANALOG INPUT FREQUENCY (MHz) Figure 13. Single Tone FFT with fIN = 1725.3 MHz Figure 16. SNR/SFDR vs. Analog Input Frequency (fIN); fIN < 500 MHz; Buffer Control 1 = 1.5× and 3.0× 0 0 AIN = –1dBFS SNR = 57.0dBFS ENOB = 9.1 BITS SFDR = 69dBFS BUFFER CURRENT = 6.0× –20 AIN1 AND AIN2 = –7dBFS SFDR = 87dBFS IMD2 = 93dBFS IMD3 = 87dBFS BUFFER CONTROL 1 = 3.0× –20 AMPLITUDE (dBFS) –40 –60 –80 –100 –40 –60 –80 –120 0 100 200 300 FREQUENCY (MHz) 400 500 –120 0 100 200 300 400 FREQUENCY (MHz) Figure 17. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz Figure 14. Single Tone FFT with fIN = 1950.3 MHz Rev. B | Page 15 of 91 500 12400-205 –100 12400-109 AMPLITUDE (dBFS) 63.3 12400-203 10 –120 AD6674 Data Sheet 0 110 AIN1 AND AIN2 = –7dBFS SFDR = 88dBFS IMD2 = 93dBFS IMD3 = 88dBFS BUFFER CONTROL 1 = 4.5× 100 SFDR (dBFS) 90 80 SNR (dBFS) 70 –40 SNR/SFDR (dB) AMPLITUDE (dBFS) –20 –60 –80 60 50 SFDR (dBc) 40 SNR (dBc) 30 20 10 –100 0 –120 100 200 300 400 –20 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 500 FREQUENCY (MHz) 12400-206 Figure 21. SNR/SFDR vs. Input Amplitude (AIN), fIN = 170.3 MHz 20 90 0 80 SNR/SFDR (dBFS) –40 IMD3 (dBc) –60 –80 SNR 60 50 40 30 SFDR (dBFS) –100 20 –120 IMD3 (dBFS) –140 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 INPUT AMPLITUDE (dBFS) 10 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) Figure 22. SNR/SFDR vs. Temperature, fIN = 170.3 MHz Figure 19. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184 MHz and fIN2 = 187 MHz 3.5 20 0 3.4 –20 SFDR (dBc) 3.3 –40 POWER (W) SNR/SFDR (dBc AND dBFS) SFDR 70 SFDR (dBc) 12400-207 SFDR/IMD3 (dBc AND dBFS) Figure 18. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz –20 0 INPUT AMPLITUDE (dBFS) 12400-210 0 12400-209 –10 IMD3 (dBc) –60 –80 L=4 M=2 F=1 3.2 3.1 SFDR (dBFS) –100 3.0 IMD3 (dBFS) Figure 20. Two-Tone IMD3/SFDR vs. Input Amplitude (AIN) with fIN1 = 338 MHz and fIN2 = 341 MHz Rev. B | Page 16 of 91 1080 1060 1040 1020 980 1000 960 940 920 900 860 880 840 820 800 760 780 740 720 SAMPLE RATE (MSPS) Figure 23. Power Dissipation vs. Sampel Rate (fS) (Default SPI) 12400-524 INPUT AMPLITUDE (dBFS) 2.9 700 –140 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 12400-208 –120 Data Sheet AD6674 AD6674-750 AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, AIN = −1.0 dBFS, VDR mode (no violation of VDR mask), clock divider = 2, otherwise default SPI settings, TA = 25°C, 128k FFT sample, unless otherwise noted. See Table 10 for recommended settings. –20 AMPLITUDE (dBFS) –40 –60 –80 –40 –60 –80 –100 –100 –120 –120 –140 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 FREQUENCY (MHz) AIN = −1dBFS SNR = 66.2dBFS ENOB = 10.5 BITS SFDR = 82dBFS BUFFER CONTROL 1 = 4.0× –20 –140 12400-219 0 FREQUENCY (MHz) Figure 24. Single Tone FFT with fIN = 10.3 MHz 0 0 AIN = −1dBFS SNR = 64.2dBFS ENOB = 10.3 BITS SFDR = 80dBFS BUFFER CONTROL 1 = 8.5× –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –40 –60 –80 –100 –120 –120 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 FREQUENCY (MHz) –140 12400-220 –140 0 FREQUENCY (MHz) Figure 25. Single Tone FFT with fIN = 170.3 MHz 0 0 AIN = −1dBFS SNR = 63.5dBFS ENOB = 10.2 BITS SFDR = 76dBFS BUFFER CONTROL 1 = 8.5× –20 AMPLITUDE (dBFS) –40 –60 –80 –100 –40 –60 –80 –100 –120 –120 –140 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 FREQUENCY (MHz) 12400-221 AMPLITUDE (dBFS) Figure 28. Single Tone FFT with fIN = 765.3 MHz AIN = −1dBFS SNR = 66.7dBFS ENOB = 10.6 BITS SFDR = 83dBFS BUFFER CONTROL 1 = 3.0× –20 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 12400-229 AMPLITUDE (dBFS) Figure 27. Single Tone FFT with fIN = 450.3 MHz AIN = −1dBFS SNR = 67.1dBFS ENOB = 10.7 BITS SFDR = 86dBFS BUFFER CONTROL 1 = 2.0× –20 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 Figure 26. Single Tone FFT with fIN = 340.3 MHz –140 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 FREQUENCY (MHz) Figure 29. Single Tone FFT with fIN = 985.3 MHz Rev. B | Page 17 of 91 12400-230 AMPLITUDE (dBFS) 0 AIN = −1dBFS SNR = 67.3dBFS ENOB = 10.7 BITS SFDR = 85dBFS BUFFER CONTROL 1 = 1.5× 12400-222 0 AD6674 Data Sheet 0 –20 90 –40 SNR/SFDR (dBFS) AMPLITUDE (dBFS) 95 AIN = −1dBFS SNR = 62.3dBFS ENOB = 9.8 BITS SFDR = 68dBFS BUFFER CONTROL 1 = 8.5× –60 –80 –100 85 SFDR 80 75 70 –120 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 FREQUENCY (MHz) 65 525 12400-231 0 625 650 675 700 725 750 775 800 100 95 90 –40 SNR/SFDR (dBFS) AMPLITUDE (dBFS) 600 Figure 33. SNR/SFDR vs. Sample Rate (fS); fIN = 170.3 MHz, Buffer Control 1 = 3.0× AIN = −1dBFS SNR = 60.5dBFS ENOB = 9.6 BITS SFDR = 71dBFS BUFFER CONTROL 1 = 8.5× –20 575 SAMPLE RATE (MSPS) Figure 30. Single Tone FFT with fIN = 1310.3 MHz 0 550 12400-223 SNR –140 –60 –80 SFDR 85 80 75 –100 70 SNR –120 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 FREQUENCY (MHz) 60 0 AMPLITUDE (dBFS) –60 –80 350 400 450 500 –80 –120 –120 FREQUENCY (MHz) 300 –60 –100 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 250 –40 –100 0 200 AIN1 AND AIN2 = −7dBFS SFDR = 81dBFS IMD2 = 86dBc IMD3 = 81dBc BUFFER CONTROL 1 = 3.0× –20 12400-233 AMPLITUDE (dBFS) 0 –40 –140 150 Figure 34. SNR/SFDR vs. Analog Input Frequency (fIN); fIN < 500 MHz; Buffer Control 1 = 3.0× AIN = −1dBFS SNR = 59.8dBFS ENOB = 9.5 BITS SFDR = 68dBFS BUFFER CONTROL 1 = 8.5× –20 100 FREQUENCY (MHz) Figure 31. Single Tone FFT with fIN = 1710.3 MHz 0 50 –140 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 FREQUENCY (MHz) Figure 35. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz Figure 32. Single Tone FFT with fIN = 1950.3 MHz Rev. B | Page 18 of 91 12400-226 0 12400-232 –140 12400-225 65 Data Sheet SFDR (dBFS) 100 SNR/SFDR (dBc AND dBFS) SNR (dBc) 20 –120 0 INPUT AMPLITUDE (dBFS) Figure 36. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz 12400-430 –5 –10 –15 –25 –20 –65 –60 –70 –80 FREQUENCY (MHz) –75 0 –85 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 –90 0 12400-227 –140 Figure 39. SNR/SFDR vs. Input Amplitude (AIN), fIN = 170.3 MHz 95 0 –20 90 SFDR (dBc) SNR/SFDR (dBFS) –40 IMD3 (dBc) –60 –80 85 SFDR 80 75 SFDR (dBFS) 70 –100 SNR IMD3 (dBFS) 65 –40 12400-428 –120 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 INPUT AMPLITUDE (dBFS) –15 10 35 60 85 TEMPERATURE (°C) Figure 37. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184 MHz and fIN2 = 187 MHz 12400-228 SFDR/IMD3 (dBc AND dBFS) SFDR (dBc) 40 –35 –100 SNR (dBFS) 60 –30 –80 80 –45 –60 –40 –40 –50 –20 AMPLITUDE (dBFS) 120 AIN1 AND AIN2 = −7dBFS SFDR = 83dBFS IMD2 = 89dBc IMD3 = 83dBc BUFFER CONTROL 1 = 4.5× –55 0 AD6674 Figure 40. SNR/SFDR vs. Temperature, fIN = 170.3 MHz 3.0 2.9 SFDR (dBc) –20 2.8 IMD3 (dBc) POWER (W) –60 –80 –100 2.7 2.6 2.5 SFDR (dBFS) 2.4 –120 IMD3 (dBFS) –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 INPUT AMPLITUDE (dBFS) Figure 38. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 338 MHz and fIN2 = 341 MHz 2.3 500 550 600 650 700 750 SAMPLE RATE (MSPS) 800 850 12400-234 –40 12400-429 SFDR/IMD3 (dBc AND dBFS) 0 Figure 41. Power Dissipation vs. Sample Rate (fS); L = 4, M = 2, F = 1 for fS ≥ 625 MSPS and L= 2, M = 2, F = 2 for fS < 625 MSPS (Default SPI) Rev. B | Page 19 of 91 AD6674 Data Sheet AD6674-500 AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, AIN = −1.0 dBFS, VDR mode (no violation of VDR mask), clock divider = 2, otherwise default SPI settings, TA = 25°C, 128k FFT sample, unless otherwise noted. See Table 10 for recommended settings. 0 0 AIN = −1dBFS SNR = 68.9dBFS ENOB = 10.9 BITS SFDR = 83dBFS BUFFER CONTROL 1 = 2.0× –20 –20 –40 AMPLITUDE (dBFS) –40 –60 –80 –100 –60 –80 –100 0 25 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) –140 12400-432 –140 0 125 150 175 200 225 250 AIN = −1dBFS SNR = 64.7dBFS ENOB = 10.4 BITS SFDR = 80dBFS BUFFER CONTROL 1 = 5.0× –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –60 –80 –100 –120 0 25 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) –140 12400-433 –140 0 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) Figure 43. Single Tone FFT with fIN = 170.3 MHz Figure 46. Single Tone FFT with fIN = 765.3 MHz 0 0 AIN = −1dBFS SNR = 68.5dBFS ENOB = 10.9 BITS SFDR = 83dBFS BUFFER CONTROL 1 = 4.5× –20 25 12400-236 AMPLITUDE (dBFS) 100 0 –40 AIN = −1dBFS SNR = 64.0dBFS ENOB = 10.3 BITS SFDR = 76dBFS BUFFER CONTROL 1 = 5.0× –20 –40 AMPLITUDE (dBFS) –40 –60 –80 –100 –120 –60 –80 –100 –120 –140 0 25 50 75 100 125 150 175 200 FREQUENCY (MHz) 225 250 12400-434 AMPLITUDE (dBFS) 75 Figure 45. Single Tone FFT with fIN = 450.3 MHz AIN = −1dBFS SNR = 68.9dBFS ENOB = 11.0 BITS SFDR = 88dBFS BUFFER CONTROL 1 = 2.0× –20 50 FREQUENCY (MHz) Figure 42. Single Tone FFT with fIN = 10.3 MHz 0 25 12400-235 –120 –120 Figure 44. Single Tone FFT with fIN = 340.3 MHz –140 0 25 50 75 100 125 150 175 200 225 FREQUENCY (MHz) Figure 47. Single Tone FFT with fIN = 985.3 MHz Rev. B | Page 20 of 91 250 12400-237 AMPLITUDE (dBFS) AIN = −1dBFS SNR = 67.8dBFS ENOB = 10.8 BITS SFDR = 83dBFS BUFFER CONTROL 1 = 4.5× Data Sheet AD6674 90 0 AIN = −1dBFS SNR = 63.0dBFS ENOB = 10.0 BITS SFDR = 69dBFS BUFFER CONTROL 1 = 8.0× SFDR 85 SNR AND SFDR (dBFS) –20 –60 –80 –100 80 75 70 25 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) 60 300 310 320 330 340 350 360 370 380 390 400 410 420 430 440 450 460 470 480 490 500 520 530 540 550 560 570 580 590 0 12400-238 –140 SAMPLE RATE (MSPS) Figure 51. SNR/SFDR vs. Sample Rate (fS), fIN = 170.3 MHz; Buffer Control 1 = 2.0× Figure 48. Single Tone FFT with fIN = 1310.3 MHz 100 0 AIN = −1dBFS SNR = 61.5dBFS ENOB = 9.8 BITS SFDR = 69dBFS BUFFER CONTROL 1 = 8.0× –20 95 90 SNR/SFDR (dBFS) –40 –60 –80 –100 85 SFDR 80 75 SNR 70 –120 125 150 175 200 225 250 FREQUENCY (MHz) 60 FREQUENCY (MHz) Figure 49. Single Tone FFT with fIN = 1710.3 MHz 500 100 400 425 450 475 75 275 300 325 350 375 50 0 25 50 75 25 12400-239 0 12400-444 65 –140 Figure 52. SNR/SFDR vs. Analog Input Frequency (fIN); fIN < 500 MHz; Buffer Control 1 = 3.0× 0 0 AIN = −1dBFS SNR = 60.8dBFS ENOB = 9.6 BITS SFDR = 68dBFS BUFFER CONTROL 1 = 8.0× –20 AIN1 AND AIN2 = –7dBFS SFDR = 88dBFS IMD2 = 94dBFS IMD3 = 88dBFS BUFFER CONTROL 1 = 2.0× –20 AMPLITUDE (dBFS) –40 –60 –80 –40 –60 –80 –100 –140 0 25 50 75 100 125 150 175 200 225 FREQUENCY (MHz) 250 Figure 50. Single Tone FFT with fIN = 1950.3 MHz –120 0 50 100 150 FREQUENCY (MHz) 200 Figure 53. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz Rev. B | Page 21 of 91 250 12400-445 –100 –120 12400-240 AMPLITUDE (dBFS) 12400-442 65 –120 AMPLITUDE (dBFS) SNR 100 125 150 175 200 225 250 AMPLITUDE (dBFS) –40 AD6674 Data Sheet 110 0 AIN1 AND AIN2 = –7dBFS SFDR = 88dBFS IMD2 = 88dBFS IMD3 = 89dBFS BUFFER CONTROL 1 = 4.5× 100 SFDR (dBFS) 90 SNR/SFDR (dBc and dBFS) AMPLITUDE (dBFS) –20 –40 –60 –80 –100 80 SNR (dBFS) 70 60 50 SFDR (dBc) 40 30 SNR (dBc) 20 10 0 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 FREQUENCY (MHz) –20 –65 250 –70 200 –75 150 –80 100 –85 50 –90 0 12400-446 –120 INPUT AMPLITUDE (dBFS) Figure 54. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz Figure 57. SNR/SFDR vs. Input Amplitude (AIN), fIN = 170.3 MHz 0 95 90 –20 SFDR SNR/SFDR (dBFS) SFDR (dBc) –40 IMD3 (dBFS) –60 –80 85 80 75 SFDR (dBc) –120 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 INPUT AMPLITUDE (dBFS) SNR 70 IMD3 (dBFS) 65 –40 –15 10 35 60 85 TEMPERATURE (°C) 12400-450 –100 12400-447 SFDR/IMD3 (dBc and dBFS) 12400-449 –10 Figure 58. SNR/SFDR vs. Temperature, fIN = 170.3 MHz Figure 55. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184 MHz and fIN2 = 187 MHz 2.40 0 2.35 2.30 SFDR (dBc) 2.25 –40 POWER (W) IMD3 (dBFS) –60 –80 2.20 L=4 M=2 F=1 2.15 2.10 L=2 M=2 F=2 2.05 SFDR (dBc) 2.00 IMD3 (dBFS) SAMPLE RATE (MSPS) Figure 59. Power Dissipation vs. Sample Rate (fS) (Default SPI) Figure 56. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 338 MHz and fIN2 = 341 MHz Rev. B | Page 22 of 91 12400-451 580 560 540 520 500 480 460 440 420 400 380 360 340 1.90 320 –120 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 INPUT AMPLITUDE (dBFS) 1.95 300 –100 12400-448 SFDR/IMD3 (dBc and dBFS) –20 Data Sheet AD6674 EQUIVALENT CIRCUITS DVDD AVDD3 AVDD3 SYNCINB+ 1kΩ VCM = 0.85V 20kΩ DVDD VCM 1kΩ AVDD3 12400-015 VCM BUFFER SYNCINB– AVDD3 20kΩ LEVEL TRANSLATOR 200Ω 67Ω 28Ω 200Ω 400Ω 10pF DGND AVDD3 3pF 1.5pF 200Ω 67Ω 200Ω 28Ω VIN+x SYNCINB± PIN CONTROL (SPI) DGND AIN CONTROL (SPI) 3pF 1.5pF 12400-011 VIN–x Figure 60. Analog Inputs Figure 64. SYNCINB± Inputs AVDD1 SPIVDD 25Ω CLK+ ESD PROTECTED SPIVDD 1kΩ SCLK 30kΩ AVDD1 20kΩ 20kΩ VCM = 0.85V 12400-012 25Ω CLK– 12400-016 ESD PROTECTED Figure 61. Clock Inputs Figure 65. SCLK Inputs AVDD1_SR 1kΩ ESD PROTECTED 20kΩ CSB LEVEL TRANSLATOR AVDD1_SR VCM = 0.85V ESD PROTECTED 20kΩ 1kΩ 12400-013 SYSREF– 30kΩ 1kΩ 12400-017 SYSREF+ SPIVDD Figure 62. SYSREF± Inputs Figure 66. CSB Input SPIVDD EMPHASIS/SWING CONTROL (SPI) ESD PROTECTED DRVDD SERDOUTx+ x = 0, 1, 2, 3 DRGND ESD PROTECTED DRVDD DATA– SDI 30kΩ SERDOUTx– x = 0, 1, 2, 3 DRGND 12400-014 OUTPUT DRIVER SDIO SPIVDD 1kΩ 12400-018 DATA+ SDO Figure 63. Digital Outputs Figure 67. SDIO Rev. B | Page 23 of 91 AD6674 Data Sheet SPIVDD AVDD2 ESD PROTECTED ESD PROTECTED FD JESD LMFC FD_A/FD_B V_1P0 TEMPERATURE DIODE (FD_A ONLY) ESD PROTECTED 12400-019 ESD PROTECTED FD_x PIN CONTROL (SPI) V_1P0 PIN CONTROL (SPI) Figure 68. FD_A/FD_B Outputs Figure 70. V_1P0 Input/Output SPIVDD ESD PROTECTED ESD PROTECTED PDWN CONTROL (SPI) 12400-020 PDWN/ STBY 30kΩ 1kΩ Figure 69. PDWN/STBY Input Rev. B | Page 24 of 91 12400-021 JESD SYNC~ Data Sheet AD6674 THEORY OF OPERATION The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD6674 has several functions that simplify the AGC function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect bits of the ADC output data stream, which are enabled and programmed via Register 0x245 through Register 0x24C. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly lower the system gain to avoid an overrange condition at the ADC input. The Subclass 1 JESD204B-based high speed serialized output data rate can be configured in one-lane (L = 1) and two-lane (L = 2) configurations depending upon the sample rate and the decimation ratio. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins. ADC ARCHITECTURE The architecture consists of an input buffered pipelined ADC. The input buffer is designed to provide a termination impedance to the analog input signal. This termination impedance can be changed using the SPI to meet the termination needs of the driver/amplifier. The default termination value is set to 400 Ω. The equivalent circuit diagram of the analog input termination is shown in Figure 60. The input buffer is optimized for high linearity, low noise, and low power. The input buffer provides a linear high input impedance (for ease of drive) and reduces the kickback from the ADC. The quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. ANALOG INPUT CONSIDERATIONS driving source. In addition, low Q inductors or ferrite beads can be placed on each section of the input to reduce high differential capacitance at the analog inputs and, thus, achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Place either a differential capacitor or two single-ended capacitors on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input, which limits unwanted broadband noise. For more information, refer to the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “TransformerCoupled Front-End for Wideband A/D Converters” (Volume 39, April 2005) at www.analog.com. In general, the precise values depend on the application. For best dynamic performance, match the source impedances driving VIN+x and VIN−x such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates a differential reference that defines the span of the ADC core. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD6674, the available span is programmable through the SPI port from 1.46 V p-p to 2.06 V p-p differential, with 1.70 V p-p differential being the default for the AD6674-1000 and AD6674-750, whereas the default for the AD6674-500 is 2.06 V p-p. Differential Input Configurations There are several ways to drive the AD6674, either actively or passively. However, optimum performance is achieved by driving the analog input differentially. For applications where SNR and SFDR are key parameters, differential transformer coupling is the recommended input configuration (see Figure 71 and Table 9) because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD6674. For low to midrange frequencies, it is recommended to use a double balun or double transformer network (see Figure 71) for optimum performance from the AD6674. For higher frequencies in the second or third Nyquist zone, it is better to remove some of the front-end passive components to ensure wideband operation (see Figure 71 and Table 9). 0.1µF The analog input to the AD6674 is a differential buffer. The internal common-mode voltage of the buffer is 2.05 V. The clock signal alternately switches the input circuit between sample mode and hold mode. When the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor, in series with each input, can help reduce the peak transient current inserted from the output stage of the R1 R3 R2 C1 C2 BALUN R2 R1 ADC 0.1µF 0.1µF R3 C1 NOTES 1. SEE TABLE 9 FOR COMPONENT VALUES. Figure 71. Differential Transformer Coupled Configuration for AD6674 Rev. B | Page 25 of 91 12400-516 The AD6674 has two analog input channels and two JESD204B output lane pairs. The AD6674 is designed to sample wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. AD6674 Data Sheet Table 9. Differential Transformer Coupled Input Configuration Component Values Frequency Range DC to 250 MHz 250 MHz to 2 GHz DC to 375 MHz 375 MHz to 2 GHz DC to 500 MHz 500 MHz to 2 GHz AD6674-750 AD6674-1000 Transformer ETC1-1-13 BAL0006/BAL0006SMG ETC1-1-13 BAL0006/BAL0006SMG ECT1-1-13/BAL0006SMG BAL0006/BAL0006SMG Input Common Mode The analog inputs of the AD6674 are internally biased to the common mode, as shown in Figure 72. The common-mode buffer has limited range in that the performance suffers greatly if the common-mode voltage drops by more than 100 mV. Therefore, in dc-coupled applications, set the common-mode voltage to 2.05 V ± 100 mV to ensure proper ADC operation. Analog Input Controls and SFDR Optimization 200Ω 67Ω 200Ω 28Ω IAVDD3 (mA) AVDD3 VCM BUFFER AD6674-500 150 50 150 200Ω 200Ω 67Ω 28Ω 200 100 250 350 650 450 550 BUFFER CURRENT SETTING 750 850 Figure 73. IAVDD3 vs. Buffer Current Setting in Register 0x018 AVDD3 AIN CONTROL SPI REGISTERS (0x008, 0x015, 0x016, 0x018, 0x019, 0x01A, 0x11A, 0x934, 0x935) 12400-517 VIN–x 3pF 1.5pF C2 (pF) 2 2 2 2 2 Open AD6674-1000 AND AD6674-750 VIN+x AVDD3 C1 (pF) 4 4 4 4 4 Open 250 AVDD3 400Ω R3 (Ω) 10 10 10 10 10 0 300 AVDD3 10pF R2 (Ω) 50 50 50 50 25 25 a high setting of 8.5×. The default setting in Register 0x018 is 3.0× for the AD6674-750 and AD6674-1000, whereas the default for the AD6674-500 is 2.0×. These settings are sufficient for operation in the first Nyquist zone. As the input buffer currents are set, the amount of current required by the AVDD3 supply changes. This relationship is shown in Figure 73. For a complete list of buffer current settings, see Table 45 for more details. The AD6674 offers flexible controls for the analog inputs such as input termination, input capacitance, buffer current, and input full-scale adjustment. All of the available controls are shown in Figure 72. 3pF 1.5pF R1 (Ω) 10 10 10 10 25 25 12400-341 Device AD6674-500 Figure 72. Analog Input Controls Use Register 0x018, Register 0x019, Register 0x01A, Register 0x11A, Register 0x934, and Register 0x935 to adjust the buffer behavior on each channel to optimize the SFDR over various input frequencies and bandwidths of interest. Input Buffer Control Registers (Register 0x018, Register 0x019, Register 0x01A, Register 0x934, Register 0x935, Register 0x11A) The input buffer has many registers that set the bias currents and other settings for operation at different frequencies. These bias currents and settings can be changed to suit the input frequency range of operation. Register 0x018 controls the buffer bias current to reduce the effects of charge kickback from the ADC core. This setting can be scaled from a low setting of 1.0× to Register 0x019, Register 0x01A, Register 0x11A, and Register 0x935 offer secondary bias controls for the input buffer for frequencies >500 MHz. Register 0x934 can be used to reduce input capacitance to achieve wider signal bandwidth but doing so may result in slightly lower linearity and noise performance. These register settings do not affect the AVDD3 power as much as Register 0x018 does. For frequencies <500 MHz, it is recommended to use the default settings for these registers. Table 10 shows the recommended values for the buffer current control registers for various speed grades. Use Register 0x11A when sampling in higher Nyquist zones (>500 MHz for the AD6674-1000). This setting enables the ADC sampling network to optimize the sampling and settling times internal to the ADC for high frequency operation. For frequencies greater than 500 MHz, it is recommended to operate the ADC core at a 1.46 V full-scale setting irrespective of the speed grade. This setting offers better SFDR without any significant decrease in SNR. Figure 74, Figure 75, and Figure 76 show the SFDR vs. analog input frequency for various buffer settings (IBUFF) for the AD6674-1000. Rev. B | Page 26 of 91 AD6674 80 The recommended settings shown in Table 10 were used to collect the data while changing only the contents of Register 0x018. 75 90 85 SFDR (dBFS) 4.5× 3.0× 75 70 65 65 1.5× 1.52GHz 1.65GHz 1.76GHz 1.9GHz 1.95GHz 60 65 60 60 55 –3 INPUT LEVEL (dBFS) 110 160 210 260 310 360 INPUT FREQUENCY (MHz) 410 460 12400-342 60 Figure 77. SNR/SFDR vs. Input Level and Input Frequencies, AD6674-1000 Figure 74. Buffer Current Sweeps, AD6674-1000 (SFDR vs. Input Frequency and IBUFF); 10 MHz < fIN < 500 MHz; Front-End Network Shown in Figure 71 85 3.0× 4.0× 5.0× 6.0× 80 Figure 78, Figure 79, and Figure 80 show the SFDR vs. analog input frequency for various buffer settings for the AD6674-500. The recommended settings shown in Table 10 were used to take the data while changing the contents of register 0x018 only. 95 75 90 70 85 65 SFDR (dBFS) 60 55 50 80 1.5× 2.0× 2.5× 3.5× 4.5× 75 70 65 45 80 450.3 INPUT FREQUENCY (MHz) 12400-581 420.3 390.3 360.3 340.7 330.3 301.3 270.3 240.3 55 Figure 75. Buffer Current Sweeps, AD6674-1000 (SFDR vs. Input Frequency and IBUFF); 500 MHz < fIN < 1500 MHz; Front-End Network Shown in Figure 71 180.3 INPUT FREQUENCY (MHz) 60 210.3 1374.8 150.3 1200.5 95.3 1026.2 125.3 851.9 10.3 677.6 12400-452 40 503.4 65.3 SFDR (dBFS) 55 –1 –2 55 12400-454 70 50 10 75 70 170.3 SFDR (dBFS) 80 80 1.65GHz 1.52GHz 1.76GHz 1.95GHz 1.9GHz SNR (dBc) Data Sheet Figure 78. Buffer Current Sweeps, AD6674-750 (SFDR vs. Input Frequency and IBUFF); 10 MHz < fIN < 450 MHz; Front-End Network Shown in Figure 71 75 95 70 4.5× 5.5× 6.5× 7.5× 65 85 60 SFDR (dBFS) 55 50 40 1513.4 75 70 1607.4 1701.5 1795.6 INPUT FREQUENCY (MHz) 1889.8 12400-453 45 4.5× 5.5× 6.5× 7.5× 8.5× 80 65 60 450.3 Figure 76. Buffer Current Sweeps, AD6674-1000 (SFDR vs. Input Frequency and IBUFF); 1500 MHz < fIN < 2 GHz; Front-End Network Shown in Figure 71 In certain high frequency applications, the SFDR can be improved by reducing the full-scale setting, as shown in Table 10. At high frequencies, the performance of the ADC core is limited by jitter. The SFDR can be improved by reducing the full-scale level. 480.3 510.3 515.3 610.3 765.3 810.3 INPUT FREQUENCY (MHz) 985.3 1010.3 12400-582 SFDR (dBFS) 90 Figure 79. Buffer Current Sweeps, AD6674-750 (SFDR vs. Input Frequency and IBUFF); 450 MHz < fIN < 800 MHz; Front-End Network Shown in Figure 71 Rev. B | Page 27 of 91 AD6674 Data Sheet 80 95 75 90 75 Figure 80. Buffer Current Sweeps, AD6674-750 (SFDR vs. Input Frequency and IBUFF); 800 MHz < fIN < 2 GHz; Front-End Network Shown in Figure 71 Figure 81, Figure 82, and Figure 83 show the SFDR vs. analog input frequency for various buffer settings for the AD6674-500. The recommended settings shown in Table 10 were used to take the data while changing the contents of register 0x018 only. 100 90 80 480.3 610.3 765.3 510.3 515.3 INPUT FREQUENCY (MHz) 75 70 65 60 55 50 60 45 50 40 1010.3 40 4.0× 5.0× 6.0× 7.0× 8.0× 1205.3 1410.3 1600.3 INPUT FREQUENCY (MHz) 10 0 10.3 95.3 1810.3 1950.3 Figure 83. Buffer Current Sweeps, AD6674-500 (SFDR vs. Input Frequency and IBUFF); 1 GHz < fIN < 2 GHz; Front-End Network Shown in Figure 71 1.0× 1.5× 2.0× 3.0× 4.5× 150.3 180.3 240.3 301.3 340.7 INPUT FREQUENCY (MHz) 390.3 450.3 12400-584 20 985.3 80 70 30 810.3 Figure 82. Buffer Current Sweeps, AD6674-500 (SFDR vs. Input Frequency and IBUFF); 450 MHz < fIN < 1000 MHz; Front-End Network Shown in Figure 71 SNR/SFDR (dBFS) 1950.3 12400-583 1910.3 1810.3 1710.3 1600.3 1510.3 1410.3 65 450.3 1310.3 50 1110.3 70 1010.3 55 INPUT FREQUENCY (MHz) SFDR (dBFS) 80 12400-586 6.5× 7.5× 8.5× 60 85 12400-585 SNR/SFDR (dBFS) 65 1205.3 SFDR (dBFS) 70 4.0× 5.0× 6.0× 7.0× 8.0× Figure 81. Buffer Current Sweeps, AD6674-500 (SFDR vs. Input Frequency and IBUFF); 10 MHz < fIN < 450 MHz; Front-End Network Shown in Figure 71 Rev. B | Page 28 of 91 Data Sheet AD6674 Table 10. AD6674 Performance Optimization for Input Frequencies Product AD6674-500 Frequency (MHz) DC to 250 250 to 500 500 to 1000 1000 to 2000 AD6674-750 DC to 200 DC to 375 200 to 500 375 to 750 500 to 750 750 to 1000 1000 to 2000 AD6674-1000 DC to 150 DC to 500 500 to 1000 1000 to 2000 1 2 Buffer Control 1 (0x018) 0x20 (2.0×) 0x70 (4.5×) 0x80 (5.0×) 0xF0 (8.5×) 0x20 (2.0×) 0x40 (3.0×) 0x70 (4.5×) 0xA0 (6.0×) 0xD0 (7.5×) 0xF0 (8.5×) 0xF0 (8.5×) 0x10 (1.5×) 0x40 (3.0×) 0xA0 (6.0×) 0xD0 (7.5×) Buffer Control 2 (0x019) 0x60 (Setting 3) 0x60 (Setting 3) 0x40 (Setting 1) 0x40 (Setting 1) 0x40 (Setting 1) 0x40 (Setting 1) 0x40 (Setting 1) 0x40 (Setting 1) 0x40 (Setting 1) 0x40 (Setting 1) 0x40 (Setting 1) 0x50 (Setting 2) 0x50 (Setting 2) 0x60 (Setting 3) 0x70 (Setting 4) Buffer Control 3 (0x01A) 0x0A (Setting 3) 0x0A (Setting 3) 0x08 (Setting 1) 0x08 (Setting 1) 0x09 (Setting 2) 0x09 (Setting 2) 0x09 (Setting 2) 0x08 (Setting 1) 0x08 (Setting 1) 0x08 (Setting 1) 0x08 (Setting 1) 0x09 (Setting 2) 0x09 (Setting 2) 0x09 (Setting 2) 0x09 (Setting 2) Buffer Control 4 (0x11A) 0x00 (off) Buffer Control 5 (0x935) 0x04 (on) Input Full-Scale Control (0x030) 0x04 0x00 (off) 0x04 (on) 0x04 0x00 (off) 0x00 (off) 0x18 0x00 (off) 0x00 (off) 0x18 0x00 (off) 0x04 (on) 0x14 0x00 (off) 0x04 (on) 0x14 0x00 (off) 0x04 (on) 0x14 0x00 (off) 0x00 (off) 0x18 0x00 (off) 0x00 (off) 0x18 0x00 (off) 0x00 (off) 0x18 0x00 (off) 0x00 (off) 0x18 0x00 (off) 0x04 (on) 0x18 0x00 (off) 0x04 (on) 0x18 0x20 (on) 0x00 (off) 0x18 0x20 (on) 0x00 (off) 0x18 Input Full-Scale Range (0x025) 0x0C (2.06 V p-p) 0x0C (2.06 V p-p) 0x08 (1.46 V p-p) 0x08 (1.46 V p-p) 0x0A (1.70 V p-p) 0x0A (1.70 V p-p) 0x0A (1.70 V p-p) 0x08 (1.46 V p-p) 0x08 (1.46 V p-p) 0x08 (1.46 V p-p) 0x08 (1.46 V p-p) 0x0A (1.70 V p-p) 0x0A (1.70 V p-p) 0x08 (1.46 V p-p) 0x08 (1.46 V p-p) Input Capacitance (0x934) 0x1F 0x1F 0x1F/0x00 2 0x1F/0x002 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F/0x002 0x1F/0x002 0x1F 0x1F 0x1F/0x002 0x1F/0x002 The input termination can be changed to accommodate the application with little or no impact to ac performance. The input capacitance can be set to 1.5 pF to achieve wider input bandwidth but results in slightly lower linearity and noise performance. Rev. B | Page 29 of 91 Input Termination (0x016) 1 0x0C/0x1C/ 0x2C/0x6C 0x0C/0x1C/ 0x2C/0x6C 0x0C/0x1C/ 0x2C/0x6C 0x0C/0x1C/ 0x2C/0x6C 0x0C/0x1C/ 0x2C/0x6C 0x0C/0x1C/ 0x2C/0x6C 0x0C/0x1C/ 0x2C/0x6C 0x0C/0x1C/ 0x2C/0x6C 0x0C/0x1C/ 0x2C/0x6C 0x0C/0x1C/ 0x2C/0x6C 0x0C/0x1C/ 0x2C/0x6C 0x0E/0x1E/ 0x2E/0x6E 0x0E/0x1E/ 0x2E/0x6E 0x0E/0x1E/ 0x2E/0x6E 0x0E/0x1E/ 0x2E/0x6E AD6674 Data Sheet Absolute Maximum Input Swing The absolute maximum input swing allowed at the inputs of the AD6674 is 4.3 V p-p differential. Signals operating near or at this level can cause permanent damage to the ADC. VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD6674. This internal 1.0 V reference sets the full-scale input range of the ADC. The full-scale input range can be adjusted via Register 0x025. For more information on adjusting the input swing, see Table 45. Figure 84 shows the block diagram of the internal 1.0 V reference controls. reference voltage. For more information on adjusting the fullscale level of the AD6674, refer to the Memory Map Register Table section. The use of an external reference may be necessary, in some applications, to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 85 shows the typical drift characteristics of the internal 1.0 V reference. 1.0010 1.0009 1.0008 V_1P0 VOLTAGE (V) 1.0007 VIN+A/ VIN+B VIN–A/ VIN–B FULL-SCALE VOLTAGE ADJUST 1.0002 1.0001 1.0000 V_1P0 0.9998 25 TEMPERATURE (°C) 90 Figure 85. Typical V_1P0 Drift 12400-031 V_1P0 PIN CONTROL SPI REGISTER (0x025 AND 0x024) Figure 84. Internal Reference Configuration and Controls Register 0x024 enables the user to either use this internal 1.0 V reference or to provide an external 1.0 V reference. When using an external voltage reference, provide a 1.0 V reference. The full-scale adjustment is made using the SPI, irrespective of the The external reference must be a stable 1.0 V reference. The ADR130 is a good option for providing the 1.0 V reference. Figure 86 shows how the ADR130 can be used to provide the external 1.0 V reference to the AD6674. The grayed out areas show unused blocks within the AD6674 while the ADR130 provides the external reference. INTERNAL V_1P0 GENERATOR ADR130 FULL-SCALE VOLTAGE ADJUST NC 6 1 NC 2 GND SET 5 3 VIN 0.1µF 0 –50 12400-106 0.9999 INPUT FULL-SCALE RANGE ADJUST SPI REGISTER (0x025 AND 0x024) INPUT 1.0004 1.0003 VOUT 4 V_1P0 0.1µF FULL-SCALE CONTROL Figure 86. External Reference Using the ADR130 Rev. B | Page 30 of 91 12400-032 INTERNAL V_1P0 GENERATOR ADC CORE 1.0006 1.0005 Data Sheet AD6674 CLOCK INPUT CONSIDERATIONS Input Clock Divider For optimum performance, drive the AD6674 sample clock inputs (CLK+ and CLK−) with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or clock drivers. These pins are biased internally and require no additional biasing. The AD6674 contains an input clock divider with the ability to divide the Nyquist input clock by 1, 2, 4, or 8. The divide ratios can be selected using Register 0x10B. This is shown in Figure 90. The maximum frequency at the output of the divider is 1.0 GHz. Figure 87 shows one preferred method for clocking the AD6674. The low jitter clock source is converted from a singleended signal to a differential signal using an RF transformer. 0.1µF CLK+ 100Ω 50Ω CLK+ ADC CLK– 0.1µF CLK– ÷2 ÷4 Figure 87. Transformer Coupled Differential Clock ÷8 Another option is to ac couple a differential CML or LVDS signal to the sample clock input pins as shown in Figure 88 and Figure 89. 3.3V 71Ω 33Ω 0.1µF ADC Z0 = 50Ω 0.1µF 12400-036 CLK+ CLK– Input Clock Divider ½ Period Delay Adjustment Figure 88. Differential CML Sample Clock LVDS DRIVER 100Ω 50Ω1 50Ω1 Clock Fine Delay Adjustment CLK– CLK– CLOCK INPUT ADC 0.1µF RESISTORS ARE OPTIONAL. 12400-037 0.1µF 150Ω CLK+ CLK+ CLOCK INPUT The input clock divider inside the AD6674 provides phase delay in increments of ½ the input clock cycle. Program Register 0x10C to enable this delay independently for each channel. Changing the register does not affect the stability of the JESD204B link. 0.1µF 0.1µF Figure 90. Clock Divider Circuit The AD6674 clock divider can be synchronized using the external SYSREF± input. A valid SYSREF± causes the clock divider to reset to a programmable state. This feature is enabled by setting Bit 7 of Register 0x10D. This synchronization feature allows multiple devices to have their clock dividers aligned to guarantee simultaneous input sampling. 10pF 33Ω Z0 = 50Ω REG 0x10B 12400-038 1:1Z 12400-035 CLOCK INPUT The maximum frequency at the CLK± inputs is 4 GHz. This is the limit of the divider. In applications where the clock input is a multiple of the sample clock, take care to program the appropriate divider ratio into the clock divider before applying the clock signal. This ensures that the current transients during device startup are controlled. Figure 89. Differential LVDS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. In applications where the clock duty cycle cannot be guaranteed to be 50%, a higher multiple frequency clock can be supplied to the AD6674. For example, the AD6674-1000 can be clocked at 2 GHz with the internal clock divider set to 2. This ensures a 50% duty cycle, high slew rate internal clock for the ADC. See the Memory Map section for more details on using this feature. Adjust the AD6674 sampling edge instant by writing to Register 0x117 and Register 0x118. Setting Bit 0 of Register 0x117 enables the feature, and Register 0x118, Bits[7:0], set the value of the delay. This value can be programmed individually for each channel. The clock delay can be adjusted from −151.7 ps to +150 ps in ~1.7 ps increments. The clock delay adjustment takes effect immediately when it is enabled via SPI writes. Enabling the clock fine delay adjustment in Register 0x117 causes a datapath reset. However, the contents of Register 0x118 can be changed without affecting the stability of the JESD204B link. Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) is calculated by SNR = 20 × log 10(2 × π × fA × tJ) In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 91). Rev. B | Page 31 of 91 AD6674 POWER-DOWN/STANDBY MODE RMS CLOCK JITTER REQUIREMENT 120 The AD6674 has a PDWN/STBY pin that can be used to configure the device in power-down or standby mode. The default operation is the PDWN function. The PDWN/STBY pin is a logic high pin. When in power-down mode, the JESD204B link is disrupted. The power-down option can also be set via Register 0x03F and Register 0x040. 100 16 BITS 90 14 BITS 80 12 BITS 70 In standby mode, the JESD204B link is not disrupted and transmits zeros for all converter samples. This can be changed using Register 0x571[7] to select /K/ characters. 10 BITS 60 50 40 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 30 10 100 ANALOG INPUT FREQUENCY (MHz) 1 1000 12400-039 8 BITS Figure 91. Ideal SNR vs. Analog Input Frequency and Jitter Treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the AD6674. Separate power supplies for clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. If the clock is generated from another type of source (by gating, dividing, or other methods), retime it using the original clock at the last step. See the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs. Figure 92 shows the estimated SNR of the AD6674-1000 across input frequency for different clock induced jitter values. The SNR can be estimated by using the following equation: − SNR ADC SNR (dBFS) = 10log 10 10 − SNRJITTER + 10 10 70 SNR (dBFS) 65 TEMPERATURE DIODE The AD6674 contains a diode-based temperature sensor for measuring the temperature of the die. This diode outputs a voltage and serve as a coarse temperature sensor to monitor the internal die temperature. The temperature diode voltage can be output to the FD_A pin using the SPI. Use Register 0x028[0] to enable or disable the diode. Register 0x028 is a local register. Channel A must be selected in the device index register (Register 0x008) to enable the temperature diode readout. Configure the FD_A pin to output the diode voltage by programming Register 0x040[2:0]. See Table 45 for more information. The voltage response of the temperature diode (with SPIVDD = 1.8 V) is shown in Figure 93. 0.90 0.85 60 55 50 45 10M 0.80 0.75 0.70 0.65 0.60 25fs 50fs 75fs 100f s 125f s 150f s 175f s 200f s –55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105 115 125 TEMPERATURE (°C) Figure 93. Temperature Diode Voltage vs. Temperature 100M 1G INPUT FREQUENCY (Hz) 10G Figure 92. Estimated SNR Degradation for the AD6674-1000 vs. Input Frequency and Jitter Rev. B | Page 32 of 91 12400-353 SNR (dB) 110 DIODE VOLTAGE (V) 130 Data Sheet Data Sheet AD6674 ADC OVERRANGE AND FAST DETECT time. This provides hysteresis and prevents the FD bit from excessively toggling. In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overrange bit in the JESD204B outputs provides information on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. In addition, because input signals can have significant slew rates, the latency of this function is of major concern. Highly pipelined converters can have significant latency. The AD6674 contains fast detect circuitry for individual channels to monitor the threshold and assert the FD_A and FD_B pins. The operation of the upper threshold and lower threshold registers, along with the dwell time registers, is shown in Figure 94. The FD_x indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold registers, located in Register 0x247 and Register 0x248. The selected threshold register is compared with the signal magnitude at the output of the ADC. The fast upper threshold detection has a latency of 28. The approximate upper threshold magnitude is defined by Upper Threshold Magnitude (dBFS) = 20 log (Threshold Magnitude/213) ADC OVERRANGE (OR) The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC. The overrange indicator can be embedded within the JESD204B link as a control bit (when CSB > 0). The latency of this overrange indicator matches the sample latency. The FD_x indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. The lower threshold is programmed in the fast detect lower threshold registers, located in Register 0x249 and Register 0x24A. The fast detect lower threshold register is a 13-bit register that is compared with the signal magnitude at the output of the ADC. This comparison is subject to the ADC pipeline latency but is accurate in terms of converter resolution. The lower threshold magnitude is defined by The AD6674 constantly monitors the analog input level and records any overrange condition in any of the eight virtual converters. For more information on the virtual converters, refer to Figure 99. The overrange status of each virtual converter is registered as a sticky bit (that is, it is set until cleared) in Register 0x563. Clear the contents of Register 0x563 using Register 0x562 by toggling the bits corresponding to the virtual converter to set and reset the position. Lower Threshold Magnitude (dBFS) = 20 log (Threshold Magnitude/213) For example, to set an upper threshold of −6 dBFS, write 0x0FFF to Register 0x247 and Register 0x248; and to set a lower threshold of −10 dBFS, write 0x0A1D to Register 0x249 and Register 0x24A. FAST THRESHOLD DETECTION (FD_A AND FD_B) The fast detect (FD) bit (enabled in the control bits via Register 0x559 and Register 0x55A) is immediately set whenever the absolute value of the input signal exceeds the programmable upper threshold level. The FD bit is only cleared when the absolute value of the input signal drops below the lower threshold level for greater than the programmable dwell The dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time registers, located in Register 0x24B and Register 0x24C. See the Memory Map section (Register 0x245 to Register 0x24C in Table 45) for more details. UPPER THRESHOLD DWELL TIME TIMER RESET BY RISE ABOVE LOWER THRESHOLD DWELL TIME FD_A OR FD_B Figure 94. Threshold Settings for FD_A and FD_B Signals Rev. B | Page 33 of 91 TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LOWER THRESHOLD 12400-040 MIDSCALE LOWER THRESHOLD AD6674 Data Sheet SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the peak magnitude of the digitized signal. This information can be used to drive an AGC loop to optimize the range of the ADC in the presence of real-world signals. The results of the signal monitor block can be obtained either by reading back the internal values from the SPI port or by embedding the signal monitoring information into the JESD204B interface as special control bits. A global, 24-bit programmable period controls the duration of the measurement. Figure 95 shows the simplified block diagram of the signal monitor block. FROM MEMORY MAP SIGNAL MONITOR PERIOD REGISTER (SMPR) 0x271, 0x272, 0x273 DOWN COUNTER When the monitor period timer reaches a count of 1, the 13-bit peak level value is transferred to the signal monitor holding register, which can be read through the memory map or output through the serial port (SPORT) over the JESD204B interface. The monitor period timer is reloaded with the value in the SMPR, and the countdown is restarted. In addition, the magnitude of the first input sample is updated in the internal magnitude storage register, and the comparison and update procedure, as explained previously, continues. IS COUNT = 1? LOAD FROM INPUT LOAD LOAD SIGNAL MONITOR HOLDING REGISTER COMPARE A>B TO SPORT OVER JESD204B AND MEMORY MAP SPORT OVER JESD204B 12400-471 CLEAR MAGNITUDE STORAGE REGISTER After enabling this mode, the value in the SMPR is loaded into a monitor period timer that decrements at the decimated clock rate. The magnitude of the input signal is compared with the value in the internal magnitude storage register (not accessible to the user), and the greater of the two is updated as the current peak level. The initial value of the magnitude storage register is set to the current ADC input signal magnitude. This comparison continues until the monitor period timer reaches a count of 1. Figure 95. Signal Monitor Block The peak detector captures the largest signal within the observation period. This period observes only the magnitude of the signal. The resolution of the peak detector is a 13-bit value, and the observation period is 24 bits and represents converter output samples. The peak magnitude is derived by using the following equation: Peak Magnitude (dBFS) = 20 log(Peak Detector Value/213) The magnitude of the input port signal is monitored over a programmable time period that is determined by the signal monitor period registers (SMPRs). Only even values of the SMPR are supported. The peak detector function is enabled by setting Bit 1 of Register 0x270 in the signal monitor control register. The 24-bit SMPR must be programmed before activating this mode. The signal monitor data can also be serialized and sent over the JESD204B interface as control bits. These control bits must be deserialized from the samples to reconstruct the statistical data. This signal control monitor function is enabled by setting Bits[1:0] of Register 0x279 and Bit 1 of Register 0x27A. Figure 96 shows two different example configurations for the signal monitor control bit locations inside the JESD204B samples. There are a maximum of three control bits that can be inserted into the JESD204B samples; however, only one control bit is required for the signal monitor. Control bits are inserted from MSB to LSB. If only one control bit is to be inserted (CS = 1), only the most significant control bit is used (see Configuration 1 and Configuration 2 in Figure 96). To select the SPORT over JESD204B option, program Register 0x559, Register 0x55A, and Register 0x58F. See the Memory Map Register Table section for more information on setting these bits. Figure 97 shows the 25-bit frame data that encapsulates the peak detector value. The frame data is transmitted MSB first with five 5-bit subframes. Each subframe contains a start bit that can be used by a receiver to validate the deserialized data. Figure 98 shows the SPORT over the JESD204B signal monitor frame data with a monitor period timer set to 80 samples. Rev. B | Page 34 of 91 Data Sheet AD6674 16-BIT JESD204B SAMPLE SIZE (N' = 16) EXAMPLE CONFIGURATION 1 (N' = 16, N = 15, CS = 1) 1-BIT CONTROL BIT (CS = 1) 15-BIT CONVERTER RESOLUTION (N = 15) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S[14] X S[13] X S[12] X S[11] X S[10] X S[9] X S[8] X S[7] X S[6] X S[5] X S[4] X S[3] X S[2] X S[1] X S[0] X CTRL [BIT 2] X SERIALIZED SIGNAL MONITOR FRAME DATA 16-BIT JESD204B SAMPLE SIZE (N' = 16) 15 S[13] X 14 S[12] X 13 S[11] X 12 11 S[10] X S[9] X 10 9 S[8] X 8 S[7] X 7 S[6] X 6 S[5] X 5 S[4] X S[3] X 4 S[2] X 3 S[1] X 2 1 0 S[0] X CTRL [BIT 2] X TAIL X SERIALIZED SIGNAL MONITOR FRAME DATA Figure 96. Signal Monitor Control Bit Example Configurations 5-BIT SUBFRAMES 5-BIT IDLE SUBFRAME (OPTIONAL) 25-BIT FRAME IDLE 1 IDLE 1 IDLE 1 IDLE 1 IDLE 1 5-BIT IDENTIFIER START 0 SUBFRAME ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 1 5-BIT DATA MSB SUBFRAME START 0 P[12] P[11] P[10] P[9] 5-BIT DATA SUBFRAME START 0 P[8] P[7] P[6] P5] 5-BIT DATA SUBFRAME START 0 P[4] P[3] P[2] P1] 5-BIT DATA LSB SUBFRAME START 0 P[0] 0 0 0 P[] = PEAK MAGNITUDE VALUE 12400-473 EXAMPLE CONFIGURATION 2 (N' = 16, N = 14, CS = 1) Figure 97. SPORT over JESD204B Signal Monitor Frame Data Rev. B | Page 35 of 91 12400-472 1 CONTROL BIT 1 TAIL (CS = 1) BIT 14-BIT CONVERTER RESOLUTION (N = 14) AD6674 Data Sheet SMPR = 80 SAMPLES (0x271 = 0x50; 0x272 = 0x00; 0x273 = 0x00) 80-SAMPLE PERIOD PAYLOAD 3 25-BIT FRAME (N) IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE 80-SAMPLE PERIOD PAYLOAD 3 25-BIT FRAME (N + 1) IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE 80-SAMPLE PERIOD IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE Figure 98. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples Rev. B | Page 36 of 91 12400-474 PAYLOAD 3 25-BIT FRAME (N + 2) Data Sheet AD6674 DIGITAL DOWNCONVERTER (DDC) The AD6674 includes four digital downconverters (DDCs) that provide filtering and reduce the output data rate. This digital processing section includes an NCO, a half-band decimating filter, an FIR filter, a gain stage, and a complex to real conversion stage. Each of these processing blocks has control lines that allow it to be independently enabled and disabled to provide the desired processing function. The digital downconverter can be configured to output either real data or complex output data. The DDCs output a 16-bit stream. To enable this operation, the converter number of bits, N, is set to a default value of 16, even though the analog core only outputs 14 bits. In full bandwidth operation, the ADC outputs are the 14-bit word followed by two zeros, unless the tail bits are enabled. DDC I/Q INPUT SELECTION The AD6674 has two ADC channels and four DDC channels. Each DDC channel has two input ports that can be paired to support both real and complex inputs through the I/Q crossbar mux. For real signals, both DDC input ports must select the same ADC channel (that is, DDC Input Port I = ADC Channel A and DDC Input Port Q = ADC Channel A). For complex signals, each DDC input port must select different ADC channels (that is, DDC Input Port I = ADC Channel A and DDC Input Port Q = ADC Channel B). The inputs to each DDC are controlled by the DDC input selection registers (Register 0x311, Register 0x331, Register 0x351, and Register 0x371). See Table 45 for information on how to configure the DDCs. DDC I/Q OUTPUT SELECTION Each DDC channel has two output ports that can be paired to support both real and complex outputs. For real output signals, only the DDC Output Port I is used (the DDC Output Port Q is invalid). For complex I/Q output signals, both DDC Output Port I and DDC Output Port Q are used. The I/Q outputs to each DDC channel are controlled by the DDC complex to real enable bit, Bit 3, in the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). The Chip Q ignore bit in the chip mode register (Register 0x200[5]) controls the chip output muxing of all the DDC channels. When all DDC channels use real outputs, set this bit high to ignore all DDC Q output ports. When any of the DDC channels are set to use complex I/Q outputs, the user must clear this bit to use both DDC Output Port I and DDC Output Port Q. For more information, see Figure 107. DDC GENERAL DESCRIPTION The four DDC blocks are used to extract a portion of the full digital spectrum captured by the ADC(s). They are intended for IF sampling or oversampled baseband radios requiring wide bandwidth input signals. Each DDC block contains the following signal processing stages: • • • • Frequency translation stage (optional) Filtering stage Gain stage (optional) Complex to real conversion stage (optional) Frequency Translation Stage (Optional) This stage consists of a 12-bit complex NCO and quadrature mixers that can be used for frequency translation of both real and complex input signals. This stage shifts a portion of the available digital spectrum down to baseband. Filtering Stage After shifting down to baseband, this stage decimates the frequency spectrum using a chain of up to four half-band lowpass filters for rate conversion. The decimation process lowers the output data rate, which in turn reduces the output interface rate. Gain Stage (Optional) Due to losses associated with mixing a real input signal down to baseband, this stage compensates by adding an additional 0 dB or 6 dB of gain. Complex to Real Conversion Stage (Optional) When real outputs are necessary, this stage converts the complex outputs back to real by performing an fS/4 mixing operation plus a filter to remove the complex component of the signal. Figure 99 shows the detailed block diagram of the DDCs implemented in the AD6674. Rev. B | Page 37 of 91 AD6674 Data Sheet GAIN = 0dB OR 6dB COMPLEX TO REAL CONVERSION (OPTIONAL) GAIN = 0dB OR 6dB COMPLEX TO REAL CONVERSION (OPTIONAL) COMPLEX TO REAL CONVERSION (OPTIONAL) COMPLEX TO REAL CONVERSION (OPTIONAL) ADC SAMPLING AT fS GAIN = 0dB OR 6dB REAL/I GAIN = 0dB OR 6dB REAL/Q Q HB1 FIR DCM = 2 NCO + MIXER (OPTIONAL) HB2 FIR DCM = BYPASS OR 2 I HB3 FIR DCM = BYPASS OR 2 REAL/I HB4 FIR DCM = BYPASS OR 2 DDC 0 REAL/I CONVERTER 0 Q CONVERTER 1 SYSREF± Q CONVERTER 3 REAL/Q Q ADC SAMPLING AT fS HB1 FIR DCM = 2 I HB2 FIR DCM = BYPASS OR 2 REAL/I HB3 FIR DCM = BYPASS OR 2 DDC 2 REAL/I CONVERTER 4 OUTPUT INTERFACE HB1 FIR DCM = 2 REAL/I CONVERTER 2 SYSREF± NCO + MIXER (OPTIONAL) REAL/I HB2 FIR DCM = BYPASS OR 2 REAL/Q Q HB3 FIR DCM = BYPASS OR 2 NCO + MIXER (OPTIONAL) HB4 FIR DCM = BYPASS OR 2 I/Q CROSSBAR MUX I HB4 FIR DCM = BYPASS OR 2 DDC 1 REAL/I Q CONVERTER 5 SYSREF± SYSREF± SYNCHRONIZATION CONTROL CIRCUITS HB1 FIR DCM = 2 REAL/I CONVERTER 6 Q CONVERTER 7 12400-041 REAL/Q Q HB2 FIR DCM = BYPASS OR 2 NCO + MIXER (OPTIONAL) HB3 FIR DCM = BYPASS OR 2 I HB4 FIR DCM = BYPASS OR 2 DDC 3 REAL/I SYSREF Figure 99. DDC Detailed Block Diagram Figure 100 shows an example usage of one of the four DDC blocks with a real input signal and four half-band filters (HB4 + HB3 + HB2 + HB1). It shows both complex (decimate by 16) and real (decimate by 8) output options. When DDCs have different decimation ratios, the chip decimation ratio (Register 0x201) must be set to the lowest decimation ratio of all the DDC blocks. In this scenario, samples of higher decimation ratio DDCs are repeated to match the chip decimation ratio sample rate. Whenever the NCO frequency is set or changed, the DDC soft reset must be issued. If the DDC soft reset is not issued, the output may potentially show amplitude variations. Table 11, Table 12, Table 13, Table 14, and Table 15 show the DDC samples when the chip decimation ratio is set to 1, 2, 4, 8, or 16, respectively. When DDCs have different decimation ratios, the chip decimation ratio must be set to the lowest decimation ratio of all the DDC channels. In this scenario, samples of higher decimation ratio DDCs are repeated to match the chip decimation ratio sample rate. Rev. B | Page 38 of 91 Data Sheet AD6674 ADC ADC SAMPLING AT fS REAL REAL INPUT—SAMPLED AT fS BANDWIDTH OF INTEREST IMAGE –fS/2 –fS/3 –fS/4 REAL BANDWIDTH OF INTEREST fS/32 –fS/32 DC fS/16 –fS/16 –fS/8 FREQUENCY TRANSLATION STAGE (OPTIONAL) DIGITAL MIXER + NCO FOR fS/3 TUNING, THE FREQUENCY TUNING WORD = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) fS/8 fS/4 fS/3 fS/2 I NCO TUNES CENTER OF BANDWIDTH OF INTEREST TO BASEBAND cos(wt) REAL 12-BIT NCO 90° 0° –sin(wt) Q DIGITAL FILTER RESPONSE –fS/2 –fS/3 –fS/4 fS/32 –fS/32 DC fS/16 –fS/16 –fS/8 BANDWIDTH OF INTEREST IMAGE (–6dB LOSS DUE TO NCO + MIXER) BANDWIDTH OF INTEREST (–6dB LOSS DUE TO NCO + MIXER) fS/8 fS/4 fS/3 fS/2 FILTERING STAGE HB4 FIR 4 DIGITAL HALF-BAND FILTERS (HB4 + HB3 + HB2 + HB1) I HALFBAND FILTER Q HALFBAND FILTER HB3 FIR 2 HALFBAND FILTER 2 HALFBAND FILTER HB4 FIR HB2 FIR 2 HALFBAND FILTER 2 HALFBAND FILTER HB3 FIR HB1 FIR 2 HB2 FIR HALFBAND FILTER I HB1 FIR 2 HALFBAND FILTER Q 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS COMPLEX (I/Q) OUTPUTS GAIN STAGE (OPTIONAL) DIGITAL FILTER RESPONSE I GAIN STAGE (OPTIONAL) Q 0dB OR 6dB GAIN COMPLEX TO REAL CONVERSION STAGE (OPTIONAL) fS/4 MIXING + COMPLEX FILTER TO REMOVE Q –fS/32 fS/32 DC –fS/16 fS/16 –fS/8 I REAL (I) OUTPUTS +6dB +6dB fS/8 2 +6dB 2 +6dB I Q –fS/32 fS/32 DC –fS/16 fS/16 DOWNSAMPLE BY 2 I DECIMATE BY 8 Q DECIMATE BY 16 0dB OR 6dB GAIN Q COMPLEX REAL/I TO REAL –fS/8 –fS/32 fS/32 DC –fS/16 fS/16 fS/8 Figure 100. DDC Theory of Operation Example (Real Input, Decimate by 16) Rev. B | Page 39 of 91 12400-042 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS AD6674 Data Sheet Table 11. DDC Samples When Chip Decimation Ratio = 1 HB1 FIR (DCM 1 = 1) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19 N + 20 N + 21 N + 22 N + 23 N + 24 N + 25 N + 26 N + 27 N + 28 N + 29 N + 30 N + 31 1 Real (I) Output (Complex to Real Enabled) HB3 FIR + HB2 HB4 FIR + HB3 FIR + HB2 FIR + FIR + HB1 FIR HB2 FIR + HB1 FIR HB1 FIR (DCM1 = 4) (DCM1 = 8) (DCM1 = 2) N N N N+1 N+1 N+1 N N N N+1 N+1 N+1 N+2 N N N+3 N+1 N+1 N+2 N N N+3 N+1 N+1 N+4 N+2 N N+5 N+3 N+1 N+4 N+2 N N+5 N+3 N+1 N+6 N+2 N N+7 N+3 N+1 N+6 N+2 N N+7 N+3 N+1 N+8 N+4 N+2 N+9 N+5 N+3 N+8 N+4 N+2 N+9 N+5 N+3 N + 10 N+4 N+2 N + 11 N+5 N+3 N + 10 N+4 N+2 N + 11 N+5 N+3 N + 12 N+6 N+2 N + 13 N+7 N+3 N + 12 N+6 N+2 N + 13 N+7 N+3 N + 14 N+6 N+2 N + 15 N+7 N+3 N + 14 N+6 N+2 N + 15 N+7 N+3 Complex (I/Q) Outputs (Complex to Real Disabled) HB2 FIR + HB3 FIR + HB2 HB4 FIR + HB3 FIR + HB1 FIR HB1 FIR FIR + HB1 FIR HB2 FIR + HB1 FIR (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 16) N N N N N+1 N+1 N+1 N+1 N N N N N+1 N+1 N+1 N+1 N+2 N N N N+3 N+1 N+1 N+1 N+2 N N N N+3 N+1 N+1 N+1 N+4 N+2 N N N+5 N+3 N+1 N+1 N+4 N+2 N N N+5 N+3 N+1 N+1 N+6 N+2 N N N+7 N+3 N+1 N+1 N+6 N+2 N N N+7 N+3 N+1 N+1 N+8 N+4 N+2 N N+9 N+5 N+3 N+1 N+8 N+4 N+2 N N+9 N+5 N+3 N+1 N + 10 N+4 N+2 N N + 11 N+5 N+3 N+1 N + 10 N+4 N+2 N N + 11 N+5 N+3 N+1 N + 12 N+6 N+2 N N + 13 N+7 N+3 N+1 N + 12 N+6 N+2 N N + 13 N+7 N+3 N+1 N + 14 N+6 N+2 N N + 15 N+7 N+3 N+1 N + 14 N+6 N+2 N N + 15 N+7 N+3 N+1 DCM = decimation. Table 12. DDC Samples When Chip Decimation Ratio = 2 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR (DCM 1 = 2) (DCM1 = 4) (DCM1 = 8) N N N N+1 N+1 N+1 N+2 N N N+3 N+1 N+1 N+4 N+2 N N+5 N+3 N+1 N+6 N+2 N N+7 N+3 N+1 N+8 N+4 N+2 N+9 N+5 N+3 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR HB1 FIR (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 16) N N N N N+1 N+1 N+1 N+1 N+2 N N N N+3 N+1 N+1 N+1 N+4 N+2 N N N+5 N+3 N+1 N+1 N+6 N+2 N N N+7 N+3 N+1 N+1 N+8 N+4 N+2 N N+9 N+5 N+3 N+1 Rev. B | Page 40 of 91 Data Sheet AD6674 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR (DCM 1 = 2) (DCM1 = 4) (DCM1 = 8) N + 10 N+4 N+2 N + 11 N+5 N+3 N + 12 N+6 N+2 N + 13 N+7 N+3 N + 14 N+6 N+2 N + 15 N+7 N+3 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR HB1 FIR (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 16) N + 10 N+4 N+2 N N + 11 N+5 N+3 N+1 N + 12 N+6 N+2 N N + 13 N+7 N+3 N+1 N + 14 N+6 N+2 N N + 15 N+7 N+3 N+1 DCM = decimation. Table 13. DDC Samples When Chip Decimation Ratio = 4 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB1 FIR (DCM1 = 8) HB1 FIR (DCM 1 = 4) N N N+1 N+1 N+2 N N+3 N+1 N+4 N+2 N+5 N+3 N+6 N+2 N+7 N+3 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR HB3 FIR + HB2 FIR + HB2 FIR + HB1 FIR (DCM1 = 4) HB1 FIR (DCM1 = 8) (DCM1 = 16) N N N N+1 N+1 N+1 N+2 N N N+3 N+1 N+1 N+4 N+2 N N+5 N+3 N+1 N+6 N+2 N N+7 N+3 N+1 DCM = decimation. Table 14. DDC Samples When Chip Decimation Ratio = 8 Real (I) Output (Complex to Real Enabled) Complex (I/Q) Outputs (Complex to Real Disabled) HB3 FIR + HB2 FIR + HB1 FIR HB4 FIR + HB3 FIR + HB2 FIR + (DCM1 = 8) HB1 FIR (DCM1 = 16) N N N+1 N+1 N+2 N N+3 N+1 N+4 N+2 N+5 N+3 N+6 N+2 N+7 N+3 HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 8) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 1 DCM = decimation. Table 15. DDC Samples When Chip Decimation Ratio = 16 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 16) Not applicable Not applicable Not applicable Not applicable 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16) N N+1 N+2 N+3 DCM -= decimation. Rev. B | Page 41 of 91 AD6674 Data Sheet For example, if the chip decimation ratio is set to decimate by 4, DDC 0 is set to use HB2 + HB1 filters (complex outputs, decimate by 4) and DDC 1 is set to use HB4 + HB3 + HB2 + HB1 filters (real outputs, decimate by 8). DDC 1 repeats its output data two times for every one DDC 0 output. The resulting output samples are shown in Table 16. Table 16. DDC Output Samples When Chip DCM 1 = 4, DDC 0 DCM1 = 4 (Complex), and DDC 1 DCM1 = 8 (Real) DDC Input Samples N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 1 Output Port I I0 (N) DDC 0 Output Port Q Q0 (N) I0 (N + 1) Q0 (N + 1) I0 (N + 2) Q0 (N + 2) I0 (N + 3) Q0 (N + 3) DCM = decimation. Rev. B | Page 42 of 91 Output Port I I1 (N) I1 (N + 1) DDC 1 Output Port Q Not applicable Not applicable Data Sheet AD6674 FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode Frequency translation is accomplished by using a 12-bit complex NCO with a digital quadrature mixer. This stage translates either a real or complex input signal from an IF to a baseband complex digital output (carrier frequency = 0 Hz). NCO and mixers are enabled. NCO output frequency can be used to digitally tune the IF frequency. 0 Hz IF (ZIF) Mode The mixers are bypassed, and the NCO is disabled. The frequency translation stage of each DDC can be controlled individually and supports four different IF modes using Bits[5:4] of the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). These IF modes are The mixers and the NCO are enabled in special downmixing by fS/4 mode to save power. Test Mode Variable IF mode 0 Hz IF or zero IF (ZIF) mode fS/4 Hz IF mode Test mode Input samples are forced to 0.999 to positive full scale. The NCO is enabled. This test mode allows the NCOs to directly drive the decimation filters. Figure 101 and Figure 102 show examples of the frequency translation stage for both real and complex inputs. NCO FREQUENCY TUNING WORD (FTW) SELECTION 12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096 I ADC + DIGITAL MIXER + NCO REAL INPUT—SAMPLED AT fS REAL ADC SAMPLING AT fS cos(wt) REAL 12-BIT NCO 90° 0° COMPLEX –sin(wt) Q BANDWIDTH OF INTEREST BANDWIDTH OF INTEREST IMAGE –fS/2 –fS/3 –fS/4 –fS/8 fS/32 –fS/32 DC –fS/16 fS/16 fS/8 fS/4 fS/3 fS/2 –6dB LOSS DUE TO NCO + MIXER 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) POSITIVE FTW VALUES –fS/32 DC fS/32 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = –1365 (0xAAB) –fS/32 NEGATIVE FTW VALUES DC fS/32 Figure 101. DDC NCO Frequency Tuning Word Selection—Real Inputs Rev. B | Page 43 of 91 12400-043 • • • • fS/4 Hz IF Mode AD6674 Data Sheet NCO FREQUENCY TUNING WORD (FTW) SELECTION 12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096 I I + I I Q Q 90° PHASE 12-BIT NCO 90° 0° Q Q ADC SAMPLING AT fS Q Q I I – –sin(wt) QUADRATURE ANALOG MIXER + 2 ADCs + QUADRATURE DIGITAL REAL MIXER + NCO COMPLEX INPUT—SAMPLED AT fS QUADRATURE MIXER ADC SAMPLING AT fS I + COMPLEX Q + BANDWIDTH OF INTEREST IMAGE DUE TO ANALOG I/Q MISMATCH –fS/3 –fS/4 fS/32 –fS/32 fS/16 –fS/16 DC –fS/8 fS/8 fS/4 fS/3 fS/2 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) POSITIVE FTW VALUES –fS/32 fS/32 12400-044 –fS/2 DC Figure 102. DDC NCO Frequency Tuning Word Selection—Complex Inputs DDC NCO + MIXER LOSS AND SFDR Setting Up the NCO FTW and POW When mixing a real input signal down to baseband, 6 dB of loss is introduced in the signal due to filtering of the negative image. An additional 0.05 dB of loss is introduced by the NCO. The total loss of a real input signal mixed down to baseband is 6.05 dB. For this reason, it is recommended that the user compensate for this loss by enabling the 6 dB of gain in the gain stage of the DDC to recenter the dynamic range of the signal within the full scale of the output bits. The NCO frequency value is given by the 12-bit twos complement number entered in the NCO FTW. Frequencies between −fS/2 and +fS/2 (fS/2 excluded) are represented using the following frequency words: When mixing a complex input signal down to baseband, the maximum value each I/Q sample can reach is 1.414 × full scale after it passes through the complex mixer. To avoid overrange of the I/Q samples and to keep the data bit-widths aligned with real mixing, 3.06 dB of loss is introduced in the mixer for complex signals. An additional 0.05 dB of loss is introduced by the NCO. The total loss of a complex input signal mixed down to baseband is −3.11 dB. The worst case spurious signal from the NCO is greater than 102 dBc SFDR for all output frequencies. NUMERICALLY CONTROLLED OSCILLATOR The AD6674 has a 12-bit NCO for each DDC that enables the frequency translation process. The NCO allows the input spectrum to be tuned to dc, where it can be effectively filtered by the subsequent filter blocks to prevent aliasing. The NCO can be set up by providing a frequency tuning word (FTW) and a phase offset word (POW). • • • 0x800 represents a frequency of −fS/2. 0x000 represents dc (frequency is 0 Hz). 0x7FF represents a frequency of +fS/2 − fS/212. The NCO frequency tuning word can be calculated using the following equation: mod( f C , f S ) NCO _ FTW = round 212 fS where: NCO_FTW is a 12-bit twos complement number representing the NCO FTW. fC is the desired carrier frequency in Hz. fS is the AD6674 sampling frequency (clock rate) in Hz. mod( ) is a remainder function. For example, mod(110,100) = 10 and for negative numbers, mod(–32,10) = −2. round( ) is a rounding function. For example, round(3.6) = 4 and for negative numbers, round(–3.4) = −3. Note that this equation applies to the aliasing of signals in the digital domain (that is, aliasing introduced when digitizing analog signals). Rev. B | Page 44 of 91 Data Sheet AD6674 For example, if the ADC sampling frequency (fS) is 1250 MSPS and the carrier frequency (fC) is 416.667 MHz, then mod( 416.667,1250 ) NCO _ FTW = round 212 = 1365 MHz 1250 Use the following two methods to synchronize multiple PAWs within the chip. • This, in turn, converts to 0x555 in the 12-bit twos complement representation for NCO_FTW. The actual carrier frequency is calculated based on the following equation: fC _ ACTUAL = NCO _ FTW × f S = 416.56 MHz 212 • A 12-bit POW is available for each NCO to create a known phase relationship between multiple AD6674 chips or individual DDC channels inside one AD6674 chip. The following procedure must be followed to update the FTW and/or POW registers to ensure proper operation of the NCO: 1. 2. 3. Write to the FTW registers for all the DDCs. Write to the POW registers for all the DDCs. Synchronize the NCOs either through the DDC NCO soft reset bit (Register 0x300[4]) accessible through the SPI or through the assertion of the SYSREF± pin. It is important to note that the NCOs must be synchronized either through the SPI or through the SYSREF± pin after all writes to the FTW or POW registers have completed. This is necessary to ensure the proper operation of the NCO. NCO Synchronization Each NCO contains a separate phase accumulator word (PAW) that determines the instantaneous phase of the NCO. The initial reset value of each PAW is determined by the POW. The phase increment value of each PAW is determined by the FTW See the Setting Up the NCO FTW and POW section for more information. Using the SPI. Use the DDC NCO soft reset bit in the DDC synchronization control register (Register 0x300[4]) to reset all the PAWs in the chip. This is accomplished by setting the DDC NCO soft reset bit high and then setting this bit low. Note that this method can only be used to synchronize DDC channels within the same AD6674 chip. Using the SYSREF± pin. When the SYSREF± pin is enabled in the SYSREF± control registers (Register 0x120 and Register 0x121) and the DDC synchronization is enabled in the DDC synchronization control register (Register 0x300[1:0]), any subsequent SYSREF± event resets all the PAWs in the chip. Note that this method can be used to synchronize DDC channels within the same AD6674 chip or DDC channels within separate AD6674 chips. Mixer The NCO is accompanied by a mixer. Its operation is similar to an analog quadrature mixer. It performs the downconversion of input signals (real or complex) by using the NCO frequency as a local oscillator. For real input signals, this mixer performs a real mixer operation (with two multipliers). For complex input signals, the mixer performs a complex mixer operation (with four multipliers and two adders). The mixer adjusts its operation based on the input signal (real or complex) provided to each individual channel. The selection of real or complex inputs can be controlled individually for each DDC block using Bit 7 of the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). Rev. B | Page 45 of 91 AD6674 Data Sheet FIR FILTERS GENERAL DESCRIPTION Table 17 shows the different bandwidths selectable by including different half-band filters. In all cases, the DDC filtering stage on the AD6674 provides <−0.001 dB of pass-band ripple and >100 dB of stop-band alias rejection. There are four sets of decimate by 2, low-pass, half-band, finite impulse response (FIR) filters (labeled HB1 FIR, HB2 FIR, HB3 FIR, and HB4 FIR in Figure 99) following the frequency translation stage. After the carrier of interest is tuned down to dc (carrier frequency = 0 Hz), these filters efficiently lower the sample rate, while providing sufficient alias rejection from unwanted adjacent carriers around the bandwidth of interest. Table 18 shows the amount of stop-band alias rejection for multiple pass-band ripple/cutoff points. The decimation ratio of the filtering stage of each DDC can be controlled individually through Bits[1:0] of the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). HB1 FIR is always enabled and cannot be bypassed. The HB2, HB3, and HB4 FIR filters are optional and can be bypassed for higher output sample rates. Table 17. DDC Filter Characteristics ADC Sample Rate (MSPS) 1000 750 500 1 Half Band Filter Selection HB1 HB1 + HB2 HB1 + HB2 + HB3 HB1 + HB2 + HB3 + HB4 HB1 HB1 + HB2 HB1 + HB2 + HB3 HB1 + HB2 + HB3 + HB4 HB1 HB1 + HB2 HB1 + HB2 + HB3 HB1 + HB2 + HB3 + HB4 Real Output Decimation Ratio 1 2 4 Output Sample Rate (MSPS) 1000 500 250 8 Complex (I/Q) Output Output Sample Rate Decimation (MSPS) Ratio 2 4 8 500 (I) + 500 (Q) 250 (I) + 250 (Q) 125 (I) + 125 (Q) Alias Protected Bandwidth (MHz) 385.0 192.5 96.3 125 16 62.5 (I) + 62.5 (Q) 48.1 10 1 2 4 750 375 187.5 2 4 8 375 (I) + 375 (Q) 187.5 (I) + 187.5 (Q) 93.75 (I) + 93.75 (Q) 288.8 144.4 72.2 1 4 7 8 93.75 16 46.875 (I) + 46.875 (Q) 36.1 10 1 2 4 500 250 125 2 4 8 250 (I) + 250 (Q) 125 (I) + 125 (Q) 62.5 (I) + 62.5 (Q) 192.5 96.3 48.1 1 4 7 8 62.5 16 31.25 (I) + 31.25 (Q) 24.1 10 Ideal SNR Improvement 1 (dB) 1 4 7 PassBand Ripple (dB) <−0.001 Alias Rejection (dB) >100 Ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(fS/2)). Table 18. DDC Filter Alias Rejection Alias Rejection (dB) >100 90 85 63.3 25 19.3 10.7 1 Pass-Band Ripple/Cutoff Point (dB) <−0.001 <−0.001 <−0.001 <−0.006 −0.5 −1.0 −3.0 Alias Protected Bandwidth for Real (I) Outputs 1 <38.5% × fOUT <38.7% × fOUT <38.9% × fOUT <40% × fOUT 44.4% × fOUT 45.6% × fOUT 48% × fOUT fOUT = ADC input sample rate ÷ DDC decimation. Rev. B | Page 46 of 91 Alias Protected Bandwidth for Complex (I/Q) Outputs <77% × fOUT <77.4% × fOUT <77.8% × fOUT <80% × fOUT 88.8% × fOUT 91.2% × fOUT 96% × fOUT Data Sheet AD6674 HALF-BAND FILTERS Table 20. HB3 Filter Coefficients The AD6674 offers four half-band filters to enable digital signal processing of the ADC converted data. These half-band filters are bypassable and can be individually selected. HB3 Coefficient Number C1, C11 C2, C10 C3, C9 C4, C8 C5, C7 C6 Table 19. HB4 Filter Coefficients HB4 Coefficient Number C1, C11 C2, C10 C3, C9 C4, C8 C5, C7 C6 Normalized Coefficient 0.006042 0 −0.049316 0 0.293273 0.500000 Decimal Coefficient (15-Bit) 99 0 −808 0 4805 8192 0 –20 –40 –60 –80 –100 –120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 NORMALIZED FREQUENCY (× π RAD/SAMPLE) Figure 104. HB3 Filter Response 0 HB2 Filter –20 MAGNITUDE (dB) Decimal Coefficient (18-Bit) 859 0 −6661 0 38,570 65,536 12400-046 The first decimate by 2, half-band, low-pass, FIR filter (HB4) uses an 11-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB4 filter is only used when complex outputs (decimate by 16) or real outputs (decimate by 8) are enabled; otherwise, it is bypassed. Table 19 and Figure 103 show the coefficients and response of the HB4 filter. MAGNITUDE (dB) HB4 Filter Normalized Coefficient 0.006554 0 −0.050819 0 0.294266 0.500000 The third decimate by 2, half-band, low-pass, FIR filter (HB2) uses a 19-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. –40 –60 The HB2 filter is only used when complex or real outputs (decimate by 4, 8, or 16) is enabled; otherwise, it is bypassed. –80 Table 21 and Figure 105 show the coefficients and response of the HB2 filter. –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 NORMALIZED FREQUENCY (× π RAD/SAMPLE) 12400-045 –120 Figure 103. HB4 Filter Response HB3 Filter The second decimate by 2, half-band, low-pass, FIR filter (HB3) uses an 11-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB3 filter is only used when complex outputs (decimate by 8 or 16) or real outputs (decimate by 4 or 8) are enabled; otherwise, it is bypassed. Table 20 and Figure 104 show the coefficients and response of the HB3 filter. Table 21. HB2 Filter Coefficients HB2 Coefficient Number C1, C19 C2, C18 C3, C17 C4, C16 C5, C15 C6, C14 C7, C13 C8, C12 C9, C11 C10 Rev. B | Page 47 of 91 Normalized Coefficient 0.000614 0 −0.005066 0 0.022179 0 −0.073517 0 0.305786 0.500000 Decimal Coefficient (19-Bit) 161 0 −1328 0 5814 0 −19,272 0 80,160 131,072 Data Sheet 0 –20 –20 –40 –60 –80 –40 –60 –80 –100 –100 –120 –120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 NORMALIZED FREQUENCY (× π RAD/SAMPLE) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 NORMALIZED FREQUENCY (× π RAD/SAMPLE) Figure 105. HB2 Filter Response 12400-048 MAGNITUDE (dB) 0 12400-047 MAGNITUDE (dB) AD6674 Figure 106. HB1 Filter Response HB1 Filter DDC GAIN STAGE The fourth and final decimate by 2, half-band, low-pass, FIR filter (HB1) uses a 55-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB1 filter is always enabled and cannot be bypassed. Table 22 and Figure 106 show the coefficients and response of the HB1 filter. Each DDC contains an independently controlled gain stage. The gain is selectable as either 0 dB or 6 dB. When mixing a real input signal down to baseband, it is recommended that the user enable the 6 dB of gain to recenter the dynamic range of the signal within the full scale of the output bits. Table 22. HB1 Filter Coefficients HB1 Coefficient Number C1, C55 C2, C54 C3, C53 C4, C52 C5, C51 C6, C50 C7, C49 C8, C48 C9, C47 C10, C46 C11, C45 C12, C44 C13, C43 C14, C42 C15, C41 C16, C40 C17, C39 C18, C38 C19, C37 C20, C36 C21, C35 C22, C34 C23, C33 C24, C32 C25, C31 C26, C30 C27, C29 C28 Normalized Coefficient −0.000023 0 0.000097 0 −0.000288 0 0.000696 0 −0.0014725 0 0.002827 0 −0.005039 0 0.008491 0 −0.013717 0 0.021591 0 −0.033833 0 0.054806 0 −0.100557 0 0.316421 0.500000 Decimal Coefficient (21-Bit) −24 0 102 0 −302 0 730 0 −1544 0 2964 0 −5284 0 8903 0 −14,383 0 22,640 0 −35,476 0 57,468 0 −105,442 0 331,792 524,288 When mixing a complex input signal down to baseband, the mixer has already recentered the dynamic range of the signal within the full scale of the output bits, and no additional gain is necessary. However, the optional 6 dB gain compensates for low signal strengths. The downsample by 2 portion of the HB1 FIR filter is bypassed when using the complex to real conversion stage. DDC COMPLEX TO REAL CONVERSION Each DDC contains an independently controlled complex to real conversion block. The complex to real conversion block reuses the last filter (HB1 FIR) in the filtering stage along with an fS/4 complex mixer to upconvert the signal. After upconverting the signal, the Q portion of the complex mixer is no longer needed and is dropped. Figure 107 shows a simplified block diagram of the complex to real conversion. Rev. B | Page 48 of 91 Data Sheet AD6674 GAIN STAGE HB1 FIR COMPLEX TO REAL ENABLE LOW-PASS FILTER I 2 0dB OR 6dB I 0 I/REAL 1 COMPLEX TO REAL CONVERSION 0dB OR 6dB I cos(wt) + 90° fS/4 REAL 0° – sin(wt) LOW-PASS FILTER 2 Q 0dB OR 6dB Q Q 12400-049 Q 0dB OR 6dB HB1 FIR Figure 107. Complex to Real Conversion Block DDC EXAMPLE CONFIGURATIONS Table 23 describes the register settings for multiple DDC example configurations. Table 23. DDC Example Configurations Chip Application Layer One DDC Chip Decimation Ratio 2 DDC Input Type Complex DDC Output Type Complex Bandwidth Per DDC 1 38.5% × fS No. of Virtual Converters Required 2 One DDC 4 Complex Complex 19.25% × fS 2 Rev. B | Page 49 of 91 Register Settings 2 0x200 = 0x01 (one DDC; I/Q selected) 0x201 = 0x01 (chip decimate by 2) 0x310 = 0x83 (complex mixer; 0 dB gain; variable IF; complex outputs; HB1 filter) 0x311 = 0x04 (DDC I input = ADC Channel A; DDC Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x200 = 0x01 (one DDC; I/Q selected) 0x201 = 0x02 (chip decimate by 4) 0x310= 0x80 (complex mixer; 0 dB gain; variable IF; complex outputs; HB2 + HB1 filters) 0x311= 0x04 (DDC I input = ADC Channel A; DDC Q input = ADC Channel B) 0x314, 0x315= FTW and POW set as required by application for DDC 0 AD6674 Data Sheet Chip Application Layer Two DDCs Chip Decimation Ratio 2 DDC Input Type Real DDC Output Type Real Bandwidth Per DDC 1 19.25%× fS No. of Virtual Converters Required 2 Two DDCs 2 Complex Complex 38.5%× fS 4 Two DDCs 4 Complex Complex 19.25% × fS 4 Two DDCs 4 Complex Real 9.63% × fS 2 Two DDCs 4 Real Real 9.63% × fS 2 Rev. B | Page 50 of 91 Register Settings 2 0x200 = 0x22 (two DDCs; I only selected) 0x201 = 0x01 (chip decimate by 2) 0x310, 0x330 = 0x48 (real mixer; 6 dB gain; variable IF; real output; HB2 + HB1 filters) 0x311 = 0x00 (DDC 0 I input = ADC Channel A; DDC 0 Q input = ADC Channel A) 0x331 = 0x05 (DDC 1 I input = ADC Channel B; DDC 1 Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x334, 0x335, 0x340, 0x341 = FTW and POW set as required by application for DDC 1 0x200 = 0x22 (two DDCs; I only selected) 0x201 = 0x01 (chip decimate by 2) 0x310, 0x330 = 0x4B (complex mixer; 6 dB gain; variable IF; complex output; HB1 filter) 0x311, 0x331 = 0x04 (DDC 0 I input = ADC Channel A; DDC 0 Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x334, 0x335, 0x340, 0x341 = FTW and POW set as required by application for DDC 1 0x200 = 0x02 (two DDCs; I/Q selected) 0x201 = 0x02 (chip decimate by 4) 0x310, 0x330 = 0x80 (complex mixer; 0 dB gain; variable IF; complex outputs; HB2 + HB1 filters) 0x311, 0x331 = 0x04 (DDC I input = ADC Channel A; DDC Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x334, 0x335, 0x340, 0x341 = FTW and POW set as required by application for DDC 1 0x200 = 0x22 (two DDCs; I only selected) 0x201 = 0x02 (chip decimate by 4) 0x310, 0x330 = 0x89 (complex mixer; 0 dB gain; variable IF; real output; HB3 + HB2 + HB1 filters) 0x311, 0x331 = 0x04 (DDC I input = ADC Channel A; DDC Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x334, 0x335, 0x340, 0x341 = FTW and POW set as required by application for DDC 1 0x200 = 0x22 (two DDCs; I only selected) 0x201 = 0x02 (chip decimate by 4) 0x310, 0x330 = 0x49 (real mixer; 6 dB gain; variable IF; real output; HB3 + HB2 + HB1 filters) 0x311 = 0x00 (DDC 0 I input = ADC Channel A; DDC 0 Q input = ADC Channel A) 0x331 = 0x05 (DDC 1 I input = ADC Channel B; DDC 1 Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x334, 0x335, 0x340, 0x341 = FTW and POW set as required by application for DDC 1 Data Sheet AD6674 Chip Application Layer Two DDCs Chip Decimation Ratio 4 DDC Input Type Real DDC Output Type Complex Bandwidth Per DDC 1 19.25% × fS No. of Virtual Converters Required 4 Two DDCs 8 Real Real 4.81% × fS 2 Four DDCs 8 Real Complex 9.63% × fS 8 Rev. B | Page 51 of 91 Register Settings 2 0x200 = 0x02 (two DDCs; I/Q selected) 0x201 = 0x02 (chip decimate by 4) 0x310, 0x330 = 0x40 (real mixer; 6 dB gain; variable IF; complex output; HB2 + HB1 filters) 0x311 = 0x00 (DDC 0 I input = ADC Channel A; DDC 0 Q input = ADC Channel A) 0x331 = 0x05 (DDC 1 I input = ADC Channel B; DDC 1 Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x334, 0x335, 0x340, 0x341 = FTW and POW set as required by application for DDC 1 0x200 = 0x22 (two DDCs; I only selected) 0x201 = 0x03 (chip decimate by 8) 0x310, 0x330 = 0x4A (real mixer; 6 dB gain; variable IF; real output; HB4 + HB3 + HB2 + HB1 filters) 0x311 = 0x00 (DDC 0 I input = ADC Channel A; DDC 0 Q input = ADC Channel A) 0x331 = 0x05 (DDC 1 I input = ADC Channel B; DDC 1 Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x334, 0x335, 0x340, 0x341 = FTW and POW set as required by application for DDC 1 0x200 = 0x03 (four DDCs; I/Q selected) 0x201 = 0x03 (chip decimate by 8) 0x310, 0x330, 0x350, 0x370 = 0x41 (real mixer; 6 dB gain; variable IF; complex output; HB3 + HB2 + HB1 filters) 0x311 = 0x00 (DDC 0 I input = ADC Channel A; DDC 0 Q input = ADC Channel A) 0x331 = 0x00 (DDC 1 I input = ADC Channel A; DDC 1 Q input = ADC Channel A) 0x351 = 0x05 (DDC 2 I input = ADC Channel B; DDC 2 Q input = ADC Channel B) 0x371 = 0x05 (DDC 3 I input = ADC Channel B; DDC 3 Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x334, 0x335, 0x340, 0x341 = FTW and POW set as required by application for DDC 1 0x354, 0x355, 0x360, 0x361 = FTW and POW set as required by application for DDC 2 0x374, 0x375, 0x380, 0x381 = FTW and POW set as required by application for DDC 3 AD6674 Data Sheet Chip Application Layer Four DDCs Chip Decimation Ratio 8 DDC Input Type Real DDC Output Type Real Bandwidth Per DDC 1 4.81% × fS No. of Virtual Converters Required 4 Four DDCs 16 Real Complex 4.81% × fS 8 1 2 Register Settings 2 0x200 = 0x23 (four DDCs; I only selected) 0x201 = 0x03 (chip decimate by 8) 0x310, 0x330, 0x350, 0x370 = 0x4A (real mixer; 6 dB gain; variable IF; real output; HB4 + HB3 + HB2 + HB1 filters) 0x311 = 0x00 (DDC 0 I input = ADC Channel A; DDC 0 Q input = ADC Channel A) 0x331 = 0x00 (DDC 1 I input = ADC Channel A; DDC 1 Q input = ADC Channel A) 0x351 = 0x05 (DDC 2 I input = ADC Channel B; DDC 2 Q input = ADC Channel B) 0x371 = 0x05 (DDC 3 I input = ADC Channel B; DDC 3 Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x334, 0x335, 0x340, 0x341 = FTW and POW set as required by application for DDC 1 0x354, 0x355, 0x360, 0x361 = FTW and POW set as required by application for DDC 2 0x374, 0x375, 0x380, 0x381 = FTW and POW set as required by application for DDC 3 0x200 = 0x03 (four DDCs; I/Q selected) 0x201 = 0x04 (chip decimate by 16) 0x310, 0x330, 0x350, 0x370 = 0x42 (real mixer; 6 dB gain; variable IF; complex output; HB4 + HB3 + HB2 + HB1 filters) 0x311 = 0x00 (DDC 0 I input = ADC Channel A; DDC 0 Q input = ADC Channel A) 0x331 = 0x00 (DDC 1 I input = ADC Channel A; DDC 1 Q input = ADC Channel A) 0x351 = 0x05 (DDC 2 I input = ADC Channel B; DDC 2 Q input = ADC Channel B) 0x371 = 0x05 (DDC 3 I input = ADC Channel B; DDC 3 Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0. 0x334, 0x335, 0x040, 0x341 = FTW and POW set as required by application for DDC 1 0x354, 0x355, 0x360, 0x361 = FTW and POW set as required by application for DDC 2 0x374, 0x375, 0x380, 0x381 = FTW and POW set as required by application for DDC 3 fS is the ADC sample rate. Bandwidths listed are <−0.001 dB of pass-band ripple and >100 dB of stop-band alias rejection. The NCOs must be synchronized either through the SPI or through the SYSREF± pin after all writes to the FTW or POW registers have completed. This is necessary to ensure the proper operation of the NCO. See the NCO Synchronization section for more information. Rev. B | Page 52 of 91 Data Sheet AD6674 NOISE SHAPING REQUANTIZER (NSR) 10 0 –10 MAGNITUDE (dB) –40 –50 –70 The 19-tap, symmetrical, fixed coefficient half-band filter has low power consumption due to its polyphase implementation. Table 24 lists the coefficients of the half-band filter in low-pass mode. In high-pass mode, Coefficient C9 is multiplied by −1. The normalized coefficients used in the implementation and the decimal equivalent values of the coefficients are listed. Coefficients not listed in Table 24 are 0s. Table 24. Fixed Coefficients for Half-Band Filter Decimal Coefficient (12-Bit) 25 −47 93 −194 644 1024 Half-Band Filter Features The half-band decimating filter is designed to provide approximately 39.5% of the output sample rate in usable bandwidth (19.75% of the input sample clock). The filter provides >40 dB of rejection. The response of the half-band filter in low-pass mode is shown in Figure 108 for an input sample clock of 1000 MHz. In low-pass mode, operation is allowed in the first Nyquist zone, which includes frequencies of up to fS/2, where fS is the decimated sample rate. For example, with an input clock of 1000 MHz, the output sample rate is 500 MSPS and fS/2 = 250 MHz. 0.35 0.40 0.45 0.50 � RAD/SAMP Figure 108. Low-Pass Half-Band Filter Response The half-band filter can also be utilized in high-pass mode. The usable bandwidth remains at 39.5% of the output sample rate (19.75% of the input sample clock), which is the same as in lowpass mode). Figure 109 shows the response of the half-band filter in high-pass mode with an input sample clock of 1000 MHz. In high-pass mode, operation is allowed in the second and third Nyquist zones, which includes frequencies from fS/2 to 3 fS/2, where fS is the decimated sample rate. For example, with an input clock of 1000 MHz, the output sample rate is 500 MSPS, fS/2 = 250 MHz, and 3 fS/2 = 750 MHz. 10 0 –10 MAGNITUDE (dB) Half-Band Filter Coefficients 0.05 0.10 0.15 0.20 0.25 0.30 NORMALIZED FREQUENCY (× 12400-484 –80 0 The AD6674 decimating half-band filter reduces the input sample rate by a factor of 2 while rejecting aliases that fall into the band of interest. For an input sample clock of 1000 MHz, this reduces the output sample rate to 500 MSPS. This filter is designed to provide >40 dB of alias protection for 39.5% of the output sample rate (79% of the Nyquist band). For an ADC sample rate of 1000 MSPS, the filter provides a maximum usable bandwidth of 197.5 MHz. Normalized Coefficient 0.012207 −0.022949 0.045410 −0.094726 0.314453 0.500000 –30 –60 DECIMATING HALF-BAND FILTER Coefficient Number 0 C2, C16 C4, C14 C6, C12 C8, C10 C9 –20 –20 –30 –40 –50 –60 –70 –80 0 0.1 0.4 0.9 0.6 0.2 0.3 0.5 0.7 0.8 NORMALIZED FREQUENCY (× π RAD/SAMPLE) 1.0 12400–485 When operating the AD6674 with the NSR enabled, a decimating half-band filter that is optimized at certain input frequency bands can also be enabled. This filter offers the user the flexibility in signal bandwidth process and image rejection. Careful frequency planning can offer advantages in analog filtering preceding the ADC. The filter can function either in high-pass or low-pass mode. On the AD6674-750 and AD6674-1000, this filter is nonbypassable when the NSR is enabled. The filter can be optionally enabled on the AD6674-500 when the NSR is enabled. When operating with NSR enabled, the decimating half-band filter mode (low pass or high pass) is selected by setting Bit 7 in Register 0x41E. Figure 109. High-Pass Half-Band Filter Response NSR OVERVIEW The AD6674 features an NSR to allow higher than 9-bit SNR to be maintained in a subset of the Nyquist band. The harmonic performance of the receiver is unaffected by the NSR feature. When enabled, the NSR contributes an additional 3.0 dB of loss to the input signal, such that a 0 dBFS input is reduced to −3.0 dBFS at the output pins. This loss does not degrade the SNR performance of the AD6674. The NSR feature can be independently controlled per channel via the SPI. Rev. B | Page 53 of 91 AD6674 Data Sheet 0 –40 –60 –80 –100 21% BW Mode (>75 MHz at 375 MSPS) 0 where: f0 is the left band edge. fADC is the ADC sample rate. TW is the tuning word. 25 50 75 100 0 –40 –60 –80 –100 –140 0 where f1 is the right band edge. 75 100 –40 –60 –80 100 125 150 175 12400-266 –120 FREQUENCY (MHz) 175 28% BW Mode (>100 MHz at 375 MSPS) f0 = fADC × 0.005 × TW –140 150 Figure 112. AD6674-750, fCLOCK = 750 MHz, fS = 375 MSPS, fIN = 140.3 MHz, 21% BW Mode, Tuning Word = 58 –100 75 125 The second NSR mode offers excellent noise performance across a bandwidth that is 28% of the ADC output sample rate (56% of the Nyquist band) and can be centered by setting the NSR mode bits in the NSR mode register (Address 0x420) to 001. In this mode, the useful frequency range can be set using the 6-bit tuning word in the NSR tuning register (Address 0x422). There are 44 possible tuning words (TW, from 0 to 43); each step is 0.5% of the ADC sample rate. AIN = −1dBFS SNR = 74.0dBFS ENOB = 11.8 BITS SFDR = 92dBFS BUFFER ONTROL 1 = 1.5× –20 50 FREQUENCY (MHz) Figure 110 to Figure 112 show the typical spectrum that can be expected from the AD6674 in the 21% BW mode for three different tuning words. 0 25 12400-268 –120 f1 = f0 + 0.21 × fADC 50 175 AIN = −1dBFS SNR = 73.9dBFS ENOB = 11.9 BITS SFDR = 93dBFS BUFFER CONTROL 1 = 1.5× –20 where fCENTER is the channel center. 25 150 Figure 111. AD6674-750, fCLOCK = 750 MHz, fS = 375 MSPS, fIN = 90.3 MHz, 21% BW Mode, Tuning Word = 26 (fS/4 Tuning) fCENTER = f0 + 0.105 × fADC 0 125 FREQUENCY (MHz) AMPLITUDE (dBFS) f0 = fADC × 0.005 × TW –140 12400-267 –120 The first NSR mode offers excellent noise performance across a bandwidth that is 21% of the ADC output sample rate (42% of the Nyquist band) and can be centered by setting the NSR mode bits in the NSR mode register (Address 0x420) to 000. In this mode, set the useful frequency range using the 6-bit tuning word in the NSR tuning register (Address 0x422). There are 59 possible tuning words (TW), from 0 to 58; each step is 0.5% of the ADC sample rate. AMPLITUDE (dBFS) AIN = −1dBFS SNR = 74.0dBFS ENOB = 11.8 BITS SFDR = 95dBFS BUFFER ONTROL 1 = 1.5× –20 AMPLITUDE (dBFS) Two different bandwidth modes are provided; select the mode from the SPI port. In each of the two modes, the center frequency of the band can be tuned such that IFs can be placed anywhere in the Nyquist band. The NSR feature is enabled by default on the AD6674. The bandwidth and mode of the NSR operation are selected by setting the appropriate bits in Register 0x420 and Register 0x422. By selecting the appropriate profile and mode bits in these two registers, the NSR feature can be enabled for the desired mode of operation. Figure 110. AD6674-750, fCLOCK = 750 MHz, fS = 375 MSPS, fIN = 10.3 MHz, 21% BW Mode, Tuning Word = 0 where: f0 is the left band edge. fADC is the ADC sample rate. TW is the tuning word. fCENTER = f0 + 0.14 × fADC where fCENTER is the channel center. f1 = f0 + 0.28 × fADC where f1 is the right band edge. Rev. B | Page 54 of 91 Data Sheet AD6674 0 Figure 113 to Figure 115 show the typical spectrum that can be expected from the AD6674 in the 28% BW mode for three different tuning words. AIN = −1dBFS SNR = 73.0dBFS ENOB = 11.3 BITS SFDR = 93dBFS BUFFER CONTROL 1 = 1.5× –20 –40 –60 –40 –60 –80 –80 –120 –100 –140 0 25 50 75 100 125 150 175 FREQUENCY (MHz) –140 0 25 50 75 100 125 FREQUENCY (MHz) 150 175 12400-269 –120 12400-270 –100 Figure 114. AD6674-750, fCLOCK = 750 MHz, fS = 375 MSPS, fIN = 90.3 MHz, 28% BW Mode, Tuning Word = 19 (fS/4 Tuning) 0 Figure 113. AD6674-750, fCLOCK = 750 MHz, fS = 375 MSPS, fIN = 10.3 MHz, 28% BW Mode, Tuning Word = 0 AIN = −1dBFS SNR = 72.5dBFS ENOB = 11.3 BITS SFDR = 94dBFS BUFFER CONTROL 1 = 1.5× AMPLITUDE (dBFS) –20 –40 –60 –80 –100 –120 –140 0 25 50 75 100 125 FREQUENCY (MHz) 150 175 12400-271 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 AIN = −1dBFS SNR = 72.4dBFS ENOB = 11.2 BITS SFDR = 96dBFS BUFFER CONTROL 1 = 1.5× –20 Figure 115. AD6674-750, fCLOCK = 750 MHz, fS = 375 MSPS, fIN = 140.3 MHz, 28% BW Mode, Tuning Word = 43 Rev. B | Page 55 of 91 AD6674 Data Sheet VARIABLE DYNAMIC RANGE (VDR) The AD6674 features a VDR digital processing block to allow up to a 14-bit dynamic range to be maintained in a subset of the Nyquist band. Across the full Nyquist band, a minimum 9-bit dynamic range is available at all times. This operation is suitable for applications such as DPD processing. The harmonic performance of the receiver is unaffected by this feature. When enabled, VDR does not contribute loss to the input signal but operates by effectively changing the output resolution at the output pins. This feature can be independently controlled per channel via the SPI. The VDR block operates in either complex or real mode. In complex mode, VDR has selectable bandwidths of 25% and 43% of the output sample rate. In real mode, the bandwidth of operation is limited to 25% of the output sample rate. The bandwidth and mode of the VDR operation are selected by setting the appropriate bits in Register 0x430. When the VDR block is enabled, input signals that violate a defined mask (signified by gray shaded areas in Figure 116) result in the reduction of the output resolution of the AD6674. The VDR block analyzes the peak value of the aggregate signal level in the disallowed zones to determine the reduction of the output resolution. To indicate that the AD6674 is reducing output, the resolution VDR punish bits and/or a VDR high/low resolution bit can optionally be inserted into the output data stream as control bits by programming the appropriate value into Register 0x559 and Register 0x55A. Up to two control bits can be used without the need to change the converter resolution parameter, N. Up to three control bits can be used, but if using three, the converter resolution parameter, N, must be changed to 13. The VDR high/low resolution bit can be programmed into either of the three available control bits and simply indicates if VDR is reducing output resolution (bit value is a 1), or if full resolution is available (bit value is a 0). Enable the two punish bits to give a clearer indication of the available resolution of the sample. To decode these two bits, see Table 25. Table 25. VDR Reduced Output Resolution Values VDR Punish Bits[1:0] 00 01 10 11 Output Resolution (Bits) 14 13 12 or 11 10 or 9 The frequency zones of the mask are defined by the bandwidth mode selected in Register 0x430. The upper amplitude limit for input signals located in these frequency zones is −30 dBFS. If the input signal level in the disallowed frequency zones goes above an amplitude level of –30 dBFS (into the gray shaded areas), the VDR block triggers a reduction in the output resolution, as shown in Figure 116. The VDR block engages and begins limiting output resolution gradually as the signal amplitudes increase in the mask regions. As the signal amplitude level increases into the mask regions, the output resolution is gradually lowered. For every 6 dB increase in signal level above −30 dBFS, one bit of output resolution is discarded from the output data by the VDR block, as shown in Table 26. These zones can be tuned within the Nyquist band by setting Bits[3:0] in Register 0x434 to determine the VDR center frequency (fVDR). The VDR center frequency in complex mode can be adjusted from 1/16 fS to 15/16 fS in 1/16 fS steps. In real mode, fVDR can be adjusted from 1/8 fS to 3/8 fS in 1/16 fS steps. Table 26. VDR Reduced Output Resolution Values Signal Amplitude Violating Defined VDR Mask Amplitude ≤ −30 dBFS −30 dBFS < amplitude ≤ −24 dBFS −24 dBFS < amplitude ≤ −18 dBFS −18 dBFS < amplitude ≤ −12 dBFS −12 dBFS < amplitude ≤ −6 dBFS −6 dBFS < amplitude ≤ 0 dBFS Output Resolution (Bits) 14 13 12 11 10 9 dBFS 0 fS 0 INTERMODULATION PRODUCTS < –30dBFS fS INTERMODULATION PRODUCTS > –30dBFS Figure 116. VDR Operation—Reduction in Output Resolution Rev. B | Page 56 of 91 12400-124 –30 Data Sheet AD6674 VDR REAL MODE VDR COMPLEX MODE The real mode of VDR works over a bandwidth of 25% of the sample rate (50% of the Nyquist band). The output bandwidth of the AD6674 can be 25% only when operating in real mode. Figure 117 shows the frequency zones for the 25% bandwidth real output VDR mode tuned to a center frequency (fVDR) of fS/4 (tuning word = 0x04). The frequency zones where the amplitude may not exceed −30 dBFS are the upper and lower portions of the Nyquist band signified by the red shaded areas. The complex mode of VDR works with selectable bandwidths of 25% of the sample rate (50% of the Nyquist band) and 43% of the sample rate (86% of the Nyquist band). Figure 118 and Figure 119 show the frequency zones for VDR in the complex mode. When operating VDR in complex mode, place I input signal data on Channel A and place Q input signal data on Channel B. dBFS Figure 118 shows the frequency zones for the 25% bandwidth VDR mode with a center frequency of fS/4 (tuning word = 0x04). The frequency zones where the amplitude may not exceed –30 dBFS are the upper and lower portions of the Nyquist band extending into the complex domain. dBFS –30 0 0 1/8 fS 3/8 fS 1/2 fS 12400-125 –1/2 fS The center frequency (fVDR) of the VDR function can be tuned within the Nyquist band from 1/8 fS to 3/8 fS in 1/16 fS steps. In real mode, Tuning Word 2 (0x02) through Tuning Word 6 (0x06) are valid. Table 27 shows the relative frequency values, and Table 28 shows the absolute frequency values based on a sample rate of 737.28 MSPS. Table 27. VDR Tuning Words and Relative Frequency Values, 25% BW, Real Mode Lower Band Edge 0 1/16 fS 1/8 fS 3/16 fS 1/4 fS Center Frequency 1/8 fS 3/16 fS 1/4 fS 5/16 fS 3/8 fS Upper Band Edge 1/4 fS 5/16 fS 3/8 fS 7/16 fS 1/2 fS Table 28. VDR Tuning Words and Absolute Frequency Values, 25% BW, Real Mode with fS = 737.28 MSPS Tuning Word 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) Lower Band Edge (MHz) 0 46.08 92.16 138.24 184.32 Center Frequency (MHz) 92.16 138.24 184.32 230.40 276.48 3/8 fS 1/2 fS Figure 118. 25% VDR Bandwidth, Complex Mode Figure 117. 25% VDR Bandwidth, Real Mode Tuning Word 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 1/8 fS 12400-126 –30 Upper Band Edge (MHz) 184.32 230.40 276.48 322.56 368.64 The center frequency (fVDR) of the VDR function can be tuned within the Nyquist band from 0 to 15/16 fS in 1/16 fS steps. In complex mode, Tuning Word 0 (0x00) through Tuning Word 15 (0x0F) are valid. Table 29 and Table 30 show the tuning words and frequency values for the 25% complex mode. Table 29 shows the relative frequency values, and Table 30 shows the absolute frequency values based on a sample rate of 737.28 MSPS. Table 29. VDR Tuning Words and Relative Frequency Values, 25% BW, Complex Mode Tuning Word 0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 7 (0x07) 8 (0x08) 9 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) 13 (0x0D) 14 (0x0E) 15 (0x0F) Rev. B | Page 57 of 91 Lower Band Edge –1/8 fS –1/16 fS 0 1/16 fS 1/8 fS 3/16 fS 1/4 fS 5/16 fS 3/8 fS 7/16 fS 1/2 fS 9/16 fS 5/8 fS 11/16 fS 3/4 fS 13/16 fS Center Frequency 0 1/16 fS 1/8 fS 3/16 fS 1/4 fS 5/16 fS 3/8 fS 7/16 fS 1/2 fS 9/16 fS 5/8 fS 11/16 fS 3/4 fS 13/16 fS 7/8 fS 15/16 fS Upper Band Edge 1/8 fS 3/16 fS 1/4 fS 5/16 fS 3/8 fS 7/16 fS 1/2 fS 9/16 fS 5/8 fS 11/16 fS 3/4 fS 13/16 fS 7/8 fS 15/16 fS fS 17/16 fS AD6674 Data Sheet Table 31. VDR Tuning Words and Relative Frequency Values, 43% BW, Complex Mode Table 30. VDR Tuning Words and Absolute Frequency Values, 25% BW, Complex Mode (fS = 737.28 MSPS) Lower Band Edge (MHz) −92.16 −46.08 0.00 46.08 92.16 138.24 184.32 230.40 276.48 322.56 368.64 414.72 460.80 506.88 552.96 599.04 Tuning Word 0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 7 (0x07) 8 (0x08) 9 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) 13 (0x0D) 14 (0x0E) 15 (0x0F) Center Frequency (MHz) 0.00 46.08 92.16 138.24 184.32 230.40 276.48 322.56 368.64 414.72 460.80 506.88 552.96 599.04 645.12 691.20 Upper Band Edge (MHz) 92.16 138.24 184.32 230.40 276.48 322.56 368.64 414.72 460.80 506.88 552.96 599.04 645.12 691.20 737.28 783.36 Tuning Word 0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 7 (0x07) 8 (0x08) 9 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) 13 (0x0D) 14 (0x0E) 15 (0x0F) Table 31 and Table 32 show the tuning words and frequency values for the 43% complex mode. Table 31 shows the relative frequency values, and Table 32 shows the absolute frequency values based on a sample rate of 737.28 MSPS. Figure 119 shows the frequency zones for the 43% BW VDR mode with a center frequency (fVDR) of fS/4 (tuning word = 0x04). The frequency zones where the amplitude may not exceed –30 dBFS are the upper and lower portions of the Nyquist band extending into the complex domain. –1/2 fS 0 1/29 fS 1/4 fS 1/2 fS 20/43 fS Figure 119. 43% VDR Bandwidth, Complex Mode 12400-127 dBFS Lower Band Edge (MHz) –14/65 fS –11/72 fS –1/11 fS –1/36 fS 1/29 fS 7/72 fS 4/25 fS 2/9 fS 2/7 fS 25/72 fS 34/83 fS 17/36 fS 23/43 fS 43/72 fS 31/47 fS 13/18 fS Center Frequency (MHz) 0 1/16 fS 1/8 fS 3/16 fS 1/4 fS 5/16 fS 3/8 fS 7/16 fS 1/2 fS 9/16 fS 5/8 fS 11/16 fS 3/4 fS 13/16 fS 7/8 fS 15/16 fS Upper Band Edge (MHz) 14/65 fS 5/18 fS 16/47 fS 29/72 fS 20/43 fS 19/36 fS 49/83 fS 47/72 fS 5/7 fS 7/9 fS 21/25 fS 65/72 fS 28/29 fS 37/36 fS 12/11 fS 83/72 fS Table 32. VDR Tuning Words and Absolute Frequency Values, 43% BW, Complex Mode (fS = 737.28 MSPS) Tuning Word 0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 7 (0x07) 8 (0x08) 9 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) 13 (0x0D) 14 (0x0E) 15 (0x0F) Rev. B | Page 58 of 91 Lower Band Edge (MHz) −158.80 −112.64 −67.03 −20.48 25.42 71.68 117.96 163.84 210.65 256.00 302.02 348.16 394.36 440.32 486.29 532.48 Center Frequency (MHz) 0.00 46.08 92.16 138.24 184.32 230.40 276.48 322.56 368.64 414.72 460.80 506.88 552.96 599.04 645.12 691.20 Upper Band Edge (MHz) 158.80 204.80 250.99 296.96 342.92 389.12 435.26 481.28 526.63 573.44 619.32 665.60 711.86 757.76 804.31 849.92 Data Sheet AD6674 DIGITAL OUTPUTS INTRODUCTION TO JESD204B INTERFACE • The AD6674 digital outputs are designed to the JEDEC Standard No. JESD204B serial interface for data converters. JESD204B is a protocol to link the AD6674 to a digital processing device over a serial interface with lane rates of up to 12.5 Gbps. The benefits of the JESD204B interface over LVDS include a reduction in required board area for data interface routing, and enabling smaller packages for converter and logic devices. • • • JESD204B OVERVIEW K is the number of frames per multiframe (AD6674 value = 4, 8, 12, 16, 20, 24, 28, or 32 ) S is the number of samples transmitted per single converter per frame cycle (AD6674 value = set automatically based on L, M, F, and N΄) HD is high density mode (AD6674 = set automatically based on L, M, F, and N΄) CF is the number of control words per frame clock cycle per converter device (AD6674 value = 0) The JESD204B data transmit block assembles the parallel data from the ADC into frames and uses 8B/10B encoding as well as optional scrambling to form serial output data. Lane synchronization is supported through the use of special control characters during the initial establishment of the link. Additional control characters are embedded in the data stream to maintain synchronization thereafter. A JESD204B receiver is required to complete the serial link. For additional details on the JESD204B interface, users are encouraged to refer to the JESD204B standard. Figure 120 shows a simplified block diagram of the AD6674 JESD204B link. By default, the AD6674 is configured to use two converters and four lanes. Converter A data is output to SERDOUT0±/SERDOUT1±, and Converter B is output to SERDOUT2±/SERDOUT3±. The AD6674 allows other configurations such as combining the outputs of both converters onto a single lane or changing the mapping of the A and B digital output paths. These modes are set up through a quick configuration register in the SPI register map, along with additional customizable options. The AD6674 JESD204B data transmit block maps up to two physical ADCs or up to eight virtual converters (when DDCs are enabled) over a link. A link can be configured to use one, two, or four JESD204B lanes. The JESD204B specification refers to a number of parameters to define the link and these parameters must match between the JESD204B transmitter (AD6674 output) and receiver (logic device input). By default in the AD6674, the 14-bit converter word from each converter is broken into two octets (eight bits of data). Bit 13 (MSB) through Bit 6 are in the first octet. The second octet contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits can be configured as zeros or a pseudorandom number (PN) sequence. The tail bits can also be replaced with control bits indicating an overrange, SYSREF±, signal monitor output, or fast detect output. The JESD204B link is described according to the following parameters: • • • • • • L is the number of lanes per converter device (lanes per link) (AD6674 value = 1, 2, or 4) M is the number of converters per converter device (virtual converters per link) (AD6674 value = 1, 2, 4, or 8) F is the number of octets per frame (AD6674 value = 1, 2, 4, 8, or 16) N΄ is the number of bits per sample (JESD204B word size) (AD6674 value = 8 or 16) N is the converter resolution (AD6674 value = 7 to 16) CS is the number of control bits per sample (AD6674 value = 0, 1, 2, or 3) The two resulting octets can be scrambled. Scrambling is optional; however, it is recommended to avoid spectral peaks when transmitting similar digital data patterns. The scrambler uses a self synchronizing, polynomial-based algorithm defined by the equation 1 + x14 + x15. The descrambler in the receiver must be a self synchronizing version of the scrambler polynomial. The two octets are then encoded with an 8B/10B encoder. The 8B/10B encoder works by taking eight bits of data (an octet) and encoding them into a 10-bit symbol. Figure 121 shows how the 14-bit data is transferred from the ADC, the tail bits are added, the two octets are scrambled, and the octets are encoded into two 10-bit symbols. Figure 121 illustrates the default data format. Rev. B | Page 59 of 91 AD6674 Data Sheet CONVERTER 0 CONVERTER A INPUT ADC A CONVERTER B INPUT ADC B NOISE SHAPING REQUANTIZER MUX/ FORMAT (SPI REG 0x561, REG 0x564) JESD204B LINK CONTROL (L, M, F) (SPI REG 0x570) LANE MUX AND MAPPING (SPI REG 0x5B0, REG 0x5B2, REG 0x5B3, REG 0x5B5, REG 0x5B6) NOISE SHAPING REQUANTIZER SERDOUT0–, SERDOUT0+ SERDOUT1–, SERDOUT1+ SERDOUT2–, SERDOUT2+ SERDOUT3–, SERDOUT3+ 12400-050 CONVERTER 1 SYSREF± SYNCINB± Figure 120. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x200 = 0x07) LSB CONTROL BITS MSB TAIL BITS REG 0x571[6] LSB A13 A12 A11 A10 A9 A8 A6 A7 MSB A5 A4 A3 A2 A1 A0 C2 T LSB S7 S6 S5 S4 S3 S2 S1 S0 a b .... OCTET1 JESD204B SAMPLE CONSTRUCTION SERDOUT0± SERDOUT1± SERIALIZER 8B/10B ENCODER OCTET0 OCTET0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SCRAMBLER 1 + x14 + x15 (OPTIONAL) i j a b .... SYMBOL0 a b c d e f g h i j a b c d e f g h i j i j SYMBOL1 S7 S6 S5 S4 S3 S2 S1 S0 12400-587 ADC FRAME CONSTRUCTION OCTET1 ADC TEST PATTERNS (REG 0x550, REG 0x551 TO REG 0x558) MSB JESD204B DATA LINK LAYER TEST PATTERNS REG 0x574[2:0] JESD204B INTERFACE TEST PATTERNS (REG 0x573, REG 0x551 TO REG 0x558) JESD204B LONG TRANSPORT TEST PATTERN REG 0x571[5] C2 C1 C0 Figure 121. ADC Output Datapath Showing Data Framing TRANSPORT LAYER SAMPLE CONSTRUCTION FRAME CONSTRUCTION SCRAMBLER ALIGNMENT CHARACTER GENERATION 8-BIT/10-BIT ENCODER PHYSICAL LAYER CROSSBAR MUX SERIALIZER Tx OUTPUT 12400-052 PROCESSED SAMPLES FROM ADC DATA LINK LAYER SYSREF± SYNCINB± Figure 122. Data Flow FUNCTIONAL OVERVIEW Data Link Layer The block diagram in Figure 122 shows the flow of data through the JESD204B hardware from the sample input to the physical output. The processing can be divided into layers that are derived from the open-source initiative (OSI) model that is widely used to describe the abstractions layers of communications systems. These are the transport layer, data link layer, and physical layer (serializer and output driver). The data link layer is responsible for the low level functions of passing data across the link. These include optionally scrambling the data, inserting control characters for multichip synchronization/lane alignment/monitoring, and encoding 8-bit octets into 10-bit symbols. The data link layer is also responsible for sending the ILAS, which contains the link configuration data, used by the receiver to verify the settings in the transport layer. Transport Layer The transport layer packs the data (consisting of samples and optional control bits) into JESD204B frames, which are mapped to 8-bit octets that are sent to the data link layer. The transport layer mapping is controlled by rules derived from the link parameters. Tail bits are added to fill gaps where required. Use the following equation to determine the number of tail bits within a sample (JESD204B word): T = N΄ − N − CS Physical Layer The physical layer consists of the high speed circuitry clocked at the serial clock rate. In this section, parallel data is converted into one, two, or four lanes of high speed differential serial data. JESD204B LINK ESTABLISHMENT The AD6674 JESD204B Tx interface operates in Subclass 1 as defined in the JEDEC Standard No. 204B (July 2011) specification. The link establishment process is divided into the following steps: code group synchronization, ILAS, and user data. Rev. B | Page 60 of 91 Data Sheet AD6674 Code Group Synchronization (CGS) and SYNCINB± Code group synchronization (CGS) is the process by which the JESD204B receiver finds the boundaries between the 10-bit symbols in the stream of data. During the CGS phase, the JESD204B transmit block transmits /K28.5/ characters. The receiver must locate /K28.5/ characters in its input data stream using clock and data recovery (CDR) techniques. The receiver issues a synchronization request by asserting the SYNCINB± pin of the AD6674 low. The JESD204B Tx begins sending /K/ characters. After the receiver has synchronized, it waits for the correct reception of at least four consecutive /K/ symbols. It then deasserts SYNCINB±. The AD6674 then transmits an ILAS on the following LMFC boundary. Multiframe 1: Begins with an /R/ character [K28.0] and ends with an /A/ character (K28.3). Multiframe 2: Begins with an /R/ character followed by a /Q/ (K28.4) character, followed by link configuration parameters over 14 configuration octets (see Table 33), and ends with an /A/ character. Many of the parameter values are of the value − 1 notation. Multiframe 3: Begins with an /R/ character (K28.0) and ends with an /A/ character (K28.3). Multiframe 4: Begins with an /R/ character (K28.0) and ends with an /A/ character (K28.3). User Data and Error Detection Initial Lane Alignment Sequence (ILAS) The ILAS phase follows the CGS phase and begins on the next LMFC boundary. The ILAS consists of four multiframes, with an /R/ character marking the beginning and an /A/ character marking the end. The ILAS begins by sending an /R/ character followed by 0 to 255 ramp data for one multiframe. On the second multiframe the link configuration data is sent, starting with the third character. The second character is a /Q/ character to confirm that the link configuration data follows. All undefined data slots are filled with ramp data. The ILAS sequence is never scrambled. C D • • The SYNCINB± pin operation can also be controlled by the SPI. The SYNCINB± signal is a differential LVDS mode signal by default, but it can also be driven single-ended. For more information on configuring the SYNCINB± pin operation, refer to Register 0x572. The SYNCINB± pin can also be configured to run in CMOS (single-ended) mode by setting Bit 4 in Register 0x572. When running SYNCINB± in CMOS mode, connect the CMOS SYNCINB signal to Pin 21 (SYNCINB+) and leave Pin 20 (SYNCINB–) floating. D A R Q C • • For more information on the CGS phase, refer to the JEDEC Standard No. 204B (July 2011), Section 5.3.3.1. K K R D The ILAS sequence construction is shown in Figure 123. The four multiframes include the following: After the ILAS is complete, the user data is sent. Normally, in a frame all characters are user data. However, to monitor the frame clock and multiframe clock synchronization, there is a mechanism for replacing characters with /F/ or /A/ alignment characters when the data meets certain conditions. These conditions are different for unscrambled and scrambled data. The scrambling operation is enabled by default but can be disabled using the SPI. For scrambled data, any 0xFC character at the end of a frame is replaced by an /F/ and any 0x7C character at the end of a multiframe is replaced with an /A/. The JESD204B Rx checks for /F/ and /A/ characters in the received data stream and verifies that they only occur in the expected locations. If an unexpected /F/ or /A/ character is found, the receiver handles the situation by using dynamic realignment or asserting the SYNCINB± signal for more than four frames to initiate a resynchronization. For unscrambled data, if the final character of two subsequent frames is equal, the second character is replaced with an /F/ if it is at the end of a frame, and an /A/ if it is at the end of a multiframe. Insertion of alignment characters can be modified using the SPI. The frame alignment character insertion is enabled by default. For more information on the link controls, see Register 0x571 in the Memory Map section. D A R D D A R D D A D START OF ILAS START OF LINK CONFIGURATION DATA START OF USER DATA 12400-053 END OF MULTIFRAME Figure 123. Initial Lane Alignment Sequence Table 33. AD6674 Control Characters Used in JESD204B Abbreviation /R/ /A/ /Q/ /K/ /F/ 1 Control Symbol K28.0 K28.3 K28.4 K28.5 K28.7 8-Bit Value 000 11100 011 11100 100 11100 101 11100 111 11100 10-Bit Value, RD 1 = −1 001111 0100 001111 0011 001111 0010 001111 1010 001111 1000 RD is running disparity. Rev. B | Page 61 of 91 10-Bit Value, RD1 = +1 110000 1011 110000 1100 110000 1101 110000 0101 110000 0111 Description Start of multiframe Lane alignment Start of link configuration data Group synchronization Frame alignment AD6674 Data Sheet 8B/10B Encoder The 8B/10B encoder converts 8-bit octets into 10-bit symbols and inserts control characters into the stream when needed. The control characters used in JESD204B are shown in Table 33. The 8B/10B encoding ensures that the signal is dc balanced by using the same number of ones and zeros across multiple symbols. The 8B/10B interface has options that can be controlled via the SPI. These operations include bypass and invert. These options are intended to be a troubleshooting tool for the verification of the digital front end (DFE). Refer to the Memory Map section, Register 0x572[2:1], for information on configuring the 8B/10B encoder. The AD6674 digital outputs can interface with custom ASICs and FPGA receivers, providing superior switching performance in noisy environments. Single point-to-point network topologies are recommended with a single differential 100 Ω termination resistor placed as close to the receiver inputs as possible. The common mode of the digital output automatically biases itself to half the DRVDD supply of 1.2 V (VCM = 0.6 V). See Figure 125 for an example of dc coupling the outputs to the receiver logic. DRVDD 100Ω DIFFERENTIAL TRACE PAIR SERDOUTx+ 100Ω RECEIVER SERDOUTx– Digital Outputs, Timing and Controls OUTPUT SWING = 300mV p-p The AD6674 physical layer consists of drivers that are defined in the JEDEC Standard No. 204B (July 2011). The differential digital outputs are powered up by default. The drivers use a dynamic 100 Ω internal termination to reduce unwanted reflections. Figure 125. DC-Coupled Digital Output Termination Example If there is no far-end receiver termination, or if there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than six inches, and that the differential output traces be close together and at equal lengths. Place a 100 Ω differential termination resistor at each receiver input, which results in a nominal 300 mV p-p swing at the receiver (see Figure 124). Alternatively, single-ended 50 Ω termination resistors can be used. When single-ended termination is used, the termination voltage is DRVDD/2; otherwise, 0.1 μF ac coupling capacitors can be used to terminate to any single-ended voltage. Figure 126 to Figure 128, Figure 129 to Figure 131, and Figure 132 to Figure 134 show examples of the digital output data eye, time interval error (TIE) jitter histogram, and bathtub curve for one AD6674 lane running at 10 Gbps, 7.37 Gbps, and 6 Gbps, respectively. The format of the output data is twos complement by default. To change the output data format, see the Memory Map section (Register 0x561 in Table 45). VRXCM DRVDD 0.1µF 100Ω DIFFERENTIAL TRACE PAIR 50Ω 50Ω De-Emphasis SERDOUTx+ 100Ω OR RECEIVER SERDOUTx– VCM = VRXCM Figure 124. AC-Coupled Digital Output Termination Example 12400-054 0.1µF OUTPUT SWING = 300mV p-p VCM = DRVDD/2 12400-055 PHYSICAL LAYER (DRIVER) OUTPUTS De-emphasis enables the receiver eye diagram mask to be met in conditions where the interconnect insertion loss does not meet the JESD204B specification. Use the de-emphasis feature only when the receiver is unable to recover the clock due to excessive insertion loss. Under normal conditions, it is disabled to conserve power. Additionally, enabling and setting too high a de-emphasis value on a short link may cause the receiver eye diagram to fail. Use the de-emphasis setting with caution because it may increase EMI. See the Memory Map section (Register 0x5C1 to Register 0x5C5 in Table 45) for more information. PLL The PLL is used to generate the serializer clock, which operates at the JESD204B lane rate. The JESD204B lane rate control bit (Register 0x56E[4]) must be set to correspond with the lane rate. Rev. B | Page 62 of 91 Data Sheet AD6674 12400-588 12400-593 Tx EYE MASK Figure 131. Bathtub, External 100 Ω Terminations at 7.37 Gbps Figure 126. Digital Output Data Eye, External 100 Ω Terminations at 10 Gbps 12400-589 12400-594 Tx EYE MASK Figure 132. Digital Output Data Eye, External 100 Ω Terminations at 6 Gbps 12400-590 12400-595 Figure 127. Histogram, External 100 Ω Terminations at 10 Gbps Figure 133. Histogram, External 100 Ω Terminations at 6 Gbps 12400-591 12400-596 Figure 128. Bathtub, External 100 Ω Terminations at 10 Gbps 12400-592 Figure 129. Digital Output Data Eye, External 100 Ω Terminations at 7.37 Gbps Figure 130. Histogram, External 100 Ω Terminations at 7.37 Gbps Rev. B | Page 63 of 91 Figure 134. Bathtub, External 100 Ω Terminations at 6 Gbps AD6674 Data Sheet ADC A SAMPLING AT fS REAL/I REAL/Q REAL/I REAL/Q I/Q CROSSBAR MUX REAL/I REAL/Q REAL/Q ADC B SAMPLING AT fS REAL/I REAL/Q DDC 0 I I Q Q DDC 1 I I Q Q DDC 2 I I Q Q DDC 3 I I Q Q REAL/I CONVERTER 0 Q CONVERTER 1 REAL/I CONVERTER 2 Q CONVERTER 3 OUTPUT INTERFACE REAL/I CONVERTER 4 Q CONVERTER 5 REAL/I CONVERTER 6 Q CONVERTER 7 12400-059 REAL/I Figure 135. DDCs and Virtual Converter Mapping JESD204B Tx CONVERTER MAPPING CONFIGURING THE JESD204B LINK To support the different chip operating modes, the AD6674 design treats each sample stream (real or I/Q) as originating from separate virtual converters. The I/Q samples are always mapped in pairs with the I samples mapped to the first virtual converter, and the Q samples mapped to the second virtual converter. With this transport layer mapping, the number of virtual converters are the same whether a single real converter is used along with a DDC block producing I/Q outputs, or an analog downconversion is used with two real converters producing I/Q outputs. The AD6674 has one JESD204B link. It offers an easy way to set up the JESD204B link through the quick configuration register (Register 0x570). The serial outputs (SERDOUT0± to SERDOUT3±) are considered to be part of one JESD204B link. The basic parameters that determine the link setup are Figure 136 shows a block diagram of the two scenarios described for I/Q transport layer mapping. I CONVERTER 0 ADC REAL DIGITAL DOWN CONVERSION JESD204B Tx If the internal DDCs are used for on-chip digital processing, the M value represents the number of virtual converters. The virtual converter mapping setup is shown in Figure 135. 10 M × N ' × × f OUT 8 Lane Line Rate = L L LANES Q CONVERTER 1 where: I/Q ANALOG MIXING M=2 REAL Σ ADC I CONVERTER 0 90° PHASE Q f OUT = JESD204B Tx ADC Q CONVERTER 1 L LANES 12400-058 I Number of lanes per link (L) Number of converters per link (M) Number of octets per frame (F) The maximum lane rate allowed by the JESD204B specification is 12.5 Gbps. The lane rate is related to the JESD204B parameters using the following equation: DIGITAL DOWNCONVERSION M=2 REAL • • • Figure 136. I/Q Transport Layer Mapping The JESD204B Tx block for AD6674 supports up to four digital DDC blocks. Each DDC block outputs either two sample streams (I/Q) for the complex data components (real + imaginary) or one sample stream for real (I) data. The JESD204B interface can be configured to use up to eight virtual converters depending on the DDC configuration. Figure 135 shows the virtual converters and their relationship to DDC outputs when complex outputs are used. Table 34 shows the virtual converter mapping for each chip operating mode when channel swapping is disabled. f ADC _ CLOCK Decimation Ratio The decimation ratio (DCM) is the parameter programmed in Register 0x201. Use the following steps to configure the output: 1. 2. 3. 4. 5. 6. Power down the link. Select the quick configuration options. Configure detailed options. Set output lane mapping (optional). Set additional driver configuration options (optional). Power up the link. If the lane rate calculated is less than 6.25 Gbps, select the low lane rate option by programming a value of 0x10 to Register 0x56E. Rev. B | Page 64 of 91 Data Sheet AD6674 See the Example 1: ADC with DDC Option (Two ADCs + Four DDCs) section and the Example 2: ADC with NSR Option (Two ADCs + NSR) section for two examples describing which JESD204B transport layer settings are valid for a given chip mode. Table 35 and Table 36 show the JESD204B output configurations supported for both N΄ = 16 and N΄ = 8, respectively, for a given number of virtual converters. Take care to ensure that the serial lane rate for a given configuration is within the supported range of 3.125 Gbps to 12.5 Gbps. Table 34. Virtual Converter Mapping No. of Virtual Converters Supported 1 2 2 4 4 8 1 to 2 1 to 2 Chip Operating Mode (Register 0x200[3:0]) One DDC mode (0x1) One DDC mode (0x1) Two DDC mode (0x2) Two DDC mode (0x2) Four DDC mode (0x3) Four DDC mode (0x3) NSR mode (0x7) VDR mode (0x8) Chip Q Ignore (Register 0x200[5]) Real (I only) (0x1) Complex (I/Q) (0x0) Real (I only) (0x1) Complex (I/Q) (0x0) Real (I only) (0x1) Complex (I/Q) (0x0) Real or complex (0x0) Real or complex (0x0) Virtual Converter Mapping 0 DDC 0 I samples DDC 0 I samples DDC 0 I samples DDC 0 I samples DDC 0 I samples DDC 0 I samples ADC A Samples 1 Unused 2 Unused 3 Unused 4 Unused 5 Unused 6 Unused 7 Unused DDC 0 Q samples DDC 1 I samples DDC 0 Q samples DDC 1 I samples DDC 0 Q samples ADC B Samples Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused DDC 1 I samples DDC 2 I samples DDC 1 I samples Unused DDC 1 Q samples DDC 3 I samples DDC 1 Q samples Unused Unused Unused Unused Unused Unused Unused Unused Unused DDC 2 I samples Unused DDC 2 Q samples Unused DDC 3 I samples Unused DDC 3 Q samples Unused ADC A Samples ADC B Samples Unused Unused Unused Unused Unused Unused Table 35. JESD204B Output Configurations for N΄ = 16 Number of Virtual Converters Supported (Same Value as M) 1 2 4 8 JESD204B Quick Configuration (Register 0x570) 0x01 0x40 0x41 0x80 0x81 0x0A 0x49 0x88 0x89 0x13 0x52 0x91 0x1C 0x5B 0x9A JESD204B Serial Lane Rate 1 20 × fOUT 10 × fOUT 10 × fOUT 5 × fOUT 5 × fOUT 40 × fOUT 20 × fOUT 10 × fOUT 10 × fOUT 80 × fOUT 40 × fOUT 20 × fOUT 160 × fOUT 80 × fOUT 40 × fOUT JESD204B Transport Layer Settings 2 L 1 2 2 4 4 1 2 4 4 1 2 4 1 2 4 M 1 1 1 1 1 2 2 2 2 4 4 4 8 8 8 F 2 1 2 1 2 4 2 1 2 8 4 2 16 8 4 S 1 1 2 2 4 1 1 1 2 1 1 1 1 1 1 HD 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 N 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 N΄ 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 CS 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 K3 Only valid K values that are divisible by 4 are supported 1 fOUT is the output sample rate. fOUT = ADC sample rate/chip decimation. The JESD204B serial lane rate must be ≥3.125 Gbps and ≤12.5 Gbps; when the serial lane rate is ≤12.5 Gbps and ≥6.25 Gbps, the low lane rate mode must be disabled (set Bit 4 to 0x0 in Register 0x56E). When the serial lane rate is <6.25 Gbps and ≥3.125 Gbps, the low lane rate mode must be enabled (set Bit 4 to 0x1 in Register 0x56E). 2 JESD204B transport layer descriptions are as described in the JESD204B Overview section. 3 For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32. Rev. B | Page 65 of 91 AD6674 Data Sheet Table 36. JESD204B Output Configurations for N΄ = 8 Number of Virtual Converters Supported (Same Value as M) 1 2 JESD204B Quick Configuration (Register 0x570) 0x00 0x01 0x40 0x41 0x42 0x80 0x81 0x09 0x48 0x49 0x88 0x89 0x8A JESD204B Transport Layer Settings 2 Serial Lane Rate 1 10 × fOUT 10 × fOUT 5 × fOUT 5 × fOUT 5 × fOUT 2.5 × fOUT 2.5 × fOUT 20 × fOUT 10 × fOUT 10 × fOUT 5 × fOUT 5 × fOUT 5 × fOUT L 1 1 2 2 2 4 4 1 2 2 4 4 4 M 1 1 1 1 1 1 1 2 2 2 2 2 2 F 1 2 1 2 4 1 2 2 1 2 1 2 4 S 1 2 2 4 8 4 8 1 1 2 2 4 8 HD 0 0 0 0 0 0 0 0 0 0 0 0 0 N 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 N΄ 8 8 8 8 8 8 8 8 8 8 8 8 8 CS 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 K3 Only valid K values that are divisible by 4 are supported fOUT is the output sample rate. fOUT = ADC sample rate/chip decimation. The JESD204B serial lane rate must be ≥3.125 Gbps and ≤12.5 Gbps; when the serial lane rate is ≤12.5 Gbps and ≥6.25 Gbps, the low lane rate mode must be disabled (set Bit 4 to 0x0 in Register 0x56E). When the serial lane rate is <6.25 Gbps and ≥3.125 Gbps, the low lane rate mode must be enabled (set Bit 4 to 0x1 in Register 0x56E). 2 JESD204B transport layer descriptions are as described in the JESD204B Overview section. 3 For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32. 1 Example 1: ADC with DDC Option (Two ADCs + Four DDCs) Example 2: ADC with NSR Option (Two ADCs + NSR) The chip application mode is four-DDC mode (see Figure 137) with the following characteristics: The chip application mode is NSR mode (see Figure 138) with the following characteristics: • • • • • • • Two 14-bit converters at 1 GSPS Four DDCs application layer mode with complex outputs (I/Q) Chip decimation ratio = 16 DDC decimation ratio = 16 (see Table 15) The JESD204B output configuration is as follows: • • Virtual converters required = 8 (see Table 35) Output sample rate (fOUT) = 1000/16 = 62.5 MSPS • • • • • The JESD204B output configuration is as follows: • • Virtual converters required = 2 (see Table 35) Output sample rate (fOUT) = 500 MSPS Supported JESD204B output configurations (see Table 35) include Supported JESD204B output configurations (see Table 35) include • • • Two 14-bit converters at 500 MSPS NSR blocks enabled for each channel Chip decimation ratio = 1 N΄ = 16 bits N = 14 bits L = 1, M = 8, and F = 16; or L = 2, M = 8, and F = 8 (quick configuration = 0x1C or 0x5B) CS = 0 to 1 K = 32 Output serial lane rate = 10 Gbps per lane (L = 1) or 5 Gbps per lane (L = 2) For L = 1, low lane rate mode disabled For L = 2, low lane rate mode enabled Example 1 shows the flexibility in the digital and lane configurations for the AD6674. The sample rate is 1 GSPS, but the outputs are all combined into either one or two lanes depending on the I/O speed capability of the receiving device. • • • • • • • • N΄ = 16 bits N = 9 bits L = 2, M = 2, and F = 2; L = 4, M = 2, and F = 1 (quick configuration = 0x49 or 0x88) CS = 0 to 2 K = 32 Output serial lane rate = 10 Gbps per lane (L = 2) or 5 Gbps per lane (L = 4) For L = 2, low lane rate mode disabled For L = 4, low lane rate mode enabled Example 2 shows the flexibility in the digital and lane configurations for the AD6674. The sample rate is 500 MSPS, but the outputs are all combined into either two or four lanes depending on the I/O speed capability of the receiving device. Rev. B | Page 66 of 91 Data Sheet AD6674 ADC A SAMPLING AT fS REAL/I REAL/Q DDC 0 I CONVERTER 0 Q CONVERTER 1 DDC 1 I CONVERTER 2 Q CONVERTER 3 DDC 2 I CONVERTER 4 Q CONVERTER 5 DDC 3 I CONVERTER 6 Q CONVERTER 7 I/Q CROSSBAR MUX REAL/I REAL/Q 12400-061 SYSREF± ADC B SAMPLING AT fS L JESD204B LANES UP TO 10Gbps L JESD204B LANES AT UP TO 10Gbps SYNCHRONIZATION CONTROL CIRCUITS Figure 137. Two-ADC + Four-DDC Mode CMOS FAST DETECTION REAL REAL AD6674 14-BIT CORE AT 500MSPS NSR (21% OR 28% BANDWIDTH) AD6674 14-BIT CORE AT 500MSPS NSR (21% OR 28% BANDWIDTH) CONVERTER 0 AT 500MSPS CONVERTER 1 AT 500MSPS 2 TO 4 LANES AT UP TO 10Gbps FAST DETECTION 12400-177 REAL JESD204B TRANSMIT INTERFACE (JTX) REAL CMOS Figure 138. Two-ADC + NSR Mode Rev. B | Page 67 of 91 AD6674 Data Sheet MULTICHIP SYNCHRONIZATION The AD6674 has a SYSREF± input that allows the user flexible options for synchronizing the internal blocks. The SYSREF± input is a source synchronous system reference signal that enables multichip synchronization. The input clock divider, DDCs, signal monitor block, and JESD204B link can be synchronized using the SYSREF± input. For the highest level of timing accuracy, SYSREF± must meet setup and hold requirements relative to the CLK± input. The flowchart in Figure 139 describes the internal mechanism by which multichip synchronization can be achieved in the AD6674. The AD6674 supports several features that aid users in meeting the requirements for capturing a SYSREF± signal. The SYSREF± sample event is defined as either a synchronous low to high transition or a synchronous high to low transition. Additionally, the AD6674 allows the SYSREF± signal to be sampled using either the rising edge or falling edge of the CLK± input. The AD6674 also has the ability to ignore a programmable number (up to 16) of SYSREF± events. The SYSREF± control options can be selected using Register 0x120 and Register 0x121. Rev. B | Page 68 of 91 Data Sheet AD6674 START INCREMENT SYSREF± IGNORE COUNTER NO NO RESET SYSREF± IGNORE COUNTER SYSREF± ENABLED? (0x120) NO NO SYSREF± ASSERTED? YES UPDATE SETUP/HOLD DETECTOR STATUS (0x128) YES SYSREF± IGNORE COUNTER EXPIRED? (0x121) YES ALIGN CLOCK DIVIDER PHASE TO SYSREF± INPUT CLOCK DIVIDER ALIGNMENT REQUIRED? YES YES NO SYNCHRONIZATION MODE? (0x1FF) CLOCK DIVIDER AUTO ADJUST ENABLED? (0x10D) NO TIMESTAMP MODE SYSREF± TIMESTAMP DELAY (0x123) INCREMENT SYSREF± COUNTER (0x12A) CLOCK DIVIDER > 1? (0x10B) YES NO SYSREF± CONTROL BITS? (0x559, 0x55A, 0x58F) YES SYSREF± INSERTED IN JESD204B CONTROL BITS NO RAMP TEST MODE ENABLED? (0x550) NORMAL MODE YES SYSREF± RESETS RAMP TEST MODE GENERATOR BACK TO START NO YES ALIGN PHASE OF ALL INTERNAL CLOCKS (INCLUDING LMFC) TO SYSREF± SEND INVALID 8B/10B CHARACTERS (ALL 0s) SYNC~ ASSERTED NO SEND K28.5 CHARACTERS NORMAL JESD204B INITIALIZATION NO NO SIGNAL MONITOR ALIGNMENT ENABLED? (0x26F) YES YES ALIGN SIGNAL MONITOR COUNTERS DDC NCO ALIGNMENT ENABLED? (0x300) YES NO Figure 139. Multichip Synchronization Rev. B | Page 69 of 91 ALIGN DDC NCO PHASE ACCUMULATOR BACK TO START 12400-509 JESD204B LMFC ALIGNMENT REQUIRED? AD6674 Data Sheet SYSREF± SETUP/HOLD WINDOW MONITOR To assist in ensuring a valid SYSREF± capture, the AD6674 has a SYSREF± setup and hold window monitor. This feature allows the system designer to determine the location of the SYSREF± signals relative to the CLK± signals by reading back the amount of setup/hold margin on the interface through the memory map. Figure 140 and Figure 141 show both the setup and hold status values for different phases of SYSREF±. The setup detector returns the status of the SYSREF± signal before the CLK± edge and the hold detector returns the status of the SYSREF± signal after the CLK± edge. Register 0x128 stores the status of SYSREF± and lets the user know if the SYSREF± signal was successfully captured by the ADC. 0xF 0xE 0xD 0xC 0xB 0xA 0x9 REG 0x128[3:0] 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 CLK± INPUT VALID SYSREF± INPUT FLIP-FLOP HOLD (MIN) FLIP-FLOP HOLD (MIN) Figure 140. SYSREF± Setup Detector Rev. B | Page 70 of 91 12400-510 FLIP-FLOP SETUP (MIN) Data Sheet AD6674 0xF 0xE 0xD 0xC 0xB 0xA 0x9 REG 0x128[7:4] 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 CLK± INPUT SYSREF± INPUT FLIP-FLOP SETUP (MIN) FLIP-FLOP HOLD (MIN) FLIP-FLOP HOLD (MIN) 12400-511 VALID Figure 141. SYSREF± Hold Detector Table 37 shows the description of the contents of Register 0x128 and how to interpret them. Table 37. SYSREF± Setup/Hold Monitor, Register 0x128 Register 0x128[7:4] Hold Status 0x0 0x0 to 0x8 0x8 0x8 0x9 to 0xF 0x0 Register 0x128[3:0] Setup Status 0x0 to 0x7 0x8 0x9 to 0xF 0x0 0x0 0x0 Description Possible setup error; the smaller this number, the smaller the setup margin No setup or hold error (best hold margin) No setup or hold error (best setup and hold margin) No setup or hold error (best setup margin) Possible hold error; the larger this number, the smaller the hold margin Possible setup or hold error Rev. B | Page 71 of 91 AD6674 Data Sheet TEST MODES ADC TEST MODES The AD6674 has various test options that aid in the system level implementation. The AD6674 has ADC test modes that are available in Register 0x550. These test modes are described in Table 38. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x550. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. JESD204B BLOCK TEST MODES In addition to the ADC test modes, the AD6674 also has flexible test modes in the JESD204B block. These test modes are listed in Register 0x573 and Register 0x574. These test patterns can be inserted at various points along the output data path. These test insertion points are shown in Figure 121. Table 39 describes the various test modes available in the JESD204B block. For the AD6674, a transition from the test modes (Register 0x573 ≠ 0x00) to normal mode (0x573 = 0x00) require a SPI soft reset. This is done by writing 0x81 to Register 0x00 (self cleared). Transport Layer Sample Test Mode The transport layer samples are implemented in the AD6674 as defined by Section 5.1.6.3 in the JEDEC JESD204B specification. These tests are enabled via Register 0x571[5]. The test pattern is equivalent to the raw samples from the ADC. Interface Test Modes The interface test modes are described in Register 0x573, Bits[3:0]. These test modes are also explained in Table 39. The interface tests can be inserted at various points along the data. See Figure 121 for more information on the test insertion points. Register 0x573, Bits[5:4], show where these tests are inserted. Table 38. ADC Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 Pattern Name Off (default) Midscale short +Full-scale short −Full-scale short Checkerboard PN sequence long PN sequence short One-/zero word toggle User input 1111 Ramp output Expression Not applicable 00 0000 0000 0000 01 1111 1111 1111 10 0000 0000 0000 10 1010 1010 1010 x23 + x18 + 1 x9 + x 5 + 1 11 1111 1111 1111 Default/Seed Value Not applicable Not applicable Not applicable Not applicable Not applicable 0x3AFF 0x0092 Not applicable Register 0x551 to Register 0x558 Not applicable (x) % 214 Not applicable Sample (N, N + 1, N + 2, …) Not applicable Not applicable Not applicable Not applicable 0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555 0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6 0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697 0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000 For repeat mode: User Pattern 1[15:2], User Pattern 2[15:2], User Pattern 3[15:2], User Pattern 4[15:2], User Pattern 1[15:2]… For single mode: User Pattern 1[15:2], User Pattern 2[15:2], User Pattern 3[15:2], User Pattern 4[15:2], 0x0000… (x) % 214, (x + 1) % 214, (x + 2) % 214, (x + 3) % 214 Table 39. JESD204B Interface Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 1110 1111 Pattern Name Off (default) Alternating checker board 1/0 word toggle 31-bit PN sequence 23-bit PN sequence 15-bit PN sequence 9-bit PN sequence 7-bit PN sequence Ramp output Continuous/repeat user test Single user test Expression Not applicable 0x5555, 0xAAAA, 0x5555… 0x0000, 0xFFFF, 0x0000… x31 + x28 + 1 x23 + x18 + 1 x15 + x14 + 1 x9 + x5 + 1 x7 + x6 + 1 (x) % 216 Register 0x551 to Register 0x558 Register 0x551 to Register 0x558 Rev. B | Page 72 of 91 Default Not applicable Not applicable Not applicable 0x0003AFFF 0x003AFF 0x03AF 0x092 0x07 Ramp size depends on test insertion point User Pattern 1 to User Pattern 4, then repeat User Pattern 1 to User Pattern 4, then zeros Data Sheet AD6674 Table 40, Table 41, and Table 42 show examples of some of the test modes when inserted at the JESD204B sample input, physical layer (PHY) 10-bit input, and scrambler 8-bit input. UP in the Table 40 to Table 42 represent the user pattern control bits from the memory map register table (see Table 45). Data Link Layer Test Modes The data link layer test modes are implemented in the AD6674 as defined by Section 5.3.3.8.2 in the JEDEC JESD204B specification. These tests are shown in Register 0x574, Bits[2:0]. Test patterns inserted at this point are useful for verifying the functionality of the data link layer. When the data link layer test modes are enabled, disable SYNCINB± by writing 0xC0 to Register 0x572. Table 40. JESD204B Sample Input for M = 2, S = 2, N΄ = 16 (Register 0x573[5:4] = 'b00) Frame No. 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 Converter No. 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Sample No. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Alternating Checkerboard 0x5555 0x5555 0x5555 0x5555 0xAAAA 0xAAAA 0xAAAA 0xAAAA 0x5555 0x5555 0x5555 0x5555 0xAAAA 0xAAAA 0xAAAA 0xAAAA 0x5555 0x5555 0x5555 0x5555 1/0 Word Toggle 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 Ramp (x) % 216 (x) % 216 (x) % 216 (x) % 216 (x + 1) % 216 (x + 1) % 216 (x + 1) % 216 (x + 1) % 216 (x + 2) % 216 (x + 2) % 216 (x + 2) % 216 (x + 2) % 216 (x + 3) % 216 (x + 3) % 216 (x + 3) % 216 (x + 3) % 216 (x + 4) % 216 (x + 4) % 216 (x + 4) % 216 (x + 4) % 216 PN9 0x496F 0x496F 0x496F 0x496F 0xC9A9 0xC9A9 0xC9A9 0xC9A9 0x980C 0x980C 0x980C 0x980C 0x651A 0x651A 0x651A 0x651A 0x5FD1 0x5FD1 0x5FD1 0x5FD1 User Repeat UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] User Single UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP4[15:0] 0x0000 0x0000 0x0000 0x0000 User Repeat UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] User Single UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] 0x000 0x000 0x000 0x000 0x000 0x000 0x000 0x000 PN23 0xFF5C 0xFF5C 0xFF5C 0xFF5C 0x0029 0x0029 0x0029 0x0029 0xB80A 0xB80A 0xB80A 0xB80A 0x3D72 0x3D72 0x3D72 0x3D72 0x9B26 0x9B26 0x9B26 0x9B26 Table 41. Physical Layer 10-Bit Input (Register 0x573[5:4] = 'b01) 10-Bit Symbol No. 0 1 2 3 4 5 6 7 8 9 10 11 Alternating Checkerboard 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 1/0 Word Toggle 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF Ramp (x) % 210 (x + 1) % 210 (x + 2) % 210 (x + 3) % 210 (x + 4) % 210 (x + 5) % 210 (x + 6) % 210 (x + 7) % 210 (x + 8) % 210 (x + 9) % 210 (x + 10) % 210 (x + 11) % 210 Rev. B | Page 73 of 91 PN9 0x125 0x2FC 0x26A 0x198 0x031 0x251 0x297 0x3D1 0x18E 0x2CB 0x0F1 0x3DD PN23 0x3FD 0x1C0 0x00A 0x1B8 0x028 0x3D7 0x0A6 0x326 0x10F 0x3FD 0x31E 0x008 AD6674 Data Sheet Table 42. Scrambler 8-Bit Input (Register 0x573[5:4] = 'b10) 8-Bit Octet No. 0 1 2 3 4 5 6 7 8 9 10 11 Alternating Checkerboard 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 1/0 Word Toggle 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF Ramp (x) % 28 (x + 1) % 28 (x + 2) % 28 (x + 3) % 28 (x + 4) % 28 (x + 5) % 28 (x + 6) % 28 (x + 7) % 28 (x + 8) % 28 (x + 9) % 28 (x + 10) % 28 (x + 11) % 28 Rev. B | Page 74 of 91 PN9 0x49 0x6F 0xC9 0xA9 0x98 0x0C 0x65 0x1A 0x5F 0xD1 0x63 0xAC PN23 0xFF 0x5C 0x00 0x29 0xB8 0x0A 0x3D 0x72 0x9B 0x26 0x43 0xFF User Repeat UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] User Single UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Data Sheet AD6674 SERIAL PORT INTERFACE (SPI) The AD6674 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the serial port. Memory is organized into bytes that can be further divided into fields. These fields are documented in the Memory Map section. For detailed operational information, see the Serial Control Interface Standard. command is issued. This bit allows the SDIO pin to change direction from an input to an output. CONFIGURATION USING THE SPI Data can be sent in MSB first mode or in LSB first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the Serial Control Interface Standard. Three pins define the SPI of this ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Table 43). The SCLK (serial clock) pin is used to synchronize the read and write data presented from/to the ADC. The SDIO (serial data input/output) pin is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an active low control that enables or disables the read and write cycles. Table 43. Serial Port Interface Pins Pin SCLK SDIO CSB Function Serial clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles. The falling edge of CSB, in conjunction with the rising edge of SCLK, determines the start of the framing. See Figure 4 and Table 5 for an example of the serial timing and its definitions. Other modes involving the CSB pin are available. The CSB pin can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pin to change direction from an input to an output at the appropriate point in the serial frame. HARDWARE INTERFACE The pins described in Table 43 comprise the physical interface between the user programming device and the serial port of the AD6674. The SCLK pin and the CSB pin function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. Do not activate the SPI port during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6674 to prevent these signals from transitioning at the converter inputs during critical sampling periods. SPI ACCESSIBLE FEATURES Table 44 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the Serial Control Interface Standard. The AD6674 device specific features are described in the Memory Map section. Table 44. Features Accessible Using the SPI Feature Name Mode Clock Test I/O Output Mode Serializer/Deserializer (SERDES) Output Setup Description Allows the user to set either power-down mode or standby mode Allows the user to access the clock divider via the SPI Allows the user to set test modes to have known data on output bits Allows the user to set up outputs Allows the user to vary SERDES settings, including swing and emphasis Rev. B | Page 75 of 91 AD6674 Data Sheet MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Logic Levels Each row in the memory map register table has eight bit locations. The memory map is roughly divided into seven sections: the Analog Devices SPI registers, the analog input buffer control registers, ADC function registers, the DDC function registers, NSR decimate by 2 and noise shaping requantizer registers, variable dynamic range registers, and the digital outputs and test modes registers. An explanation of logic level terminology follows: Table 45 (see the Memory Map Register Table section) documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x561, the output mode register, has a hexadecimal default value of 0x01. This means that Bit 0 = 1, and the remaining bits are 0s. This setting is the default output format value, which is twos complement. For more information on this function and others, see the Table 45. Open and Reserved Locations All address and bit locations that are not included in Table 45 are not currently supported for this device. Write unused bits of a valid address location with 0s unless the default value is set otherwise. Writing to these locations is required only when part of an address location is open (for example, Address 0x561). If the entire address location is open (for example, Address 0x013), do not write to this address location. Default Values After the AD6674 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 45. • • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” “X” denotes a “don’t care”. Channel Specific Registers Some channel setup functions such as buffer input termination (Register 0x016) can be programmed to a different value for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 45 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x008. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, set only Channel A or Channel B to read one of the two registers. If both bits are set during an SPI read cycle, the device returns the value for Channel A. Registers and bits designated as global in Table 45 affect the entire device and the channel features for which independent settings are not allowed between channels. The settings in Register 0x008 do not affect the global registers and bits. SPI Soft Reset After issuing a soft reset by programming 0x81 to Register 0x000, the AD6674 requires 5 ms to recover. Therefore, when programming the AD6674 for application setup, ensure that an adequate delay is programmed into the firmware after asserting the soft reset and before starting the device setup. Rev. B | Page 76 of 91 Data Sheet AD6674 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 45 are not currently supported for this device. Table 45. Memory Map Registers Reg. Addr. Register Bit 7 (Hex) Name (MSB) Analog Devices SPI Registers Soft reset 0x000 INTERFACE_ CONFIG_A (self clearing) Single 0x001 INTERFACE_ CONFIG_B instruction 0x002 0x003 0x004 0x005 0x006 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) LSB first 0 = MSB 1 = LSB 0 Address ascension 0 0 0 0 0 0 0 0 0 Soft reset LSB first (self 0 = MSB clearing) 1 = LSB Datapath 0 0 soft reset (self clearing) 00 = normal operation 0 10 = standby 11 = power-down 011 = high speed ADC Address ascension Default Notes 0x00 0x00 DEVICE_ CONFIG (local) CHIP_TYPE 0 CHIP_ID (low byte) CHIP_ID (high byte) CHIP_ GRADE 1 1 0 0 1 1 1 1 0xCF Read only 0 0 0 0 0 0 0 0 0 0x00 0 0 X X X X Read only Channel A 0x03 0 1 0 0x00 0x01 0x56 Device 0 index 0x00A Scratch pad 0 0x00B SPI revision 0 0x00C Vendor ID 0 (low byte) 0x00D Vendor ID 0 (high byte) Analog Input Buffer Control Registers 0x015 Analog 0 Input (local) 0x008 0x016 Input termination (local) 0x934 Input capacitance Buffer Control 1 (local) 0x018 Bit 6 0x03 Chip speed grade 1010 = 1000 MSPS 0111 = 750 MSPS 0101 = 500 MSPS 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 Channel B 0 0 1 0 0 0 0 1 0 0 0x04 0 0 0 0 0 0 0x00 1 1 1 Input disable 0 = normal operation 1 = input disabled 0 0 0x40; 0x20 for AD6674 -500 Analog input differential termination 0000 = 400 Ω 0001 = 200 Ω 0010 = 100 Ω 0110 = 50 Ω 0 0x00 0 0 0000 = 1.0× buffer current 0001 = 1.5× buffer current 0010 = 2.0× buffer current (default for AD6674-500) 0011 = 2.5× buffer current 0100 = 3.0× buffer current (default for AD6674-750 and AD6674-1000) 0101 = 3.5× buffer current … 1111 = 8.5× buffer current 0 0x1F = 3 pF to GND (default) 0x00 = 1.5 pF to GND 0 0 Rev. B | Page 77 of 91 0x0C; 0x0E for AD6674 -1000 and AD6674 -750 0x1F Read only Read only AD6674 Reg. Addr. (Hex) 0x019 Register Name Buffer Control 2 (local) Data Sheet Bit 7 (MSB) Bit 6 Bit 5 Bit 4 0100 = Setting 1 (default for AD6674-750) 0101 = Setting 2 (default for AD6674-1000) 0110 = Setting 3 (default for AD6674-500) 0111 = Setting 4 (see Table 10 for setting per frequency range) 0 0 0 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 (LSB) 0 0 1000 = Setting 1 1001 = Setting 2 (default for AD6674-750 and AD6674-1000) 1010 = Setting 3 (default for AD6674-500) (see Table 10 for setting per frequency range) 0 0 0 0 0 0 Default 0xXX 0x09; 0x0A for AD6674 -500 0x00 0x01A Buffer Control 3 (local) 0x11A Buffer Control 4 (local) 0 0 0x935 Buffer Control 5 (local) 0 0 0x025 Input fullscale range (local) 0 0 0 0 0x030 Input fullscale control (local) 0 0 0 Full-scale control See Table 10 for recommended settings for different frequency bands; default values: AD6674-1000 = 110 AD6674-750 = 101 AD6674-500 = 001 AD6674-500 = 110 (for <1.82 V) 0 0 0xXX ADC Function Registers 0x024 V_1P0 0 control 0 0 0 0 0 0 1.0 V reference select 0= internal 1= external Diode selection 0 = no diode selected 1= temperature diode selected 0 0x00 High frequency setting 0 = off (default) 1 = on 0 Low 0 0 frequency operation 0 = off 1 = on (default) Full-scale adjust 0000 = 1.94 V 1000 = 1.46 V 1001 = 1.58 V 1010 = 1.70 V (default for AD6674-750 and AD6674-1000) 1011 = 1.82 V 1100 = 2.06 V (default for AD6674-500) 0x028 Temperature diode 0 0 0 0 0 0 0 0x03F PDWN/ STBY pin control (local) 0= PDWN/ STBY enabled 1= disabled 0 0 0 0 0 0 Rev. B | Page 78 of 91 Notes 0x04 0x0A; 0x0C for AD6674 -500 V p-p differential; use in conjunction with Reg. 0x030 Used in conjunction with Reg. 0x025 0x00 0x00 Used in conjunction with Reg. 0x040 Data Sheet Reg. Addr. (Hex) 0x040 AD6674 Register Name Chip pin control Bit 7 (MSB) Bit 6 PDWN/STBY function 00 = power down 01 = standby 10 = disabled 0x10B Clock divider 0 0 0 0 0x10C Clock divider phase (local) 0 0 0 0 0x10D Clock divider and SYSREF± control 0 0 0 0x117 Clock delay control Clock divider autophase adjust 0= disabled 1= enabled 0 0 0 0 0x118 Clock fine delay 0x11C Clock status 0 0x120 SYSREF± Control 1 0 0x121 SYSREF± Control 2 0 Bit 5 Bit 4 Bit 3 Fast Detect B (FD_B) 000 = Fast Detect B output 001 = JESD204B LMFC output 010 = JESD204B internal SYNC~ output 111 = disabled Bit 2 Bit 1 Bit 0 (LSB) Fast Detect A (FD_A) 000 = Fast Detect A output 001 = JESD204B LMFC output 010 = JESD204B internal SYNC~ output 011 = temperature diode 111 = disabled 000 = divide by 1 0 001 = divide by 2 011 = divide by 4 111 = divide by 8 Independently controls Channel A and Channel B clock divider phase offset 0000 = 0 input clock cycles delayed 0001 = ½ input clock cycles delayed 0010 = 1 input clock cycles delayed 0011 = 1½ input clock cycles delayed 0100 = 2 input clock cycles delayed 0101 = 2½ input clock cycles delayed … 1111 = 7½ input clock cycles delayed Clock divider positive Clock divider negative skew window skew window 00 = no positive skew 00 = no negative skew 01 = 1 device clock of 01 = 1 device clock of positive skew negative skew 10 = 2 device clocks of 10 = 2 device clocks of positive skew negative skew 11 = 3 device clocks of 11 = 3 device clocks of positive skew negative skew clock fine 0 0 0 delay adjustment enable 0= disabled 1= enabled Clock Fine Delay Adjust[7:0] twos complement coded control to adjust the fine sample clock skew in ~1.7 ps steps ≤−88 = −151.7 ps skew −87 = −150.0 ps skew … 0 = 0 ps skew … ≥ +87 = +150 ps skew 0 = no 0 0 0 0 0 0 input clock detected 1 = input clock detected SYSREF± mode select CLK± SYSREF± SYSREF± 0 0 00 = disabled edge transition flag reset 01 = continuous select select 0 = normal 10 = N shot 0= 0 = low to operation rising high 1 = flags 1 = high to 1 = held in falling low reset SYSREF± N shot ignore counter select 0 0 0 0000 = next SYSREF± only 0001 = ignore the first SYSREF± transitions 0010 = ignore the first two SYSREF± transitions … 1111 = ignore the first 16 SYSREF± transitions Rev. B | Page 79 of 91 Default 0x3F Notes 0x00 0x00 0x00 Clock dvider must be >1 0x00 Enabling the clock fine delay adjust causes a datapath soft reset Used in conjunction with Reg. 0x117 0x00 0x00 Read only 0x00 0x00 Mode select (Reg. 0x120, Bits[2:1]) must be N shot AD6674 Reg. Addr. (Hex) 0x123 0x128 0x129 0x12A 0x1FF Register Name SYSREF± timestamp delay control SYSREF± Status 1 SYSREF± and clock divider status SYSREF± counter Chip sync mode Data Sheet Bit 7 (MSB) 0 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) SYSREF± Timestamp Delay[6:0] 0x00 = no delay 0x01 = 1 clock delay … 0x7F = 127 clocks delay SYSREF± hold status SYSREF± setup status Refer to Table 37 Refer to Table 37 Clock divider phase when SYSREF± was captured 0 0 0 0000 = in phase 0001 = SYSREF± is ½ cycle delayed from clock 0010 = SYSREF± is 1 cycle delayed from clock 0011 = 1½ input clock cycles delayed 0100 = 2 input clock cycles delayed 0101 = 2½ input clock cycles delayed … 1111 = 7½ input clock cycles delayed SYSREF± counter, Bits[7:0], increments when a SYSREF± signal is captured 0 0 0 0 Chip Q ignore 0= normal (I/Q) 1= ignore (I only) 0 0 0x200 Chip application mode 0 0 0x201 Chip decimation ratio 0 0 0x228 Customer offset Fast detect (FD) control (local) 0x245 0x247 0x248 0x249 0x24A 0x24B 0x24C FD upper threshold LSB (local) FD upper threshold MSB (local) FD lower threshold LSB (local) FD lower threshold MSB (local) FD dwell time LSB (local) FD dwell time MSB (local) Bit 5 0 0 0 0 Synchronization mode 00 = normal 01 = timestamp Chip operating mode 0001 = DDC 0 on 0010 = DDC 0 and DDC 1 on 0011 = DDC 0, DDC 1, DDC 2, and DDC3 on 0111 = NSR enabled (default) 1000 = VDR enabled 0 0 Chip decimation ratio select 000 = decimate by 1 001 = decimate by 2 010 = decimate by 4 011 = decimate by 8 100 = decimate by 16 Offset adjust in LSBs from +127 to −128 (twos complement format) 0 0 0 0 Force value Force of FD_A/ FD_A/ FD_B pins; if FD_B force pins is pins; true, this 0= value is normal output on funcFD_x pins tion; 1 = force to value Fast Detect Upper Threshold[7:0] 0 0 Fast Detect Upper Threshold[12:8] Fast Detect Lower Threshold[7:0] 0 0 0 Fast Detect Lower Threshold[12:8] Enable fast detect output Default 0x00 Read only 0x00 0x07 0x01; 0x00 for AD6674 -500 0x00 0x00 0x00 0x00 0x00 0x00 Fast Detect Dwell Time[7:0] 0x00 Fast Detect Dwell Time[15:8] 0x00 Rev. B | Page 80 of 91 Notes Ignored when Reg. 0x1FF = 0x00 Read only Read only Data Sheet Reg. Addr. (Hex) 0x26F 0x270 0x271 0x272 0x273 0x274 0x275 0x276 0x277 0x278 0x279 0x27A Register Name Signal monitor synchronization control Signal monitor control (local) Signal Monitor Period Register 0 (local) Signal Monitor Period Register 1 (local) Signal Monitor Period Register 2 (local) Signal monitor result control (local) Signal Monitor Result Register 0 (local) Signal Monitor Result Register 1 (local) Signal Monitor Result Register 1 (local) Signal monitor period counter result (local) Signal monitor SPORT over JESD204B control (local) SPORT over JESD204B input selection (local) AD6674 Bit 7 (MSB) 0 Bit 6 0 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 (LSB) Synchronization mode 00 = disabled 01 = continuous 11 = 1 shot Default 0x00 0 0 0 0 0 Peak detector 0= disabled 1= enabled 0 0x00 0 0x80 Signal Monitor Period[7:1] 0 0 0 0 Signal Monitor Period[15:8] 0x00 Signal Monitor Period[23:16] 0x00 Result update 1 = update results (self clear) 0 0 Result selection 0= reserved 1 = Peak detector 0 Read only Signal Monitor Result[15:8] Readonly 0 0 Readonly Signal Monitor Result[19:16] Readonly Period Count Result[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 Rev. B | Page 81 of 91 00 = reserved 11 = enabled Peak detector 0= disabled 1= enabled 0 In decimated output clock cycles In decimated output clock cycles In decimated output clock cycles 0x01 Signal Monitor Result[7:0] When 0x0274[0] = 1, Result Bits[19:7] = Peak Detector Absolute Value[12:0]; Result Bits[6:0] = 0 0 Notes See the Signal Monitor section 0x00 0x02 Updated based on Reg. 0x0274, Bit 4 Updated based on Reg. 0x0274, Bit 4 Updated based on Reg. 0x0274, Bit 4 Updated based on Reg. 0x0274, Bit 4 AD6674 Data Sheet Reg. Addr. Register Bit 7 (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Digital Downconverter (DDC) Function Registers—see the Digital Downconverter (DDC) section DDC NCO Synchronization mode 0x300 DDC 0 0 0 0 0 synchrosoft reset 00 = disabled nization 0 = normal 01 = continuous control operation 11 = one shot 1 = reset IF mode Decimation ratio select Gain select Complex 0 Mixer 0x310 DDC 0 00 = variable IF mode (complex to real 0 = 0 dB to real control select (mixers and NCO disabled) gain enable 0 = real enabled) 11 = decimate by 2 1 = 6 dB 0= mixer 01 = 0 Hz IF mode 00 = decimate by 4 gain disabled 1= (mixer bypassed, NCO 01 = decimate by 8 1= complex disabled) 10 = decimate by 16 enabled mixer 10 = fADC/4 Hz IF mode (complex to real enabled) (fADC/4 downmixing 11 = decimate by 1 mode) 00 = decimate by 2 11 = test mode (mixer 01 = decimate by 4 inputs forced to +FS, 10 = decimate by 8 NCO enabled) I input Q input 0 0 0 0 0 0 0x311 DDC 0 select select input 0 = Ch. A 0 = Ch. A selection 1 = Ch. B 1 = Ch. B DDC 0 NCO FTW[7:0] twos complement 0x314 DDC 0 frequency LSB X X X X DDC 0 NCO FTW[11:8] twos complement 0x315 DDC 0 frequency MSB 0x320 DDC 0 DDC 0 NCO POW[7:0] twos complement phase LSB 0x321 DDC 0 X X X X DDC0 NCO POW[11:8] twos complement phase MSB Q output I output 0x327 DDC 0 0 0 0 0 0 0 output test test mode test mode mode enable enable selection 0 = disabled 0= 1 = enabled disabled from Ch. B 1= enabled from Ch. A IF mode Decimation ratio select Gain select Complex 0 Mixer 0x330 DDC 1 00 = variable IF mode (complex to real 0 = 0 dB to real control select (mixers and NCO disabled) gain enable 0 = real enabled) 11 = decimate by 2 1 = 6 dB 0= mixer 01 = 0 Hz IF mode 00 = decimate by 4 gain disabled 1= (mixer bypassed, NCO 01 = decimate by 8 1= complex disabled) 10 = decimate by 16 enabled mixer 10 = fADC/4 Hz IF mode (complex to real enabled) (fADC/4 downmixing 11 = decimate by 1 mode) 00 = decimate by 2 11 = test mode (mixer 01 = decimate by 4 inputs forced to +FS, 10 = decimate by 8 NCO enabled) Q input I input 0x331 DDC 1 0 0 0 0 0 0 input select select selection 0 = Ch. A 0 = Ch. A 1 = Ch. B 1 = Ch. B DDC 1 NCO FTW[7:0] twos complement 0x334 DDC 1 frequency LSB X X X X DDC1 NCO FTW[11:8] twos complement 0x335 DDC 1 frequency MSB 0x340 DDC 1 DDC 1 NCO POW[7:0] twos complement phase LSB Rev. B | Page 82 of 91 Default 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x00 0x00 0x00 Notes Data Sheet Reg. Addr. (Hex) 0x341 AD6674 Register Name DDC 1 phase MSB DDC 1 output test mode selection Bit 7 (MSB) X Bit 6 X Bit 5 X Bit 4 X Bit 3 0 0 0 0 0 Q output test mode enable 0 = disabled 1 = enabled from Ch. B 0x350 DDC 2 control Mixer select 0 = real mixer 1= complex mixer Gain select 0 = 0 dB gain 1 = 6 dB gain Complex to real enable 0= disabled 1= enabled 0 0x351 DDC 2 input selection 0 0 IF mode 00 = variable IF mode (mixers and NCO enabled) 01 = 0 Hz IF mode (mixer bypassed, NCO disabled) 10 = fADC/4 Hz IF mode (fADC/4 downmixing mode) 11 = test mode (mixer inputs forced to +FS, NCO enabled) 0 0 0x354 DDC 2 frequency LSB DDC 2 frequency MSB DDC 2 phase LSB DDC 2 phase MSB DDC 2 output test mode selection 0x347 0x355 0x360 0x361 0x367 X X Bit 2 Bit 1 Bit 0 (LSB) DDC1 NCO POW[11:8] twos complement Q input select 0 = Ch. A 1 = Ch. B DDC 2 NCO FTW[7:0] twos complement X 0 X I output test mode enable 0= disabled 1= enabled from Ch. A Decimation ratio select (complex to real disabled) 11 = decimate by 2 00 = decimate by 4 01 = decimate by 8 10 = decimate by 16 (complex to real enabled) 11 = decimate by 1 00 = decimate by 2 01 = decimate by 4 10 = decimate by 8 I input 0 select 0 = Ch. A 1 = Ch. B 0 DDC 2 NCO Phase Offset[7:0] twos complement X X X 0 0 0 0 IF mode 00 = variable IF mode (mixers and NCO enabled) 01 = 0 Hz IF mode (mixer bypassed, NCO disabled) 10 = fS/4 Hz IF mode (fS/4 downmixing mode) 11 = test mode (mixer inputs forced to +FS, NCO enabled) 0 0 0x370 DDC 3 control Mixer select 0 = real mixer 1= complex mixer Gain select 0 = 0 dB gain 1 = 6 dB gain 0x371 DDC 3 input selection 0 0 0x374 DDC 3 frequency LSB Q output test mode enable 0 = disabled 1 = enabled from Ch. B Complex to real enable 0= disabled 1= enabled 0 Q input select 0 = Ch. A 1 = Ch. B DDC3 NCO FTW[7:0] twos complement 0 Rev. B | Page 83 of 91 0x00 0x00 0x00 0x00 DDC2 NCO Phase Offset[11:8] twos complement 0 0x00 0x00 DDC2 NCO FTW[11:8] twos complement X Default 0x00 I output test mode enable 0= disabled 1= enabled from Ch. A Decimation ratio select (complex to real disabled) 11 = decimate by 2 00 = decimate by 4 01 = decimate by 8 10 = decimate by 16 (complex to real enabled) 11 = decimate by 1 00 = decimate by 2 01 = decimate by 4 10 = decimate by 8 I input 0 select 0 = Ch. A 1 = Ch. B 0 0x00 0x00 0x00 0x05 0x00 Notes AD6674 Reg. Addr. (Hex) 0x375 0x380 0x381 0x387 Register Name DDC 3 frequency MSB DDC 3 phase LSB DDC 3 phase MSB DDC 3 output test mode selection Data Sheet Bit 7 (MSB) X Bit 6 X Bit 5 X Bit 4 X Bit 2 Bit 1 Bit 0 (LSB) DDC3 NCO FTW[11:8] twos complement DDC3 NCO POW[7:0] twos complement Default 0x00 X X X 0 0 0 0 0 Q output test mode enable 0 = disabled 1 = enabled from Ch. B 0 I output test mode enable 0= disabled 1= enabled from Ch. A 0x00 0 X X X NSR decimate by 2 enable 0= disabled 1= enabled 0x01; 0x00 for AD6674 -500 0x420 NSR mode X X 0x422 NSR tuning X X DDC3 NCO POW[11:8] twos complement 0x00 0 = dual VDR BW real mode mode 1 = dual 0 = 25% complex BW mode mode (Channel A 1 = 43% = I, BW Channel B mode = Q) (only available for dual complex mode) VDR center frequency; see the Variable Dynamic Range (VDR) section for more details on the center frequency, which is dependent on the VDR mode 0x01 X Variable Dynamic Range (VDR) 0x430 VDR control X X X 0 0x434 X X X 0 Reset PN long gen 0 = long PN enable 1 = long PN reset Reset PN short gen 0 = short PN enable 1 = short PN reset X Digital Outputs and Test Modes User 0x550 ADC test pattern modes selection (local) 0= continuous repeat 1 = single pattern 0x00 NSR mode X 000 = 21% BW mode 001 = 28% BW mode NSR tuning word; see the Noise Shaping Requantizer (NSR) section; equations for the tuning word are dependent on the NSR mode X X X Test mode selection 0000 = off (normal operation) 0001 = midscale short 0010 = positive full scale 0011 = negative full scale 0100 = alternating checker board 0101 = PN sequence, long 0110 = PN sequence, short 0111 = 1/0 word toggle 1000 = user pattern test mode (used with Register 0x550, Bit 7, and User Pattern 1 to User Patten 4 registers) 1111 = ramp output Rev. B | Page 84 of 91 Notes 0x00 X NSR Decimate by 2 and Noise Shaping Requantizer (NSR) HighNSR X 0 0x41E pass/ decimate low-pass by 2 mode: 0= enable LPF 1= enable HPF VDR tuning Bit 3 0x00 0x00 0x00 Bit 0 is ignored on AD6674 -750 and AD6674 -1000 when in NSR mode Data Sheet Reg. Addr. (Hex) 0x551 AD6674 Register Name User Pattern 1 LSB Bit 7 (MSB) 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 (LSB) 0 Default 0x00 0x552 User Pattern 1 MSB 0 0 0 0 0 0 0 0 0x00 0x553 User Pattern 2 LSB 0 0 0 0 0 0 0 0 0x00 0x554 User Pattern 2 MSB 0 0 0 0 0 0 0 0 0x00 0x555 User Pattern 3 LSB 0 0 0 0 0 0 0 0 0x00 0x556 User Pattern 3 MSB 0 0 0 0 0 0 0 0 0x00 0x557 User Pattern 4 LSB 0 0 0 0 0 0 0 0 0x00 0x558 User Pattern 4 MSB 0 0 0 0 0 0 0 0 0x00 0x559 Output Mode Control 1 0 Converter Control Bit 1 selection (only used when CS (0x58F) = 2 or 3) 000 = tie low (1’b0) 001 = overrange bit 010 = signal monitor bit or VDR Punish Bit 0 011 = fast detect (FD) bit or VDR Punish Bit 1 100 = VDR high/low resolution bit 101 = system reference 0 Converter Control Bit 0 selection (only used when CS (0x58F) = 3) 000 = tie low (1’b0) 001 = overrange bit 010 = signal monitor bit or VDR Punish Bit 0 011 = fast detect (FD) bit or VDR Punish Bit 1 100 = VDR high/low resolution bit 101 = system reference Rev. B | Page 85 of 91 0x00 Notes Used with Reg. 0x550, Reg. 0x573 Used with Reg. 0x550, Reg. 0x573 Used with Reg. 0x550, Reg. 0x573 Used with Reg. 0x550, Reg. 0x573 Used with Reg. 0x550, Reg. 0x573 Used with Reg. 0x550, Reg. 0x573 Used with Reg. 0x550, Reg. 0x573 Used with Reg. 0x550, Reg. 0x573 AD6674 Reg. Addr. (Hex) 0x55A Data Sheet Register Name Output Mode Control 2 Bit 7 (MSB) 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 0x561 Output mode 0 0 0 0 0 0x562 Output overrange (OR) clear Virtual Converter 7 OR 0 = OR bit enabled 1 = OR bit cleared Virtual Converter 6 OR 0 = OR bit enabled 1 = OR bit cleared Virtual Converter 4 OR 0 = OR bit enabled 1 = OR bit cleared 0x563 Output overrange status Virtual Converter 7 OR 0 = no OR 1 = OR occurred Virtual Converter 6 OR 0 = no OR 1 = OR occurred Virtual Converter 5 OR 0 = OR bit enabled 1 = OR bit cleared Virtual Converter 5 OR 0 = no OR 1 = OR occurred 0x564 Output channel select 0 0 0 0 Virtual Converter 3 OR 0 = OR bit enabled 1 = OR bit cleared Virtual Converter 3 OR 0 = no OR 1 = OR occurre d 0 0x56E JESD204B lane rate control 0 0 0 0x56F JESD204B PLL lock status PLL lock 0 = not locked 1= locked 0 0 0 = serial lane rate ≥ 6.25 Gbps and ≤ 12.5 Gbps 1 = serial lane rate must be ≥ 3.125 Gbps and <6.25 Gbps 0 0x570 JESD204B quick configuration Virtual Converter 4 OR 0 = no OR 1 = OR occurred Default 0x01 0 Bit 2 Bit 1 Bit 0 (LSB) Converter Control Bit 2 selection (used when CS (0x58F) = 1, 2, or 3) 000 = tie low (1’b0) 001 = overrange bit 010 = signal monitor bit or VDR Punish Bit 0 011 = fast detect (FD) bit or VDR Punish Bit 1 100 = VDR high/low resolution bit 101 = system reference Data format select Sample 00 = offset binary invert 01 = twos complement 0 = normal 1 = sample invert Virtual Virtual Virtual Converter 0 ConConverter 2 OR verter 1 OR 0 = OR bit OR 0 = or bit enabled 0 = OR enabled 1 = OR bit bit 1 = OR bit cleared enabled cleared 1 = OR bit cleared Virtual Virtual Virtual Converter 0 ConConverter 2 OR verter 1 OR 0 = no OR OR 0 = no OR 1 = OR 0 = no 1 = OR occurred OR occurred 1 = OR occurre d Converter 0 0 channel swap 0 = normal channel ordering 1= channel swap enabled 0 0 0 0 0 0x00 Read only 0x88 Refer to Table 35 and Table 36 JESD204B quick configuration Number of lanes (L) = 20x570[7:6] Number of converters (M) = 20x570[5:3] Number of octets/frame (F) = 20x570[2:0] Rev. B | Page 86 of 91 0 0 Notes 0x01 0x00 0x00 Read only 0x00 0x10 Data Sheet Reg. Addr. (Hex) 0x571 Register Name JESD204B Link Mode Control 1 AD6674 Bit 7 (MSB) Standby mode 0 = all converter outputs 0 1 = CGS (K28.5) Bit 6 Tail bit (T) PN 0 = disable 1 = enable T= N’ − N − CS Bit 5 Long transport layer test 0= disable 1= enable SYNCINB± pin invert 0 = active low 1 = active high Bit 4 Lane synchronization 0 = disable FACI uses /K28.7/ 1 = enable FACI uses /K28.3/ and /K28.7/ SYNCINB± pin type 0= differential 1 = CMOS 0x572 JESD204B Link Mode Control 2 SYNCINB± pin control 00 = normal 10 = ignore SYNCINB± (force CGS) 11 = ignore SYNCINB± (force ILAS/user data) 0x573 JESD204B Link Mode Control 3 CHKSUM mode 00 = sum of all 8-bit link configuration registers 01 = sum of individual link configuration fields 10 = checksum set to zero 0x574 JESD204B Link Mode Control 4 0x578 JESD204B LMFC offset JESD204B DID config JESD204B BID config JESD204B LID Config 1 JESD204B LID Config 2 JESD204B LID Config 3 JESD204B LID Config 4 JESD204B parameters (SCR/L) ILAS delay 0000 = transmit ILAS on first LMFC after SYNCINB± deasserted 0001 = transmit ILAS on second LMFC after SYNCINB± deasserted … 1111 = transmit ILAS on 16th LMFC after SYNCINB± deasserted 0 0 0 0x580 0x581 0x583 0x584 0x585 0x586 0x58B Test insertion point 00 = N’ sample input 01 = 10-bit data at 8B/10B output (for PHY testing) 10 = 8-bit data at scrambler input Bit 3 Bit 2 ILAS sequence mode 00 = ILAS disabled 01 = ILAS enabled 11 = ILAS always on test mode Bit 1 Frame alignment character insertion (FACI) 0= enabled 1= disabled Bit 0 (LSB) Link control 0 = active 1 = power down 8B/10B 0 bit invert 0= normal 1= invert abcde fghij symbols JESD204B test mode patterns 0000 = normal operation (test mode disabled) 0001 = alternating checker board 0010 = 1/0 word toggle 0011 = 31-bit PN sequence—x31 + x28 + 1 0100 = 23-bit PN sequence—x23 + x18 + 1 0101 = 15-bit PN sequence—x15 + x14 + 1 0110 = 9-bit PN sequence—x9 + x5 + 1 0111 = 7-bit PN sequence—x7 + x6 + 1 1000 = ramp output 1110 = continuous/repeat user test 1111 = single user test Link layer test mode 0 000 = normal operation (link layer test mode disabled) 001 = continuous sequence of /D21.5/ characters 100 = modified RPAT test sequence 101 = JSPAT test sequence 110 = JTSPAT test sequence LMFC Phase Offset Value[4:0] 8B/10B bypass 0 = normal 1 = bypass 0 JESD204B Tx DID Value[7:0] 0 Default 0x14 0x00 0x00 0x00 0x00 0x00 0 0 0 0 0 0 Lane 0 LID Value[4:0] 0x00 0 0 0 Lane 1 LID Value[4:0] 0x01 0 0 0 Lane 2 LID Value[4:0] 0x01 0 0 0 Lane 3 LID Value[4:0] 0x03 JESD204B scrambling (SCR) 0= disabled 1= enabled 0 0 0 JESD204B Tx BID Value[3:0] 0 Rev. B | Page 87 of 91 0 JESD204B lanes (L) 00 = 1 lane 01 = 2 lanes 11 = 4 lanes read only; see Register 0x570 0x00 0x83 Notes AD6674 Reg. Addr. (Hex) 0x58C Data Sheet Register Name JESD204B F config Bit 7 (MSB) Bit 6 JESD204B K config JESD204B M config 0 0 0x58F JESD204B parameters (CS/N) 0x590 JESD204B parameter (NP) 0x591 JESD204B parameter (S) JESD204B parameters (HD and CF) Number of control bits (CS) per sample 00 = no control bits (CS = 0) 01 = 1 control bit (CS = 1); Control Bit 2 only 10 = 2 control bits (CS = 2); Control Bit 2 and Control Bit 1 only 11 = 3 control bits (CS = 3); all control bits (2, 1, 0) Subclass support 000 = Subclass 0 (no deterministic latency) 001 = Subclass 1 0 0 1 0x58D 0x58E 0x592 0x5A0 0x5A1 0x5A2 0x5A3 JESD204B CHKSUM 0 JESD204B CHKSUM 1 JESD204B CHKSUM 2 JESD204B CHKSUM 3 JESD204B lane powerdown HD value 0= disabled 1= enabled 0 Bit 5 Bit 4 Bit 3 Bit 2 Number of octets per frame, F = 0x58C[7:0] + 1 Number of frames per multi-frame, K = 0x58D[4:0] + 1 Only values where (F × K) mod 4 = 0 are supported Number of Converters per Link[7:0] 0x00 = link connected to one virtual converter (M = 1) 0x01 = link connected to two virtual converters (M = 2) 0x03 = link connected to four virtual converters (M = 4) 0x07 = link connected to eight virtual converters (M = 8) Converter resolution (N) 0 0x06 = 7-bit resolution 0x07 = 8-bit resolution 0x08 = 9-bit resolution 0x09 = 10-bit resolution 0x0A = 11-bit resolution 0x0B = 12-bit resolution 0x0C = 13-bit resolution 0x0D = 14-bit resolution 0x0E = 15-bit resolution 0x0F = 16-bit Resolution Number of bits per sample (N’) 0x7 = 8 bits 0xF = 16 bits Control words per frame clock cycle per link (CF) CF value = 0x592[4:0] 0x1F 0x01 Notes Read only, see Reg. 0x570 See Reg. 0x570 Read only 0x0F 0x2F Read only 0x80 Read only CHKSUM value for SERDOUT0±[7:0] 0x81 CHKSUM value for SERDOUT1±[7:0] 0x82 CHKSUM value for SERDOUT2±[7:0] 0x82 CHKSUM value for SERDOUT3±[7:0] 0x84 Read only Read only Read only Read only 0 X SERDOUT2± 0 = on 1 = off X JESD204B lane SERDOUT0± assign X 0 0x5B3 JESD204B lane SERDOUT1± assign X X X X 0 0x5B5 JESD204B lane SERDOUT2± assign X X X X 0 1 Default 0x00 Samples per converter frame cycle (S) S value = 0x591[4:0] +1 0x5B2 1 Bit 0 (LSB) 0 SERDOUT3± 0 = on 1 = off X 0x5B0 Bit 1 1 Rev. B | Page 88 of 91 SERDOUT1± 0 = on 1 = off SERDOUT0± 0 = on 1 = off Physical Lane 0 assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 Physical Lane 1 assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 Physical Lane 2 assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 1 0xAA 0x00 0x11 0x22 Data Sheet Reg. Addr. (Hex) 0x5B6 AD6674 Register Name JESD204B lane SERDOUT3± assign Bit 7 (MSB) X Bit 6 X Bit 5 X Bit 4 X 0x5BF JESD serializer drive adjust 0 0 0 0 0x5C1 Deemphasis select 0 0 0x5C2 Deemphasis setting for SERDOUT0± 0 SERDOUT3± 0 = disable 1 = enable 0 0 SERDOUT2± 0 = disable 1 = enable 0 0x5C3 Deemphasis setting for SERDOUT1± 0 0 0 0 0x5C4 Deemphasis setting for SERDOUT2± 0 0 0 0 0x5C5 Deemphasis setting for SERDOUT3± 0 0 0 0 Bit 3 0 0 Rev. B | Page 89 of 91 Bit 2 Bit 1 Bit 0 (LSB) Physical Lane 3 assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 Swing voltage 0000 = 237.5 mV 0001 = 250 mV 0010 = 262.5 mV 0011 = 275 mV 0100 = 287.5 mV 0101 = 300 mV 0110 = 312.5 mV 0111 = 325 mV 1000 = 337.5 mV 1001 = 350 mV 1010 = 362.5 mV 1011 = 375 mV 1100 = 387.5 mV 1101 = 400 mV 1110 = 412.5 mV 1111 = 425 mV SERSERDOUT1± 0 DOUT0± 0 = disable 0 = disable 1 = enable 1 = enable De-emphasis settings 0000 = de-emphasis disabled 1000 = 0.5 dB 1001 = 1.0 dB 1010 = 1.7 dB 1011 = 2.5 dB 1100 = 3.5 dB 1101 = 4.9 dB 1110 = 6.7 dB 1111 = 9.6 dB De-emphasis settings 0000 = de-emphasis disabled 1000 = 0.5 dB 1001 = 1.0 dB 1010 = 1.7 dB 1011 = 2.5 dB 1100 = 3.5 dB 1101 = 4.9 dB 1110 = 6.7 dB 1111 = 9.6 dB De-emphasis settings 0000 = de-emphasis disabled 1000 = 0.5 dB 1001 = 1.0 dB 1010 = 1.7 dB 1011 = 2.5 dB 1100 = 3.5 dB 1101 = 4.9 dB 1110 = 6.7 dB 1111 = 9.6 dB De-emphasis settings 0000 = de-emphasis disabled 1000 = 0.5 dB 1001 = 1.0 dB 1010 = 1.7 dB 1011 = 2.5 dB 1100 = 3.5 dB 1101 = 4.9 dB 1110 = 6.7 dB 1111 = 9.6 dB Default 0x33 0x05 0x00 0x00 0x00 0x00 0x00 Notes AD6674 Data Sheet APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS The AD6674 must be powered by the following seven supplies: AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V. For applications requiring an optimal high power efficiency and low noise performance, it is recommended that the ADP2164 and ADP2370 switching regulators be used to convert the 3.3 V, 5.0 V, or 12 V input rails to an intermediate rail (1.8 V and 3.8 V). These intermediate rails are then postregulated by very low noise, low dropout (LDO) regulators (ADP1741, ADM7172, and ADP125). Figure 142 shows the recommended method. For more detailed information on the recommended power solution, refer to the AD6674 evaluation board documentation. ADP1741 1.8V AVDD1 1.25V AVDD1_SR 1.25V ADP1741 thermal performance of the AD6674. Connect an exposed continuous copper plane on the PCB to the AD6674 exposed pad, Pin 0. The copper plane must have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias must be solder filled or plugged. The number of vias and the fill determine the resultant θJA measured on the board. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. See Figure 143 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). DVDD 1.25V DRVDD 1.25V 3.6V ADP125 AVDD3 3.3V 3.3V ADM7172 OR ADP1741 AVDD2 2.5V 12400-518 SPIVDD (1.8V OR 3.3V) It is not necessary to split all of these power domains in all cases. The recommended solution shown in Figure 142 provides the lowest noise, highest efficiency power delivery system for the AD6674. If only one 1.25 V supply is available, it must be routed to AVDD1 first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for AVDD1_SR, DVDD, and DRVDD, in that order. The user can use several different decoupling capacitors to cover both high and low frequencies. These must be located close to the point of entry at the PCB level and close to the devices, with minimal trace lengths. EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS It is required that the exposed pad on the underside of the ADC be connected to ground to achieve the best electrical and 12400-180 Figure 142. High Efficiency, Low Noise Power Solution for the AD6674 Figure 143. Recommended PCB Layout of Exposed Pad for the AD6674 AVDD1_SR (PIN 57) AND AGND (PIN 56, PIN 60) AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) can be used to provide a separate power supply node to the SYSREF± circuits of the AD6674. If running in Subclass 1, the AD6674 can support periodic one-shot or gapped signals. To minimize the coupling of this supply into the AVDD1 supply node, adequate supply bypassing is needed. Rev. B | Page 90 of 91 Data Sheet AD6674 9.10 9.00 SQ 8.90 0.30 0.25 0.18 PIN 1 INDICATOR 49 1 0.50 BSC EXPOSED PAD 7.70 7.60 SQ 7.50 33 TOP VIEW 0.80 0.75 0.70 0.45 0.40 0.35 16 32 17 BOTTOM VIEW 7.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF PKG-004396 SEATING PLANE PIN 1 INDICATOR 64 48 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WMMD 02-12-2014-A OUTLINE DIMENSIONS Figure 144. 64-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 9 mm × 9 mm Body, Very Very Thin Quad (CP-64-15) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD6674BCPZ-500 AD6674BCPZRL7-500 AD6674BCPZ-750 AD6674BCPZRL7-750 AD6674BCPZ-1000 AD6674BCPZRL7-1000 AD6674-500EBZ AD6674-750EBZ AD6674-1000EBZ 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 2 64-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board for AD6674-500 Evaluation Board for AD6674-750 Evaluation Board for AD6674-1000 Z = RoHS Compliant Part. The AD6674-500EBZ, AD6674-750EBZ, and AD6674-1000EBZ evaluation boards are optimized for the full analog input frequency range. ©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12400-0-4/15(B) Rev. B | Page 91 of 91 Package Option CP-64-15 CP-64-15 CP-64-15 CP-64-15 CP-64-15 CP-64-15