BSI BS616LV8015BI Very low power/voltage cmos sram 512k x 16 bit Datasheet

BSI
Very Low Power/Voltage CMOS SRAM
512K X 16 bit
„ FEATURES
BS616LV8015
„ DESCRIPTION
• Very low operation voltage : 4.5~5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 45mA (Max.) operating current
I-grade : 50mA (Max.) operating current
3uA (Typ.) CMOS standby current
• High speed access time :
-55
70ns (Max.) at Vcc=5V
-70
70ns (Max.) at Vcc=5V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1,CE2 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV8015 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a wide range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 3uA and maximum access time of 55/70ns in 5V operation.
Easy memory expansion is provided by an active LOW chip enable(CE1),
active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
The BS616LV8015 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8015 is available in 48-pin BGA package.
„ PRODUCT FAMILY
OPERATING
TEMPERATURE
PRODUCT FAMILY
O
Vcc
RANGE
O
POWER DISSIPATION
STANDBY
Operating
SPEED
(ns)
(ICCSB1, Max)
(ICC, Max)
Vcc=5V
Vcc=5V
Vcc=5V
PKG TYPE
BS616LV8015BC
+0 C to +70 C
4.5V ~ 5.5V
55 / 70
30uA
45mA
BGA-48-0810
BS616LV8015BI
-40 O C to +85 O C
4.5V ~ 5.5V
55 / 70
100uA
50mA
BGA-48-0810
„ PIN CONFIGURATIONS
A
„ BLOCK DIAGRAM
1
2
3
4
5
6
LB
OE
A0
A1
A2
CE2
B
D8
UB
A3
A4
CE1
D0
C
D9
D10
A5
A6
D1
D2
D
VSS
D11
A17
A7
D3
VCC
E
VCC
D12
VSS
A16
D4
VSS
A4
A3
A2
A1
Address
A0
A17
Input
A16
A15
A14
A13
A12
Buffer
D14
D13
A14
A15
D5
D6
G
D15
NC
.
A12
A13
WE
D7
H
A 18
A8
A9
A10
A11
NC
2048
Row
Memory Array
Decoder
2048 x 4096
4096
16
D0
.
.
.
.
.
.
.
.
Data
Input
Buffer
16
Column I/O
Write Driver
Sense Amp
16
Data
Output
Buffer
D15
F
22
256
16
Column Decoder
CE2
CE1
16
WE
OE
UB
LB
Control
Address Input Buffer
A11 A10 A9 A8 A7 A6 A5 A18
Vcc
Gnd
48-Ball CSP top View
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV8015
1
Revision 2.4
April 2002
BSI
BS616LV8015
„ PIN DESCRIPTIONS
Name
Function
A0-A18 Address Input
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
D0 - D15 Data Input/Output Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
„ TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
Read
CE1
H
CE2
OE
LB
UB
D8~D15
Vcc CURRENT
X
X
X
X
X
High Z
High Z
I CCSB , I CCSB1
L
X
X
X
X
High Z
High Z
I CCSB , I CCSB1
L
H
H
H
X
X
High Z
High Z
ICC
L
L
Dout
Dout
ICC
H
L
High Z
Dout
ICC
L
H
Dout
High Z
ICC
L
L
Din
Din
ICC
L
H
H
H
L
L
X
H
L
X
Din
ICC
L
H
Din
X
ICC
„ OPERATING RANGE
„ ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
D0~D7
X
L
Write
WE
PARAMETER
RATING
UNITS
-0.5 to
Vcc+0.5
V
V TERM
Terminal Voltage with
Respect to GND
T BIAS
Temperature Under Bias
T STG
Storage Temperature
PT
Power Dissipation
1.0
W
I OUT
DC Output Current
20
mA
-40 to +125
-60 to +150
O
O
C
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0 O C to +70 O C
4.5V ~ 5.5V
Industrial
C
O
O
-40 C to +85 C
4.5V ~ 5.5V
„ CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
PARAMETER
CONDITIONS
MAX.
Input
CIN
VIN=0V
6
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
Capacitance
RATINGS may cause permanent damage to the device. This is a
Input/Output
CDQ
VI/O=0V
8
stress rating only and functional operation of the device at these
Capacitance
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
1. This parameter is guaranteed and not tested.
maximum rating conditions for extended periods may affect reliability.
R0201-BS616LV8015
2
UNIT
pF
pF
Revision 2.4
April 2002
BSI
BS616LV8015
„ DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
PARAMETER
PARAMETER
TEST CONDITIONS
NAME
MIN. TYP.(1) MAX.
UNITS
VIL
Guaranteed Input Low
Voltage (2)
Vcc=5V
-0.5
--
0.8
V
VIH
Guaranteed Input High
Voltage (2)
Vcc=5V
2.2
--
Vcc+0.2
V
IIL
Input Leakage Current
Vcc = Max, V IN = 0V to Vcc
--
--
1
uA
IOL
Output Leakage Current
Vcc = Max, CE1=V IH, or CE2 = ViL , or
OE = VIH , VI/O = 0V to Vcc
--
--
1
uA
VOL
Output Low Voltage
Vcc = Max, IOL = 2mA
Vcc=5V
--
--
0.4
V
VOH
Output High Voltage
Vcc = Min, I OH = -1mA
Vcc=5V
2.4
--
--
V
ICC
Operating Power Supply
Current
Vcc= max, CE1=VIL and CE2 =
VIH , IDQ = 0mA, F = Fmax(3)
Vcc=5V
--
--
45
mA
ICCSB
Standby Current - TTL
Vcc= max, CE1 = VIH or CE2 =
VIL , IDQ = 0mA
Vcc=5V
--
--
2
mA
ICCSB1
Њ
Vcc= max,CE1 Vcc -0.2V, or
Standby Current - CMOS CE2 Љ 0.2V, V Њ Vcc 0.2V
IN
or V IN Љ0.2V
Vcc=5V
--
3
30
uA
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
„ DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
VDR
Vcc for Data Retention
CE1 Њ Vcc - 0.2V or CE2Љ0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
1.5
--
--
V
ICCDR
Data Retention Current
CE1 Њ Vcc - 0.2V or CE2Љ0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
--
0.2
2
uA
tCDR
Chip Deselect to Data
Retention Time
--
--
ns
--
--
ns
tR
See Retention Waveform
Operation Recovery Time
0
TRC
(2)
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
„ LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
Vcc
VDR ≥ 1.5V
Vcc
CE1
Vcc
tR
t CDR
CE1≥ Vcc - 0.2V
VIH
VIH
„ LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
Vcc
VDR Њ 1.5V
Vcc
CE2
R0201-BS616LV8015
VIL
Vcc
tR
t CDR
CE2 Љ 0.2V
3
VIL
Revision 2.4
April 2002
BSI
BS616LV8015
„ KEY TO SWITCHING WAVEFORMS
„ AC TEST CONDITIONS
Vcc/0V
5ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
1928 Ω
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
5PF
DON T CARE:
ANY CHANGE
PERMITTED
CHANGE :
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
0.5Vcc
„ AC TEST LOADS AND WAVEFORMS
1928 Ω
5.0V
5.0V
OUTPUT
,
OUTPUT
100PF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
1020 Ω
1020 Ω
FIGURE 1A
FIGURE 1B
THEVENIN EQUIVALENT
667 Ω
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
90% 90%
10%
→
←
→
10%
← 5ns
FIGURE 2
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC, Vcc=5V)
READ CYCLE
JEDEC
PARAMETER
PARAMETER
NAME
NAME
BS616LV8015-70
MIN. TYP. MAX.
DESCRIPTION
BS616LV8015-55
MIN. TYP. MAX.
UNIT
tAVAX
tAVQV
tELQV
tELQV
tBA
tGLQV
tRC
tAA
t ACS1
t ACS2
tBA(1)
tOE
Read Cycle Time
70
--
--
55
--
--
ns
Address Access Time
--
--
70
--
--
55
ns
tELQX
tBE
tGLQX
tEHQZ
tBDO
tCLZ
tBE
tOLZ
tCHZ
tBDO
Chip Select to Output Low Z
tGHQZ
tOHZ
tAXOX
tOH
Chip Select Access Time
(CE1)
--
--
70
--
--
55
ns
Chip Select Access Time
(CE2)
--
--
70
--
--
55
ns
(LB,UB)
--
--
35
--
--
30
ns
--
--
35
--
--
30
ns
10
--
--
ns
Data Byte Control Access Time
Output Enable to Output Valid
(CE2,CE1)
10
--
--
Data Byte Control to Output Low Z (LB,UB)
10
--
--
10
--
--
ns
Output Enable to Output in Low Z
10
--
--
10
--
--
ns
Chip Deselect to Output in High Z (CE2,CE1)
0
--
35
0
--
30
ns
Data Byte Control to Output High Z (LB,UB)
0
--
35
0
--
30
ns
Output Disable to Output in High Z
0
--
30
0
--
25
ns
Output Disable to Address Change
10
--
--
10
--
--
ns
NOTE :
1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle .
tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
R0201-BS616LV8015
4
Revision 2.4
April 2002
BSI
BS616LV8015
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t RC
ADDRESS
t
t
AA
t
ACS2
t
ACS1
t OH
OH
D OUT
READ CYCLE2 (1,3,4)
CE2
CE1
t
t CHZ(5)
(5)
CLZ
D OUT
READ CYCLE3 (1,4)
t RC
ADDRESS
t
AA
OE
t
CE2
t
t
CE1
t
t
t
OE
OH
ACS2
OLZ
t
ACS1
(5)
CLZ
OHZ
(5)
(1,5)
t
CHZ
t
BDO
LB,UB
t
BE
t
BA
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS616LV8015
5
Revision 2.4
April 2002
BSI
BS616LV8015
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC, Vcc=5V)
WRITE CYCLE
JEDEC
PARAMETER
PARAMETER
NAME
NAME
t AVAX
tE1LWH
t AVWL
t AVWH
tWLWH
tWHAX
tBW
tWLQZ
tDVWH
tWHDX
tGHQZ
t WC
t CW
t AS
t AW
t WP
t WR
t BW (1)
t WHZ
t DW
t DH
t OHZ
tWHOX
t OW
BS616LV8015-70
MIN. TYP. MAX.
BS616LV8015-55
MIN. TYP. MAX.
Write Cycle Time
70
--
55
Chip Select to End of Write
70
--
--
55
Address Setup Time
0
--
--
0
Address Valid to End of Write
70
--
--
55
Write Pulse Width
35
--
--
0
--
Date Byte Control to End of Write (LB,UB)
30
Write to Output in High Z
0
Data to Write Time Overlap
30
Data Hold from Write Time
0
Output Disable to Output in High Z
0
End of Write to Output Active
5
DESCRIPTION
(CE2,CE1,WE)
Write recovery Time
--
--
UNIT
--
ns
--
--
ns
--
--
ns
--
--
ns
30
--
--
ns
--
0
--
--
ns
--
--
25
--
--
ns
--
30
0
--
25
ns
--
--
25
--
--
ns
--
--
0
--
--
ns
--
30
0
--
25
ns
--
--
5
--
--
ns
NOTE :
1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle.
„ SWITCHING WAVEFORMS (WRITE CYCLE)
t
WRITE CYCLE1 (1)
WC
ADDRESS
(3)
t WR
OE
CE2
(5)
(11)
t CW
(5)
CE1
t
BW
(5)
LB,UB
t AW
WE
(3)
t WP
t AS
(2)
(4,10)
t OHZ
D OUT
t DH
t DW
D IN
R0201-BS616LV8015
6
Revision 2.4
April 2002
BSI
BS616LV8015
WRITE CYCLE2 (1,6)
t WC
ADDRESS
CE2
(11)
t
(5)
CE1
t
BW
(5)
LB,UB
t
WE
CW
AW
t WR
t WP
(3)
(2)
t
t AS
DH
(4,10)
t WHZ
D OUT
(7)
(8)
t DW
t
DH
(8,9)
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
R0201-BS616LV8015
7
Revision 2.4
April 2002
BSI
BS616LV8015
„ ORDERING INFORMATION
BS616LV8015
X X
-- Y Y
SPEED
55:55ns
70: 70ns
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
B :BGA - 48 PIN(8x10mm)
1.4 Max.
0.25 ̈́ 0.05
„ PACKAGE DIMENSIONS
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
SIDE VIEW
D
0.1
D1
N
D
E
D1
E1
e
48
10.0
8.0
5.25
3.75
0.75
0.35̈́ 0.05
E1
E ̈́ 0.1
e
SOLDER BALL
VIEW A
48 mini-BGA (8 x 10mm)
R0201-BS616LV8015
8
Revision 2.4
April 2002
BSI
BS616LV8015
REVISION HISTORY
Revision
Description
Date
2.2
2001 Data Sheet release
Apr. 15, 2001
2.3
Modify Standby Current (Typ.
and Max.)
Jun. 29, 2001
2.4
April,11,2002
Modify some AC parameters.
Modify 5V ICCSB1_Max(I-grade)
from 50uA to 100uA.
R0201-BS616LV8015
9
Note
Revision 2.4
April 2002
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