PHILIPS FBL2040 3.3v btl8-bit ttl to btl transceiver Datasheet

INTEGRATED CIRCUITS
FBL2040
3.3V BTL8-bit TTL to BTL transceiver
Product specification
IC23 Data Handbook
1998 Dec 07
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
• Compatible with IEEE Futurebus+ or proprietary BTL backplanes
• Controlled output ramp and multiple GND pins minimize ground
FEATURES
• 3.3V version of FB2040A with 70% power savings
• 8-bit BTL transceivers
• Separate I/O on TTL A-port
• Inverting
• Drives heavily loaded backplanes with equivalent load
bounce
• Each BTL driver has a dedicated Bus GND for a signal return
• Glitch-free power up/power down operation
• Low ICC current
• Tight output skew
• Supports live insertion
• Pins for the optional JTAG boundary scan function are provided
• High density packaging in plastic Quad Flat Pack
impedances down to 10Ω.
• High drive 100mA BTL open collector drivers on B-port
• Allows incident wave switching in heavily loaded backplane buses
• Reduced BTL voltage swing produces less noise and reduces
power consumption
• Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
QUICK REFERENCE DATA
SYMBOL
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
AIn to Bn
4.4
3.1
ns
tPLH
tPHL
Propagation delay
Bn to AOn
3.4
3.2
ns
COB
Output capacitance (B0 – B7 only)
IOL
Output current (B0 – B7 only)
ICC
PARAMETER
Supply current
4
pF
100
mA
Standby
4
AIn to Bn
(outputs Low )
8
Bn to AOn
(outputs Low)
18
AIn to Bn
(outputs High)
13
Bn to AOn
(outputs High)
16
mA
ORDERING INFORMATION
PACKAGES
COMMERCIAL RANGE
VCC = 3V±10%; Tamb = –40°C to +85°C
DRAWING
NUMBER
52-pin Plastic Quad Flat Pack (QFP)
FBL2040BB
SOT379-1
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.
PARAMETER
SYMBOL
VCC
Supply voltage
VIN
Input voltage
IIN
RATING
UNIT
-0.5 to +4.6
V
AI0 – AI7, OEB0, OEB1, OEA
-0.5 to +7.0
B0 – B7
-0.5 to +3.5
V
Input current
-18 to +5.0
mA
VOUT
Voltage applied to output in High output state
-0.5 to +7.0
V
IOUT
O
Current applied to output in Low
output state
Tamb
Operating free-air temperature range
-40 to +85
°C
TSTG
Storage temperature
-65 to +150
°C
1998 Dec 07
2
A0 – A7
64, –64
B0 – B7
200
mA
853-2136 20492
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
B0/B0
TMS (option)
BUS GND
TCK (option)
BUS VCC
OEB1
OEA
OEB0
BIAS V
LOGIC VCC
AI0
AO0
AO1
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
BUS GND
LOGIC GND
1
39
AI1
2
38
B1
AI2
3
37
BUS GND
36
B2
35
BUS GND
34
B3
33
BUS GND
32
B4
31
BUS GND
AO2
4
LOGIC GND
5
AO3
6
LOGIC GND
7
AI3
8
AI4
9
AO4
10
30
B5
LOGIC GND
11
29
BUS GND
AO5
12
28
B6
LOGIC GND
13
27
BUS GND
8-Bit Transceiver
FBL2040
52-lead PQFP
NC
AI7
BUS VCC
TDI (option)
AO7
B7
SG00089
or if OEB1 is High, the B-port is inactive and is at the level of the
backplane signal.
DESCRIPTION
The FBL2040 is an 8-bit bidirectional BTL transceiver and is
intended to provide the electrical interface to a high performance
wired-OR bus. The FBL2040 is an inverting transceiver.
To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
3.3V level while VCC is Low. If live insertion is not a requirement, the
BIAS V pin should be tied to a VCC pin.
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V.
The LOGIC GND and BUS GND pins are isolated in the package to
minimize noise coupling between the BTL and TTL sides. These
pins should be tied to a common ground external to the package.
The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced
capacitive loading by placing an internal series diode on the drivers.
BTL also provides incident wave switching, a necessity for high
performance backplanes.
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be very
infrequent and impossible to trouble-shoot.
The A-port operates at TTL levels with separate I/O. The 3-state
A-port drivers are enabled when OEA goes High after an extra 6ns
delay which is built in to provide a break-before-make function.
When OEA goes Low, A-port drivers become High impedance
without any extra delay. During power on/off cycles, the A-port
drivers are held in a High impedance state when VCC is below 1.3V.
The LOGIC VCC and BUS VCC pins are also isolated internally to
minimize noise and may be externally decoupled separately or
simply tied together.
JTAG boundary scan pins are provided with signals TMS, TCK, TDI
and TDO. TMS and TCK are no-connects (no bond wires) and TDI
and TDO are shorted together internally. Boundary scan
functionality is not implemented at this time.
The B-port has two output enables, OEB0 and OEB1. When OEB0
is High and OEB1 is Low the output is enabled. When OEB0 is Low
1998 Dec 07
TDO (option)
AI6
BG GND
BG VCC
AO6
AI5
LOGIC GND
14 15 16 17 18 19 20 21 22 23 24 25 26
3
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
PIN DESCRIPTION
SYMBOL
PIN NUMBER
TYPE
AI0 – AI7
51, 2, 3, 8, 9, 14, 18, 24
Input
NAME AND FUNCTION
AO0 – AO7
50, 52, 4, 6, 10, 12, 16, 20
Output
B0 – B7
40, 38, 36, 34,
32, 30, 28, 26
I/O
OEB0
46
Input
Enables the B outputs when High
OEB1
45
Input
Enables the B outputs when Low
OEA
47
Input
Enables the A outputs when High
BUS GND
41, 39, 37, 35, 33, 31, 29, 27
GND
Bus ground (0V)
LOGIC GND
1, 5, 7, 11, 13, 15
GND
Logic ground (0V)
BUS VCC
23, 43
Power
Positive supply voltage
LOGIC VCC
49
Power
Positive supply voltage
BG VCC
17
Power
Band Gap threshold voltage reference
BG GND
19
GND
Band Gap threshold voltage reference ground
BIAS V
48
Power
Live insertion pre-bias pin
TMS
42
Input
Test Mode Select (optional, if not implemented then no-connect)
TCK
44
Input
Test Clock (optional, if not implemented then no-connect)
TDI
22
Input
Test Data In (optional, if not implemented then shorted to TDO)
TDO
21
Output
Test Data Out (optional, if not implemented then shorted to TDI)
NC
25
NC
Data inputs (TTL)
3-state outputs (TTL)
Data inputs/Open Collector outputs. High current drive (BTL)
No Connect
FUNCTION TABLE
MODE
AIn to Bn
Disable Bn out
outputs
uts
Bn to AOn
Disable AOn outputs
H** =
B* =
INPUTS
OUTPUTS
AIn
Bn*
OEB0
OEB1
OEA
AOn
Bn*
L
—
H
L
L
Z
H**
H
—
H
L
L
Z
L
L
—
H
L
H
L
H**
H
—
H
L
H
H
L
X
X
L
X
X
X
H**
X
X
X
H
X
X
H**
X
L
L
X
H
H
Input
X
H
X
H
H
L
Input
X
L
X
H
H
H
Input
X
H
L
X
H
L
Input
—
X
X
X
L
Z
X
Goes to level of pull-up voltage
Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.
1998 Dec 07
4
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
LIMITS
PARAMETER
MIN
NOM
MAX
3.0
3.3
3.6
Supply voltage
VIH
High-level in
input
ut voltage
VIL
Low-level in
input
ut voltage
IIK
Input clamp current
IOH
High-level output current
IOL
Low-level out
output
ut current
COB
Output capacitance on B port
Tamb
Operating free-air temperature range
Except B0–B7
2.0
B0 – B7
1.62
UNIT
V
V
1.55
Except B0–B7
0.8
B0 – B7
1.47
V
-18
mA
AO0 – AO7
-32
mA
AO0 – AO7
32
B0 – B7
100
6
–40
mA
7
pF
+85
°C
LIVE INSERTION SPECIFICATIONS
SYMBOL
LIMITS
PARAMETER
Voltage difference between the Bias voltage
and VCC after the PCB is plugged in.
UNIT
MIN
TYP
MAX
–
–
0.5
V
VBIASV
Bias pin voltage
IBIASV
S
Bias pin ((IBIASV) input
DC current
VCC = 0 V, Bias V = 3.6V
1.2
mA
VCC = 3.3V, Bias V = 3.6V
10
µA
VBn
Bus voltage during prebias
B0 – B8 = 0V, Bias V = 3.3V
ILM
Fall current during prebias
B0 – B8 = 2V, Bias V = 1.3 to 2.5V
IHM
Rise current during prebias
B0 – B8 = 1V, Bias V = 3 to 3.6V
IBnPEAK
Peak bus current during
insertion
VCC = 0 to 3.3V, B0 – B8 = 0 to 2.0V,
Bias V = 2.7 to 3.6V, OEB0 = 0.8V, tr = 2ns
10
IOL
O OFF
Power up current
VCC = 0 to 3.3V, OEB0 = 0.8V
100
VCC = 0 to 1.2V, OEB0 = 0 to 5V
100
tGR
Input glitch rejection
1998 Dec 07
VCC = 3.3V
5
1.62
2.1
V
1
µA
µA
-1
1.0
1.35
mA
µA
ns
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
LOGIC DIAGRAM FOR FBL2040
OEB0
OEB1
OEA
46
45
47
40
AI0
AO0
51
50
38
AI1
AO1
2
AO2
3
TTL
Levels
AO3
8
AO4
BTL
Levels
9
AO5
14
AO6
18
AO7
TMS
TCK
TDI
TDO
NC
=
LOGIC VCC
=
LOGIC GND
=
=
BUS VCC
BUS GND
=
BIAS V
=
=
BG VCC
BG GND
=
B6
16
26
AI7
B5
12
28
AI6
B4
10
30
AI5
B3
6
32
AI4
B2
4
34
AI3
B1
52
36
AI2
B0
24
B7
20
42
44
22
21
(Future JTAG Boundary Scan option)
25
49
1, 5, 7, 11, 13, 15
23, 43
27, 29, 31, 33, 35, 37, 39, 41
48
17
19
SG00077
1998 Dec 07
6
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
symbol
IOH
High level output current
IOFF
O
Power off output current
Power-off
VOH
High level output
High-level
out ut
voltage
VOL
test conditions1
parameter
Low-level output voltage
B0 – B7
B0 – B7
AO0 –
AO73
AO0 – AO73
B0 – B7
VIK
Input clamp voltage
g current
Input leakage
High-level input current
max
100
VCC = 0V, VIL = MAX, VOH = 1.9V
100
VCC = 0V, VIL = MAX, VOH = 1.9V@85°C
300
µA
µA
VCC
–0.2
V
VCC = MIN; IOH = -8mA
2.4
V
VCC = MIN; IOH = -32mA
2.0
V
VCC = MIN; IOL = 16mA
0.4
V
VCC = MIN; IOL = 32mA
0.5
V
VCC = MIN, IOL = 4mA
0.5
VCC = MIN, IOL = 100mA
0.75
1.0
–0.85
1.20
-1.2
V
V
±1.0
VCC = 3.6V; VI = VCC or 100mV
VCC = 0V or 3.6V; VI = 5.5V
10
AI0 – AI7
VCC = 3.6V; VI = VCC
1
B0 – B7
unit
VCC = MIN to MAX; IOH = -100µA
Control/
AI0 – AI7
Note 4
IIH
typ2
VCC = MAX, VIL = MAX, VOH = 1.9V
VCC = MIN, II = IIK = –18mA
Control pins
II
limits
min
VCC = 3.6V; VI = 100mV
–5
MAX VI = 1
9V
VCC = MAX,
1.9V
100
VCC = MAX, VI = 3.5V, note 5
100
VCC = MAX, VI = 3.75V, Note 5 @ –40°C
100
µ
µA
µA
mA
IIL
Low level input current
Low-level
B0 – B7
-100
100
µA
IOZH
Off-state output current
AO0 – AO7
VCC = MAX, VO =3V
5
µA
IOZL
Off-state output current
AO0 – AO7
VCC = MAX, VO = 0.5V
-5
µA
ICCZ
ICCH
ICCL
ICCH
ICCL
Supply current
Supply
Su
ly current (total)
Supply
Su
ly current (total)
B→A
A→B
VCC = MAX,
MAX VI = 0.75V
0 75V
VCC = MAX, outputs disabled, VI = GND or 0.0
16
31
VCC = MAX, outputs High, VI = GND or 0.0
16
35
VCC = MAX, outputs Low, VI = GND or 0.0
18
39
VCC = MAX, outputs High, VI = GND or 0.0
13
30
VCC = MAX, outputs Low, VI = GND or 0.0
8
16
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at VCC = 3.3V, TA = 25°C.
3. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side.
4. Unused pins are at VCC or GND.
5. For B port input voltage between 3 and 5 volt; IIH will be greater than 100mA but the part will continue to function normally (clamping circuit
is Active). This is not a tested condition.
1998 Dec 07
7
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (A TO B)
SYMBOL
PARAMETER
Tamb = +25°C, VCC = 3.3V,
RL = 9Ω
TEST CONDITION
Tamb = –40 to +85°C,
VCC = 3.3V±10%,
RL = 9Ω
UNIT
MIN
TYP
MAX
MIN
MAX
tPLH
tPHL
Propagation delay,
AIn to Bn
1.0
1.2
2.7
3.0
5.7
5.1
1.0
1.0
6.3
5.6
ns
tPLH
tPHL
OEB0 to Bn
1.4
2.0
3.1
4.1
5.0
6.4
1.0
1.9
6.1
6.9
ns
tPLH
tPHL
OEB1 to Bn
1.5
1.4
3.3
3.2
5.3
5.0
1.0
1.1
6.0
5.8
ns
tTLH
tTHL
Transition time, Bn Port
(1.3V to 1.8V)
1.0
1.2
1.7
1.9
2.5
2.5
0.5
0.5
3.0
3.0
ns
tSK(O)
Output skew between receivers
in same package
0.5
1.0
1.5
ns
tSK(P)
Pulse skew
|tPHL – tPLH| MAX
0.3
1.0
1.5
ns
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (A TO B)
SYMBOL
PARAMETER
Tamb = +25°C, VCC = 3.3V,
RL = 16.5Ω
TEST CONDITION
Tamb = –40 to +85°C,
VCC = 3.3V±10%,
RL = 16.5Ω
UNIT
MIN
TYP
MAX
MIN
MAX
tPLH
tPHL
Propagation delay,
AIn to Bn
1.2
1.2
2.8
2.8
4.4
4.6
1.0
1.1
5.2
5.1
ns
tPLH
tPHL
OEB0 to Bn
1.8
1.8
3.6
3.8
5.6
5.9
1.2
1.7
6.5
6.3
ns
tPLH
tPHL
OEB1 to Bn
1.6
1.3
3.4
3.0
6.2
4.8
1.0
1.0
6.0
5.6
ns
tTLH
tTHL
Transition time, Bn Port
(1.3V to 1.8V)
1.0
1.2
1.7
1.9
2.5
2.5
0.5
0.5
3.0
3.0
ns
tSK(O)
Output skew between receivers
in same package
0.5
1.0
1.5
ns
tSK(P)
Pulse skew
|tPHL – tPLH| MAX
0.3
1.0
1.5
ns
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (B TO A)
SYMBOL
PARAMETER
Tamb = +25°C, VCC = 3.3V
TEST CONDITION
Tamb = –40 to +85°C,
VCC = 3.3V±10%
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation delay,
Bn to AOn
1.5
1.7
3.4
3.6
5.4
5.5
1.3
1.5
6.1
6.8
ns
tPLH
tPHL
OEA to AOn
2.1
2.0
4.0
3.7
5.9
5.5
1.9
1.4
6.5
6.5
ns
tPLH
tPHL
OEA to AOn
2.0
1.0
1.8
1.0
5.9
4.3
1.8
1.0
6.2
4.8
ns
tTLH
tTHL
Transition time, AOn Port
(10% to 90% or 90% to 10%)
1.3
1.7
2.2
2.6
2.5
2.5
0.9
0.8
3.0
3.0
ns
tSK(O)
Output skew between receivers
in same package
0.5
1.0
1.5
ns
tSK(P)
Pulse skew
|tPHL – tPLH| MAX
0.3
1.0
1.5
ns
1998 Dec 07
8
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
AC WAVEFORMS
VM
AIn, Bn
OEB1
AIn, Bn
OEB0
VM
tPLH
VM
tPHL
VM
AOn, Bn
VM
tPHL
VM
tPLH
AOn, Bn
Waveform 1. Propagation Delay for Data
or Output Enable to Output
VM
VM
Waveform 2. Propagation Delay for Data
or Output Enable to Output
VM
AIn, Bn
tSK(o)
AOn, Bn
VM
Waveform 3. Output Skews
OEA
tPZH
AOn
OEA
VM
VM
VM
VOH -0.3V
AOn
OV
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
VM
tPLZ
VM
VOL +0.3V
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
NOTE: VM = 1.55V for Bn, VM = 1.5V for all others.
1998 Dec 07
VM
tPZL
tPHZ
9
SG00078
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL to BTL transceiver
FBL2040
TEST CIRCUIT AND WAVEFORMS
VCC
BIAS
V
VIN
RL
VOUT
PULSE
GENERATOR
tW
90%
7.0V
NEGATIVE
PULSE
RT
CL
VM
VM
10%
D.U.T.
RL
10%
tTHL
(tf)
tTLH
(tr)
tTHL
VM
(tr)
(tf)
VIN
90%
VM
10%
Test Circuit for 3-State Outputs on A Port
LOW V
tTLH
90%
POSITIVE
PULSE
VIN
90%
10%
tW
LOW V
VM = 1.55V for Bn, VM = 1.5V for all others.
Input Pulse Definitions
SWITCH POSITION
TEST
SWITCH
tPLZ, tPZL
All other
closed
open
VCC
BIAS
V
VIN
2.0V (for RU = 9 Ω)
2.1V (for RU = 16.5 Ω)
VOUT
PULSE
GENERATOR
INPUT PULSE REQUIREMENTS
Family
FB+
Amplitude
Low V
Rep. Rate
A Port
3.0V
0.0V
1MHz
500ns 2.5ns
2.5ns
B Port
2.0V
1.0V
1MHz
500ns 2.5ns
2.5ns
tW
tTLH
tTHL
RU
D.U.T.
RT
CD
Test Circuit for Outputs on B Port
DEFINITIONS:
RL = Load Resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of pulse generators.
CD = Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
RU = Pull up resistor; see AC CHARACTERISTICS for value.
SG00059
1998 Dec 07
10
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL TO BTL transceiver
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
1998 Dec 07
11
74FBL2040
SOT379-1
Philips Semiconductors
Product specification
3.3V BTL 8-bit TTL TO BTL transceiver
74FBL2040
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Document order number:
1998 Dec 07
12
Date of release: 05-96
9397-750-04973