Anachip AP3845S8 High performance current mode pwm controller Datasheet

AP3842/3/4/5
High Performance Current Mode PWM Controller
„ Features
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„ General Description
Optimized for Off-Line and DC to DC Converters
Low Start-Up Current (≦0.5mA)
Automatic Feed Forward Compensation
Pulse-by-Pulse Current Limiting
Enhanced Load Response Characteristics
Under-Voltage Lockout (UVLO) with Hysteresis
Double Pulse Suppression
High Current Totem Pole Output
Internally Trimmed Bandgap Reference
Current Mode Operation to 500KHZ
Low Ro Error Amplifier
The AP3842/3/4/5 family of control ICs provides the
necessary features to implement off-line or DC to
DC fixed frequency current mode control schemes
with a minimal external parts count. Internally
implemented circuits include under voltage lockout
featuring start-up current less than 0.5 mA, a
precision reference trimmed for accuracy at the
error amp input, logic to insure latched operation, a
PWM comparator which also provides current limit
control, and a totem pole output stage designed to
source or sink high peak current. The output stage,
suitable for driving N-Channel MOSFETs, is low in
the off-state.
„ Pin Connections
Differences between members of this family are the
under-voltage lockout thresholds and maximum
duty cycle ranges. The AP3842 and AP3844 have
UVLO thresholds of 16V(on) and 10V(off), ideally
suited for off-line applications. The corresponding
thresholds for the AP3843 and AP3845 are 8.5V
and 7.6V. The AP3842 and AP3843 can operate to
duty cycles approaching 100%. A range of the zero
to < 50% is obtained by the AP3844 and AP3845
by the addition of an internal toggle flip flop which
blanks the output off every other clock cycle.
PDIP-8L, SOP-8L
Top View
COMP.
1
8
VREF
VFB
2
7
VI
ISENSE
3
6
OUTPUT
RT/CT
4
5
GROUND
„ Ordering Information
AP 384X X X X
Part No.
2:3842
3:3843
4:3844
5:3845
Package
S8:SOP-8L
N8:PDIP-8L
Lead Free
Packing
Blank: Tube
Blank : Normal
L : Lead Free Package A : Taping
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev.1.0 Oct.11, 2004
1/8
AP3842/3/4/5
High Performance Current Mode PWM Controller
„ Block Diagram ( toggle flip flop used only in AP3844 and AP3845 )
Vi
7
36V
GROUND
5
UVLO
16V
2.50V
RT/CT
4
ERROR AMP.
VREF GOOD
LOGIC
6
OUTPUT
T
2R
VFB
CURRENT
SENSE
VREF
5V 50mA
INTERNAL
BIAS
OSC.
2
COMP
8
5V
REF
S/R
S
R
R
1
1V
CURRENT
SENSE
COMPARATOR
3
PWM
LATCH
AP384X
„ Absolute Maximum Ratings
Symbol
Vi
Vi
Io
Eo
Ptot
Ptot
Tstg
TL
Parameter
Supply Voltage (low impedance source)
Supply Voltage (li < 30mA)
Output Current
Output Energy (capacitive load)
Analog Inputs (pins2,3)
Error Amplifier Output Sink Current
Power Dissipation at Tamb ≦500C (PDIP8)
Power Dissipation at Tamb ≦250C (SOP8)
Storage Temperature Range
Lead Temperature (soldering 10s)
Value
36
Self Limiting
±0.7
5
-0.3 to 5.5
10
1.25
800
-65 to 150
260
Unit
V
A
µJ
V
mA
W
mW
o
C
o
C
*Notes: 1. All voltages are with respect to pin 5, all currents are positive into the specified terminal.
„ Electrical Characteristics
(Unless otherwise stated, these specifications apply for
Symbol
Parameter
o
0≦Tamb≦70 C for AP384X ; Vi = 15V(note 5); RT = 10KΩ;CT = 3.3nF)
Test Conditions
AP384X
Min. Typ. Max.
Unit
REFERENCE SECTION
VREF
Output Voltage
∆VREF
Line Regulation
∆VREF
Load Regulation
∆VREF/∆T
Temperature Stability
Total Output Variation
eN
ISC
Tj = 250C I0=1mA
4.90 5.00 5.10
V
12V≦Vi≦25V
2
20
mV
1mA≦Io≦20mA
3
25
mV
(Notes 2)
0.2 0.4 mV/0C
Line, Load, Temperature (Notes 2) 4.82
5.18
V
10Hz≦f≦10KHz Tj=250C (Notes
50
µV
Output Noise Voltage
2)
0
Long Term Stability
Tamb=125 C, 1000Hrs (Notes 2)
5
25
mV
Output Short Circuit current
-85 -120 mA
Anachip Corp.
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Rev.1.0 Oct.11, 2004
2/8
AP3842/3/4/5
High Performance Current Mode PWM Controller
„ Electrical Characteristics(Continued)
(Unless otherwise stated, these specifications apply for
Symbol
Parameter
OSCILLATOR SECTION
fs
Oscillator Frequency
Voltage Stability
Temperature Stability
V4
Amplitude
Discharge Current
ERROR AMP SECTION
V2
Feedback Input Voltage
Ib
Input Bias Current
AVOL
B
Unity Gain Bandwidth
Supply Voltage Rejection
SVRR
Ratio
IO
Output Sink Current
IO
Output Source Current
VOUT High
VOUT Low
CURRENT SENSE SECTION
Gv
Gain
V3
Maximum Input Signal
Supply Voltage Rejection
SVRR
Ratio
Ib
Input Bias Current
Delay to Output
OUTPUT SECTION
VOL
Output Low Level
VOH
Output High Level
Tr
Rise Time
Tf
Fall Time
VOLS
UVLO Saturation
UNDER-VOLTAGE LOCKOUT SECTION
o
0≦Tamb≦70 C for AP384X ; Vi = 15V(note 5); RT = 10KΩ;CT = 3.3nF)
Test Conditions
Tj=250C (Notes 6, 7)
12V≦Vi≦25V
TMIN≦Tamb≦TMAX (Notes 2)
VPIN4 Peak to Peak
0
Tj=25 C VPIN4=2V
VPIN1=2.5V
VFB=5V
0V≦V0≦4V
Tj=25oC
AP384X
Min. Typ. Max.
49
8.8
KHz
%
%
V
mA
2.42 2.50 2.58
-0.1
-2
65
90
0.7
1
V
µA
dB
MHz
7.8
52
0.2
0.5
1.6
8.3
12V≦Vi≦25V
60
70
dB
VPIN2=2.7V VPIN1=1.1V
VPIN2=2.3V VPIN1=5V
VPIN2=2.3V; RL=15KΩ to ground
VPIN2=2.7V; RL=15KΩ to pin 8
2
-0.5
5
6
-0.8
7
0.8
1.1
mA
mA
V
V
(Notes3&Notes4)
VPIN1=5V (Notes3)
2.85
0.9
3
1
3.15
1.1
V/V
V
12≦Vi≦25V (Notes3)
ISINK= 20mA
ISINK= 200mA
ISOURCE= 20mA
ISOURCE= 200mA
Tj=250C CL=1nF (Notes2)
Tj=250C CL=1nF (Notes2)
Vcc = 6V ; Isink = 1mA
Start Threshold
Min Operating Voltage After
Turn-on
PWM SECTION
Maximum Duty Cycle
70
13
12
Start-up Current
-10
300
µA
ns
0.1
1.6
13.5
13.5
50
50
0.1
0.4
2.2
150
150
1.1
V
V
V
V
ns
ns
V
17.5
9
11.5
8.2
V
V
V
V
50
0
%
%
%
0.3
0.5
mA
12
36
17
mA
V
3842/4
3843/5
3842/4
3843/5
14.5
7.8
8.5
7.0
16
8.4
10
7.6
3842/3
3844/5
94
47
96
48
Ii
Viz
Operating Supply Current
Zener Voltage
Vi=14V,3842/4 ;
Vi=6.5V 3843/5
VPIN2=VPIN3=0V
Ii=25mA
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30
dB
-2
150
Minimum Duty Cycle
TOTAL STANDBY CURRENT
Ist
55
1
Unit
Rev.1.0 Oct.11, 2004
3/8
AP3842/3/4/5
High Performance Current Mode PWM Controller
Notes:2.These parameters, although guaranteed, are not 100% tested in production.
3.Parameter measured at trip point of latch with VPIN2=0.
4.Gain defined as:
∆VPIN1
; 0≦VPIN3≦0.8V
A=
∆VPIN3
5.Adjust Vi above the start threshold before setting at 15V.
6.Output frequency equals oscillator frequency for the AP3842 and AP3843.
7.Output frequency is one and half oscillator frequency for the AP3844 and AP3845.
Figure 1 : Error Amp Configuration.
2.5V
0.8 mA
VFB
Zf
2
COMP
1
Zf
Error amp can source or sink up to 0.5mA
Figure 2 : Under Voltage Lockout.
V
i
I
CC
ON/OFF COMMAND
TO REST OF IC
7
AP3842 AP3843
AP3844 AP3845
V
ON
16V
8.4V
VOFF
10V
7.6V
<17 mA
<1 mA
V
OFF VON
VCC
During Under-Voltage Lockout, the output driver is biased to sink minor amounts of current. Pin 6 should be
shunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakage
currents.
Figure 3 : Current Sense Circuit.
ERROR
AMP
IS
COMP
R
1
R
Rs
2R
C
3
5
1V
CURRENT
SENSE
COMPARATOR
CURRENT
SENSE
GND
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Rev.1.0 Oct.11, 2004
4/8
AP3842/3/4/5
High Performance Current Mode PWM Controller
Peak current(is) is determined by the formula
1.0V
IS max ≈
RS
A small RC filter may be required to suppress switch transients.
Figure 4.
VREF
8
RT/CT
4
RT
CT
GROUND
5
for RT > 5KΩ f=
1.72
RTCT
Figure 5 : Open Loop Test Circuit.
VREF
R
4.7K
T
A
2N2222
1
COMP.
2
VFB
3
ISENSE
VREF
8
Vi
7
100K
ERROR AMP.
ADJUST
1K
ISENSE
AP3842
5K
ADJUST
4.7K
4
OUTPUT
R T/CT
GROUND
C
6
Vi
0.1
uF
0.1
uF
TW
1K
OUTPUT
5
GROUND
T
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and
bypass apacitors should be connected close to pin 5 in a single point ground. The transistor and 5 KΩ
potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
Figure 6 : Shutdown Techniques.
1K
B VREF
1 COMP
330K
3
500K
I
SENSE
SHUTDOWN
SHUTDOWN
TO CURRENT
SENSE RESISTOR
Anachip Corp.
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Rev.1.0 Oct.11, 2004
5/8
AP3842/3/4/5
High Performance Current Mode PWM Controller
Shutdown of the AP3842 can be accomplished in two ways; either raise pin 3 above 1V or pull pin 1 below a
voltage two diode drops above ground. Either one of them causes the output of the PWM comparator to be
high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the
next clock cycle after the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally
latched shutdown may be accomplished by adding an SCR that will be reset by cycling Vi below the lower
UVLO threshold. At this point the reference turns off, allowing the SCR to reset.
Figure 7 : Slope Compensation.
Uref
8
0.1uF
RT
RT/CT 4
CT
R1
Isense
R2
Isense 3
C
Rsense
AP3842/3
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope
compensation for converters requiring duty cycles over 50%. Note that capacitor, C, forms a filter with R2 to
suppress the leading edge switch spikes.
Anachip Corp.
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Rev.1.0 Oct.11, 2004
6/8
AP3842/3/4/5
High Performance Current Mode PWM Controller
„ Package Diagrams
(1) PDIP-8L (Plastic Dual-in-line Package)
D
E1
E-PIN O0.118 inch
E
15 (4X)
PIN #1 INDENT O0.025 DEEP 0.006-0.008 inch
C
7 (4X)
A1
L
A
A2
eB
B
S
Symbol
A
A1
A2
B
B1
B2
C
D
E
E1
e
L
eB
S
e
B1
B2
Dimensions in millimeters
Min.
Nom.
Max.
5.33
0.38
3.1
3.30
3.5
0.36
0.46
0.56
1.4
1.52
1.65
0.81
0.99
1.14
0.20
0.25
0.36
9.02
9.27
9.53
7.62
7.94
8.26
6.15
6.35
6.55
2.54
2.92
3.3
3.81
8.38
8.89
9.40
0.71
0.84
0.97
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Dimensions in inches
Min.
Nom.
Max.
0.210
0.015
0.122
0.130
0.138
0.014
0.018
0.022
0.055
0.060
0.065
0.032
0.039
0.045
0.008
0.010
0.014
0.355
0.365
0.375
0.300
0.313
0.325
0.242
0.250
0.258
0.100
0.115
0.130
0.150
0.330
0.350
0.370
0.028
0.033
0.038
Rev.1.0 Oct.11, 2004
7/8
AP3842/3/4/5
High Performance Current Mode PWM Controller
H
E
(2) SOP-8L (JEDEC Small Outline Package)
L
VIEW "A"
D
0.015x45
7 (4X)
B
e
A1
C
A
A2
7 (4X)
VIEW "A"
y
Symbol
A
A1
A2
B
C
D
E
e
H
L
y
θ
Dimensions In Millimeters
Min.
Nom.
Max.
1.40
1.60
1.75
0.10
0.25
1.30
1.45
1.50
0.33
0.41
0.51
0.19
0.20
0.25
4.80
5.05
5.30
3.70
3.90
4.10
1.27
5.79
5.99
6.20
0.38
0.71
1.27
0.10
0O
8O
Dimensions In Inches
Min.
Nom.
Max.
0.055
0.063
0.069
0.040
0.100
0.051
0.057
0.059
0.013
0.016
0.020
0.0075
0.008
0.010
0.189
0.199
0.209
0.146
0.154
0.161
0.050
0.228
0.236
0.244
0.015
0.028
0.050
0.004
0O
8O
„ Marking Information
Logo
Part No.
2,3,4,5
Blank: normal
L: Lead Free Package
AP384XB
YYWW X X
ID code: internal
Xth Week : 01~52
Year : "01"=2001
"02"=2002
~
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Rev.1.0 Oct.11, 2004
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