FUNCTIONAL BLOCK DIAGRAM AVDD GENERAL DESCRIPTION The AD9253 is a quad, 14-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sampleand-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such DIGITAL SERIALIZER PIPELINE ADC SENSE PIPELINE ADC VIN+D VIN–D PIPELINE ADC DIGITAL SERIALIZER 14 DIGITAL SERIALIZER CLK– CLK+ CLOCK MANAGEMENT SYNC SERIAL PORT INTERFACE SCLK/DTP VCM D0+B D0–B SERIAL LVDS SERIAL LVDS D1+B D1–B FCO+ FCO– D0+C D0–C D1+C D1–C SERIAL LVDS D0+D D0–D SERIAL LVDS D1+D D1–D DCO+ DCO– SERIAL LVDS 14 VIN+C VIN–C SERIAL LVDS AD9253 1V REF SELECT SERIAL LVDS D0+A D0–A D1+A D1–A SERIAL LVDS 14 VIN–B RBIAS VREF AGND DRVDD DIGITAL SERIALIZER PIPELINE ADC VIN+B APPLICATIONS Medical ultrasound High speed imaging Quadrature radio receivers Diversity radio receivers Test equipment PDWN 14 VIN+A VIN–A CSB 1.8 V supply operation Low power: 110 mW per channel at 125 MSPS with scalable power options SNR = 74 dB (to Nyquist) SFDR = 90 dBc (to Nyquist) DNL = ±0.75 LSB (typical); INL = ±2.0 LSB (typical) Serial LVDS (ANSI-644, default) and low power, reduced signal option (similar to IEEE 1596.3) 650 MHz full power analog bandwidth 2 V p-p input voltage range Serial port control Full chip and individual channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Multichip sync and clock divider Programmable output clock and data alignment Programmable output resolution Standby mode 10065-001 FEATURES SDIO/OLM Data Sheet Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter AD9253 Figure 1. as programmable output clock and data alignment and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). The AD9253 is available in a RoHS-compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Small Footprint. Four ADCs are contained in a small, spacesaving package. Low power of 110 mW/channel at 125 MSPS with scalable power options. Pin compatible to the AD9633 12-bit quad ADC. Ease of Use. A data clock output (DCO) operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD9253 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations...................................................... 24 Applications....................................................................................... 1 Power Dissipation and Power-Down Mode ........................... 26 General Description ......................................................................... 1 Digital Outputs and Timing ..................................................... 27 Functional Block Diagram .............................................................. 1 Output Test Modes..................................................................... 30 Product Highlights ........................................................................... 1 Serial Port Interface (SPI).............................................................. 31 Revision History ............................................................................... 2 Configuration Using the SPI..................................................... 31 Specifications..................................................................................... 3 Hardware Interface..................................................................... 32 DC Specifications ......................................................................... 3 Configuration Without the SPI ................................................ 32 AC Specifications.......................................................................... 4 SPI Accessible Features.............................................................. 32 Digital Specifications ................................................................... 5 Memory Map .................................................................................. 33 Switching Specifications .............................................................. 6 Reading the Memory Map Register Table............................... 33 Timing Specifications .................................................................. 6 Memory Map Register Table..................................................... 34 Absolute Maximum Ratings.......................................................... 11 Memory Map Register Descriptions........................................ 37 Thermal Resistance .................................................................... 11 Applications Information .............................................................. 39 ESD Caution................................................................................ 11 Design Guidelines ...................................................................... 39 Pin Configuration and Function Descriptions........................... 12 Power and Ground Recommendations ................................... 39 Typical Performance Characteristics ........................................... 14 Exposed Pad Thermal Heat Slug Recommendations............ 39 AD9253-80 .................................................................................. 14 VCM............................................................................................. 39 AD9253-105 ................................................................................ 16 Reference Decoupling................................................................ 39 AD9253-125 ................................................................................ 18 SPI Port ........................................................................................ 39 Equivalent Circuits ......................................................................... 21 Crosstalk Performance .............................................................. 39 Theory of Operation ...................................................................... 22 Outline Dimensions ....................................................................... 40 Analog Input Considerations.................................................... 22 Ordering Guide .......................................................................... 40 Voltage Reference ....................................................................... 23 REVISION HISTORY 10/11—Revision 0: Initial Version Rev. 0 | Page 2 of 40 Data Sheet AD9253 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation at 1.0 mA (VREF = 1 V) Input Resistance INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Common-Mode Voltage Differential Input Resistance Differential Input Capacitance POWER SUPPLY AVDD DRVDD IAVDD 2 IDRVDD (ANSI-644 Mode)2 IDRVDD (Reduced Range Mode)2 TOTAL POWER CONSUMPTION DC Input Sine Wave Input (Four Channels Including Output Drivers ANSI-644 Mode) Sine Wave Input (Four Channels Including Output Drivers Reduced Range Mode) Power-Down Standby 3 Temp AD9253-80 Min Typ Max 14 AD9253-105 Min Typ Max 14 AD9253-125 Min Typ Max 14 Unit Bits Full Full Full Full Full Full 25°C Full 25°C Guaranteed −0.7 −0.3 +0.1 −0.6 +0.2 +0.6 −10 −5 0 1 1.6 −1 +1.6 ±0.8 −4.0 +4.0 ±1.5 Guaranteed −0.7 −0.3 +0.1 −0.6 +0.2 +0.6 −10 −5 0 1 1.6 −0.8 +1.5 ±0.75 −4.0 4.0 ±2.0 Guaranteed −0.7 −0.3 +0.1 −0.6 +0.2 +0.6 −10 −5 0 1.1 1.6 −0.8 +1.5 ±0.75 −4.0 +4.0 ±2.0 % FSR % FSR % FSR % FSR LSB LSB LSB LSB Full Full Full Full ±2 0.98 1.0 2 7.5 ±2 1.02 0.98 1.0 2 7.5 ±2 1.02 0.98 1.0 2 7.5 ppm/°C 1.02 V mV kΩ 25°C 0.94 0.94 0.94 LSB rms Full Full 2 0.9 5.2 3.5 2 0.9 5.2 3.5 2 0.9 5.2 3.5 V p-p V kΩ pF Full Full Full Full Full 25°C 1.7 1.7 1.8 1.8 131 63 42 1.9 1.9 144 81 1.7 1.7 1.8 1.8 158 67 48 1.7 1.7 1.8 1.8 183 71 53 V V mA mA mA 326 349 25°C 311 371 425 mW Full Full 2 178 2 209 2 236 mW mW 1 481 423 457 1.9 1.9 200 100 Full Full 405 375 405 1.9 1.9 172 95 540 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Measured with a low input frequency, full-scale sine wave on all four channels. 3 Can be controlled via the SPI. 2 Rev. 0 | Page 3 of 40 mW mW AD9253 Data Sheet AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz WORST HARMONIC (SECOND OR THIRD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz WORST OTHER HARMONIC (EXCLUDING SECOND OR THIRD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 70.5 MHz, fIN2 = 72.5 MHz CROSSTALK 2 CROSSTALK (OVERRANGE CONDITION) 3 POWER SUPPLY REJECTION RATIO (PSRR)1, 4 AVDD DRVDD ANALOG INPUT BANDWIDTH, FULL POWER Temp 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C AD9253-80 Min Typ Max AD9253-105 Min Typ Max AD9253-125 Min Typ Max Unit 72.2 75.4 74.9 74.7 72.3 70.7 72.2 75.1 75.0 74.4 73.1 71.2 73 75.3 75.2 74.2 72.2 70.7 dBFS dBFS dBFS dBFS dBFS 70.8 75.3 74.8 74.6 72.1 70.5 69.8 75.0 74.9 74.2 72.8 70.8 71.6 75.2 75.1 74.1 71.9 70.4 dBFS dBFS dBFS dBFS dBFS 25°C 25°C Full 25°C 25°C 12.2 12.1 11.9 11.6 11.5 12.1 12.1 12.0 11.8 11.5 12.2 12.1 12.0 11.6 11.4 Bits Bits Bits Bits Bits 25°C 25°C Full 25°C 25°C 98 93 94 85 84 98 92 89 85 82 98 92 90 85 83 dBc dBc dBc dBc dBc −75 −98 −92 −90 −85 −83 −77 dBc dBc dBc dBc dBc −77 −101 −100 −95 −96 −92 −84 dBFS dBFS dBFS dBFS dBFS 77 75 25°C 25°C Full 25°C 25°C −98 −93 −94 −85 −84 25°C 25°C Full 25°C 25°C −100 −99 −98 −98 −95 25°C Full 25°C 90 −95 −89 88 −95 −89 86 −95 −89 dBc dB dB 25°C 25°C 25°C 48 75 650 48 75 650 48 75 650 dB dB MHz 1 −77 −98 −92 −89 −85 −82 −77 −99 −99 −95 −98 −92 77 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. 3 Overrange condition is specified with 3 dB of the full-scale input range. 4 PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the amplitudes of the spur voltage over the pin voltage, expressed in decibels. 2 Rev. 0 | Page 4 of 40 Data Sheet AD9253 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 Input Voltage Range Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SYNC, SCLK) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO) 3 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) DIGITAL OUTPUTS (D0±x, D1±x), ANSI-644 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D0±x, D1±x), LOW POWER, REDUCED SIGNAL OPTION Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) 1 2 3 Temp Min Full Full Full 25°C 25°C 0.2 AGND − 0.2 Full Full 25°C 25°C 1.2 0 Full Full 25°C 25°C 1.2 0 Full Full 25°C 25°C 1.2 0 Typ Max Unit 3.6 AVDD + 0.2 V p-p V V kΩ pF AVDD + 0.2 0.8 V V kΩ pF AVDD + 0.2 0.8 V V kΩ pF AVDD + 0.2 0.8 V V kΩ pF CMOS/LVDS/LVPECL 0.9 15 4 30 2 26 2 26 5 Full Full 1.79 0.05 V V Full Full 290 1.15 LVDS 345 400 1.25 1.35 Twos complement mV V Full Full 160 1.15 LVDS 200 230 1.25 1.35 Twos complement mV V See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. This is specified for LVDS and LVPECL only. This is specified for 13 SDIO/OLM pins sharing the same connection. Rev. 0 | Page 5 of 40 AD9253 Data Sheet SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 4. Parameter1, 2 CLOCK3 Input Clock Rate Conversion Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD)4 DCO to Data Delay (tDATA)4 DCO to FCO Delay (tFRAME)4 Lane Delay (tLD) Data to Data Skew (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down)5 Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Out-of-Range Recovery Time Temp Min Full Full Full Full 10 10 Full Full Full Full Full Full Full Typ Max Unit 1000 80/105/125 MHz MSPS ns ns 6.25/4.76/4.00 6.25/4.76/4.00 Full 25°C 25°C Full 2.3 300 300 2.3 tFCO + (tSAMPLE/16) (tSAMPLE/16) (tSAMPLE/16) 90 ±50 250 375 16 25°C 25°C 25°C 1 135 1 1.5 (tSAMPLE/16) − 300 (tSAMPLE/16) − 300 ns ps ps ns ns ps ps ps ps ns μs 3.1 (tSAMPLE/16) + 300 (tSAMPLE/16) + 300 ±200 Clock cycles ns fs rms Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Measured on standard FR-4 material. 3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider. 4 tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS. 5 Wake-up time is defined as the time required to return to normal operation from power-down mode. 2 TIMING SPECIFICATIONS Table 5. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Description Limit Unit SYNC to rising edge of CLK+ setup time SYNC to rising edge of CLK+ hold time See Figure 74 Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 74) Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 74) 0.24 0.40 ns typ ns typ 2 2 40 2 2 10 10 10 ns min ns min ns min ns min ns min ns min ns min ns min 10 ns min Rev. 0 | Page 6 of 40 Data Sheet AD9253 Timing Diagrams Refer to the Memory Map Register Descriptions section and Table 21 for SPI register settings. N–1 VIN±x N tA CLK– tEH N+1 tEL CLK+ DCO– tCPD DDR DCO+ DCO– SDR DCO+ FCO– FCO+ D0–A BITWISE MODE D0+A tFCO tFRAME tPD tDATA D12 N – 17 D10 N – 17 D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 0 N – 17 MSB N – 17 D11 N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 0 N – 17 D10 N – 16 D08 N – 16 D06 N – 16 D04 N – 16 D02 N – 16 LSB N – 16 0 N – 16 MSB N – 16 D11 N – 16 D09 N – 16 D07 N – 16 D05 N – 16 D03 N – 16 D01 N – 16 0 N – 16 D05 N – 17 D04 N – 17 D03 N – 17 D02 N – 17 D01 N – 17 LSB N – 17 0 N – 17 0 N – 17 D05 N – 16 D04 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 0 N – 16 0 N – 16 MSB N – 17 D12 N – 17 D11 N – 17 D10 N – 17 D09 N – 17 D08 N – 17 D07 N – 17 D06 N – 17 MSB N – 16 D12 N – 16 D11 N – 16 D10 N – 16 D09 N – 16 D08 N – 16 D07 N – 16 D06 N – 16 tLD D1–A D1+A D12 N – 16 FCO– D0–A D0+A D1–A D1+A Figure 2. 16-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default) Rev. 0 | Page 7 of 40 10065-003 FCO+ BYTEWISE MODE AD9253 Data Sheet N–1 VIN±x N+1 tA N tEH CLK– CLK+ tEL tCPD DCO– DDR DCO+ DCO– SDR DCO+ FCO+ BITWISE MODE tFRAME tFCO FCO– tDATA tPD D0–A D0+A D10 N – 17 D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 D10 N – 16 D08 N – 16 D06 N – 16 MSB N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 MSB N – 16 D09 N – 16 D07 N – 16 D05 N – 17 D04 N – 17 D03 N – 17 D02 N – 17 D01 N – 17 LSB N – 17 D05 N – 16 D04 N – 16 MSB N – 17 D10 N – 17 D09 N – 17 D08 N – 17 D07 N – 17 D06 N – 17 MSB N – 16 D10 N – 16 D04 N – 16 D02 N – 16 LSB N – 16 D05 N – 16 D03 N – 16 D01 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 D09 N – 16 D08 N – 16 D07 N – 16 D06 N – 16 tLD D1–A D1+A FCO– FCO+ BYTEWISE MODE D0–A D0+A 10065-004 D1–A D1+A Figure 3. 12-Bit DDR/SDR, Two-Lane, 1× Frame Mode N–1 VIN±x N tA CLK– tEH N+1 tEL CLK+ DCO– tCPD DDR DCO+ DCO– SDR DCO+ FCO– FCO+ D0–A BITWISE MODE D0+A tFCO tFRAME tPD tDATA D12 N – 17 D10 N – 17 D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 0 N – 17 MSB N – 17 D11 N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 0 N – 17 D10 N – 16 D08 N – 16 D06 N – 16 D04 N – 16 D02 N – 16 LSB N – 16 0 N – 16 MSB N – 16 D11 N – 16 D09 N – 16 D07 N – 16 D05 N – 16 D03 N – 16 D01 N – 16 0 N – 16 D05 N – 17 D04 N – 17 D03 N – 17 D02 N – 17 D01 N – 17 LSB N – 17 0 N – 17 0 N – 17 D05 N – 16 D04 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 0 N – 16 0 N – 16 MSB N – 17 D12 N – 17 D11 N – 17 D10 N – 17 D09 N – 17 D08 N – 17 D07 N – 17 D06 N – 17 MSB N – 16 D12 N – 16 D11 N – 16 D10 N – 16 D09 N – 16 D08 N – 16 D07 N – 16 D06 N – 16 tLD D1–A D1+A D12 N – 16 FCO– D0–A D0+A D1–A D1+A Figure 4. 16-Bit DDR/SDR, Two-Lane, 2× Frame Mode Rev. 0 | Page 8 of 40 10065-005 FCO+ BYTEWISE MODE Data Sheet AD9253 N–1 VIN±x N+1 tA N tEH CLK– CLK+ tEL tCPD DCO– DDR DCO+ DCO– SDR DCO+ tFCO FCO– FCO+ tDATA tPD D0–A BITWISE MODE tFRAME D0+A D10 N – 17 D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 D10 N – 16 D08 N – 16 D06 N – 16 MSB N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 MSB N – 16 D09 N – 16 D07 N – 16 D05 N – 17 D04 N – 17 D03 N – 17 D02 N – 17 D01 N – 17 LSB N – 17 D05 N – 16 D04 N – 16 MSB N – 17 D10 N – 17 D09 N – 17 D08 N – 17 D07 N – 17 D06 N – 17 MSB N – 16 D10 N – 16 D04 N – 16 D02 N – 16 LSB N – 16 D05 N – 16 D03 N – 16 D01 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 D09 N – 16 D08 N – 16 D07 N – 16 D06 N – 16 tLD D1–A D1+A FCO– FCO+ D0–A BYTEWISE MODE D1–A D1+A 10065-006 D0+A Figure 5. 12-Bit DDR/SDR, Two-Lane, 2× Frame Mode N–1 VIN±x tA N tEH CLK– tEL CLK+ DCO– tCPD DCO+ FCO– tFCO tFRAME FCO+ D0+x tDATA tPD MSB N – 17 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB 0 0 MSB D14 D13 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 Figure 6. Wordwise DDR, One-Lane, 1× Frame, 16-Bit Output Mode Rev. 0 | Page 9 of 40 10065-002 D0–x AD9253 Data Sheet N–1 VIN±x tA N tEH CLK– tEL CLK+ DCO– tCPD DCO+ FCO– tFCO tFRAME FCO+ MSB N – 17 D0+x D10 D9 D8 D7 D6 D5 D4 D3 D2 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 D1 N – 17 Figure 7. Wordwise DDR, One-Lane, 1× Frame, 12-Bit Output Mode CLK+ tSSYNC tHSYNC SYNC Figure 8. SYNC Input Timing Requirements Rev. 0 | Page 10 of 40 D0 MSB N – 17 N – 16 D10 N – 16 10065-082 tDATA tPD 10065-079 D0–x Data Sheet AD9253 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND Digital Outputs (D0±x, D1±x, DCO+, DCO−, FCO+, FCO−) to AGND CLK+, CLK− to AGND VIN+x, VIN−x to AGND SCLK/DTP, SDIO/OLM, CSB to AGND SYNC, PDWN to AGND RBIAS to AGND VREF, SENSE to AGND Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Rating Table 7. Thermal Resistance −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V Package Type 48-Lead LFCSP 7 mm × 7 mm (CP-48-13) −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V 1 Air Flow Velocity (m/sec) 0.0 1.0 2.5 θJA1 23.7 20.0 18.7 θJB 7.8 N/A N/A θJC 7.1 N/A N/A Unit °C/W °C/W °C/W θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB. ESD CAUTION −40°C to +85°C 150°C 300°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 11 of 40 AD9253 Data Sheet 48 47 46 45 44 43 42 41 40 39 38 37 VIN+C VIN–C AVDD AVDD SYNC VCM VREF SENSE RBIAS AVDD VIN–B VIN+B PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9253 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 VIN+A VIN–A AVDD PDWN CSB SDIO/OLM SCLK/DTP DRVDD D0+A D0–A D1+A D1–A NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 10065-007 D1–C D1+C D0–C D0+C DCO– DCO+ FCO– FCO+ D1–B D1+B D0–B D0+B 13 14 15 16 17 18 19 20 21 22 23 24 VIN+D 1 VIN–D 2 AVDD 3 AVDD 4 CLK– 5 CLK+ 6 AVDD 7 DRVDD 8 D1–D 9 D1+D 10 D0–D 11 D0+D 12 Figure 9. 48-Lead LFCSP Pin Configuration, Top View Table 8. Pin Function Descriptions Pin No. 0 1 2 3, 4, 7, 34, 39, 45, 46 5, 6 8, 29 9, 10 11, 12 13, 14 15, 16 17, 18 19, 20 21, 22 23, 24 25, 26 27, 28 30 31 32 33 Mnemonic AGND, Exposed Pad VIN+D VIN−D AVDD CLK−, CLK+ DRVDD D1−D, D1+D D0−D, D0+D D1−C, D1+C D0−C, D0+C DCO−, DCO+ FCO−, FCO+ D1−B, D1+B D0−B, D0+B D1−A, D1+A D0−A, D0+A SCLK/DTP SDIO/OLM CSB PDWN 35 36 37 38 40 41 42 43 VIN−A VIN+A VIN+B VIN−B RBIAS SENSE VREF VCM Description Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. ADC D Analog Input True. ADC D Analog Input Complement. 1.8 V Analog Supply Pins. Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. Digital Output Driver Supply. Channel D Digital Outputs. Channel D Digital Outputs. Channel C Digital Outputs. Channel C Digital Outputs. Data Clock Outputs. Frame Clock Outputs. Channel B Digital Outputs. Channel B Digital Outputs. Channel A Digital Outputs. Channel A Digital Outputs. SPI Clock Input/Digital Test Pattern. SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode. SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up. Digital Input, 30 kΩ Internal Pull-Down. PDWN high = power-down device. PDWN low = run device, normal operation. ADC A Analog Input Complement. ADC A Analog Input True. ADC B Analog Input True. ADC B Analog Input Complement. Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. Reference Mode Selection. Voltage Reference Input and Output. Analog Input Common-Mode Voltage. Rev. 0 | Page 12 of 40 Data Sheet Pin No. 44 47 48 AD9253 Mnemonic SYNC VIN−C VIN+C Description Digital Input. SYNC input to clock divider. ADC C Analog Input Complement. ADC C Analog Input True. Rev. 0 | Page 13 of 40 AD9253 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AD9253-80 0 0 AIN = –1dBFS SNR = 75.5dB ENOB = 12.07BITS SFDR = 99.3dBc –40 –60 –80 –100 –120 5 10 15 20 25 30 35 40 5 0 10 15 20 25 30 35 40 Figure 13. Single-Tone 16k FFT with fIN = 140 MHz, fSAMPLE = 80 MSPS 0 AIN = –1dBFS SNR = 73.9dB ENOB = 11.9 BITS SFDR = 92.7dBc –20 AIN = –1dBFS SNR = 70.7dB ENOB = 11.3 BITS SFDR = 83.7dBc –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –40 –60 –80 –100 5 10 15 20 25 30 35 40 FREQUENCY (MHz) –140 10065-089 0 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) Figure 11. Single-Tone 16k FFT with fIN = 30.5 MHZ, fSAMPLE = 80 MSPS 10065-019 –120 Figure 14. Single-Tone 16k FFT with fIN = 200 MHz, fSAMPLE = 80 MSPS 0 120 AIN = –1dBFS SNR = 74.7dB ENOB = 11.9 BITS SFDR = 94.2dBc –20 SFDRFS 100 SNR/SFDR (dBFS/dBc) –40 –60 –80 –100 –120 SNRFS 80 60 SFDR 40 SNR 20 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) Figure 12. Single-Tone 16k FFT with fIN = 70 MHz, fSAMPLE = 80 MSPS –20 –100 10065-017 0 –90 –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 0 10065-030 AMPLITUDE (dBFS) –100 FREQUENCY (MHz) 0 AMPLITUDE (dBFS) –80 –140 Figure 10. Single-Tone 16k FFT with fIN = 9.7 MHz, fSAMPLE = 80 MSPS –140 –60 10065-018 0 FREQUENCY (MHz) –140 –40 –120 10065-016 –140 AIN = –1 DBFS SNR = 72.3dB ENOB = 11.5 BITS SFDR = 85dBc –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –20 Figure 15. SNR/SFDR vs. Analog Input Level, fIN = 9.7 MHz, fSAMPLE = 80 MSPS Rev. 0 | Page 14 of 40 Data Sheet AD9253 100 0 AIN1 AND AIN2 = –7dBFS SFDR = 90.9dBc IMD2 = 91dBc IMD3 = 90.9dBc 90 SFDR (dBc) 80 –40 SNR/SFDR (dBFS/dBc) AMPLITUDE (dBFS) –20 –60 –80 –100 70 SNR (dBFS) 60 50 40 30 20 –120 5 10 15 20 25 30 35 40 FREQUENCY (MHz) 0 10065-033 0 0 –20 100 SNR/SFDR (dBFS/dBc) IMD3 (dBc) –80 80 100 120 140 160 180 200 SFDR (dBc) 95 90 85 80 SFDR (dBFS) SNR (dBFS) –100 75 –78 –66 –54 –42 –30 –18 –6 INPUT AMPLITUDE (dBFS) Figure 17. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 80 MSPS 70 –40 –15 10 35 TEMPERATURE (°C) 60 85 10065-042 IMD3 (dBFS) –120 –90 10065-036 SFDR/IMD3 (dBc/dBFS) 105 –60 60 Figure 18. SNR/SFDR vs. fIN, fSAMPLE = 80 MSPS 0 SFDR (dBc) 40 INPUT FREQUENCY (MHz) Figure 16. Two-Tone 16k FFT with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 80 MSPS –40 20 10065-039 10 –140 Figure 19. SNR/SFDR vs. Temperature, fIN = 10.3 MHz, fSAMPLE = 80 MSPS Rev. 0 | Page 15 of 40 AD9253 Data Sheet AD9253-105 0 0 AIN = –1dBFS SNR = 75.1dB ENOB = 12.02 BITS SFDR = 97.8dBc –40 –60 –80 –100 10 20 30 40 50 0 10 20 30 40 50 Figure 23. Single-Tone 16k FFT with fIN = 140 MHz, fSAMPLE = 105 MSPS 0 AIN = –1dBFS SNR = 74dB ENOB = 11.9 BITS SFDR = 92.1dBc –20 AIN = –1dBFS SNR = 71.2dB ENOB = 11.3 BITS SFDR = 82dBc –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –40 –60 –80 –100 10 20 30 40 50 FREQUENCY (MHz) Figure 21. Single-Tone 16k FFT with fIN = 30.5 MHZ, fSAMPLE = 105 MSPS –140 10 20 30 40 50 FREQUENCY (MHz) Figure 24. Single-Tone 16k FFT with fIN = 200 MHz, fSAMPLE = 105 MSPS 0 120 AIN = –1dBFS SNR = 73.4dB ENOB = 11.9 BITS SFDR = 89.8dBc –20 0 10065-023 0 10065-090 –120 SFDRFS 100 SNR/SFDR (dBFS/dBc) –40 –60 –80 –100 –120 SNRFS 80 60 SFDR 40 SNR 20 0 10 20 30 FREQUENCY (MHz) 40 50 10065-021 0 Figure 22. Single-Tone 16k FFT with fIN = 70 MHz, fSAMPLE = 105 MSPS –20 –100 –90 –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 0 10065-031 AMPLITUDE (dBFS) –100 FREQUENCY (MHz) 0 AMPLITUDE (dBFS) –80 –140 10065-020 0 Figure 20. Single-Tone 16k FFT with fIN = 9.7 MHz, fSAMPLE = 105 MSPS –140 –60 –120 FREQUENCY (MHz) –140 –40 10065-022 –120 –140 AIN = –1dBFS SNR = 73.1dB ENOB = 11.6 BITS SFDR = 85dBc –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –20 Figure 25. SNR/SFDR vs. Analog Input Level, fIN = 9.7 MHz, fSAMPLE = 105 MSPS Rev. 0 | Page 16 of 40 Data Sheet AD9253 100 0 AIN1 AND AIN2 = –7dBFS SFDR = 87.5dBc IMD2 = 92.6dBc IMD3 = 87.5dBc 90 SFDR (dBc) 80 –40 SNR/SFDR (dBFS/dBc) AMPLITUDE (dBFS) –20 –60 –80 –100 70 SNR (dBFS) 60 50 40 30 20 –120 10 20 30 40 0 10065-034 0 50 FREQUENCY (MHz) 0 20 40 60 80 100 120 140 160 180 200 INPUT FREQUENCY (MHz) Figure 26. Two-Tone 16k FFT with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 105 MSPS 10065-040 10 –140 Figure 28. SNR/SFDR vs. fIN, fSAMPLE = 105 MSPS 0 100 –20 95 SNR/SFDR (dBFS/dBc) SFDR (dBc) –40 IMD3 (dBc) –60 –80 90 85 80 SNR (dBFS) SFDR (dBFS) –100 75 –78 –66 –54 –42 –30 –18 –6 INPUT AMPLITUDE (dBFS) Figure 27. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 105 MSPS 70 –40 –15 10 35 TEMPERATURE (°C) 60 85 10065-043 IMD3 (dBFS) –120 –90 10065-037 SFDR/IMD3 (dBc/dBFS) SFDR (dBc) Figure 29. SNR/SFDR vs. Temperature, fIN = 10.3 MHz, fSAMPLE = 105 MSPS Rev. 0 | Page 17 of 40 AD9253 Data Sheet AD9253-125 0 0 AIN = –1dBFS SNR = 75.3dB ENOB = 12.04 BITS SFDR = 98.52dBc –40 –60 –80 –100 –120 10 20 30 40 50 60 Figure 30. Single-Tone 16k FFT with fIN = 9.7 MHz, fSAMPLE = 125 MSPS 0 10 20 30 40 50 60 Figure 33. Single-Tone 16k FFT with fIN = 140 MHz, fSAMPLE = 125 MSPS 0 AIN = –1dBFS SNR = 70.6dB ENOB = 11.2 BITS SFDR = 83.2dBc –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –40 –60 –80 –100 10 20 30 40 50 60 FREQUENCY (MHz) –140 10065-091 0 Figure 31. Single-Tone 16k FFT with fIN = 30.5 MHZ, fSAMPLE = 125 MSPS 0 10 20 30 40 50 60 FREQUENCY (MHz) 10065-027 –120 –120 Figure 34. Single-Tone 16k FFT with fIN = 200 MHz, fSAMPLE = 125 MSPS 0 0 AIN = –1dBFS SNR = 73.2dB ENOB = 11.9 BITS SFDR = 91.2dBc –20 AIN = –1dBFS SNR = 72.4dB ENOB = 11.7 BITS SFDR = 88.4dBc –20 AMPLITUDE (dBFS) –40 –60 –80 –100 –40 –60 –80 –100 –120 –120 10 20 30 40 FREQUENCY (MHz) 50 60 –140 10065-025 0 Figure 32. Single-Tone 16k FFT with fIN = 70 MHz, fSAMPLE = 125 MSPS 0 10 20 30 40 FREQUENCY (MHz) 50 60 10065-081 AMPLITUDE (dBFS) –100 FREQUENCY (MHz) AIN = –1dBFS SNR = 74.2dB ENOB = 12 BITS SFDR = 92.5dBc –20 AMPLITUDE (dBFS) –80 –140 0 –140 –60 10065-026 0 FREQUENCY (MHz) –140 –40 –120 10065-024 –140 AIN = –1dBFS SNR = 73.1dB ENOB = 11.6 BITS SFDR = 85dBc –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –20 Figure 35. Single-Tone 16k FFT with fIN = 140 MHz at fSAMPLE = 122.88 MSPS Rev. 0 | Page 18 of 40 Data Sheet AD9253 100 120 90 SFDRFS SFDR (dBc) 80 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 100 SNRFS 80 60 SFDR 40 SNR 70 SNR (dBFS) 60 50 40 30 20 20 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) 0 10065-032 –90 0 40 60 80 100 120 140 160 180 200 INPUT FREQUENCY (MHz) Figure 36. SNR/SFDR vs. Analog Input Level, fIN = 9.7 MHz, fSAMPLE = 125 MSPS Figure 39. SNR/SFDR vs. fIN, fSAMPLE = 125 MSPS 0 100 SFDR (dBc) AIN1 AND AIN2 = –7dBFS SFDR = 86.2dBc IMD2 = 98.3dBc IMD3 = 86.2dBc –20 95 –40 SNR/SFDR (dBFS/dBc) AMPLITUDE (dBFS) 20 10065-041 10 0 –100 –60 –80 –100 90 85 80 SNR (dBFS) 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 –40 10065-035 –140 Figure 37. Two-Tone 16k FFT with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 125 MSPS –15 10 35 60 85 TEMPERATURE (°C) 10065-044 75 –120 Figure 40. SNR/SFDR vs. Temperature, fIN = 10.3 MHz, fSAMPLE = 125 MSPS 2.5 0 2.0 1.5 SFDR (dBc) 1.0 INL (LSB) –40 IMD3 (dBc) –60 –80 0 –0.5 –1.5 –100 –78 –66 –54 –42 –30 –18 –6 INPUT AMPLITUDE (dBFS) –2.5 0 2000 4000 6000 8000 10000 12000 14000 OUTPUT CODE Figure 41. INL, fIN = 9.7 MHz, fSAMPLE = 125 MSPS Figure 38. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 125 MSPS Rev. 0 | Page 19 of 40 16000 10065-045 –2.0 IMD3 (dBFS) –120 –90 0.5 –1.0 SFDR (dBFS) 10065-038 SFDR/IMD3 (dBc/dBFS) –20 AD9253 Data Sheet 1.0 105 SFDR 0.8 100 0.6 SNR/SFDR (dBFS/dBc) 95 0.4 DNL (LSB) 0.2 0 –0.2 –0.4 90 85 80 SNRFS 75 –0.6 0 2000 4000 6000 8000 10000 12000 14000 65 20 10065-046 –1.0 16000 OUTPUT CODE 45 70 95 120 SAMPLE FREQUENCY (MSPS) 10065-028 70 –0.8 Figure 45. SNR/SFDR vs. Encode, fIN = 9.7 MHz, fSAMPLE = 125 MSPS Figure 42. DNL, fIN = 9.7 MHz, fSAMPLE = 125 MSPS 500,000 105 450,000 0.94 LSB rms 100 400,000 95 SNR/SFDR (dBFS/dBc) 300,000 250,000 200,000 150,000 100,000 N 10065-050 N–4 N–3 N–2 N–1 N+1 N+2 N+3 N+4 N+5 CODE 100 DRVDD 80 60 50 AVDD 30 20 10 0 1 10 FREQUENCY (MHz) 10065-087 PSRR (dB) 70 40 85 80 SNRFS 75 65 20 45 70 95 120 SAMPLE FREQUENCY (MSPS) Figure 46. SNR/SFDR vs. Encode, fIN = 70 MHz, fSAMPLE = 125 MSPS Figure 43. Input-Referred Noise Histogram, fSAMPLE = 125 MSPS 90 90 70 50,000 0 SFDR Figure 44. PSRR vs. Frequency, fCLK = 125 MHz, fSAMPLE = 125 MSPS Rev. 0 | Page 20 of 40 10065-029 NUMBER OF HITS 350,000 Data Sheet AD9253 EQUIVALENT CIRCUITS AVDD AVDD 350Ω SCLK/DTP, SYNC, AND PDWN 30kΩ 10065-012 10065-008 VIN±x Figure 47. Equivalent Analog Input Circuit Figure 51. Equivalent SCLK/DTP, SYNC, and PDWN Input Circuit AVDD 5Ω CLK+ AVDD 15kΩ 0.9V AVDD 15kΩ 10065-009 10065-013 5Ω CLK– 375Ω RBIAS AND VCM Figure 52. Equivalent RBIAS and VCM Circuit Figure 48. Equivalent Clock Input Circuit AVDD AVDD 30kΩ 350Ω SDIO/OLM 30kΩ 30kΩ 350Ω 10065-010 10065-014 CSB Figure 53. Equivalent CSB Input Circuit Figure 49. Equivalent SDIO/OLM Input Circuit DRVDD V AVDD V D0–x, D1–x D0+x, D1+x V V 375Ω VREF 10065-015 DRGND 10065-011 7.5kΩ Figure 50. Equivalent Digital Output Circuit Figure 54. Equivalent VREF Circuit Rev. 0 | Page 21 of 40 AD9253 Data Sheet THEORY OF OPERATION The AD9253 is a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The serializer transmits this converted data in a 16-bit output. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized and aligned to the frame and data clocks. ANALOG INPUT CONSIDERATIONS The analog input to the AD9253 is a differential switchedcapacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance. the output stage of the driving source. In addition, low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a differential capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “Transformer-Coupled FrontEnd for Wideband A/D Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application. Input Common Mode The analog inputs of the AD9253 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 56. An on-chip, common-mode voltage reference is included in the design and is available from the VCM pin. The VCM pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9253, the largest input span available is 2 V p-p. 100 CPAR 80 SNR/SFDR (dBFS/dBc) H VIN+x CSAMPLE S S S S CSAMPLE VIN–x H 10065-051 H CPAR SFDR 90 H SNRFS 70 60 50 40 30 The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 55). When the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from Rev. 0 | Page 22 of 40 20 0.5 0.7 0.9 1.1 VCM (V) Figure 56. SNR/SFDR vs. Common-Mode Voltage, fIN = 9.7 MHz, fSAMPLE = 125 MSPS 1.3 10065-052 Figure 55. Switched-Capacitor Input Circuit Data Sheet AD9253 Differential Input Configurations Internal Reference Connection There are several ways to drive the AD9253 either actively or passively. However, optimum performance is achieved by driving the analog inputs differentially. Using a differential double balun configuration to drive the AD9253 provides excellent performance and a flexible interface to the ADC (see Figure 58) for baseband applications. A comparator within the AD9253 detects the potential at the SENSE pin and configures the reference into two possible modes, which are summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 57), setting VREF to 1.0 V. Table 9. Reference Configuration Summary For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration (see Figure 59), because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9253. SENSE Voltage (V) AGND to 0.2 AVDD Selected Mode Fixed Internal Reference Fixed External Reference Regardless of the configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed. It is not recommended to drive the AD9253 inputs single-ended. Resulting VREF (V) 1.0 internal 1.0 applied to external VREF pin Resulting Differential Span (V p-p) 2.0 2.0 VIN+A/VIN+B VOLTAGE REFERENCE VIN–A/VIN–B A stable and accurate 1.0 V voltage reference is built into the AD9253. VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are summarized in the Internal Reference Connection section and the External Reference Operation section. The VREF pin should be externally decoupled to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. ADC CORE VREF 1.0µF 0.1µF SELECT LOGIC SENSE ADC Figure 57. Internal Reference Configuration 0.1µF 0.1µF C 2V p-p R 33Ω *C1 C 0.1µF ET1-1-I3 VIN+x 33Ω ADC 5pF 33Ω R VCM VIN–x 33Ω C *C1 200Ω 0.1µF C 0.1µF *C1 IS OPTIONAL Figure 58. Differential Double Balun Input Configuration for Baseband Applications ADT1-1WT 1:1 Z RATIO R *C1 VIN+x 33Ω 49.9Ω C R 33Ω ADC 5pF VIN–x VCM *C1 200Ω 0.1µF 0.1μF *C1 IS OPTIONAL Figure 59. Differential Transformer-Coupled Configuration for Baseband Applications Rev. 0 | Page 23 of 40 10065-056 2V p-p 10065-059 R 10065-060 0.5V AD9253 Data Sheet If the internal reference of the AD9253 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 60 shows how the internal reference voltage is affected by loading. 0 –0.5 –1.0 –2.5 –3.0 –3.5 –4.0 0.5 1.0 1.5 2.0 2.5 3.0 LOAD CURRENT (mA) Figure 60. VREF Error vs. Load Current External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 61 shows the typical drift characteristics of the internal reference in 1.0 V mode. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9253 while preserving the fast rise and fall times of the signal that are critical to achieving low jitter performance. However, the diode capacitance comes into play at frequencies above 500 MHz. Care must be taken in choosing the appropriate signal limiting diode. 4 Mini-Circuits® ADT1-1WT, 1:1 Z CLOCK INPUT VREF ERROR (mV) 2 0.1µF XFMR 0.1µF CLK+ 100Ω 50Ω ADC 0.1µF 0 CLK– SCHOTTKY DIODES: HSMS2822 0.1µF –2 10065-064 0 10065-061 –4.5 The RF balun configuration is recommended for clock frequencies between 125 MHz and 1 GHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary winding limit clock excursions into the AD9253 to approximately 0.8 V p-p differential. Figure 62. Transformer-Coupled Differential Clock (Up to 200 MHz) –4 –6 0.1µF –8 –40 –15 10 35 60 TEMPERATURE (°C) 85 10065-062 CLOCK INPUT It is not recommended to leave the SENSE pin floating. CLOCK INPUT CONSIDERATIONS For optimum performance, clock the AD9253 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 48) and require no external bias. CLK+ 50Ω ADC 0.1µF 0.1µF CLK– SCHOTTKY DIODES: HSMS2822 Figure 61. Typical VREF Drift When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7.5 kΩ load (see Figure 54). The internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V. 0.1µF 10065-065 VREF ERROR (%) –2.0 –5.0 The AD9253 has a flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 62 and Figure 63 show two preferred methods for clocking the AD9253 (at clock rates up to 1 GHz prior to internal CLK divider). A low jitter clock source is converted from a singleended signal to a differential signal using either an RF transformer or an RF balun. INTERNAL VREF = 1V –1.5 Clock Input Options Figure 63. Balun-Coupled Differential Clock (Up to 1 GHz) If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 65. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 66. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. In some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and Rev. 0 | Page 24 of 40 Data Sheet AD9253 bypass the CLK− pin to ground with a 0.1 μF capacitor (see Figure 67). 80 Input Clock Divider 75 SNRFS (dBFS) The AD9253 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. The AD9253 clock divider can be synchronized using the external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. SNRFS (DCS ON) SNRFS (DCS OFF) 70 65 55 40 42 44 46 48 50 52 54 DUTY CYCLE (%) Clock Duty Cycle 0.1µF 0.1µF CLK+ 50kΩ AD951x PECL DRIVER 240Ω 50kΩ 100Ω 0.1µF ADC CLK– 10065-066 CLOCK INPUT 240Ω Figure 65. Differential PECL Sample Clock (Up to 1 GHz) 0.1µF CLOCK INPUT 50kΩ AD951x LVDS DRIVER 100Ω 0.1µF ADC CLK– 10065-067 CLOCK INPUT 0.1µF CLK+ 0.1µF 50kΩ Figure 66. Differential LVDS Sample Clock (Up to 1 GHz) VCC 0.1µF 50Ω1 1kΩ AD951x CMOS DRIVER OPTIONAL 0.1µF 100Ω 1kΩ CLK+ ADC CLK– 0.1µF 150Ω RESISTOR IS OPTIONAL. Figure 67. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) Rev. 0 | Page 25 of 40 10065-068 CLOCK INPUT 60 Jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 20 MHz, nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. The AD9253 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9253. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on, as shown in Figure 64. 0.1µF 58 Figure 64. SNR vs. DCS On/Off Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. CLOCK INPUT 56 10065-069 60 AD9253 Data Sheet Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by As shown in Figure 69, the power dissipated by the AD9253 is proportional to its sample rate. The digital power dissipation does not vary significantly because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. 350 The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9253. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. RMS CLOCK JITTER REQUIREMENT 90 14 BITS 80 12 BITS 70 10 BITS 60 8 BITS 50 40 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 30 1 10 100 ANALOG INPUT FREQUENCY (MHz) Figure 68. Ideal SNR vs. Input Frequency and Jitter 1000 10065-070 SNR (dB) 110 16 BITS 250 105 MSPS 80 MSPS 200 65 MSPS 50 MSPS 150 40 MSPS 20 MSPS 100 10 20 30 40 50 60 70 80 90 100 110 120 130 SAMPLE RATE (MSPS) The AD9253 is placed in power-down mode either by the SPI port or by asserting the PDWN pin high. In this state, the ADC typically dissipates 2 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9253 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. 120 100 125 MSPS Figure 69. Analog Core Power vs. fSAMPLE for fIN = 10.3 MHz Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs. 130 300 10065-071 In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 68). ANALOG CORE POWER (mW) 1 SNR Degradation = 20 log10 2 f A t J Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering power-down mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map section for more details on using these features. Rev. 0 | Page 26 of 40 Data Sheet AD9253 DIGITAL OUTPUTS AND TIMING When operating in reduced range mode, the output current is reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p differential) across a 100 Ω termination at the receiver. D0 400mV/DIV D1 400mV/DIV DCO 400mV/DIV FCO 400mV/DIV 4ns/DIV Figure 71. AD9253-125, LVDS Output Timing Example in Reduced Range Mode An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on standard FR-4 material is shown in Figure 72. 500 EYE: ALL BITS ULS: 7000/400354 400 EYE DIAGRAM VOLTAGE (mV) The AD9253 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. If there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than 24 inches and that the differential output traces be close together and at equal lengths. An example of the FCO and data stream with proper trace length and position is shown in Figure 70. Figure 71 shows the LVDS output timing example in reduced range mode. 10065-083 The AD9253 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option (similar to the IEEE 1596.3 standard) via the SPI. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing (or 700 mV p-p differential) at the receiver. 300 200 100 0 –100 –200 –300 –400 –500 –0.8ns –0.4ns 0ns 0.4ns 0.8ns 7k Figure 70. AD9253-125, LVDS Output Timing Example in ANSI-644 Mode (Default) 5k 4k 3k 2k 1k 0 200ps 250ps 300ps 350ps 400ps 450ps 500ps 10065-075 4ns/DIV TIE JITTER HISTOGRAM (Hits) D0 500mV/DIV D1 500mV/DIV DCO 500mV/DIV FCO 500mV/DIV 10065-074 6k Figure 72. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End Termination Only Rev. 0 | Page 27 of 40 AD9253 500 Data Sheet EYE: ALL BITS Figure 73 shows an example of trace lengths exceeding 24 inches on standard FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is the user’s responsibility to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (increasing the current) of all four outputs to drive longer trace lengths. This can be achieved by programming Register 0x15. Even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. ULS: 8000/414024 EYE DIAGRAM VOLTAGE (mV) 400 300 200 100 0 –100 –200 –300 –400 –500 –0.8ns –0.4ns 0ns 0.4ns –0.8ns The format of the output data is twos complement by default. An example of the output coding format can be found in Table 10. To change the output data format to offset binary, see the Memory Map section. 12k TIE JITTER HISTOGRAM (Hits) 10k Data from each ADC is serialized and provided on a separate channel in two lanes in DDR mode. The data rate for each serial stream is equal to 16 bits times the sample clock rate, with a maximum of 500 Mbps/lane [(16 bits × 125 MSPS)/(2 × 2) = 500 Mbps/lane)]. The lowest typical conversion rate is 10 MSPS. See the Memory Map section for details on enabling this feature. 8k 6k 4k 0k –800ps –600ps –400ps –200ps 0ps 200ps 400ps 600ps 10065-076 2k Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Greater than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End Termination Only Two output clocks are provided to assist in capturing data from the AD9253. The DCO is used to clock the output data and is equal to four times the sample clock (CLK) rate for the default mode of operation. Data is clocked out of the AD9253 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) capturing. The FCO is used to signal the start of a new output byte and is equal to the sample clock rate in 1× frame mode. See the Timing Diagrams section for more information. Table 10. Digital Output Coding Input (V) VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− Condition (V) <−VREF − 0.5 LSB −VREF 0V +VREF − 1.0 LSB >+VREF − 0.5 LSB Offset Binary Output Mode 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 1111 1111 1111 1100 1111 1111 1111 1100 Rev. 0 | Page 28 of 40 Twos Complement Mode 1000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 1100 0111 1111 1111 1100 Data Sheet AD9253 Table 11. Flexible Output Test Modes Output Test Mode Bit Sequence 0000 0001 Digital Output Word 2 N/A N/A N/A Yes N/A Yes 0101 0101 0101 (12-bit) 0101 0101 0101 0100 (16-bit) N/A No PN sequence long 1 Digital Output Word 1 N/A 1000 0000 0000 (12-bit) 1000 0000 0000 0000 (16-bit) 1111 1111 1111 (12-bit) 0000 0000 0000 0000 (16-bit) 0000 0000 0000 (12-bit) 0000 0000 0000 0000 (16-bit) 1010 1010 1010 (12-bit) 1010 1010 1010 1010 (16-bit) N/A Subject to Data Format Select N/A Yes Pattern Name Off (default) Midscale short 0010 +Full-scale short 0011 −Full-scale short 0100 Checkerboard 0101 0110 PN sequence short1 N/A N/A Yes 0111 0000 0000 0000 (12-bit) 0000 0000 0000 0000 (16-bit) Register 0x1B to Register 0x1C N/A 1010 1× sync N/A No 1011 One bit high 1111 1111 1111 (12-bit) 111 1111 1111 1100 (16-bit) Register 0x19 to Register 0x1A 1010 1010 1010 (12-bit) 1010 1010 1010 1000 (16-bit) 0000 0011 1111 (12-bit) 0000 0001 1111 1100 (16-bit) 1000 0000 0000 (12-bit) 1000 0000 0000 0000 (16-bit) No 1000 1001 One-/zero-word toggle User input 1-/0-bit toggle N/A No 1100 Mixed frequency 1010 0011 0011 (12-bit) 1010 0001 1001 1100 (16-bit) N/A No 1 Yes Notes Offset binary code shown Offset binary code shown Offset binary code shown PN23 ITU 0.150 X23 + X18 + 1 PN9 ITU 0.150 X 9 + X5 + 1 No No Pattern associated with the external pin All test mode options except PN sequence short and PN sequence long can support 12-bit to 16-bit word lengths to verify data capture to the receiver. When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in Figure 2, is 90° relative to the output data edge. A 12-bit serial stream can also be initiated from the SPI. This allows the user to implement and test compatibility to lower resolution systems. When changing the resolution to a 12-bit serial stream, the data stream is shortened. See Figure 3 for the 12-bit example. However, in the default option with the serial output number of bits at 16, the data stream stuffs two 0s at the end of the 14-bit serial data. In default mode, as shown in Figure 2, the MSB is first in the data output serial stream. This can be inverted so that the LSB is first in the data output serial stream by using the SPI. There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 11 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns do not adhere to the data format select option. In addition, custom user-defined test patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 − 1 or 511 bits. A description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value is all 1s (see Table 12 for the initial values). The output is a parallel representation of the serial PN9 sequence in MSB-first format. The first output word is the first 14 bits of the PN9 sequence in MSB aligned form. The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 − 1 or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The seed value is all 1s (see Table 12 for the initial values) and the AD9253 inverts the bit stream with relation to the ITU standard. The output is a parallel representation of the serial PN23 sequence in MSB-first format. The first output word is the first 14 bits of the PN23 sequence in MSB aligned form Rev. 0 | Page 29 of 40 AD9253 Data Sheet Table 12. PN Sequence Sequence PN Sequence Short PN Sequence Long Initial Value 0x1FE0 0x1FFF First Three Output Samples (MSB First) Twos Complement 0x1DF1, 0x3CC8, 0x294E 0x1FE0, 0x2001, 0x1C00 Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI. SDIO/OLM Pin For applications that do not require SPI mode operation, the CSB pin is tied to AVDD, and the SDIO/OLM pin controls the output lane mode according to Table 13. For applications where this pin is not used, CSB should be tied to AVDD. When using the one-lane mode, the encode rate should be ≤62.5 MSPS to meet the maximum output rate of 1 Gbps. Table 14. Digital Test Pattern Pin Settings Selected DTP Normal Operation DTP DTP Voltage 10 kΩ to AGND AVDD Resulting D0±x and D1±x Normal operation 1000 0000 0000 0000 Additional and custom test patterns can also be observed when commanded from the SPI port. Consult the Memory Map section for information about the options available. CSB Pin The CSB pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. RBIAS Pin To set the internal core bias current of the ADC, place a 10.0 kΩ, 1% tolerance resistor to ground at the RBIAS pin. Table 13. Output Lane Mode Pin Settings OLM Pin Voltage AVDD (Default) GND and output data. This pin has an internal 10 kΩ resistor to GND. It can be left unconnected. OUTPUT TEST MODES Output Mode Two-lane. 1× frame, 16-bit serial output One-lane. 1× frame, 16-bit serial output SCLK/DTP Pin The SCLK/DTP pin is for use in applications that do not require SPI mode operation. This pin can enable a single digital test pattern if it and the CSB pin are held high during device powerup. When SCLK/DTP is tied to AVDD, the ADC channel outputs shift out the following pattern: 1000 0000 0000 0000. The FCO and DCO function normally while all channels shift out the repeatable test pattern. This pattern allows the user to perform timing alignment adjustments among the FCO, DCO, The output test options are described in Table 11 and controlled by the output test mode bits at Address 0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877"QQMJDBUJPO/PUF, Interfacing to High Speed ADCs via SPI. Rev. 0 | Page 30 of 40 Data Sheet AD9253 SERIAL PORT INTERFACE (SPI) The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 74 and Table 5. The AD9253 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI offers the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Other modes involving the CSB are available. The CSB can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits. CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Table 15). The SCLK (a serial clock) is used to synchronize the read and write data presented from and to the ADC. The SDIO (serial data input/output) is a dualpurpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB (chip select bar) is an active low control that enables or disables the read and write cycles. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Table 15. Serial Port Interface Pins Pin SCLK SDIO CSB Function Serial clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles. tHIGH tDS tS tDH All data is composed of 8-bit words. Data can be sent in MSBfirst mode or in LSB-first mode. MSB-first mode is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. tCLK tH tLOW CSB SDIO DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 Figure 74. Serial Port Interface Timing Diagram Rev. 0 | Page 31 of 40 D4 D3 D2 D1 D0 DON’T CARE 10065-078 SCLK DON’T CARE AD9253 Data Sheet HARDWARE INTERFACE The pins described in Table 15 comprise the physical interface between the user programming device and the serial port of the AD9253. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9253 to prevent these signals from transitioning at the converter inputs during critical sampling periods. Some pins serve a dual function when the SPI interface is not being used. When the pins are strapped to DRVDD or ground during device power-on, they are associated with a specific function. Table 16 describes the strappable functions supported on the AD9253. When the device is in SPI mode, the PDWN pin (if enabled) remains active. For SPI control of power-down, the PDWN pin should be set to its default state. SPI ACCESSIBLE FEATURES Table 16 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9253 part-specific features are described in detail following Table 17, the external memory map register table. Table 16. Features Accessible Using the SPI Feature Name Power Mode Clock Offset Test I/O Output Mode Output Phase ADC Resolution CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/OLM pin, the SCLK/DTP pin, and the PDWN pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, and power-down feature control. In this mode, CSB should be connected to AVDD, which disables the serial port interface. Rev. 0 | Page 32 of 40 Description Allows the user to set either power-down mode or standby mode Allows the user to access the DCS, set the clock divider, set the clock divider phase, and enable the sync Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set the output mode Allows the user to set the output clock polarity Allows for power consumption scaling with respect to sample rate. Data Sheet AD9253 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Default Values Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the device index and transfer registers (Address 0x05 and Address 0xFF); and the global ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x109). After the AD9253 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 17. The memory map register table (see Table 17) lists the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x05, the device index register, has a hexadecimal default value of 0x3F. This means that in Address 0x05, Bits[7:6] = 0, and the remaining Bits[5:0] = 1. This setting is the default channel index setting. The default value results in both ADC channels receiving the next write command. For more information on this function and others, see the AN-877"QQMJDBUJPO/PUF, Interfacing to High Speed ADCs via SPI. This application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining registers are documented in the Memory Map Register Descriptions section. Open Locations All address and bit locations that are not included in Table 17 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x05). If the entire address location is open or not listed in Table 17 (for example, Address 0x13), this address location should not be written. Logic Levels An explanation of logic level terminology follows: • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Channel-Specific Registers Some channel setup functions, such as the signal monitor thresholds, can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 17 as local. These local registers and bits can be accessed by setting the appropriate data channel bits (A, B, C, or D) and the clock channel DCO bit (Bit 5) and FCO bit (Bit 4) in Register 0x05. If all the bits are set, the subsequent write affects the registers of all channels and the DCO/FCO clock channels. In a read cycle, only one of the channels (A, B, C, or D) should be set to read one of the four registers. If all the bits are set during a SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 17 affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. Rev. 0 | Page 33 of 40 AD9253 Data Sheet MEMORY MAP REGISTER TABLE The AD9253 uses a 3-wire interface and 16-bit addressing and, therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3 and Bit 4 are set to 1. When Bit 5 in Register 0x00 is set high, the SPI enters a soft reset, where all of the user registers revert to their default values and Bit 2 is automatically cleared. Table 17. ADDR (Hex) Parameter Name Chip Configuration Registers 0x00 SPI port configuration 0x01 Chip ID (global) 0x02 Chip grade (global) Bit 7 (MSB) 0= SDO active Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first Soft reset 1= 16-bit address 1= 16-bit address Soft reset LSB first Bit 0 (LSB) 0 = SDO active 8-bit chip ID, Bits[7:0] AD9253 0x8F = quad 14-bit 80 MSPS/105 MSPS/125 MSPS serial LVDS Open Speed grade ID[6:4] 100 = 80 MSPS 101 = 105 MSPS 110 = 125 MSPS Default Value (Hex) 0x18 0x8F Open Open Open Open Device Index and Transfer Registers 0x05 Device index Open Open Clock Channel DCO Clock Channel FCO Data Channel D Data Channel C Data Channel B Data Channel A 0x3F 0xFF Open Open Open Open Open Open Open Initiate override 0x00 Global ADC Function Registers 0x08 Power modes Open (global) Open Open Open 0x09 Open External powerdown pin function 0 = full powerdown 1= standby Open Open Open Transfer Clock (global) Open Rev. 0 | Page 34 of 40 Open Open Power mode 00 = chip run 01 = full powerdown 10 = standby 11 = reset Open Duty cycle stabilize 0 = off 1 = on Comments The nibbles are mirrored so that LSBfirst or MSBfirst mode registers correctly. The default for ADCs is 16-bit mode. Unique chip ID used to differentiate devices; read only. Unique speed grade ID used to differentiate graded devices; read only. Bits are set to determine which device on chip receives the next write command. The default is all devices on chip. Set resolution/ sample rate override. 0x00 Determines various generic modes of chip operation. 0x01 Turns duty cycle stabilizer on or off. Data Sheet ADDR (Hex) 0x0B Parameter Name Clock divide (global) 0x0C Enhancement control 0x0D Test mode (local except for PN sequence resets) 0x10 0x14 Offset adjust (local) Output mode 0x15 Output adjust 0x16 Output phase AD9253 Bit 7 (MSB) Open Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Open Open Open Open Clock divide ratio[2:0] 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 Open Open Open Open Open Chop Open Open mode 0 = off 1 = on User input test mode Reset Reset PN Output test mode[3:0] (local) PN long short 0000 = off (default) 00 = single gen gen 0001 = midscale short 01 = alternate 0010 = positive FS 10 = single once 0011 = negative FS 11 = alternate once 0100 = alternating checkerboard (affects user input test 0101 = PN 23 sequence mode only, 0110 = PN 9 sequence Bits[3:0] = 1000) 0111 = one/zero word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency 8-bit device offset adjustment [7:0] (local) Offset adjust in LSBs from +127 to −128 (twos complement format) Open Open Open Output Open Output Open LVDS-ANSI/ invert format LVDS-IEEE 0= option (local) offset 0 = LVDSbinary ANSI 1= 1 = LVDStwos IEEE complereduced ment range link (global) (global) see Table 18 Open Open Output driver Open Open Open Output termination[1:0] drive 0 = 1× 00 = none drive 01 = 200 Ω 1 = 2× 10 = 100 Ω drive 11 = 100 Ω Open Input clock phase adjust[6:4] Output clock phase adjust[3:0] (value is number of input clock (0000 through 1011) cycles of phase delay) see Table 20 see Table 19 Rev. 0 | Page 35 of 40 Default Value (Hex) 0x00 Comments 0x00 Enables/ disables chop mode. 0x00 When set, the test data is placed on the output pins in place of normal data. 0x00 Device offset trim. Configures the outputs and the format of the data. 0x01 0x00 Determines LVDS or other output properties. 0x03 On devices that use global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. AD9253 ADDR (Hex) 0x18 Data Sheet Default Value (Hex) 0x04 Bit 7 (MSB) Open Bit 6 Open Bit 5 Open Bit 4 Open Bit 3 Open USER_PATT1_LSB (global) USER_PATT1_MSB (global) USER_PATT2_LSB (global) USER_PATT2_MSB (global) Serial output data control (global) B7 B6 B5 B4 B3 Bit 0 Bit 2 Bit 1 (LSB) Internal VREF adjustment digital scheme[2:0] 000 = 1.0 V p-p 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.6 V p-p 100 = 2.0 V p-p B2 B1 B0 B15 B14 B13 B12 B11 B10 B9 B8 0x00 B7 B6 B5 B4 B3 B2 B1 B0 0x00 B15 B14 B13 B12 B11 B10 B9 B8 0x00 LVDS output LSB first Open Select 2× frame 0x22 Serial channel status (local) Open SDR/DDR one-lane/two-lane, bitwise/bytewise[6:4] 000 = SDR two-lane, bitwise 001 = SDR two-lane, bytewise 010 = DDR two-lane, bitwise 011 = DDR two-lane, bytewise 100 = DDR one-lane Open Open Open Open Open 0x100 Resolution/ sample rate override Open Resolution/ sample rate override enable 0x101 User I/O Control 2 Open Open Open Open Open Open 0x102 User I/O Control 3 Open Open Open Open Open 0x109 Sync Open Open Open Open VCM powerdown Open 0x19 0x1A 0x1B 0x1C 0x21 Parameter Name VREF Resolution 01 = 14 bits 10 = 12 bits Open Rev. 0 | Page 36 of 40 Open Serial output number of bits 00 = 16 bits 10 = 12 bits Channel output reset Channel powerdown Sample rate 000 = 20 MSPS 001 = 40 MSPS 010 = 50 MSPS 011 = 65 MSPS 100 = 80 MSPS 101 = 105 MSPS 110 = 125 MSPS Open SDIO pulldown Open Open Sync next only Enable sync 0x00 0x30 0x00 0x00 Comments Selects and/or adjusts the VREF. User Defined Pattern 1 LSB. User Defined Pattern 1 MSB. User Defined Pattern 2 LSB. User Defined Pattern 2 MSB. Serial stream control. Default causes MSB first and the native bit stream. Used to power down individual sections of a converter. Resolution/ sample rate override (requires transfer register, 0xFF). 0x00 Disables SDIO pull-down. 0x00 VCM control. 0x00 Data Sheet AD9253 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Device Index (Register 0x05) There are certain features in the map that can be set independently for each channel, whereas other features apply globally to all channels (depending on context) regardless of which are selected. The first four bits in Register 0x05 can be used to select which individual data channels are affected. The output clock channels can be selected in Register 0x05 as well. A smaller subset of the independent feature list can be applied to those devices. Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Setting this bit chooses LVDS-IEEE (reduced range) option. The default setting is LVDS-ANSI. As described in Table 18, when LVDS-ANSI or LVDS-IEEE reduced range link is selected, the user can select the driver termination. The driver current is automatically selected to give the proper output swing. Table 18. LVDS-ANSI/LVDS-IEEE Options Output Mode, Bit 6 0 Output Mode LVDS-ANSI Transfer (Register 0xFF) All registers except Register 0x100 are updated the moment they are written. Setting Bit 0 of this transfer register high initializes the settings in the ADC sample rate override register (Address 0x100). Power Modes (Register 0x08) Bits[7:6]—Open 1 LVDS-IEEE reduced range link Output Driver Termination User selectable User selectable Output Driver Current Automatically selected to give proper swing Automatically selected to give proper swing Bits[5:3]—Open Bit 2—Output Invert Setting this bit inverts the output bit stream. Bit 5—External Power-Down Pin Function If set, the external PDWN pin initiates power-down mode. If cleared, the external PDWN pin initiates standby mode. Bit 1—Open Bit 0—Output Format By default, this bit is set to send the data output in twos complement format. Resetting this bit changes the output mode to offset binary. Bits[4:2]—Open Bits[1:0]—Power Mode In normal operation (Bits[1:0] = 00), all ADC channels are active. Output Adjust (Register 0x15) Bits[7:6]—Open In power-down mode (Bits[1:0] = 01), the digital datapath clocks are disabled while the digital datapath is reset. Outputs are disabled. In standby mode (Bits[1:0] = 10), the digital datapath clocks and the outputs are disabled. Bits[5:4]—Output Driver Termination These bits allow the user to select the internal termination resistor. Bits[3:1]—Open During a digital reset (Bits[1:0] = 11), all the digital datapath clocks and the outputs (where applicable) on the chip are reset, except the SPI port. Note that the SPI is always left under control of the user; that is, it is never automatically disabled or in reset (except by power-on reset). Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode For applications that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct conversion receivers, chopping in the first stage of the AD9253 is a feature that can be enabled by setting Bit 2. In the frequency domain, chopping translates offsets and other low frequency noise to fCLK/2 where it can be filtered. Bit 0—Output Drive Bit 0 of the output adjust register controls the drive strength on the LVDS driver of the FCO and DCO outputs only. The default values set the drive to 1× while the drive can be increased to 2× by setting the appropriate channel bit in Register 0x05 and then setting Bit 0. These features cannot be used with the output driver termination select. The termination selection takes precedence over the 2× driver strength on FCO and DCO when both the output driver termination and output drive are selected. Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[1:0]—Open Rev. 0 | Page 37 of 40 AD9253 Data Sheet Table 19. Input Clock Phase Adjust Options Serial Output Data Control (Register 0x21) Input Clock Phase Adjust, Bits[6:4] 000 (Default) 001 010 011 100 101 110 111 The serial output data control register is used to program the AD9253 in various output data modes depending upon the data capture solution. Table 21 describes the various serialization options available in the AD9253. Number of Input Clock Cycles of Phase Delay 0 1 2 3 4 5 6 7 This register is designed to allow the user to downgrade the device. Any attempt to upgrade the default speed grade results in a chip power-down. Settings in this register are not initialized until Bit 0 of the transfer register (Register 0xFF) is written high. User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bits[3:0]—Output Clock Phase Adjust Table 20. Output Clock Phase Adjust Options Output Clock (DCO), Phase Adjust, Bits[3:0] 0000 0001 0010 0011 (Default) 0100 0101 0110 0111 1000 1001 1010 1011 Resolution/Sample Rate Override (Register 0x100) DCO Phase Adjustment (Degrees Relative to D0±x/D1±x Edge) 0 60 120 180 240 300 360 420 480 540 600 660 Bit 0—SDIO Pull-Down Bit 0 can be set to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus. User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bit 3 can be set high to power down the internal VCM generator. This feature is used when applying an external reference. Bits[2:0]—Open Table 21. SPI Register Options Register 0x21 Contents 0x30 0x20 0x10 0x00 0x34 0x24 0x14 0x04 0x40 0x32 0x22 0x12 0x02 0x36 0x26 0x16 0x06 0x42 Serialization Options Selected Serial Output Number of Bits (SONB) Frame Mode Serial Data Mode 16-bit 1× DDR two-lane bytewise 16-bit 1× DDR two-lane bitwise 16-bit 1× SDR two-lane bytewise 16-bit 1× SDR two-lane bitwise 16-bit 2× DDR two-lane bytewise 16-bit 2× DDR two-lane bitwise 16-bit 2× SDR two-lane bytewise 16-bit 2× SDR two-lane bitwise 16-bit 1× DDR one-lane 12-bit 1× DDR two-lane bytewise 12-bit 1× DDR two-lane bitwise 12-bit 1× SDR two-lane bytewise 12-bit 1× SDR two-lane bitwise 12-bit 2× DDR two-lane bytewise 12-bit 2× DDR two-lane bitwise 12-bit 2× SDR two-lane bytewise 12-bit 2× SDR two-lane bitwise 12-bit 1× DDR one-lane Rev. 0 | Page 38 of 40 DCO Multiplier 4 × fS 4 × fS 8 × fS 8 × fS 4 × fS 4 × fS 8 × fS 8 × fS 8 × fS 3 × fS 3 × fS 6 × fS 6 × fS 3 × fS 3 × fS 6 × fS 6 × fS 6 × fS Timing Diagram Figure 2 (default setting) Figure 2 Figure 2 Figure 2 Figure 4 Figure 4 Figure 4 Figure 4 Figure 6 Figure 3 Figure 3 Figure 3 Figure 3 Figure 5 Figure 5 Figure 5 Figure 5 Figure 7 Data Sheet AD9253 APPLICATIONS INFORMATION DESIGN GUIDELINES VCM Before starting design and layout of the AD9253 as a system, it is recommended that the designer become familiar with these guidelines, which describes the special circuit connections and layout requirements that are needed for certain pins. The VCM pin should be decoupled to ground with a 0.1 μF capacitor. When connecting power to the AD9253, it is recommended that two separate 1.8 V supplies be used. Use one supply for analog (AVDD); use a separate supply for the digital outputs (DRVDD). For both AVDD and DRVDD, several different decoupling capacitors should be used to cover both high and low frequencies. Place these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length. A single PCB ground plane should be sufficient when using the AD9253. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS It is required that the exposed pad on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9253. An exposed continuous copper plane on the PCB should mate to the AD9253 exposed pad, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. See Figure 75 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772"QQMJDBUJPO/PUF, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. The VREF pin should be externally decoupled to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. SPI PORT The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9253 to keep these signals from transitioning at the converter inputs during critical sampling periods. CROSSTALK PERFORMANCE The AD9253 is available in a 48-lead LFCSP package with the input pairs on either corner of the chip. See Figure 9 for the pin configuration. To maximize the crosstalk performance on the board, add grounded filled vias in between the adjacent channels as shown in Figure 76. VIN CHANNEL A GROUNDED FILLED VIAS FOR ADDED CROSSTALK ISOLATION 10065-080 SILKSCREEN PARTITION PIN 1 INDICATOR Figure 75. Typical PCB Layout Rev. 0 | Page 39 of 40 VIN CHANNEL B VIN CHANNEL D PIN 1 VIN CHANNEL C Figure 76. Layout Technique to Maximize Crosstalk Performance 10065-088 POWER AND GROUND RECOMMENDATIONS REFERENCE DECOUPLING AD9253 Data Sheet OUTLINE DIMENSIONS 0.30 0.23 0.18 PIN 1 INDICATOR 37 36 48 1 0.50 BSC TOP VIEW 0.80 0.75 0.70 0.45 0.40 0.35 EXPOSED PAD 24 SEATING PLANE 5.65 5.60 SQ 5.55 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PIN 1 INDICATOR 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD. 02-14-2011-B 7.10 7.00 SQ 6.90 Figure 77. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 7 mm × 7 mm Body, Very Very Thin Quad (CP-48-13) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9253BCPZ-80 AD9253BCPZRL7-80 AD9253BCPZ-105 AD9253BCPZRL7-105 AD9253BCPZ-125 AD9253BCPZRL7-125 AD9253-125EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) Evaluation Board Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10065-0-10/11(0) Rev. 0 | Page 40 of 40 Package Option CP-48-13 CP-48-13 CP-48-13 CP-48-13 CP-48-13 CP-48-13