11-/14-Bit, 5.6 GSPS, RF Digital-to-Analog Converter AD9119/AD9129 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM RESET I250U VREF IRQ AD9129 1.2V SPI DCO_x Tx DAC CORE IOUTP IOUTN 2× PLL CLOCK DISTRIBUTION DCR DACCLK_x 11149-001 DCI_x BASEBAND MODE DATA LATCH DLL DATA ASSEMBLER P0_D[13:0]P, P0_D[13:0]N P1_D[13:0]P, P1_D[13:0]N MIXNORMAL MODE LVDS DDR RECEIVER FRM_x (FRAME/ PARITY) 4× FIFO SDIO SDO CS SCLK LVDS DDR RECEIVER DAC update rate: up to 5.6 GSPS Direct RF synthesis at 2.8 GSPS data rate DC to 1.4 GHz in baseband mode DC to 1.0 GHz in 2× interpolation mode 1.4 GHz to 4.2 GHz in Mix-Mode Bypassable 2× interpolation Excellent dynamic performance Supports DOCSIS 3.0 wideband ACLR/harmonic performance 8 QAM carriers: ACLR > 65 dBc Industry-leading single/multicarrier IF or RF synthesis 4-carrier W-CDMA ACLR at 2457.6 MSPS fOUT = 900 MHz, ACLR = 71 dBc (baseband mode) fOUT = 2100 MHz, ACLR = 68 dBc (Mix-Mode) fOUT = 2700 MHz, ACLR = 67 dBc (Mix-Mode) Dual-port LVDS and DHSTL data interface Up to 1.4 GSPS operation Source synchronous DDR clocking with parity bit Low power: 1.0 W at 2.8 GSPS (1.3 W at 5.6 GSPS) Figure 1. APPLICATIONS Broadband communications systems CMTS/VOD Wireless infrastructure: W-CDMA, LTE, point-to-point Instrumentation, automatic test equipment (ATE) Radars, jammers GENERAL DESCRIPTION The AD9119/AD9129 are high performance, 11-/14-bit RF digitalto-analog converters (DACs) supporting data rates up to 2.8 GSPS. The DAC core is based on a quad-switch architecture that enables dual-edge clocking operation, effectively increasing the DAC update rate to 5.6 GSPS when configured for Mix-Mode™ or 2× interpolation. The high dynamic range and bandwidth enable multicarrier generation up to 4.2 GHz. In baseband mode, wide bandwidth capability combines with high dynamic range to support from 1 to 158 contiguous carriers for CATV infrastructure applications. A choice of two optional 2× interpolation filters is available to simplify the postreconstruction filter by effectively increasing the DAC update rate by a factor of 2. In Mix-Mode operation, the AD9119/AD9129 can reconstruct RF carriers in the second and third Nyquist zone while still maintaining exceptional dynamic range up to 4.2 GHz. The high performance NMOS DAC core features a quad-switch architecture that enables industry-leading direct RF synthesis performance with minimal loss in output power. The output current can be programmed over a range of 9.5 mA to 34.4 mA. Rev. 0 The AD9119/AD9129 include several features that may further simplify system integration. A dual-port, source synchronous LVDS interface simplifies the data interface to a host FPGA/ASIC. A differential frame/parity bit is also included to monitor the integrity of the interface. On-chip delay locked loops (DLLs) are used to optimize timing between different clock domains. A serial peripheral interface (SPI) is used to configure the AD9119/AD9129 and monitor the status of readback registers. The AD9119/AD9129 is manufactured on a 0.18 µm CMOS process and operates from +1.8 V and −1.5 V supplies. It is supplied in a 160-ball chip scale package ball grid array. PRODUCT HIGHLIGHTS 1. 2. 3. High dynamic range and signal reconstruction bandwidth support RF signal synthesis of up to 4.2 GHz. Dual-port interface with double data rate (DDR) LVDS data receivers supports 2800 MSPS maximum conversion rate. Manufactured on a CMOS process; a proprietary switching technique enhances dynamic performance. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9119/AD9129 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Peripheral Interface Pin Descriptions .......................... 36 Applications ....................................................................................... 1 MSB/LSB Transfers .................................................................... 37 Functional Block Diagram .............................................................. 1 Serial Port Configuration .......................................................... 37 General Description ......................................................................... 1 Theory of Operation ...................................................................... 38 Product Highlights ........................................................................... 1 LVDS Data Port Interface .......................................................... 39 Revision History ............................................................................... 2 Digital Datapath Description ................................................... 42 Specifications..................................................................................... 3 Interrupt Requests ...................................................................... 46 DC Specifications ......................................................................... 3 Interface Timing Validation .......................................................... 48 LVDS Digital Specifications ........................................................ 4 Sample Error Detection (SED) Operation .............................. 48 HSTL Digital Specifications ........................................................ 4 SED Example............................................................................... 48 Serial Port and CMOS Pin Specifications ................................. 5 Analog Interface Considerations.................................................. 49 AC Specifications.......................................................................... 6 Analog Modes of Operation ..................................................... 49 Absolute Maximum Ratings ............................................................ 7 Clock Input.................................................................................. 50 Thermal Resistance ...................................................................... 7 PLL ............................................................................................... 50 ESD Caution .................................................................................. 7 Voltage Reference ....................................................................... 51 Pin Configurations and Function Descriptions ........................... 8 Analog Outputs .......................................................................... 51 Typical Performance Characteristics ........................................... 12 Start-Up Sequence ...................................................................... 54 AD9119 ........................................................................................ 12 Device Configuration Registers.................................................... 55 AD9129 ........................................................................................ 22 Device Configuration Register Map ........................................ 55 Terminology .................................................................................... 35 Device Configuration Register Descriptions .......................... 56 Serial Communications Port Overview....................................... 36 Outline Dimensions ....................................................................... 66 Serial Peripheral Interface (SPI) ............................................... 36 Ordering Guide .......................................................................... 66 General Operation of the SPI.................................................... 36 Instruction Mode (8-Bit Instruction) ...................................... 36 REVISION HISTORY 1/13—Revision 0: Initial Version Rev. 0 | Page 2 of 68 Data Sheet AD9119/AD9129 SPECIFICATIONS DC SPECIFICATIONS VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. Table 1. Parameter RESOLUTION ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) ANALOG OUTPUTS Gain Error (with Internal Reference) Full-Scale Output Current Maximum Full-Scale Output Current Minimum Output Compliance Range Output Impedance 1 DAC CLOCK INPUT (DACCLK_P, DACCLK_N) Differential Peak-to-Peak Voltage Common-Mode Voltage TEMPERATURE DRIFT Gain Reference Voltage REFERENCE Internal Reference Voltage Output Resistance ANALOG SUPPLY VOLTAGES VDDA VSSA DIGITAL SUPPLY VOLTAGES VDD FIR40 Enabled, DACCLK > 2600 MSPS SUPPLY CURRENTS AND POWER DISSIPATION, 2.3 GSPS (NORMAL MODE) IVDDA IVSSA IDVDD Power Dissipation Normal Mode FIR25 Enabled FIR40 Enabled Reduced Power Mode, Power-Down Enabled (Register 0x01 = 0xEF) IVDDA IVSSA IVDD SUPPLY CURRENTS AND POWER DISSIPATION, 2.8 GSPS (NORMAL MODE) IVDDA IVSSA IDVDD Power Dissipation (Normal Mode) 1 Min AD9119 Typ 11 Max Min 0.2 0.15 33.4 9.1 1.5 0.4 +2.5 34.2 9.4 1 1.2 AD9129 Typ 14 Max 1.4 1.1 34.9 9.6 2.5 33.4 9.1 1.5 2 0.4 +2.5 34.2 9.4 1 1.2 Unit Bits LSB LSB 34.9 9.6 2.5 2 % mA mA V V V 60 20 60 20 ppm/°C ppm/°C 1.0 5 1.0 5 V kΩ 1.70 −1.4 1.80 −1.5 1.90 −1.6 1.70 −1.4 1.80 −1.5 1.90 −1.6 V V 1.70 1.8 1.8 1.9 1.90 2.0 1.70 1.8 1.8 1.9 1.90 2.0 V V 202 53 307 209 54 327 202 53 307 209 54 327 mA mA mA 1.0 1.17 1.3 1.05 1.24 1.4 1.0 1.17 1.3 1.05 1.24 1.4 W W W 7.6 6 0.4 7.6 6 0.4 mA µA mA 230 53 336 1.1 230 53 336 1.1 mA mA mA W For more information about output impedance, see the Output Stage Configuration section. Rev. 0 | Page 3 of 68 AD9119/AD9129 Data Sheet LVDS DIGITAL SPECIFICATIONS VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. LVDS drivers and receivers are compatible with the IEEE Standard 1596.3-1996, unless otherwise noted. Table 2. Parameter LVDS DATA INPUTS (P1_D[13:0]P, P1_D[13:0]N, P0_D[13:0]P, P0_D[13:0]N) Input Voltage Range Input Differential Threshold Input Differential Hysteresis Receiver Differential Input Impedance LVDS Input Rate Input Capacitance LVDS CLOCK INPUTS (DCI_P, DCI_N) Input Voltage Range Input Differential Threshold Input Differential Hysteresis Receiver Differential Input Impedance Maximum Clock Rate LVDS CLOCK OUTPUTS (DCO_P, DCO_N) Symbol Test Conditions/Comments Px_DxP = VIA, Px_DxN = VIB Min VIA, VIB VIDTH VIDTHH − VIDTHL RIN Typ 825 −100 Max Unit 1575 +100 mV mV mV Ω MSPS pF 20 80 1400 120 1.2 DCI_P = VIA, DCI_N = VIB VIA, VIB VIDTH VIDTHH − VIDTHL RIN 825 −225 1575 +225 20 80 700 120 mV mV mV Ω MHz DCO_P = VOA, DCO_N = VOB, 100 Ω termination Output Voltage High Output Voltage Low Output Differential Voltage Output Offset Voltage Output Impedance, Single-Ended RO Mismatch Between A and B Change in |VOD| Between Setting 0 and Setting 1 Change in VOS Between Setting 0 and Setting 1 Output Current Driver Shorted to Ground Drivers Shorted Together Power-Off Output Leakage Maximum Clock Rate VOA, VOB VOA, VOB |VOA|, |VOB| VOS RO ∆RO |∆VOD| ∆VOS 1375 Register 0x7C[7:6] = 01b (default) 1025 200 1150 80 225 100 ISA, ISB ISAB |IXA|, |IXB| 250 1250 120 10 25 25 20 4 10 700 mV mV mV mV Ω % mV mV mA mA µA MHz HSTL DIGITAL SPECIFICATIONS VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. HSTL receiver levels are compatible with the EIA/JEDEC JESD8-6 standard, unless otherwise noted. Table 3. Parameter HSTL DATA INPUTS (P1_D[13:0]P, P1_D[13:0]N, P0_D[13:0]P, P0_D[13:0]N) Common-Mode Input Voltage Range Differential Input Voltage Receiver Differential Input Impedance HSTL Input Rate Input Capacitance HSTL CLOCK INPUT (DCI_P, DCI_N) Common-Mode Input Voltage Range Differential Input Voltage Receiver Differential Input Impedance Maximum Clock Rate Symbol Test Comments/Conditions Px_DxP = VIA, Px_DxN = VIB VIA, VIB Min Typ 0.68 200 80 RIN Max Unit 0.9 V mV Ω MSPS pF 120 1400 1.2 DCI_P = VIA, DCI_N = VIB VIA, VIB 0.68 450 80 700 RIN Rev. 0 | Page 4 of 68 0.9 120 mV mV Ω MHz Data Sheet AD9119/AD9129 SERIAL PORT AND CMOS PIN SPECIFICATIONS VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. Table 4. Parameter WRITE OPERATION SCLK Clock Rate SCLK Clock High SCLK Clock Low SDIO to SCLK Setup Time SCLK to SDIO Hold Time CS to SCLK Setup Time SCLK to CS Hold Time READ OPERATION SCLK Clock Rate SCLK Clock High SCLK Clock Low SDIO to SCLK Setup Time SCLK to SDIO Hold Time CS to SCLK Setup Time SCLK to SDIO (or SDO) Data Valid Time CS to SDIO (or SDO) Output Valid to High-Z INPUTS (SDI, SDIO, SCLK, CS) Voltage In High Voltage In Low Current In High Current In Low OUTPUTS (SDIO, SYNC) Voltage Out High Voltage Out Low Current Out High Current Out Low Symbol Test Comments/Conditions See Figure 126 fSCLK, 1/tSCLK tHIGH tLOW tDS tDH tS tH Min Typ Max Unit 20 MHz ns ns ns ns ns ns 20 MHz ns ns ns ns ns ns 20 20 10 5 10 5 See Figure 127 fSCLK, 1/tSCLK tHIGH tLOW tDS tDH tS tDV tEZ 20 20 10 5 10 10 2 VIH VIL IIH IIL 1.2 1.8 0 0.4 +75 −150 VOH VOL IOH IOL 1.3 0 2.0 0.3 4 4 Rev. 0 | Page 5 of 68 V V µA µA V V mA mA AD9119/AD9129 Data Sheet AC SPECIFICATIONS VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C, unless otherwise noted. Table 5. Parameter DYNAMIC PERFORMANCE DAC Update Rate (DACCLK_x Inputs) Normal Mode, FIR25 Enabled, or FIR40 Enabled with VDD = 1.9 V FIR40 Filter Enabled, VDD = 1.8 V Adjusted DAC Update Rate 1 Output Settling Time to 0.1% SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 2600 MSPS fOUT = 100 MHz fOUT = 350 MHz fOUT = 550 MHz fOUT = 950 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 2600 MSPS, fOUT2 = fOUT1 + 1.4 MHz fOUT = 100 MHz fOUT = 350 MHz fOUT = 550 MHz fOUT = 950 MHz NOISE SPECTRAL DENSITY (NSD) Single Tone, fDAC = 2800 MSPS fOUT = 100 MHz fOUT = 350MHz fOUT = 550 MHz fOUT = 850 MHz DOCSIS ACLR PERFORMANCE (50 MHz to 1000 MHz) at ≥6 MHz OFFSET fDAC = 2782 MSPS 8 Contiguous Carriers 16 Contiguous Carriers 32 Contiguous Carriers W-CDMA ACLR (SINGLE CARRIER) Adjacent Channel fDAC = 2605.056 MSPS, fOUT = 750 MHz fDAC= 2605.056 MSPS, fOUT = 950 MHz fDAC = 2605.056 MSPS, fOUT = 1700 MHz (Mix-Mode) fDAC = 2605.056 MSPS, fOUT = 2100 MHz (Mix-Mode) Alternate Adjacent Channel fDAC = 2605.056 MSPS, fOUT = 750 MHz fDAC = 2605.056 MSPS, fOUT = 950 MHz fDAC = 2605.056 MSPS, fOUT = 1700 MHz (Mix-Mode) fDAC = 2605.056 MSPS, fOUT = 2100 MHz (Mix-Mode) 1 Min AD9119 Typ 1400 1400 1400 Max Min 2800 2600 2800 1400 1400 1400 AD9129 Typ Max 2800 2600 2800 Unit 13 13 MSPS MSPS MSPS ns −76 −65 −63 −55 −76 −65 −64 −55 dBc dBc dBc dBc −82 −78 −73 −67 −86 −85 −83 −76 dBc dBc dBc dBc −157 −157 −155 −154 −166 −162 −158 −157 dBm/Hz dBm/Hz dBm/Hz dBm/Hz 64 62 60 64 63 61 dBc dBc dBc 75 74 73.5 69 75 74 73.5 69 dBc dBc dBc dBc 80 78 74 72 80 78 74 72 dBc dBc dBc dBc Adjusted DAC update rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9119/AD9129, the minimum interpolation factor is 1. Thus, with fDAC = 2800 MSPS, fDAC adjusted = 2800 MSPS. Rev. 0 | Page 6 of 68 Data Sheet AD9119/AD9129 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter DCI, DCO to VSS LVDS Data Inputs to VSS IOUTP, IOUTN to VSSA I250U, VREF to VSSA IRQ, CS, SCLK, SDO, SDIO, RESET, SYNC to VSS Junction Temperature Operating Temperature Range Storage Temperature Range Rating −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V VSSA − 0.3V to +2.5V VSSA − 0.3 V to VDDA + 0.3 V −0.3 V to VDD + 0.3 V θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance Package Type 160-Ball CSP_BGA 1 150°C −40°C to +85°C −65°C to +150°C With no airflow movement. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 68 θJA 31.2 θJC 7.0 Unit °C/W1 AD9119/AD9129 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A I250U VREF VSSA VSSA VDDA SH IOUTP IOUTN VDDA SH VDDA VDDA VDDA VSSC VSSC VSSC B VDDA VDDA VSSA VSSA VSSA VDDA SH VDDA SH VDDA VDDA VDDA VDDA VSSC VSSC SYNC C DACCLK_N VDDA VDDA VSSA VSSA VSSA VDDA VDDA VDDA VDDA VSSC VSSC VSS VSS D DACCLK_P VDDA VDDA VDDA VSSC VSSC VDDA VSSC VSSC VSSC VSSC VSS VSS VSS E VDDA VDDA VSSC VSSC VSS VSS VSS VSS F VSSC VSSC VSSC VSSC VSS VSS VSS VSS G VSS VSS VSS VSSC VSS VDD VDD VDD AD9119 RESET IRQ VSS VSS VDD VDD VDD VDD J SDIO SDO VDD VDD VDD VDD VDD VDD K SCLK CS DCI_P DCI_N DCO_P DCO_N FRM_P FRM_N L NC NC NC P1_D0P P1_D1P P1_D2P P1_D3P P1_D4P P1_D5P P1_D6P P1_D7P P1_D8P P1_D9P P1_D10P M NC NC NC P1_D0N P1_D1N P1_D2N P1_D3N P1_D4N P1_D5N P1_D6N P1_D7N P1_D8N P1_D9N P1_D10N N NC NC NC P0_D0P P0_D1P P0_D2P P0_D3P P0_D4P P0_D5P P0_D6P P0_D7P P0_D8P P0_D9P P0_D10P P NC NC NC P0_D0N P0_D1N P0_D2N P0_D3N P0_D4N P0_D5N P0_D6N P0_D7N P0_D8N P0_D9N P0_D10N 11149-002 H NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 2. AD9119 Pin Configuration Table 8. AD9119 Pin Function Descriptions Pin No. A1 Mnemonic I250U A2 A3, A4, B3, B4, B5, C4, C5, C6 A5, A8, B6, B7 A9, A10, A11, B1, B2, B8, B9, B10, B11, C2, C3, C7, C8, C9, C10, D2, D3, D4, D7, E1, E2 VREF VSSA VDDA SH VDDA Description Nominal 1.0 V Reference. Tie this pin to VSSA via a 4.0 kΩ resistor to generate a 250 µA reference current. Voltage Reference Input/Output. Decouple to VSSA with a 1 nF capacitor. −1.5 V Analog Supply Voltage Input. +1.8 V Analog Supply Shield. Tie these pins to VDDA at the DAC. +1.8 V Analog Supply Voltage Input. Rev. 0 | Page 8 of 68 Data Sheet Pin No. G12, G13, G14, H11, H12, H13, H14, J3, J4, J11, J12, J13, J14 C13, C14, D12, D13, D14, E11, E12, E13, E14, F11, F12, F13, F14, G1, G2, G3, G11, H3, H4 A12, A13, A14, B12, B13, C11, C12, D5, D6, D8, D9, D10, D11, E3, E4, F1, F2, F3, F4, G4 A6 A7 B14 C1, D1 H1 H2 J1 J2 K1 K2 K3, K4 K11, K12 K13, K14 L1, M1 L2, M2 L3, M3 L4, M4 L5, M5 L6, M6 L7, M7 L8, M8 L9, M9 L10, M10 L11, M11 L12,M12 L13, M13 L14, M14 N1, P1 N2, P2 N3, P3 N4, P4 N5, P5 N6, P6 N7, P7 N8, P8 N9, P9 N10, P10 N11, P11 N12, P12 N13, P13 N14, P14 AD9119/AD9129 Mnemonic VDD Description +1.8 V Digital Supply Voltage Input. VSS +1.8 V Digital Supply Return. VSSC Analog Supply Return. IOUTP IOUTN SYNC DACCLK_N, DACCLK_P RESET IRQ DAC Positive Current Output Source. DAC Negative Current Output Source. Synchronization Signal Output. Negative/Positive DAC Clock Input. Reset Input. Active high. If unused, tie this pin to VSS. Interrupt Request Open Drain Output. Active high. Pull up this pin to VDD with a 1 kΩ resistor. Serial Port Data Input/Output. Serial Port Data Output. Serial Port Clock Input. Serial Port Enable Input. Positive, Negative Data Clock Input (DCI). Positive, Negative Data Clock Output (DCO). Positive, Negative Data Frame/Parity Signal (FRAME/PARITY). No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. Data Port 1 Positive/Negative Data Input Bit 0. Data Port 1 Positive/Negative Data Input Bit 1. Data Port 1 Positive/Negative Data Input Bit 2. Data Port 1 Positive/Negative Data Input Bit 3. Data Port 1 Positive/Negative Data Input Bit 4. Data Port 1 Positive/Negative Data Input Bit 5. Data Port 1 Positive/Negative Data Input Bit 6. Data Port 1 Positive/Negative Data Input Bit 7. Data Port 1 Positive/Negative Data Input Bit 8. Data Port 1 Positive/Negative Data Input Bit 9. Data Port 1 Positive/Negative Data Input Bit 10. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. Data Port 0 Positive/Negative Data Input Bit 0. Data Port 0 Positive/Negative Data Input Bit 1. Data Port 0 Positive/Negative Data Input Bit 2. Data Port 0 Positive/Negative Data Input Bit 3. Data Port 0 Positive/Negative Data Input Bit 4. Data Port 0 Positive/Negative Data Input Bit 5. Data Port 0 Positive/Negative Data Input Bit 6. Data Port 0 Positive/Negative Data Input Bit 7. Data Port 0 Positive/Negative Data Input Bit 8. Data Port 0 Positive/Negative Data Input Bit 9. Data Port 0 Positive/Negative Data Input Bit 10. SDIO SDO SCLK CS DCI_P, DCI_N DCO_P, DCO_N FRM_P, FRM_N NC, NC NC, NC NC, NC P1_D0P, P1_D0N P1_D1P, P1_D1N P1_D2P, P1_D2N P1_D3P, P1_D3N P1_D4P, P1_D4N P1_D5P, P1_D5N P1_D6P, P1_D6N P1_D7P, P1_D7N P1_D8P, P1_D8N P1_D9P, P1_D9N P1_D10P, P1_D10N NC, NC NC, NC NC, NC P0_D0P, P0_D0N P0_D1P, P0_D1N P0_D2P, P0_D2N P0_D3P, P0_D3N P0_D4P, P0_D4N P0_D5P, P0_D5N P0_D6P, P0_D6N P0_D7P, P0_D7N P0_D8P, P0_D8N P0_D9P, P0_D9N P0_D10P, P0_D10N Rev. 0 | Page 9 of 68 AD9119/AD9129 1 Data Sheet 2 3 4 5 6 7 8 9 10 11 12 13 14 A I250U VREF VSSA VSSA VDDA SH IOUTP IOUTN VDDA SH VDDA VDDA VDDA VSSC VSSC VSSC B VDDA VDDA VSSA VSSA VSSA VDDA SH VDDA SH VDDA VDDA VDDA VDDA VSSC VSSC SYNC C DACCLK_N VDDA VDDA VSSA VSSA VSSA VDDA VDDA VDDA VDDA VSSC VSSC VSS VSS D DACCLK_P VDDA VDDA VDDA VSSC VSSC VDDA VSSC VSSC VSSC VSSC VSS VSS VSS E VDDA VDDA VSSC VSSC VSS VSS VSS VSS F VSSC VSSC VSSC VSSC VSS VSS VSS VSS G VSS VSS VSS VSSC VSS VDD VDD VDD AD9129 RESET IRQ VSS VSS VDD VDD VDD VDD J SDIO SDO VDD VDD VDD VDD VDD VDD K SCLK CS DCI_P DCI_N DCO_P DCO_N FRM_P FRM_N L P1_D0P P1_D1P P1_D2P P1_D3P P1_D4P P1_D5P P1_D6P P1_D7P P1_D8P P1_D9P P1_D10P P1_D11P P1_D12P P1_D13P M P1_D0N P1_D1N P1_D2N P1_D3N P1_D4N P1_D5N P1_D6N P1_D7N P1_D8N P1_D9N P1_D10N P1_D11N P1_D12N P1_D13N N P0_D0P P0_D1P P0_D2P P0_D3P P0_D4P P0_D5P P0_D6P P0_D7P P0_D8P P0_D9P P0_D10P P0_D11P P0_D12P P0_D13P P P0_D0N P0_D1N P0_D2N P0_D3N P0_D4N P0_D5N P0_D6N P0_D7N P0_D8N P0_D9N P0_D10N P0_D11N P0_D12N P0_D13N 11149-003 H Figure 3. AD9129 Pin Configuration Table 9. AD9129 Pin Function Descriptions Pin No. A1 Mnemonic I250U A2 A3, A4, B3, B4, B5, C4, C5, C6 A5, A8, B6, B7 A9, A10, A11, B1, B2, B8, B9, B10, B11, C2, C3, C7, C8, C9, C10, D2, D3, D4, D7, E1, E2 G12, G13, G14, H11, H12, H13, H14, J3, J4, J11, J12, J13, J14 C13, C14, D12, D13, D14, E11, E12, E13, E14, F11, F12, F13, F14, G1, G2, G3, G11, H3, H4 VREF VSSA VDDA SH VDDA Description Nominal 1.0 V Reference. Tie this pin to VSSA via a 4.0 kΩ resistor to generate a 250 µA reference current. Voltage Reference Input/Output. Decouple to VSSA with a 1 nF capacitor. −1.5 V Analog Supply Voltage Input. +1.8 V Analog Supply Shield. Tie these pins to VDDA at the DAC. +1.8 V Analog Supply Voltage Input. VDD +1.8 V Digital Supply Voltage Input. VSS +1.8 V Digital Supply Return. Rev. 0 | Page 10 of 68 Data Sheet AD9119/AD9129 Pin No. A12, A13, A14, B12, B13, C11, C12, D5, D6, D8, D9, D10, D11, E3, E4, F1, F2, F3, F4, G4 A6 A7 B14 C1, D1 H1 H2 Mnemonic VSSC Description Analog Supply Return. IOUTP IOUTN SYNC DACCLK_N, DACCLK_P RESET IRQ J1 J2 K1 K2 K3, K4 K11, K12 K13, K14 L1, M1 L2, M2 L3, M3 L4, M4 L5, M5 L6, M6 L7, M7 L8, M8 L9, M9 L10, M10 L11, M11 L12,M12 L13, M13 L14, M14 N1, P1 N2, P2 N3, P3 N4, P4 N5, P5 N6, P6 N7, P7 N8, P8 N9, P9 N10, P10 N11, P11 N12, P12 N13, P13 N14, P14 SDIO SDO SCLK CS DCI_P, DCI_N DCO_P, DCO_N FRM_P, FRM_N P1_D0P, P1_D0N P1_D1P, P1_D1N P1_D2P, P1_D2N P1_D3P, P1_D3N P1_D4P, P1_D4N P1_D5P, P1_D5N P1_D6P, P1_D6N P1_D7P, P1_D7N P1_D8P, P1_D8N P1_D9P, P1_D9N P1_D10P, P1_D10N P1_D11P, P1_D11N P1_D12P, P1_D12N P1_D13P, P1_D13N P0_D0P, P0_D0N P0_D1P, P0_D1N P0_D2P, P0_D2N P0_D3P, P0_D3N P0_D4P, P0_D4N P0_D5P, P0_D5N P0_D6P, P0_D6N P0_D7P, P0_D7N P0_D8P, P0_D8N P0_D9P, P0_D9N P0_D10P, P0_D10N P0_D11P, P0_D11N P0_D12P, P0_D12N P0_D13P, P0_D13N DAC Positive Current Output Source. DAC Negative Current Output Source. Synchronization Signal Output. Negative/Positive DAC Clock Input. Reset Input. Active high. If unused, tie this pin to VSS. Interrupt Request Open-Drain Output. Active high. Pull up this pin to VDD with a 1 kΩ resistor. Serial Port Data Input/Output. Serial Port Data Output. Serial Port Clock Input. Serial Port Enable Input. Positive, Negative Data Clock Input (DCI). Positive, Negative Data Clock Output (DCO). Positive, Negative Data Frame/Parity Signal (FRAME/PARITY). Data Port 1 Positive/Negative Data Input Bit 0. Data Port 1 Positive/Negative Data Input Bit 1. Data Port 1 Positive/Negative Data Input Bit 2. Data Port 1 Positive/Negative Data Input Bit 3. Data Port 1 Positive/Negative Data Input Bit 4. Data Port 1 Positive/Negative Data Input Bit 5. Data Port 1 Positive/Negative Data Input Bit 6. Data Port 1 Positive/Negative Data Input Bit 7. Data Port 1 Positive/Negative Data Input Bit 8. Data Port 1 Positive/Negative Data Input Bit 9. Data Port 1 Positive/Negative Data Input Bit 10. Data Port 1 Positive/Negative Data Input Bit 11. Data Port 1 Positive/Negative Data Input Bit 12. Data Port 1 Positive/Negative Data Input Bit 13. Data Port 0 Positive/Negative Data Input Bit 0. Data Port 0 Positive/Negative Data Input Bit 1. Data Port 0 Positive/Negative Data Input Bit 2. Data Port 0 Positive/Negative Data Input Bit 3. Data Port 0 Positive/Negative Data Input Bit 4. Data Port 0 Positive/Negative Data Input Bit 5. Data Port 0 Positive/Negative Data Input Bit 6. Data Port 0 Positive/Negative Data Input Bit 7. Data Port 0 Positive/Negative Data Input Bit 8. Data Port 0 Positive/Negative Data Input Bit 9. Data Port 0 Positive/Negative Data Input Bit 10. Data Port 0 Positive/Negative Data Input Bit 11. Data Port 0 Positive/Negative Data Input Bit 12. Data Port 0 Positive/Negative Data Input Bit 13. Rev. 0 | Page 11 of 68 AD9119/AD9129 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AD9119 Static Linearity IOUTFS = 28 mA, nominal supplies, TA = 25°C, unless otherwise noted. 0.3 0.10 0.08 0.2 0.06 0.1 DNL (LSB) INL (LSB) 0.04 0 0.02 0 –0.02 –0.04 –0.06 –0.1 200 400 600 800 1000 1200 1400 1600 1800 2000 CODE –0.10 11149-004 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 CODE Figure 4. Typical INL, 11 mA at 25°C 11149-007 –0.08 –0.2 Figure 7. Typical DNL, 11 mA at 25°C 0.10 0.3 0.08 0.06 0.2 DNL (LSB) INL (LSB) 0.04 0.1 0 0.02 0 –0.02 –0.04 –0.06 –0.1 0 200 400 600 800 1000 1200 1400 1600 1800 2000 CODE –0.10 11149-005 –0.2 0 200 400 600 800 1000 1200 1400 1600 1800 2000 CODE 11149-008 –0.08 Figure 8. Typical DNL, 22 mA at 25°C Figure 5. Typical INL, 22 mA at 25°C 0.10 0.3 0.08 0.06 0.2 DNL (LSB) 0.1 0 0.02 0 –0.02 –0.04 –0.06 –0.1 –0.2 –0.10 0 200 400 600 800 1000 1200 1400 1600 1800 2000 CODE 0 200 400 600 800 1000 1200 1400 1600 1800 2000 CODE Figure 9. Typical DNL, 33 mA at 25°C Figure 6. Typical INL, 33 mA at 25°C Rev. 0 | Page 12 of 68 11149-009 –0.08 11149-006 INL (LSB) 0.04 Data Sheet AD9119/AD9129 AC (Normal Mode) IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. REF 5dBm 5 –5 –15 –25 –25 –35 –35 10dB/DIV –5 –15 –45 –55 –45 –55 –65 –65 –75 –75 –85 –85 –95 START 20MHz RES BW 20kHz VBW 20kHz STOP 2.6GHz SWEEP 7.78s (1001 pts) –95 START 20MHz RES BW 20kHz VBW 20kHz STOP 2.6GHz SWEEP 7.78s (1001 pts) 11149-012 REF 5dBm 11149-011 10dB/DIV 5 Figure 13. Single-Tone Spectrum at fOUT = 1000 MHz Figure 10. Single-Tone Spectrum at fOUT = 70 MHz –55 0 1400MSPS 1600MSPS 2200MSPS 2600MSPS 2800MSPS –10 –20 1600MSPS 2200MSPS 2600MSPS 2800MSPS –60 –65 IMD (dBc) SFDR (dBc) –30 –40 –50 –60 –70 –75 –80 –70 –85 –90 –90 200 400 600 800 1000 1200 1400 fOUT (MHz) 0 11149-013 0 200 400 600 800 1000 1200 1400 fOUT (MHz) Figure 11. SFDR vs. fOUT over fDAC 11149-014 –80 Figure 14. IMD vs. fOUT over fDAC –150 –145 1600MSPS 2200MSPS 2800MSPS 1600MSPS 2200MSPS 2800MSPS –150 NSD (dBm/Hz) –155 –160 –160 –165 –165 0 200 400 600 800 1000 fOUT (MHz) 1200 1400 Figure 12. Single-Tone NSD vs. fOUT 0 200 400 600 800 fOUT (MHz) Figure 15. W-CDMA NSD vs. fOUT Rev. 0 | Page 13 of 68 1000 1200 11149-016 –170 –170 11149-015 NSD (dBm/Hz) –155 AD9119/AD9129 Data Sheet IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –30 –45 –16dBFS –12dBFS –6dBFS 0dBFS –50 11mA 22mA 33mA –40 –55 SFDR (dBc) SFDR (dBc) –50 –60 –65 –60 –70 –70 –80 –75 400 600 800 1000 1200 1400 fOUT (MHz) 0 600 800 1000 1200 1400 1400 Figure 18. SFDR vs. fOUT over DAC IOUTFS –55 –16dBFS –12dBFS –6dBFS 0dBFS –50 400 fOUT (MHz) Figure 16. SFDR vs. fOUT over Digital Full Scale –40 200 11149-021 200 11149-017 0 11149-022 –90 –80 11mA 22mA 33mA –60 –65 IMD (dBc) –70 –70 –75 –80 –80 –90 –85 –100 0 200 400 600 800 1000 1200 fOUT (MHz) 1400 11149-020 IMD (dBc) –60 Figure 17. IMD vs. fOUT over Digital Full Scale –90 0 200 400 600 800 1000 fOUT (MHz) Figure 19. IMD vs. fOUT over DAC IOUTFS Rev. 0 | Page 14 of 68 1200 Data Sheet AD9119/AD9129 IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –150 –145 –40°C +25°C +85°C –40°C +25°C +85°C –150 NSD (dBm/Hz) NSD (dBm/Hz) –155 –155 –160 –160 –165 –165 400 600 800 1000 1200 1400 fOUT (MHz) 0 –40 –40 –50 –50 NSD (dBm/Hz) –30 –60 –70 –80 800 1000 1200 –60 –70 –80 –90 –90 –100 –100 –110 –110 –120 –120 SPAN 53.84MHz SWEEP 1.485s CENTER 877.5MHz VBW 3kHz SPAN 58.84MHz SWEEP 1.623s TOTAL CARRIER POWER –10.646dBm/7.68MHz FILTER OFF OFF OFF OFF OFF OFFSET FREQ 5MHz 10MHz 15MHz 20MHz 25MHz 11149-027 NSD (dBm/Hz) –20 –30 TOTAL CARRIER POWER –10.705dBm/3.84MHz LOWER UPPER OFFSET FREQ INTEG BW dBc dBm dBc dBm 5MHz 3.84MHz –74.97 –85.68 –75.24 –85.95 10MHz 3.84MHz –77.99 –88.69 –78.44 –89.14 15MHz 3.84MHz –78.68 –89.38 –78.94 –89.65 20MHz 3.84MHz –78.79 –89.50 –78.58 –89.29 25MHz 3.84MHz –76.81 –87.52 –77.20 –87.91 600 Figure 22. W-CDMA NSD vs. fOUT over Temperature –20 VBW 3kHz 400 fOUT (MHz) Figure 20. Single-Tone NSD vs. fOUT over Temperature CENTER 877.5MHz 200 INTEG BW 3.84MHz 3.84MHz 3.84MHz 3.84MHz 3.84MHz LOWER dBc dBm –71.62 –85.23 –74.36 –87.96 –74.35 –87.95 –72.89 –86.50 –67.34 –80.95 UPPER dBc dBm –71.61 –85.22 –74.94 –88.55 –74.91 –88.52 –74.53 –88.14 –73.68 –87.29 FILTER OFF OFF OFF OFF OFF Figure 23. Two-Carrier W-CDMA at 877.5 MHz Figure 21. Single-Carrier W-CDMA at 877.5 MHz Rev. 0 | Page 15 of 68 11149-028 200 11149-025 0 11149-026 –170 –170 AD9119/AD9129 Data Sheet AC (Mix-Mode) IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –5 –20 –15 –30 –25 10dB/DIV –10 –40 –50 –45 –55 –70 –65 –80 –75 –90 –85 –100 START 20MHz RES BW 20kHz STOP 2.6GHz SWEEP 7.78s (1001 pts) VBW 20kHz –95 START 20MHz RES BW 20kHz Figure 24. Single Tone Spectrum at fOUT = 2350 MHz –40 REF 5dBm –35 –60 11149-029 10dB/DIV 5 STOP 2.6GHz SWEEP 7.78s (1001 pts) VBW 20kHz 11149-030 REF 0dBm 0 Figure 27. Single-Tone Spectrum at fOUT = 1600 MHz –50 1600MSPS 2200MSPS 2800MSPS 1600MSPS 2200MSPS 2800MSPS –55 –50 IMD (dBc) SFDR (dBc) –60 –60 –70 –65 –70 –75 –80 1500 2000 2500 3000 fOUT (MHz) –85 500 2000 2500 3000 3500 4000 Figure 28. IMD vs. fOUT over fDAC –145 –150 –150 NSD (dBm/Hz) –145 –155 –160 –165 –155 –160 –165 1500 2000 2500 3500 3500 fOUT (MHz) 4000 4500 11149-033 NSD (dBm/Hz) 1500 fOUT (MHz) Figure 25. SFDR vs. fOUT over fDAC –170 1000 1000 11149-032 1000 11149-031 –90 500 11149-034 –80 Figure 26. Single-Tone NSD vs. fOUT –170 1500 2000 2500 3000 fOUT (MHz) Figure 29. W-CDMA NSD vs. fOUT Rev. 0 | Page 16 of 68 Data Sheet AD9119/AD9129 IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –25 –35 –40 –45 –50 –50 –55 –60 –60 –65 –65 –70 1000 1500 2000 2500 3000 3500 4000 fOUT (MHz) –70 1000 2500 4000 4000 –55 –65 –60 –65 –70 –70 –75 –75 SECOND NYQUIST ZONE THIRD NYQUIST ZONE 1500 3500 –50 –16dBFS –12dBFS –6dBFS 0dBFS –60 –80 1000 3500 –45 SECOND NYQUIST ZONE THIRD NYQUIST ZONE 2000 2500 3000 3500 fOUT (MHz) 4000 11149-036 IMD (dBc) –55 2000 Figure 32. SFDR vs. fOUT over DAC IOUTFS IMD (dBc) –50 1500 fOUT (MHz) Figure 30. SFDR vs. fOUT over Digital Full Scale –45 11mA 22mA 33mA –45 –55 11149-035 SFDR (dBc) –40 –16dBFS –12dBFS –6dBFS 0dBFS SECOND NYQUIST ZONE THIRD NYQUIST ZONE 11149-039 –35 –30 SFDR (dBc) –30 SECOND NYQUIST ZONE THIRD NYQUIST ZONE 11149-040 –25 Figure 31. IMD vs. fOUT over Digital Full Scale –80 1000 1500 2000 11mA 22mA 33mA 2500 3000 3500 fOUT (MHz) Figure 33. IMD vs. fOUT over DAC IOUTFS Rev. 0 | Page 17 of 68 AD9119/AD9129 Data Sheet IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –145 –145 –40°C +25°C +85°C –40°C +25°C +85°C –150 NSD (dBm/Hz) NSD (dBm/Hz) –150 –155 –160 –155 –160 –165 2000 2500 3500 3500 4000 fOUT (MHz) 1500 –40 –40 –50 –50 NSD (dBm/Hz) –30 –60 –70 –80 3500 3500 –60 –70 –80 –90 –90 –100 –100 –110 –110 –120 –120 SPAN 53.84MHz SWEEP 1.485s CENTER 1.98GHz VBW 3kHz SPAN 58.84MHz SWEEP 1.623s TOTAL CARRIER POWER –10.251dBm/15.36MHz FILTER OFF OFF OFF OFF OFF OFFSET FREQ 5MHz 10MHz 15MHz 20MHz 11149-045 NSD (dBm/Hz) –20 –30 VBW 3kHz 3000 Figure 36. W-CDMA NSD vs. fOUT over Temperature –20 CENTER 1.888GHz 2500 fOUT (MHz) Figure 34. Single-Tone NSD vs. fOUT over Temperature TOTAL CARRIER POWER –10.125dBm/3.84MHz LOWER UPPER OFFSET FREQ INTEG BW dBc dBm dBc dBm 5MHz 3.84MHz –70.25 –80.37 –70.38 –80.50 10MHz 3.84MHz –74.47 –84.60 –74.54 –84.66 15MHz 3.84MHz –75.55 –85.68 –75.72 –85.85 20MHz 3.84MHz –76.03 –86.15 –76.25 –86.37 25MHz 3.84MHz –76.62 –86.75 –76.70 –86.83 2000 Figure 35. Single-Carrier W-CDMA at 1887.5 MHz INTEG BW 3.84MHz 3.84MHz 3.84MHz 3.84MHz LOWER dBc dBm –65.84 –82.06 –67.02 –83.23 –68.05 –84.27 –69.07 –85.29 UPPER dBc dBm –65.79 –82.01 –66.75 –82.97 –67.99 –84.21 –69.03 –85.25 FILTER OFF OFF OFF OFF Figure 37. Four-Carrier W-CDMA at 1980 MHz Rev. 0 | Page 18 of 68 11149-046 1500 11149-043 –170 1000 11149-044 –165 Data Sheet AD9119/AD9129 DOCSIS Performance (Normal Mode) IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. REF –20dBm –20 REF –20dBm 1 –30 –30 –40 –40 –50 –50 –60 –60 10dB/DIV 10dB/DIV 1 –70 –80 –90 –80 –90 –100 –110 –110 –120 TRC 1 1 1 SCL f f f X 70MHz (Δ) 70MHz (Δ) 140MHz VBW 2kHz Y –3.819dBm (Δ) –74.107dB (Δ) –74.148dB –120 STOP 1.1GHz SWEEP 27.9s (1001 pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –3.819dBm (Δ) –74.24dB (Δ) –74.17dB START 0Hz RES BW 20kHz 11149-049 START 0Hz RES BW 20kHz MODE N Δ1 Δ1 TRC 1 1 1 REF –20dBm –20 X 950MHz (Δ) –68MHz (Δ) –882MHz Y –6.351dBm (Δ) –66.696dB (Δ) –70.598dB STOP 1.1GHz SWEEP 27.9s (1001 pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –6.349dBm (Δ) –66.696dB (Δ) –70.598dB REF –20dBm –30 1 1 –40 –40 –50 –50 –60 –60 10dB/DIV 10dB/DIV –30 SCL f f f VBW 2kHz Figure 41. Single Carrier at 950 MHz Output Figure 38. Single Carrier at 70 MHz Output –20 2Δ1 3Δ1 2Δ1 3Δ1 –100 MODE N Δ1 Δ1 –70 11149-052 –20 –70 –80 –70 –80 –90 –90 2Δ1 2Δ1 –100 –100 3Δ1 –110 –110 –120 TRC 1 1 1 SCL f f f X 79MHz (Δ) 61MHz (Δ) 131MHz VBW 2kHz Y –12.143dBm (Δ) –70.38dB (Δ) –67.78dB START 0Hz RES BW 20kHz STOP 1.1GHz SWEEP 27.9s (1001 pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –12.142dBm (Δ) –70.351dB (Δ) –67.775dB 11149-050 START 0Hz RES BW 20kHz MODE N Δ1 Δ1 TRC 1 1 1 Figure 39. Four Carrier at 70 MHz Output –20 SCL X f 959MHz f (Δ) –77MHz f (Δ) –891MHz VBW 2kHz Y –14.282dBm (Δ) –64.535dB (Δ) –68.529dB STOP 1.1GHz SWEEP 27.9s (1001 pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –14.264dBm (Δ) –64.535dB (Δ) –68.597dB 11149-053 –120 MODE N Δ1 Δ1 3Δ1 Figure 42. Four Carrier at 950 MHz Output REF –20dBm –20 REF –20dBm 1 –30 –30 –40 –40 –50 –50 –60 –60 10dB/DIV –70 –80 –90 –70 –80 –90 3Δ1 –100 –110 –110 –120 START 0Hz RES BW 20kHz MODE N Δ1 Δ1 TRC 1 1 1 SCL X f 91MHz f (Δ) 49MHz f (Δ) 117.9MHz VBW 20kHz Y –15.295dBm (Δ) –66.768dB (Δ) –66.821dB –120 STOP 1.1GHz SWEEP 27.9s (1001 pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –15.294dBm (Δ) –66.669dB (Δ) –66.833dB 2Δ1 3Δ1 START 0Hz RES BW 20kHz MODE N Δ1 Δ1 Figure 40. Eight Carrier at 70 MHz Output TRC 1 1 1 SCL f f f X 971MHz (Δ) –89MHz (Δ) –903MHz VBW 2kHz Y –14.632dBm (Δ) –62.657dB (Δ) –66.131dB STOP 1.1GHz SWEEP 27.9s (1001 pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –18.397dBm (Δ) –62.657dB (Δ) –66.195dB Figure 43. Eight Carrier at 950 MHz Output Rev. 0 | Page 19 of 68 11149-054 2Δ1 –100 11149-051 10dB/DIV 1 AD9119/AD9129 Data Sheet IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –40 IN-BAND THIRD HARMONIC (dBc) –60 –70 –80 –90 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) Figure 44. Second Harmonic vs. fOUT Performance for One DOCSIS Carrier –80 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) Figure 47. Third Harmonic vs. fOUT Performance for One DOCSIS Carrier –40 IN-BAND THIRD HARMONIC (dBc) –50 –60 –70 –80 –90 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) Figure 45. Second Harmonic vs. fOUT Performance for Four DOCSIS Carriers –60 –70 –80 –90 11149-056 0 –50 0 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) 11149-059 IN-BAND SECOND HARMONIC (dBc) –70 0 –40 Figure 48. Third Harmonic vs. fOUT Performance for Four DOCSIS Carriers –40 IN-BAND THIRD HARMONIC (dBc) –40 IN-BAND SECOND HARMONIC (dBc) –60 –90 11149-055 0 –50 11149-058 –50 –50 –60 –70 –80 –50 –60 –70 –80 –90 –90 0.2 0.4 0.6 fOUT (GHz) 0.8 1.0 0 11149-057 0 Figure 46. Second Harmonic vs. fOUT Performance for Eight DOCSIS Carriers 0.2 0.4 0.6 fOUT (GHz) 0.8 1.0 11149-060 IN-BAND SECOND HARMONIC (dBc) –40 Figure 49. Third Harmonic vs. fOUT Performance for Eight DOCSIS Carriers Rev. 0 | Page 20 of 68 Data Sheet AD9119/AD9129 –50 –50 –55 –55 –60 –60 –65 –65 ACPR (dBc) –70 –75 ACP1 ACP2 ACP3 ACP4 ACP5 –70 –75 –80 –80 ACP1 ACP2 ACP3 ACP4 ACP5 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) –90 0 0.2 –65 –65 ACPR (dBc) ACPR (dBc) –55 –60 –70 –75 –70 –75 –80 –80 –85 –85 –90 0.1 0.4 0.6 0.8 1.0 fOUT (GHz) 11149-168 –90 0.2 –20 0.3 0.4 0.5 0.6 0.7 0.8 0.9 REF –20dBm –30 –40 –60 –50 10dB/DIV –65 –70 –75 –60 –70 –80 –90 –80 –100 –85 –110 –90 0 0.2 0.4 0.6 0.8 fOUT (GHz) 1.0 11149-169 ACPR (dBc) 0.2 Figure 54. 32-Carrier ACPR vs. fOUT ACP1 ACP2 ACP3 ACP4 ACP5 –55 ACP1 ACP2 ACP3 ACP4 ACP5 fOUT (MHz) Figure 51. Four-Carrier ACPR vs. fOUT –50 1.0 –50 –60 0 0.8 Figure 53. 16-Carrier ACPR vs. fOUT ACP1 ACP2 ACP3 ACP4 ACP5 –55 0.6 fOUT (GHz) Figure 50. Single-Carrier ACPR vs. fOUT –50 0.4 11149-170 0 11149-171 –90 –85 11149-167 –85 Figure 52. Eight-Carrier ACPR vs. fOUT –120 CENTER 77MHz RES BW 10kHz VBW 1kHz SPAN 60MHz SWEEP 6.08s (1001 pts) Figure 55. Gap Channel ACPR at 77 MHz Rev. 0 | Page 21 of 68 11149-172 ACPR (dBc) IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. AD9119/AD9129 Data Sheet AD9129 Static Linearity IOUTFS = 28 mA, nominal supplies, TA = 25°C, unless otherwise noted. 1.0 2.0 1.5 0.5 DNL (LSB) INL (LSB) 1.0 0.5 0 0 –0.5 –0.5 –1.0 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE –1.5 11149-065 –1.5 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE Figure 56. Typical INL, 11 mA at 25°C 11149-068 –1.0 Figure 59. Typical DNL, 11 mA at 25°C 1.0 2.0 1.5 0.5 DNL (LSB) INL (LSB) 1.0 0.5 0 0 –0.5 –0.5 –1.0 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE –1.5 11149-066 –1.5 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE Figure 57. Typical INL, 22 mA at 25°C 11149-069 –1.0 Figure 60. Typical DNL, 22 mA at 25°C 2.0 1.0 1.5 0.5 DNL (LSB) 0.5 0 0 –0.5 –0.5 –1.0 –1.5 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE –1.5 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE Figure 58. Typical INL, 33 mA at 25°C Figure 61. Typical DNL, 33 mA at 25°C Rev. 0 | Page 22 of 68 11149-070 –1.0 11149-067 INL (LSB) 1.0 Data Sheet AD9119/AD9129 AC (Normal Mode) IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. 5 –5 –15 –25 –25 –35 –35 10dB/DIV –5 –15 –45 –55 –45 –55 –65 –65 –75 –75 –85 –85 –95 START 20MHz RES BW 20kHz VBW 20kHz STOP 2.6GHz SWEEP 7.78s (1001 pts) –95 START 20MHz RES BW 20kHz Figure 62. Single-Tone Spectrum at fOUT = 70 MHz VBW 20kHz STOP 2.6GHz SWEEP 7.78s (1001 pts) Figure 65. Single-Tone Spectrum at fOUT = 1000 MHz 0 –40 1400MSPS 1600MSPS 2200MSPS 2600MSPS 2800MSPS –10 –20 1600MSPS 2200MSPS 2600MSPS 2800MSPS –50 –60 IMD (dBc) –30 SFDR (dBc) REF 5dBm 11149-072 REF 5dBm 11149-071 10dB/DIV 5 –40 –50 –70 –80 –60 –70 –90 0 200 400 600 800 1000 1200 1400 fOUT (MHz) –100 11149-073 –90 0 200 400 600 800 1000 1200 1400 fOUT (MHz) Figure 63. SFDR vs. fOUT over fDAC 11149-074 –80 Figure 66. IMD vs. fOUT over fDAC 0 –145 1600MSPS 2200MSPS 2800MSPS 1600MSPS 2200MSPS 2800MSPS –10 –150 –20 NSD (dBm/Hz) –160 –40 –50 –60 –70 –165 –170 0 200 400 600 800 1000 fOUT (MHz) 1200 1400 Figure 64. Single-Tone NSD vs. fOUT –90 0 200 400 600 800 fOUT (MHz) Figure 67. W-CDMA NSD vs. fOUT Rev. 0 | Page 23 of 68 1000 1200 11149-076 –80 11149-075 NSD (dBm/Hz) –30 –155 AD9119/AD9129 Data Sheet IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –40 –45 –16dBFS –12dBFS –6dBFS 0dBFS –50 –16dBFS –12dBFS –6dBFS 0dBFS –50 –55 IMD (dBc) SFDR (dBc) –60 –60 –65 –70 –80 –70 –100 0 200 400 600 800 1000 1200 1400 fOUT (MHz) 11149-077 0 1200 1400 11mA 22mA 33mA –70 –60 –80 –70 –90 –80 0 200 400 600 800 1000 1200 1400 –90 0 200 600 800 1000 1200 1400 1400 fOUT (MHz) Figure 69. SFDR for Second Harmonic vs. fOUT over Digital Full Scale Figure 72. SFDR vs. fOUT over DAC IOUTFS –40 –55 –16dBFS –12dBFS –6dBFS 0dBFS –50 400 11149-081 SFDR (dBc) –50 11149-078 IN-BAND SECOND HARMONIC (dBc) 1000 –40 fOUT (MHz) 11mA 22mA 33mA –60 –65 IMD (dBc) –60 –70 –70 –75 –80 –80 –90 –85 –100 0 200 400 600 800 1000 1200 1400 fOUT (MHz) 11149-079 IN-BAND THIRD HARMONIC (dBc) 800 –30 –60 –100 600 Figure 71. IMD vs. fOUT over Digital Full Scale –16dBFS –12dBFS –6dBFS 0dBFS –50 400 fOUT (MHz) Figure 68. SFDR vs. fOUT over Digital Full Scale –40 200 11149-082 –80 11149-080 –90 –75 –90 0 200 400 600 800 1000 fOUT (MHz) Figure 73. IMD vs. fOUT over DAC IOUTFS Figure 70. SFDR for Third Harmonic vs. fOUT over Digital Full Scale Rev. 0 | Page 24 of 68 1200 Data Sheet AD9119/AD9129 IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –50 –150 –40°C +25°C +85°C –55 –40°C +25°C +85°C –155 NSD (dBm/Hz) SFDR (dBc) –60 –65 –160 –70 –165 0 200 400 600 1000 800 1200 1400 fOUT (MHz) –170 11149-083 0 200 400 600 1000 800 Figure 74. SFDR vs. fOUT over Temperature Figure 77. W-CDMA NSD vs. fOUT over Temperature –145 –60 –40°C +25°C +85°C –40°C +25°C +85°C –150 NSD (dBm/Hz) –70 –75 –155 –160 –165 0 200 400 600 800 1000 1200 1400 fOUT (MHz) 11149-084 –80 –170 0 –30 –40 –40 –50 –50 NSD (dBm/Hz) –30 –60 –70 –80 –100 –110 –110 –120 –120 SPAN 53.84MHz SWEEP 1.485s dBc –75.85 –79.88 –81.09 –81.89 –80.89 1400 CENTER 877.5MHz VBW 3kHz SPAN 58.84MHz SWEEP 1.623s TOTAL CARRIER POWER –10.599dBm/7.68MHz TOTAL CARRIER POWER –10.794dBm/3.84MHz dBm –87.08 –91.39 –92.16 –92.56 –90.08 1200 –80 –90 dBc –76.29 –80.60 –81.37 –81.76 –79.29 1000 –70 –100 INTEG BW 3.84MHz 3.84MHz 3.84MHz 3.84MHz 3.84MHz 800 –60 –90 dBm –86.64 –90.68 –91.89 –92.68 –91.69 FILTER OFF OFF OFF OFF OFF OFFSET FREQ 5MHz 10MHz 15MHz 20MHz 25MHz 11149-087 NSD (dBm/Hz) –20 OFFSET FREQ 5MHz 10MHz 15MHz 20MHz 25MHz 600 Figure 78. Single-Tone NSD vs. fOUT over Temperature –20 VBW 3kHz 400 fOUT (MHz) Figure 75. IMD vs. fOUT over Temperature CENTER 877.5MHz 200 11149-085 IMD (dBc) –65 –85 1200 fOUT (MHz) INTEG BW 3.84MHz 3.84MHz 3.84MHz 3.84MHz 3.84MHz dBc –72.33 –75.18 –74.76 –72.69 –65.42 dBm –85.89 –88.74 –88.32 –86.25 –78.99 dBc –72.37 –75.19 –74.92 –74.60 –73.53 dBm –85.93 –88.75 –88.48 –88.16 –87.09 FILTER OFF OFF OFF OFF OFF Figure 79. Two-Carrier W-CDMA at 875 MHz Figure 76. Single-Carrier W-CDMA at 877.5 MHz Rev. 0 | Page 25 of 68 11149-088 –80 11149-086 –75 AD9119/AD9129 Data Sheet IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –60 –65 –70 –70 ACLR (dBc) –65 –80 –80 –85 –85 –90 700 750 800 850 900 950 1000 fOUT (MHz) Figure 80. Single-Carrier W-CDMA ACLR vs. fOUT (First ACLR, Second ACLR) –90 700 –60 –65 –70 –70 ACLR (dBc) –65 –80 –85 –85 800 850 fOUT (MHz) 900 950 1000 –90 700 11149-090 750 Figure 81. Single-Carrier W-CDMA ACLR vs. fOUT (Third ACLR, Fourth ACLR, Fifth ACLR) 850 900 950 THIRD ACLR (dBc) FOURTH ACLR (dBc) FIFTH ACLR (dBc) –75 –80 –90 700 800 Figure 82. Two-Carrier W-CDMA ACLR vs. fOUT (First ACLR, Second ACLR) THIRD ACLR (dBc) FOURTH ACLR (dBc) FIFTH ACLR (dBc) –75 750 fOUT (MHz) –60 ACLR (dBc) –75 750 800 850 fOUT (MHz) 900 950 11149-092 –75 FIRST ACLR (dBc) SECOND ACLR (dBc) 11149-091 FIRST ACLR (dBc) SECOND ACLR (dBc) 11149-089 ACLR (dBc) –60 Figure 83. Two-Carrier W-CDMA ACLR vs. fOUT (Third ACLR, Fourth ACLR, Fifth ACLR) Rev. 0 | Page 26 of 68 Data Sheet AD9119/AD9129 AC (Mix-Mode) IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. REF 0dBm –5 –10 –15 –20 –25 10dB/DIV –30 10dB/DIV REF 5dBm 5 –40 –50 –60 –35 –45 –55 –65 –70 –75 –80 –90 START 20MHz RES BW 20kHz VBW 20kHz STOP 2.6GHz SWEEP 7.78s (1001 pts) 11149-093 –85 –95 START 20MHz RES BW 20kHz Figure 84. Single-Tone Spectrum at fOUT = 2350 MHz STOP 2.6GHz SWEEP 7.78s (1001 pts) VBW 20kHz 11149-094 0 Figure 87. Single-Tone Spectrum at fOUT = 1600 MHz –50 –40 –55 –50 –60 IMD (dBc) SFDR (dBm) –60 –70 –65 –70 –75 –80 1000 1500 2000 2500 3000 fOUT (MHz) –85 500 11149-095 1500 2000 2500 3000 3500 4000 Figure 88. IMD vs. fOUT over fDAC –145 –145 –150 –150 NSD (dBm/Hz) –155 –160 –165 –155 –160 –165 1500 2000 2500 3000 3500 fOUT (MHz) 4000 4500 11149-097 NSD (dBm/Hz) 1000 fOUT (MHz) Figure 85. SFDR vs. fOUT over fDAC –170 1000 1600MSPS 2200MSPS 2800MSPS Figure 86. Single-Tone NSD vs. fOUT –170 1500 2000 2500 3000 fOUT (MHz) Figure 89. W-CDMA NSD vs. fOUT Rev. 0 | Page 27 of 68 11149-098 –90 500 –80 11149-096 1600 2200 2800 AD9119/AD9129 Data Sheet IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –25 –20 –45 –50 –40 –50 –55 –60 –60 –70 –65 –80 –70 1000 1500 2000 2500 3000 3500 4000 fOUT (MHz) –90 1000 2500 3000 3500 4000 –30 SECOND NYQUIST ZONE THIRD NYQUIST ZONE SECOND NYQUIST ZONE THIRD NYQUIST ZONE –40 –16dBFS –12dBFS –6dBFS 0dBFS 11mA 22mA 33mA –50 IMD (dBc) –60 –65 –60 –70 –70 –80 1000 1500 2000 2500 3000 3500 fOUT (MHz) 4000 –90 1000 1500 2000 2500 3000 3500 fOUT (MHz) Figure 93. IMD vs. fOUT over DAC IOUTFS Figure 91. IMD vs. fOUT over Digital Full Scale Rev. 0 | Page 28 of 68 4000 11149-193 –80 –75 11149-100 IMD (dBc) 2000 Figure 92. SFDR vs. fOUT over DAC IOUTFS –45 –55 1500 fOUT (MHz) Figure 90. SFDR vs. fOUT over Digital Full Scale –50 11mA 22mA 33mA –30 11149-099 SFDR (dBm) –40 –16dBFS –12dBFS –6dBFS 0dBFS SECOND NYQUIST ZONE THIRD NYQUIST ZONE 11149-101 –35 –10 SFDR (dBm) –30 0 SECOND NYQUIST ZONE THIRD NYQUIST ZONE Data Sheet AD9119/AD9129 IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –145 –145 –40°C +25°C +85°C –40°C +25°C +85°C –150 NSD (dBm/Hz) NSD (dBm/Hz) –150 –155 –155 –160 –160 2000 2500 3000 3500 4000 fOUT (MHz) –165 1500 –30 –40 –40 –50 –50 NSD (dBm/Hz) –30 –60 –70 –80 3500 –60 –70 –80 –90 –90 –100 –100 –110 –110 –120 –120 SPAN 53.84MHz SWEEP 1.485s CENTER 1.98GHz VBW 3kHz SPAN 58.84MHz SWEEP 1.623s TOTAL CARRIER POWER –10.211dBm/15.36MHz FILTER OFF OFF OFF OFF OFF OFFSET FREQ 5MHz 10MHz 15MHz 20MHz 11149-107 NSD (dBm/Hz) –20 VBW 3kHz 3000 Figure 96. W-CDMA NSD vs. fOUT over Temperature –20 CENTER 1.888GHz 2500 fOUT (MHz) Figure 94. Single-Tone NSD vs. fOUT over Temperature TOTAL CARRIER POWER –9.445dBm/3.84MHz LOWER UPPER OFFSET FREQ INTEG BW dBc dBm dBc dBm 5MHz 3.84MHz –73.71 –83.15 –74.00 –83.45 10MHz 3.84MHz –77.40 –86.84 –77.31 –86.75 15MHz 3.84MHz –78.04 –87.48 –77.85 –87.30 20MHz 3.84MHz –78.13 –87.57 –78.51 –87.96 25MHz 3.84MHz –78.01 –87.46 –78.43 –87.87 2000 11149-106 1500 Figure 95. Single-Carrier W-CDMA at 1887.5 MHz INTEG BW 3.84MHz 3.84MHz 3.84MHz 3.84MHz LOWER dBc dBm –69.05 –85.24 –69.86 –86.05 –70.81 –87.00 –71.03 –87.22 UPPER dBc dBm –69.03 –85.22 –69.71 –85.90 –70.52 –86.71 –70.91 –87.10 FILTER OFF OFF OFF OFF Figure 97. Four-Carrier W-CDMA at 1980 MHz Rev. 0 | Page 29 of 68 11149-108 –170 1000 11149-105 –165 AD9119/AD9129 Data Sheet IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –50 FIRST ACLR (dBc) SECOND ACLR (dBc) –55 –60 –60 –65 –65 –70 –75 –75 –80 –85 –85 1.8 2.0 2.2 2.4 2.6 Figure 98. Single-Carrier W-CDMA ACLR vs. fOUT (First ACLR, Second ACLR) –50 –55 –90 1.4 2.2 2.4 2.6 –50 –55 –65 –65 ACLR (dBc) –60 –70 –75 –75 –80 –85 –85 fOUT (GHz) 2.2 2.4 2.6 –90 1.4 11149-110 2.0 Figure 99. Single-Carrier W-CDMA ACLR vs. fOUT (Third ACLR, Fourth ACLR, Fifth ACLR) THIRD ACLR (dBc) FOURTH ACLR (dBc) FIFTH ACLR (dBc) –70 –80 1.8 2.0 Figure 100. Four-Carrier W-CDMA ACLR vs. fOUT (First ACLR, Second ACLR) THIRD ACLR (dBc) FOURTH ACLR (dBc) FIFTH ACLR (dBc) 1.6 1.8 fOUT (GHz) –60 –90 1.4 1.6 1.6 1.8 2.0 fOUT (GHz) 2.2 2.4 2.6 11149-112 1.6 fOUT (GHz) ACLR (dBc) –70 –80 –90 1.4 FIRST ACLR (dBc) SECOND ACLR (dBc) 11149-111 ACLR (dBc) –55 11149-109 ACLR (dBc) –50 Figure 101. Four-Carrier W-CDMA ACLR vs. fOUT (Third ACLR, Fourth ACLR, Fifth ACLR) Rev. 0 | Page 30 of 68 Data Sheet AD9119/AD9129 DOCSIS Performance (Normal Mode) IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. REF –20dBm –20 1 –30 –40 –40 –50 –50 –60 –60 –70 –80 –70 –80 –90 –90 2Δ1 2Δ1 3Δ1 3Δ1 –100 –100 –110 –110 –120 TRC 1 1 1 SCL f f (Δ) f (Δ) X 70MHz (Δ) 70MHz (Δ) 140MHz VBW 20kHz Y –3.611dBm (Δ) –72.929dB (Δ) –74.629dB START 0Hz RES BW 20kHz STOP 1.1GHz SWEEP 27.9s (1001 pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –3.612dBm (Δ) –72.903dB (Δ) –74.583dB MODE N Δ1 Δ1 11149-113 START 0Hz RES BW 20kHz TRC 1 1 1 Y –6.221dBm (Δ) –68.115dB (Δ) –71.783dB STOP 1.1GHz SWEEP 27.9s (1001 pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –6.223dBm (Δ) –68.115dB (Δ) –71.783dB Figure 105. Single Carrier at 950 MHz Output Figure 102. Single Carrier at 70 MHz Output REF –20dBm –20 –30 REF –20dBm –30 1 –40 –50 –50 –60 –60 10dB/DIV 10dB/DIV 1 –40 –70 –80 –90 3Δ1 2Δ1 –100 –110 3Δ1 –110 START 0Hz RES BW 20kHz TRC 1 1 1 SCL f f (Δ) f (Δ) X 79MHz (Δ) 61MHz (Δ) 131MHz VBW 20kHz Y –11.506dBm (Δ) –71.473dB (Δ) –69.109dB –120 STOP 1.1GHz SWEEP 27.9s (1001 pts) FUNCTION FUNCTION WIDTH BAND POWER 6MHz BAND POWER 6MHz BAND POWER 6MHz FUNCTION VALUE –11.506dBm (Δ) –71.606dB (Δ) –69.155dB 11149-114 MODE N Δ1 Δ1 –80 –90 2Δ1 –100 –120 –70 MODE N Δ1 Δ1 START 0Hz RES BW 20kHz TRC 1 1 1 Figure 103. Four Carrier at 70 MHz Output –20 Y –14.583dBm (Δ) –65.064dB (Δ) –71.759dB STOP 1.1GHz SWEEP 27.9s (1001 pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –14.584dBm (Δ) –65.064dB (Δ) –71.759dB Figure 106. Four Carrier at 950 MHz Output REF –20dBm –30 SCL X f 959MHz f (Δ) –77MHz f (Δ) –891MHz VBW 2kHz 11149-117 –20 SCL X f 950MHz f (Δ) –68MHz f (Δ) –882MHz VBW 2kHz 11149-211 –120 MODE N Δ1 Δ1 REF –20dBm 1 –30 10dB/DIV 10dB/DIV –20 –20 REF –20dBm –30 1 –50 –50 –60 –60 10dB/DIV –40 –70 –80 –90 –70 –80 –90 2Δ1 –100 3Δ1 2Δ1 –100 3Δ1 –110 –120 START 0Hz RES BW 20kHz MODE N Δ1 Δ1 TRC 1 1 1 SCL X f 91MHz f (Δ) (Δ) 49MHz f (Δ) (Δ) 117.9MHz VBW 20kHz Y –15.917dBm (Δ) –66.430dB (Δ) –67.401dB STOP 1.1GHz SWEEP 27.9s (1001 pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –15.919dBm (Δ) –66.658dB (Δ) –67.436dB START 0Hz RES BW 20kHz MODE N Δ1 Δ1 Figure 104. Eight Carrier at 70 MHz Output TRC 1 1 1 SCL X f 971MHz f (Δ) –89MHz f (Δ) –903.0MHz VBW 2kHz Y –18.364dBm (Δ) –63.858dB (Δ) –70.065dB STOP 1.1GHz SWEEP 27.9s (1001 pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –18.364dBm (Δ) –63.858dB (Δ) –70.065dB Figure 107. Eight Carrier at 950 MHz Output Rev. 0 | Page 31 of 68 11149-118 –110 –120 11149-115 10dB/DIV 1 –40 AD9119/AD9129 Data Sheet IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –40 IN-BAND THIRD HARMONIC (dBc) –50 –60 –70 –80 –70 –80 0.4 0.6 0.8 1.0 fOUT (GHz) 0 Figure 108. Second Harmonic vs. fOUT Performance for One DOCSIS Carrier 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) 11149-122 0.2 11149-119 0 Figure 111. Third Harmonic vs. fOUT Performance for One DOCSIS Carrier –40 –40 IN-BAND THIRD HARMONIC (dBc) –50 –60 –70 –80 –90 –50 –60 –70 –80 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) 11149-120 –90 0 Figure 109. Second Harmonic vs. fOUT Performance for Four DOCSIS Carriers 0 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) 11149-123 IN-BAND SECOND HARMONIC (dBc) –60 –90 –90 Figure 112. Third Harmonic vs. fOUT Performance for Four DOCSIS Carriers –40 –40 IN-BAND THIRD HARMONIC (dBc) IN-BAND SECOND HARMONIC (dBc) –50 –50 –60 –70 –80 –90 –50 –60 –70 –80 0.2 0.4 0.6 fOUT (GHz) 0.8 1.0 11149-121 –90 0 Figure 110. Second Harmonic vs. fOUT Performance for Eight DOCSIS Carriers 0 0.2 0.4 0.6 fOUT (GHz) 0.8 1.0 11149-124 IN-BAND SECOND HARMONIC (dBc) –40 Figure 113. Third Harmonic vs. fOUT Performance for Eight DOCSIS Carriers Rev. 0 | Page 32 of 68 Data Sheet AD9119/AD9129 IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –55 –60 –65 –65 ACPR (dBc) –60 –70 –75 –70 –75 –80 –80 –85 –85 ACP1 ACP2 ACP3 ACP4 ACP5 –90 –90 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) 0 11149-219 0 0.2 –65 –65 ACPR (dBc) ACPR (dBc) –55 –60 –70 –75 –75 –80 –85 –85 ACP1 ACP2 ACP3 ACP4 ACP5 –90 0.4 0.6 0.8 1.0 fOUT (GHz) 11149-220 –90 Figure 115. Four-Carrier ACPR vs. fOUT –55 –60 –65 –70 –75 –80 –90 0 0.2 0.4 0.6 0.8 fOUT (GHz) 1.0 11149-221 ACP1 ACP2 ACP3 ACP4 ACP5 –85 1 2 3 4 5 6 7 fOUT (GHz) Figure 118. 32-Carrier ACPR vs. fOUT –50 ACPR (dBc) –70 –80 0.2 9 –50 –60 0 1.0 Figure 117. 16-Carrier ACPR vs. fOUT ACP1 ACP2 ACP3 ACP4 ACP5 –55 0.8 fOUT (GHz) Figure 114. Single-Carrier ACPR vs. fOUT –50 0.6 0.4 11149-222 –55 ACPR (dBc) –50 ACP1 ACP2 ACP3 ACP4 ACP5 11149-223 –50 Figure 116. Eight-Carrier ACPR vs. fOUT Rev. 0 | Page 33 of 68 8 AD9119/AD9129 Data Sheet IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –20 –40 REF –20dBm ACLR IN GAP CHANNEL (dBc) –30 –40 –60 –70 –80 –90 –100 –60 –70 –80 –110 CENTER 77MHz RES BW 10kHz VBW 1kHz SPAN 60MHz SWEEP 6.08s (1001 pts) –90 0 0.2 0.4 0.6 0.8 fOUT (GHz) Figure 119. Gap Channel ACLR at 77 MHz Figure 120. Gap Channel ACLR vs. fOUT Rev. 0 | Page 34 of 68 1.0 11149-225 –120 11149-125 10dB/DIV –50 –50 Data Sheet AD9119/AD9129 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) The maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Spurious-Free Dynamic Range The difference, in decibels (dB), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Differential Nonlinearity (DNL) The measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Total Harmonic Distortion (THD) The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of zero. For IOUTP, 0 mA output is expected when the inputs are all 0s. For IOUTN, 0 mA output is expected when all inputs are set to 1. Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0. Output Compliance Range The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree Celsius (°C). For reference drift, the drift is reported in ppm per °C. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Noise Spectral Density (NSD) The converter noise power per unit of bandwidth. This is usually specified in dBm/Hz in the presence of a 0 dBm fullscale signal. Adjacent Channel Leakage Ratio (ACLR) The ratio, in dBc, between the measured power within a channel relative to its adjacent channels. Adjacent Channel Power Ratio (ACPR) The ratio, in dBc, between the total power of an adjacent channel (intermodulation signal) to the main channel's power (useful signal). Modulation Error Ratio (MER) A measure of the discrepancy between the average output symbol magnitude and the rms error magnitude of the individual symbol. Modulated signals create a discrete set of output values referred to as a constellation, and each symbol creates an output signal corresponding to one point on the constellation. Intermodulation Distortion (IMD) The result of two or more signals at different frequencies mixing together. Many products are created according to the formula aF1 ± bF2, where a and b are integer values. Rev. 0 | Page 35 of 68 AD9119/AD9129 Data Sheet SERIAL COMMUNICATIONS PORT OVERVIEW The AD9119/AD9129 are 11-bit/14-bit DACs that operate at an update rate of up to 2.8 GSPS. Due to internal timing requirements, the minimum allowable sample rate is 1400 MSPS. Input data is sampled through two 11-/14-bit LVDS ports that are internally multiplexed. Each port has its own data inputs, but both ports share a common data clock input (DCI). The LVDS inputs meet the IEEE-1596 specification with the exception of input hysteresis, which is not guaranteed over all process corners. Each DCI input runs at one-quarter the input data rate in a double data rate (DDR) format. Each edge of the DCI is used to transfer data into the AD9119/AD9129. Control of the AD9119/AD9129 functions is via a SPI. SERIAL PERIPHERAL INTERFACE (SPI) The AD9119/AD9129 SPI is a flexible, synchronous serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including the Motorola® SPI and the Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9119/AD9129. Most significant bit first (MSB-first) or least significant bit first (LSB-first) transfer formats are supported. The AD9119/AD9129 serial interface port can be configured as a single I/O pin (SDIO) or two unidirectional pins for input/ output (SDIO and SDO). SPI PORT CS (PIN K2) 11149-126 SCLK (PIN K1) The instruction byte is shown in the following table. I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0 R/W, Bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation. Logic 0 indicates a write operation, the data transfer cycle. A6 to A0 (Bit 6 through Bit 0 of the instruction byte) determine which register is accessed during the data transfer portion of the communications cycle. SERIAL PERIPHERAL INTERFACE PIN DESCRIPTIONS SCLK—Serial Clock The serial clock pin is used to synchronize data to and from the AD9119/AD9129 and to run the internal state machines. The maximum frequency of SCLK is 20 MHz. All data input to the AD9119/AD9129 is registered on the rising edge of SCLK. All data is driven out of the AD9119/AD9129 on the rising edge of SCLK. CS—Chip Select Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDO and SDIO pins go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle. SDO (PIN J2) AD9119/ AD9129 INSTRUCTION MODE (8-BIT INSTRUCTION) MSB I7 R/W The DACCLK_N and DACCLK_P inputs directly drive the DAC core to minimize clock jitter. The DACCLK signal is divided by 4 and then output as the DCO for each port. The DCO signal can be used to clock the data source. The DAC expects DDR LVDS data (P0_D[13:0]x, P1_D[13:0]x), with each channel aligned with the single DDR DCI signal. SDIO (PIN J1) AD9129 and the system controller. Phase 2 of the communication cycle is a transfer of one byte only. Single-byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte. CS (chip select) can be raised after each sequence of eight bits (except the last byte) to stall the bus. The serial transfer resumes when CS is lowered. Stalling on nonbyte boundaries resets the SPI. Figure 121. AD9119/AD9129 SPI Port SDIO—Serial Data I/O GENERAL OPERATION OF THE SPI There are two phases to a communication cycle with the AD9119/ AD9129. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9119/AD9129, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9119/AD9129 serial port controller with information about the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9119/AD9129. Data is always written into the AD9119/AD9129 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Register 0x00, Bit 7 (SDIO_DIR). The default is Logic 1, which configures the SDIO pin as bidirectional. SDO—Serial Data Out Data is read from this pin for protocols that use separate lines for transmitting and receiving data. When the AD9119/AD9129 are operating in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9119/ Rev. 0 | Page 36 of 68 Data Sheet AD9119/AD9129 MSB/LSB TRANSFERS INSTRUCTION CYCLE When LSB/MSB = 1 (LSB first), the instruction and data bytes must be written from the least significant bit to the most significant bit. SERIAL PORT CONFIGURATION SDIO R/W A0 A1 A2 A3 D40 D5N D6N D7N A5 A6 D00 D10 D20 A4 Figure 124. Serial Register Interface Timing, LSB-First Write INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK In the event of unexpected programming sequences, the AD9119/AD9129 SPI can become inaccessible. For example, if user code inadvertently changes the LSB/MSB bit, the bits that follow experience unexpected results. The SPI can be returned to a known state by writing an incomplete byte (1 to 7 bits) of all 0s, followed by three bytes of 0x00. This returns to the MSBfirst instructions (Register 0x00 = 0x00) so that the device can be reinitialized. SDIO R/W A0 A1 A2 A3 A4 A5 A6 D10 D20 D40 D5N D6N D7N D10 D20 D40 D5N D6N D7N SDO D0 11149-130 D0 Figure 125. Serial Register Interface Timing, LSB-First Read tDS tSCLK CS SCLK tDS SDIO tDH INSTRUCTION BIT 7 11149-131 The AD9119/AD9129 serial port configuration is controlled by Register 0x00, Bits[7:5]. Note that the configuration changes immediately upon writing to the last bit of the register. When setting the software reset bit (SoftReset in Register 0x00, Bit 5), all registers are set to their default values except Register 0x00, which remains unchanged. INSTRUCTION CYCLE SCLK 11149-129 The AD9119/AD9129 serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by the LSB/MSB bit, Bit 6 in Register 0x00. The default is MSB first (LSB/MSB = 0). When the MSB-first data format is selected, the instruction and data bytes must be written from the most significant bit to the least significant bit. DATA TRANSFER CYCLE CS INSTRUCTION BIT 6 Figure 126. Timing Diagram for an SPI Register Write DATA TRANSFER CYCLE CS CS R/W A6 A5 A4 A3 A2 A1 A0 D7N D6N D5N D30 D20 D10 D00 SCLK tDNV Figure 122. Serial Register Interface Timing, MSB-First Write SDIO I1 INSTRUCTION CYCLE SCLK R/W A6 A5 A4 A3 A2 A1 A0 D6N D5N D30 D20 D10 D00 D6N D5N D30 D20 D10 D00 D7 Figure 123. Serial Register Interface Timing, MSB-First Read 11149-128 D7 SDO D7 D6 D5 Figure 127. Timing Diagram for an SPI Register Read DATA TRANSFER CYCLE CS SDIO I0 tDV 11149-132 SDIO 11149-127 SCLK After the last instruction bit is written to the SDIO pin, the driving signal must be set to a high impedance in time for the bus to turn around. The serial output data from the AD9119/ AD9129 is enabled by the falling edge of SCLK. This causes the first output data bit to be shorter than the remaining data bits, as shown in Figure 127. To assure proper reading of data, read the SDIO pin or the SDO pin before changing SCLK from low to high. Due to the more complex multibyte protocol, multiple AD9119/ AD9129 devices cannot be daisy-chained on the SPI bus. Control multiple DACs by using independent CS signals. Rev. 0 | Page 37 of 68 AD9119/AD9129 Data Sheet THEORY OF OPERATION The AD9119/AD9129 are 11-bit/14-bit DACs that are capable of reconstructing signal bandwidths up to 1.4 GHz while operating with an input data rate up to 2.8 GSPS. Figure 128 shows a top level functional diagram of the AD9119/AD9129. A high performance NMOS DAC delivers a signal dependent, differential current to a balanced external load referenced a nominal 1.8 V analog supply. The current source array of the DAC is referenced to an external −1.5 V supply, and its full-scale current, IOUTFS, can be adjusted over a 9.5 mA to 34.4 mA span. RESET I250U VREF IRQ AD9129 1.2V SPI Tx DAC CORE IOUTP IOUTN 2× PLL CLOCK DISTRIBUTION DCR DACCLK_x 11149-133 DCO_x LVDS DDR RECEIVER DCI_x BASEBAND MODE DATA LATCH DLL DATA ASSEMBLER P0_D[13:0]P, P0_D[13:0]N P1_D[13:0]P, P1_D[13:0]N MIXNORMAL MODE LVDS DDR RECEIVER FRM_x (FRAME/ PARITY) 4× FIFO SDIO SDO CS SCLK This effectively reduces the bus interface speed to ½ the data rate (for example, fDATA/2) with the DCI clock operating at fDATA/4. An optional parity bit can also be sent along with the data to enhance the robustness of the interface. In this case, a counter is available to count parity errors and generate an interrupt request (IRQ) when a programmable threshold is exceeded. The AD9119/AD9129 provide the host with a DCO clock that is equal to the DCI clock frequency to establish synchronous operation. A delay locked loop (DLL) with programmable phase offset is used to generate an internal sampling clock with optimum edge placement for the input data latches of the LVDS DDR receivers. When data is latched into the AD9119/AD9129, an eight-sampledeep FIFO is used to hand off the data between the host and the AD9119/AD9129 clock domains. The FIFO can be reset with an external synchronization signal, fSYNC, to ensure consistent pipeline latency. The pipeline delay, from a sample being latched into the data port to when it appears at the DAC output, varies depending on the chosen configuration (see the Pipeline Delay (Latency) section). The de-interleaved data is reassembled into its original data stream after passing into the internal clock domain of the AD9119/ AD9129. Because the quad-switch architecture of the DAC updates its output on both the rising and falling edge (for example, dual edge clocking) of the DACCLK signal, the following two additional modes of operation are available: • Figure 128. Functional Block Diagram of the AD9119/AD9129 A low jitter differential clock receiver is used to square up the signal appearing at the DACCLK_x input that sets the update rate of the DAC. The differential clock receiver can accept sinusoidal signals with negligible noise spectral density degradation if the input signal level is maintained above 0 dBm. A +1 dB degradation occurs at a −5 dBm input, and degradation increases as the signal approaches −10 dBm and its associated +2 dB additional degradation. A duty cycle restorer (DCR), following the clock receiver, ensures near 50% duty-cycle to the subsequent circuitry. The output of the DCR serves as the master clock and is routed directly to the DAC, as well as to a clock distribution block that generates all critical internal and external clocks. The clock source quality, as defined by its phase noise characteristics, jitter, and drive capability, is an important consideration in maintaining optimum ac performance. The AD9119/AD9129 supports a source synchronous, LVDS double data-rate (DDR) data interface to the host processor. Two 11-bit/14-bit LVDS data ports (P0_DxP, P0_DxN and P1_DxP, P1_DxN) are used to sample de-interleaved data from the host on the rising and falling edge of the host DCI clock. • A 2× interpolation filter can be selected to increase the effective DAC update rate (fDAC) to be 2× the input data rate, hence simplifying the analog postfiltering requirements and reducing the effects of alias harmonics in the desired baseband region. A Mix-Mode option essentially generates the complement sample on the falling edge such that the original Nyquist spectrum is shifted to fDACCLK, with the sinc null of the DAC falling at 2 × fDACCLK. The digital handoff between the digital domain and mixed signal domain of a high speed DAC is critical in preserving its output dynamic range. A phase locked loop (PLL) with programmable phase offset is used to optimize the timing handoff between these two clock domains. State machines are used to initialize both the DLL and the PLL during the initial boot sequence after receiving a stable DACCLK signal. Following initialization of the two loops, they maintain optimum timing alignment over temperature, time, and power supply variation. The AD9119/AD9129 also provide IRQ capability to monitor the DLL, the PLL, and other internal circuitry. Rev. 0 | Page 38 of 68 Data Sheet AD9119/AD9129 LVDS DATA PORT INTERFACE The data timing requirements are defined by a minimum data valid margin that is dependent on the data clock input skew, input data jitter, and the variations of the DLL delay line across delay settings. This margin is defined by subtracting from the data period any data skew, data jitter, and the keep-out window (KOW) that is defined by the sum of the set and hold times, as follows: The AD9119/AD9129 can operate with input data rates of up to 2.8 GSPS. A source synchronous LVDS interface is used between the host and the AD9119/AD9129 to achieve these high data rates, while simplifying the interface. As shown in Figure 129, the host feeds the AD9119/AD9129 with de-interleaved input data into two 11-bit/14-bit LVDS data ports (P0_DxP, P0_DxN and P1_DxP, P1_DxN) at ½ the DAC clock rate (that is, fDACCLK/2). Along with the input data, the host provides an embedded DDR data clock input (DCI_x) at fDACCLK/4. tDATA VALID MARGIN = tDATA PERIOD − tDATA SKEW − tDATA JITTER − (tH + tS) The keep-out window, which is the sum of the set and hold times, is the area where data transitions should not occur. The timing margin allows tuning of the DLL delay setting, either automatically or in manual mode (see Figure 130). A DLL circuit that is designed to operate with DCI clock rates of between 350 MHz and 700 MHz is used to generate a phase shifted version of DCI, called the data sampling clock (DSC), to register the input data on both the rising and falling edges. Figure 130 shows that the ideal location for the DSC signal is 90° out of phase from the DCI input. However, due to skew of the DCI relative to the data, it may be necessary to change the DSC phase offset to sample the data at the center of its eye diagram. The sampling instance can be varied in discrete increments by offsetting the nominal DLL phase shift value of 90° via Register 0x0A, Bits[3:0]. The following equation defines the phase offset relationship: As shown in Figure 130, the DCI clock edges must be coincident with the data bit transitions with minimum skew and jitter. The nominal sampling point of the input data occurs in the middle of the DCI clock edges because this point corresponds to the center of the data eye. This is also equivalent to a nominal phase shift of 90°of the DCI clock. Phase Offset = 90° ± n × 11.25°, |n| < 8 AD9129 LVDS DDR RECEIVER DELAY LOCK LOOP fDATA = fDACCLK /2 1×2 fDCI = fDACCLK /4 DCI 1×2 DCO fDCO = fDACCLK /4 CLOCK DISTRIBUTION fDACCLK 11149-134 ODD DATA SAMPLES 14 × 2 LVDS DDR RECEIVER LVDS DDR DRIVER DATA DE-INTERLEAVER EVEN DATA SAMPLES 14 × 2 P0_D[13:0]x OPTIONAL PARITY P1_D[13:0]x HOST PROCESSOR COMBINED ODD/EVEN PARITY BIT Figure 129. Recommended Digital Interface Between the AD9119/AD9129 and the Host Processor tDATA SKEW INPUT DATA[13:0] DLL PHASE DELAY tDSC SETUP AND HOLD tDATA JITTER DATA EYE tDATA PERIOD 11149-135 DCI DATA SAMPLE CLOCK Figure 130. LVDS Data Port Timing Requirements Rev. 0 | Page 39 of 68 AD9119/AD9129 Data Sheet Figure 131 shows the DSC set and hold times with respect to the DCI signal and data signals. DATA DCI Table 10 lists the values that are guaranteed over the operating conditions. These values were taken with 50% duty cycle and DCI swing of 450 mV p-p. For best performance, the duty cycle variation should be kept below ±5%, and the DCI input should be as high as possible, up to 800 mV p-p. Table 10. Data Port Set and Hold Time Window (Guaranteed) 11149-238 DSC tS tH Figure 131. LVDS Data Port Set and Hold Times Table 11 shows the typical times for various DAC clock frequencies that are required to calculate the data valid margin. The amount of margin that is available for tuning of the DSC sampling point can be determined using Table 11. Frequency, fDAC (MHz) 1600 2300 2800 Time (ps) tS tH tS tH tS tH Data Port Set and Hold Times (ps) at DLL Phase −3 0 +3 −272 −489 −683 682 911 1120 −168 −292 −420 564 705 839 −88 −185 −285 457 559 652 Table 11. Data Port Set and Hold Time Window (Typical) Frequency, fDAC 1 (MHz) 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 1 Time (ps) tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH −6 −106 426 −124 427 −120 421 −111 382 −93 400 −90 398 −82 389 −87 370 −94 415 −93 390 −130 426 −73 370 −43 338 −54 316 −36 335 −5 −205 499 −197 490 −191 485 −184 429 −133 442 −139 443 −122 423 −133 409 −143 453 −131 422 −156 459 −106 407 −76 369 −77 340 −72 355 −4 −274 571 −291 556 −252 550 −226 489 −209 492 −182 488 −170 468 −161 451 −182 487 −182 456 −196 494 −142 433 −115 396 −108 372 −101 379 −3 −353 651 −351 637 −335 619 −301 549 −265 555 −254 535 −220 522 −206 491 −245 523 −227 500 −244 529 −177 467 −145 430 −144 406 −143 404 Data Port Set and Hold Times (ps) at DLL Phase −2 −1 0 +1 +2 +3 −436 −523 −604 −680 −798 −906 730 813 900 977 1069 1152 −453 −524 −600 −670 −732 −815 713 795 870 942 1025 1100 −402 −495 −552 −626 −704 −776 689 760 836 910 989 1049 −370 −442 −528 −580 −641 −719 619 700 762 825 907 970 −326 −401 −475 −524 −596 −646 617 677 754 816 883 950 −298 −359 −430 −496 −547 −593 593 664 717 778 849 900 −272 −346 −399 −452 −517 −565 571 625 683 733 789 854 −274 −331 −384 −443 −488 −540 536 592 636 696 751 794 −283 −334 −378 −427 −487 −521 571 622 673 722 778 818 −270 −312 −357 −388 −439 −485 542 595 644 686 731 778 −277 −313 −366 −404 −457 −496 567 607 653 698 731 769 −216 −258 −308 −348 −394 −430 502 546 582 619 662 702 −184 −228 −275 −306 −351 −375 466 503 535 567 614 652 −179 −228 −277 −305 −336 −354 441 475 499 539 580 622 −175 −208 −243 −287 −320 −347 442 480 511 545 575 607 +4 −993 1235 −908 1181 −847 1128 −784 1032 −709 1003 −663 963 −607 908 −586 855 −565 859 −531 821 −534 815 −458 740 −402 690 −400 654 −382 638 +5 −1064 1303 −982 1241 −902 1195 −822 1095 −765 1061 −700 1021 −660 958 −623 911 −604 908 −570 858 −560 862 −486 780 −443 725 −424 685 −408 676 Table 11 shows characterization data for selected fDAC frequencies. Other frequencies are possible, and Table 11 can be used to estimate performance. Rev. 0 | Page 40 of 68 +6 −1131 1387 −1071 1320 −978 1250 −895 1151 −823 1122 −765 1070 −713 1015 −675 954 −659 956 −623 902 −615 911 −535 828 −491 766 −471 729 −463 717 Data Sheet AD9119/AD9129 Before losing lock, the DLL controller issues a DLL warning by setting Register 0x0E, Bit 6, to 1b and setting either Bit 5 or Bit 4 to 1b. This setting indicates that the DLL is near to losing lock. If the DLL is going to reach the beginning of the delay line soon, the controller issues a start warning by setting Register 0x0E, Bit 5 and Bit 6 to 1b. This setting indicates that the DLL is at the start of the delay line, and losing lock is imminent. USER DCI For synchronous operation between the host and the AD9119/ AD9129, the AD9119/AD9129 provide a data clock output, DCO, to the host at the same rate as DCI (that is, fDACCLK/4). Note that the DCI signal can have arbitrary phase alignment with respect to the DCO because the DLL of the AD9119/AD9129 ensures proper data hand-off between the two clock domains (that is, the host processors and the internal digital core of the AD9119/AD9129). The default reset state of the AD9119/AD9129 is to have the DCO signal disabled. To enable it, write a 1b to Register 0x0C, Bit 6. The DCO output level is controlled in Register 0x7C, Bits[7:6]. The default setting is 01b, or 2.8 mA, but it can be increased to as high as 4 mA (11b) if higher swing is necessary. The DCI signal is ac-coupled internally; therefore, a possibility exists that removing the DCI signal can cause DAC output chatter due to randomness on the DCI input. To avoid this chatter, it is recommended that the DAC output be disabled when the DCI signal is not present. To do this, program the DAC output current power-down bit in Register 0x01, Bit 6, to 1b. When the DCI signal is again present, the DAC output can be enabled by programming Register 0x01, Bit 6, to 0b. The DAC output powers up in ~2 µs. The status of the DLL can be polled by reading the data status register at Address 0x0E. Bit 0 indicates that the DLL is running and attempting lock, and Bit 7 is set to 1b when the DLL is locked. Bit 2 is set to 1b when a valid data clock is detected. The warning bits in Address 0x0E, Bits[6:4] can be used as indicators that the DAC may be operating in a nonideal location in the delay line. Note that these bits are read at the SPI port speed, which is much slower than the actual speed of the DLL. This means that these bits can show only a snapshot of what is happening, rather than giving real-time feedback. Temperature Effects The length of the delay line varies slightly across the operating temperature range, as the amount of delay through a delay cell expands or contracts slightly due to the temperature change. This can introduce a situation where the DLL may lock at one temperature extreme and then approach an unlocked state as the temperature changes (see Figure 132). In the example shown in Figure 132, the DLL can lock at Phase Setting 0 at 90° in a cold temperature. As the temperature gets hotter, the delay line changes length, and the controller adjusts the DLL control voltage to keep the 90° offset. In this case, a voltage beyond the acceptable control voltage range is required to hold the 90° phase offset. D0 USER DATA D1 DATA SAMPLE CLK 90° DELAY LINE – COLD DELAY LINE – HOT 11149-236 Maximizing the opening of the eye in both the DCI and data signals improves reliability of the data port interface. Use differential controlled impedance traces of equal length (that is, delay) between the host processor and the AD9119/AD9129 input. To ensure coincident transitions with the data bits, implement the DCI as an additional data line with an alternating (010101…) bit sequence from the same output drivers that are used for the data. Figure 132. Example of DLL Length Variation Across Temperature A similar situation can happen at the end of the delay line, in which case a DLL warning and a DLL end is issued. DLL end is indicated when Register 0x0E, Bit 4 and Bit 6 are set to 1b. In case of a DLL warning, action must be taken to prevent loss of lock. On a start warning, reduce the minimum delay of the delay line by removing one or several of the delay cells. This can be accomplished by setting the bits in Registers 0x70 and Register 0x71 to 0b. Begin by setting Bit 0 of Register 0x70 to 0b, then Bit 1, and so on. In some cases, up to three delay cells may need to be disabled. It is possible to disable up to six delay cells. However, in most cases, none of the cells need to be disabled. The situation varies, depending on the temperature range needed, as well as the DACCLK signal rate used. The end warning case is a theoretical possibility, but practical conditions normally dictate that it is not reachable. If the end warning is reached, the DLL must be relocked immediately. When doing initial lock (or relock) of the DLL, all delay cells must be active, with all delay cell bits in Register 0x70 and Register 0x71 set to 1b. Parity The data interface can be continuously monitored by enabling the parity bit feature in Register 0x5C, Bit 7, and configuring the FRM_P, FRM_N pins (Pin K13 and Pin K14) as parity pins by setting Register 0x07, Bits[1:0] = 1 dec. When this pin configuration is used, the host sends a parity bit along with each data sample. This bit is set according to the following formulas, where n is the data sample that is being checked. For even parity on the AD9129, XOR[FRM(n), P0_D0(n), P0_D1(n), P0_D2(n), ..., P0_D13(n), P1_D0(n), P1_D1(n), P1_D2(n), …, P1_D13(n)] = 0. For odd parity on the AD9129, XOR[FRM(n), P0_D0(n), P0_D1(n), P0_D2(n), ..., P0_D13(n), P1_D0(n), P1_D1(n), P1_D2(n), …, P1_D13(n)] = 1. Rev. 0 | Page 41 of 68 AD9119/AD9129 Data Sheet pin and more than one IRQ is enabled, check Register 0x06, Bits[3:2] when an IRQ event occurs to determine whether the IRQ was caused by a parity error. The IRQ can also be cleared by writing 1b to Register 0x06, Bit 2 or Register 0x06, Bit 3. For the AD9119, the data port is 11-bit instead of 14-bit, so P0_D11, P0_D12, P0_D13, P1_D11, P1_D12, and P1_D13 are not used in the calculation of the parity bit. Thus, the parity bit is calculated over 29 bits (including the frame/parity bit) for the AD9129 and over 23 bits for the AD9119. The parity bit feature can also be used to validate the interface timing. As described previously, the host provides a parity bit with the data samples and configures the AD9119/AD9129 to generate an IRQ. The user can then sweep the sampling instance of the AD9119/AD9129 input registers to determine at what point a sampling error occurs. If a parity error occurs, the parity error counter (Register 0x5D or Register 0x5E) is incremented. Parity errors on the bits that are sampled by the rising edge of DCI increment the parity rising edge error counter (Register 0x5D) and set the parity error rising edge bit (Register 0x5C, Bit 0). Parity errors on the bits that are sampled by the falling edge of DCI increment the parity falling edge error counter (Register 0x5E) and set the parity error falling edge bit (Register 0x5C, Bit 1). The parity counter continues to accumulate until it is cleared, or until it reaches a maximum value of 255. The count can be cleared by writing 1b to Register 0x5C, Bit 5. DIGITAL DATAPATH DESCRIPTION Figure 133 provides a more detailed diagram of the AD9119/ AD9129 digital datapath. The 22-bit/28-bit datapath with internal DDR clocking interfaces with the dual 11-bit/14-bit input data ports. Because two 11-bit/14-bit samples are captured on each clock edge of DCI, four consecutive samples are captured per DCI clock cycle. Samples captured on the rising edge of DCI propagate through the upper section at a rate of DACCLK/2 (DDR), and those captured on the falling edge propagate through the lower section. An IRQ can be enabled to trigger when a parity error occurs by writing 1b to Register 0x04, Bit 2 for rising edge-based parity detection or to Register 0x04, Bit 3 for falling edge-based parity. The status of IRQ can be measured via Register 0x06, Bit 2 or Register 0x06, Bit 3 or by using the IRQ pin. When using the IRQ 14 BITS FIFO PH0 REG 0 FIFO PH1 FRAME FRAME/ 1 PARITY REG 1 14 14 REG 2 TO DAC DECODE REG 3 REG 4 28 PARITY/ SED LOGIC 14 28 REG 5 14 FIFO PH2 FIFO PH3 14 DATA ASSEMBLER RD PTR RESET DLL DACCLK/4 REG 0 14 REG 1 REG 2 INPUT LATCH PARITY/ SED LOGIC 28 14 14 REG 3 REG 4 REG 5 REG 6 FRAME SPI FIFO ALIGN REQUEST REG 0x11[7] RD PTR RESET REG 7 WR PTR RESET 1 WR PTR RESET REG 7 DCI MIX-MODE 2× REG 6 RESET LOGIC DACCLK/4 DIST. SPI FIFO ALIGN ACKNOWLEDGE REG 0x11[6] FIFO WRITE POINTER OFFSET REG 0x12[2:0] Figure 133. Digital Datapath of the AD9119/AD9129 Rev. 0 | Page 42 of 68 DACCLK/4 11149-136 DATA INPUT LATCH Data Sheet AD9119/AD9129 FIFO Description The next functional block in the datapath is a set of four FIFOs that are eight registers deep. The dual port data is clocked into the FIFOs on both the rising and the falling edge of the DCI signal. The FIFO acts as a buffer that absorbs timing variations between the data source and DAC, such as the clock-to-data variation of an FPGA or ASIC. For the greatest timing margin, maintain the FIFO level near half full (that is, a difference of four between the write and read pointers). The value of the write pointer determines the FIFO register into which the input data is written, and the value of the read pointer determines the register from which data is read and fed into the data assembler. The write and read pointers are updated every time new data is loaded and removed, respectively, from the FIFO. Valid data is transmitted through the FIFO as long as the FIFO does not overflow or become empty. Note that an overflow or empty condition of the FIFO is the same as the write pointer and read pointer being equal. When both pointers are equal, an attempt is made to simultaneously read and write a single FIFO register. This simultaneous register access leads to unreliable data transfer through the FIFO and must be avoided by ensuring that data is written to the FIFO at the same rate that data is read from the FIFO, keeping the data level in the FIFO constant. This condition must be met by ensuring that DCI is equal to DACCLK/4 (or equivalently, DCO). Resetting the FIFO Data Level FIFO initialization is required to ensure a four-sample spacing and a deterministic pipeline latency. If the clocks are running at power-up, the FIFO initializes to 50% full. The AD9119/ AD9129 has an internal delay that effectively offsets the FIFO pointers by 2, such that the optimal FIFO data level of 4 (center) reads back as 2 (0000011b) from Register 0x13 to Register 0x16. To achieve this level, set Register 0x12 to 0x20 (hexadecimal) before resetting the FIFO. This sets the read pointer to Level 2 and the write pointer to Level 0. To maximize the timing margin between the DCI input and the internal DAC data rate clock, initialize the FIFO data level before beginning data transmission. The value of the FIFO data level can be initialized in three ways: by resetting the device, by strobing the FRM_x input, and via a write sequence to the serial port. The two preferred methods are use of the FRAME signal and via a write sequence to the serial port. Before initializing the FIFO data level, the LVDS DLL and the DAC clock PLL must be locked. The FRM_x input can be used to initialize the FIFO data level value. First, set up the FRM_N and FRM_P pins for frame mode (Register 0x07, Bits[1:0] = 2). Next, assert the FRAME signal high for at least one DCI clock cycle. When the FRAME signal is asserted in this manner, the write pointer is set to 4 (by default or to the FIFO start level (Register 0x12, Bits[2:0])) the next time the read pointer becomes 0 (see Figure 134). READ POINTER 0 1 2 3 5 6 7 0 1 2 3 4 5 6 7 FIFO WRITE RESETS FRAME WRITE POINTER 4 3 4 5 6 7 0 1 2 11149-137 After the input data has been captured, the data is passed through a logic block that monitors and/or determines the signal integrity of the high speed digital data interface. The optional parity check is used to continuously monitor the digital interface on a sampleper-sample basis, and the sample error detection (SED) can be used to validate the input data interface for system debug/test purposes. Note that the FRAME and PARITY signals share the same pin assignment because the FRAME signal is typically used during system initialization (for FIFO synchronization purposes), and parity is used in normal operation. Figure 134. Timing of the Frame Input vs. Write Pointer Value To initialize the FIFO data level through the serial port, toggle Bit 7 of Register 0x11 from 0b to 1b. When the write to the register is complete, the FIFO data level is initialized. The recommended procedure for a serial port FIFO data level initialization is as follows: 1. 2. 3. 4. Request FIFO level reset by setting Register 0x11, Bit 7, to 1b. Verify that the part acknowledges the request by ensuring that Register 0x11, Bit 6, is set to 1b. Remove the request by setting Register 0x11, Bit 7, to 0b. Verify that the part drops the acknowledge signal by ensuring that Register 0x11, Bit 6, is set to 0b. Monitoring the FIFO Status The relative FIFO data levels can be read from Register 0x13 through Register 0x16 at any time. The FIFO data level reported by the serial port is denoted as a 7-bit thermometer code of the write counter state, relative to the absolute read counter being at 0. For example, the FIFO data level of 2 is reported as a value of 0000011b in the status register. Adding the internal delay of 2 to this value makes the reported FIFO level equal to 4. It should be noted that, depending on the timing relationship between DCI and the main DACCLK signal, the FIFO level value can be off by a count of ±1. Therefore, it is important that the difference between the read and write pointers be maintained at ≥2. Multiple DAC Synchronization Synchronization of multiple AD9119/AD9129s implies that all of the DAC outputs are time aligned to the same phase when all devices are fed with the same data pattern (along with DCI) at the same instance of time. FIFO initialization ensures that the initial pipeline latency in the FIFO is set to four samples and remains at this level, assuming that no process, voltage, or temperature variations occur between the host and the AD9119/ AD9129 clock domains. Rev. 0 | Page 43 of 68 AD9119/AD9129 Data Sheet provide a DACCLK/8 signal. Using the SYNC output from each DAC, enabled by Register 0x1A, Bit 4 = 1, the user can create a simple phase detector with an external XOR gate. DAC 1 Even after FIFO initialization, a phase ambiguity exists between the read pointers of each device because the read counter of each device powers up in an arbitrary state. Therefore, the exact instance when the respective write pointer is set to 4, after the FRAME signal is asserted, also remains ambiguous. It is possible for the read pointer of one device to reach its 0 count several clock cycles before another device (see Figure 134). Synchronization within a data sample requires insight into the difference between the read pointers of the master and slave devices, as well as the ability to vary the delay of the slave device(s) within the host to compensate for initial offsets between devices. It is possible to calculate how many data samples the slave device(s) is offset from the master device for the following reasons: • • • The pipeline delay of each device is the same after FIFO initialization. The read counter of each device is derived from the same phase aligned DACCLK source. The state of the read counters of each device is sampled at the same instance in time via the FRAME signal. The readback value (Register 0x12[6:4]) is normalized to a data sample (that is, a DACCLK period). By calculating the difference between the read pointer settings of the master and slave devices, the user can advance or delay the data stream of the slave device within the FPGA. Because this difference can be up to ±4 data samples, the FPGA must provide this adjustment range for DAC synchronization alone. Note that additional range must be added to compensate for any other system delay variation. In addition to synchronizing to the data sample level, the AD9119/ AD9129 can enable synchronization to the DACCLK level (see Figure 135). A 1.8 V CMOS output pin, SYNC, can be used to XOR DAC 2 SYNC Figure 135. Example of Synchronization of Two DACs to ±1 DACCLK Accuracy By adjusting the internal delay (incrementing or decrementing by one DACCLK cycle with each write to Register 0x1A, Bit 7 or Bit 6, respectively), the user can align the DACCLKs inside the two DACs to within ±1 DACCLK cycle, when errors from the external phase detector, low-pass filter, and delay differences are taken into account. The existing phase position can be read from Register 0x1A, Bits[2:0]. Align the SYNC outputs first, then reset the FIFOs on each DAC to ensure that proper sync is achieved. This calibration must be performed at each power-up because the FIFOs can be reset to any of four levels based on the divideby-4 output of the clock distribution block (see Figure 133). For example, a FIFO reset to Level 2 could have an actual FIFO level of 1.5, 1.75, 2, or 2.25, based on the location of the div-by-4 clock edge. Adjusting the SYNC signals to align with each other eliminates this ambiguity. When the two DACs are aligned, the drift over temperature and supply voltage of the DACCLK signal of one DAC, relative to another DAC, is expected to be no more than 450 ps. The DCO signal is derived from the SYNC signal such that if the SYNC signal is adjusted by a DACCLK cycle, the DCO signal must also be adjusted by the same amount. When all adjustments of the SYNC signal are complete, it is recommended to disable the SYNC output by programming Register 0x1A, Bit 4 = 0, to eliminate a possible source of clock spurious signals. MATCHED DELAYS COMMON CLOCK SOURCE 1.4GHz TO 2.8GHz 0+ dBm DCI ADCLK925 DCO_x DACCLK AD9129 MASTER DCI_x FRM_x 0+ dBm FPGA DCI_x DACCLK FRM_x AD9129 SLAVE DCO_x Figure 136. Example of Synchronization of Two DACs to One FPGA Rev. 0 | Page 44 of 68 11149-138 • SYNC 11149-139 Figure 136 shows an example of two AD9119/AD9129 devices that are synchronized to the same host (that is, FPGA and ASIC). Note that, when the same resources are used to generate these output signals, synchronization to a single host IC ensures minimum data and DCI time skew between devices. Data Sheet AD9119/AD9129 5 Data Assembler and Signal Processing Modes There are two different filters, FIR25 and FIR40, that can be chosen using Register 0x18, Bit 5, when the 2× interpolator is enabled with Register 0x18, Bit 7. The FIR25 half-band filter provides 25 dB of stop-band rejection. Its response is shown in Figure 137. Coefficients were optimized for practical implementation purposes with the notion that the ±0.5 dB pass-band ripple effects on a multicarrier application (for example, DOCSIS) can be compensated by the digital host adjusting individual channel powers. Note that the worst-case tilt across any 6 MHz channel is less than −0.05 dB. The FIR40 half-band filter provides 40 dB of stop-band rejection, and its response is shown in Figure 139. Coefficients were chosen to reduce pass-band ripple and increase out-of-band rejection for multicarrier applications (for example, DOCSIS). As a result, the frequency response has a flatter in-band response and a sharper transition region, and the trade-off is a higher phase count, leading to higher pipeline delay and higher power consumption. The two filters are compared in Table 12. –20 –25 –30 –35 –40 500 1000 1500 2000 2500 FREQUENCY (MHz) 11149-140 0 Figure 137. FIR25 2× Interpolation Filter Plot, Complete Frequency Response; fDAC = 2.5 GHz 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 200 400 600 800 1000 1200 FREQUENCY (MHz) 11149-141 The AD9119/AD9129 include a bypassable 2× half-band interpolation filter to help simplify the analog reconstruction filter. The filter has the potential benefit of minimizing the impact of folded back harmonics in the desired baseband region. The filter operates in a dual-edge clocking mode, where it generates a new interpolated sample value for every alternate DACCLK edge. This effectively increases the DAC update rate to 2 × fDACCLK with the DAC’s sinc response null moving from fDACCLK to 2 × fDACCLK. –15 –50 MAGNITUDE (Normalized to 0dB) 2× Digital Filter –10 –45 Figure 138. FIR25 2× Interpolation Filter Plot, Pass-Band Ripple; fDAC = 2.5 GHz 5 0 –5 –10 MAGNITUDE (dB) The data assembler reconstructs the original sample sequence. It consists of a 4:1 multiplexer operating at fDACCLK. Each of the four FIFOs provides a sample that is now referenced to the internal clock domain of the AD9119/AD9129, fDACCLK. The reconstructed sample sequence can be directed to the DAC decode logic or undergo additional signal processing. In 2× interpolation mode, a FIR filter is used to generate a new data sample that is inserted between each sample, such that it can update the DAC decode logic on the falling edge of DACCLK. In Mix-Mode, the complement of each data sample is generated and inserted after it, such that it also updates the DAC in a similar manner. The 2× interpolator can be used with Mix-Mode enabled. MAGNITUDE (Normalized to 0dB) 0 –5 –15 –20 –25 –30 –35 –40 –45 –50 Table 12. Features of the Two 2× Interpolation Filters Ripple (dB) ±0.5 ±0.1 Attenuation (dB) 25 40 –55 Power (mW) 150 450 –60 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NORMALIZED FREQUENCY (×π RAD/Sample) 0.9 1.0 11149-142 Filter FIR25 FIR40 Figure 139. FIR40 2× Interpolation Filter Plot, Complete Frequency Response A duty cycle restore circuit follows the DACCLK clock receiver to minimize impact of duty cycle errors on image rejection. Rev. 0 | Page 45 of 68 AD9119/AD9129 Data Sheet 1.0 To ensure repeatable pipeline delay over multiple power-up cycles, the SYNC output of the DAC must be aligned with a known system sync reference. Follow a calibration process that is similar to the multiple DAC sync process (see the Multiple DAC Synchronization section for more information) after each power-up event to align the DAC to the system sync reference. 0.5 MAGNITUDE (dB) 0 –0.5 –1.0 Power-Up Time –1.5 The AD9119/AD9129 have a power-down register (Register 0x01) that enables the user to power down various portions of the DAC. The power-up time for several usage cases is shown in Table 14. –2.0 –3.0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 NORMALIZED FREQUENCY (×π RAD/Sample) 11149-143 –2.5 Figure 140. FIR40 2× Interpolation Filter Plot, Pass-Band Ripple Pipeline Delay (Latency) Table 14. Power-Up Times for Several Usage Cases The pipeline delay, or latency, of the AD9129 varies, based on the configuration that is chosen and can be calculated using the following formula: Pipeline_Total = Pipeline_Delay + 2×_Delay + Group_Delay + FIFO_Level Mode No 2× filter With FIR25 With FIR40 Total Pipeline (fDAC cycles) 74 117 141 Total Delay (fDAC cycles) 74 119 150 The terms used in Table 13 are defined as follows: Register State From 0x01 = 0xEF to 0x01 = 0x08 From 0x01 = 0x0C to 0x01 = 0x08 From 0x01 = 0x48 to 0x01 = 0x08 Time (μs) 250 220 2 The AD9119/AD9129 can provide the host processor with an interrupt request output signal (IRQ), indicating that one or more of the following events has occurred: Table 13. Pipeline Delay Values for Each Block Group Delay (fDAC cycles) N/A 2 9 State Power-Up Clock Path Up Wake-Up INTERRUPT REQUESTS The values listed in Table 13 can be used, depending on the mode of operation that is selected. Pipeline Delay (fDAC cycles) 74 43 67 The recommended way to power up the AD9119/AD9129 is to power up all parts of the circuit with IREF disabled (by setting Register 0x01, Bit 6 = 1b), and then enable IREF by programming Register 0x01, Bit 6 = 0b. Pipeline delay is the time from DAC code latched until the DAC output begins to move. Group delay is the time for the maximum amplitude pulse to reach the DAC output, as compared to the first time the output moves. No 2× filter is the base pipeline delay, including data interface, analog circuitry (six cycles), and data FIFO at half-full/Position 3. FIR25 is the 2× interpolator with 25 dB of out-of-band rejection. FIR40 is the 2× interpolator with 40 dB of out-of-band rejection. Note that the values for pipeline delay apply in both normal mode and Mix-Mode. After the total delay through the digital blocks is calculated, add the FIFO level to that delay to find the total pipeline delay. Note that the pipeline delay can be considered fixed, with the only ambiguity being the FIFO state. The FIFO state can be initialized as part of the startup sequence to ensure a four sample spacing and, therefore, a fixed pipeline delay, or deterministic latency (see the Resetting the FIFO Data Level section for more information). One of the clock controllers has established or lost lock. A parity error has occurred. A sample error detection status or result is ready. The FIFO is nearing an overwrite status. The IRQ output signal is an active low output signal that is available on the IRQ pin (Pin H2). If used, connect the output to VDD via a 10 kΩ pull-up resistor. Each IRQ is enabled by setting the enable bits in Register 0x03 and Register 0x04 that have the same bit mapping as the IRQ status bits in Registers 0x05 and Register 0x06. If an interrupt bit is not enabled, a read request of that bit shows a direct readback of the current state of the source. Thus, a read request of either register shows the current state of all eight interrupts in that register, regardless of whether each individual bit is actually enabled to generate an interrupt. When an interrupt bit is enabled, it captures a rising edge of the interrupt source and holds it, even if the source subsequently returns to its zero state. It is possible, for example, for the retimer lost interrupt enable and retimer lock interrupt enable status bits (Register 0x03[1:0], respectively) to be set when a controller temporarily loses lock but then reestablishes lock before the IRQ is serviced by the host. In such a case, the host should validate the present status of the suspect block by reading back its current status bits. Based on the status of these bits, the host can take appropriate action, if required. Rev. 0 | Page 46 of 68 Data Sheet AD9119/AD9129 interrupt enable bit (Register 0x03[0]) can be set, and the IRQ output signal can be monitored to determine when lock is established, before continuing in a similar manner with the data receiver controller. Clear the relevant lock bit, after locking, before continuing to the next controller. When all of the controllers are locked, set the appropriate lost lock enable bits in Register 0x03 to continuously monitor the controllers for loss of lock. The IRQ pin responds only to those interrupts that are enabled. To clear an IRQ, it is necessary to write a 1b to the bit in Register 0x05 or Register 0x06 that caused the interrupt. See Figure 141 for a detailed diagram of the interrupt circuitry. The IRQ can also be used during the AD9119/AD9129 initialization phase after power-up to determine when the retimer PLL and data receiver controllers achieve lock. For example, before enabling the retimer PLL, the retimer lock WRITE 1b TO REQUEST BIT SINGLE IRQ BIT R SOURCE IRQ ENABLE IRQ PIN Q IRQ REQUEST IRQ ENABLE 11149-144 D OTHER IRQ BITS IRQ ENABLE Figure 141. Interrupt Request Circuitry Table 15. Interrupt Request Registers Addr (Hex) 0x05 0x06 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Bit Name FIFO_Warn2 interrupt status FIFO_Warn1 interrupt status SPIFrmAck interrupt status Reserved DLL warn interrupt status DLL lock interrupt status Retimer lost interrupt status Retimer lock interrupt status Reserved AED pass interrupt status AED fail interrupt status SED fail interrupt status Parity error falling edge status Parity error rising edge status Reserved Reserved Description Indicates that the FIFO is within two slots of overwrite Indicates that the FIFO is within one slot of overwrite Indicates acknowledgement that the SFrmReq bit has changed from 0b to 1b Reserved Indicates that the DLL is close to coming unlocked and action is needed Indicates that the DLL is now locked Indicates that the retimer PLL is no longer locked Indicates that the retimer PLL is now locked Reserved Indicates that the AED logic has captured eight valid samples Indicates that the AED logic has detected a miscompare Indicates that the SED logic has detected a miscompare Indicates a parity fault due to data captured on the falling edge Indicates a parity fault due to data captured on the rising edge Reserved Reserved Rev. 0 | Page 47 of 68 AD9119/AD9129 Data Sheet INTERFACE TIMING VALIDATION The AD9119/AD9129 provide on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED compares the input data samples captured at the digital input pins with a set of comparison values. The comparison values are loaded into registers through the SPI port. Differences between the captured values and the comparison values are detected and stored. The compare pass bit is set if the last comparison indicates that the sample is error free. The compare fail bit is set if an error is detected. The compare fail bit is automatically cleared by the reception of eight consecutive error-free comparisons. When autoclear mode is enabled, Register 0x51 through Register 0x58 accumulate errors as previously described but reset to all 0s after eight consecutive error-free sample comparisons are made. SAMPLE ERROR DETECTION (SED) OPERATION The sample error, compare pass, and compare fail flags can be configured to trigger an IRQ when active, if desired. This is accomplished by enabling the appropriate bits in the event flag register (Register 0x06, Bit 4, Bit 5, and Bit 6). The SED circuitry operates on a data set made up of eight 11-bit/14-bit input words, denoted as R0L, R1L, R0H, R1H, F0L, F1L, F0H, and F1H. These represent the rising edge and falling edge data of Data Port 0 and Data Port 1. (The AD9119/ AD9129 use both edges of the DCI clock to sample data on each input port.) To properly align the input samples, the rising edge data-words of the data ports (that is, RxL and RxH) are indicated by asserting the FRAME signal for a minimum of two complete input samples. Figure 142 shows the input timing of the interface in word mode. The FRAME signal can be issued once at the start of the data transmission, or it can be asserted repeatedly at intervals coinciding with the RxL and RxH data-words. SED EXAMPLE Normal Operation The following example illustrates the SED configuration for continuously monitoring the input data and assertion of an IRQ when a single error is detected. 1. DCI P0[7:0] R0L F0L P0[13:8] R0H F0H P1[7:0] R1L F1L P1[13:8] R1H F1H 11149-249 FRAME 2. Figure 142. Timing Diagram of FRAME Signal Required to Align Input Data for SED The SED has three flag bits (Register 0x50, Bit 0, Bit 1, and Bit 2) that indicate the results of the input sample comparisons. The SED fail bit (Register 0x50, Bit 0) is set when an error is detected and remains set until cleared. The SED also provides registers that indicate which input data bits experienced errors (Register 0x51 through Register 0x58). These bits are latched and indicate the accumulated errors detected until cleared. To clear the SED registers, write 1b to Register 0x50, Bit 6. The autosample error detection (AED) mode is an autoclear mode that has the following two effects: • • 3. 4. Write to the following registers to load the comparison values: a) Register 0x51: SED Patt/Err R0L, Bits[7:0]. b) Register 0x52: SED Patt/Err R0H, Bits[13:8]. c) Register 0x53: SED Patt/Err R1L, Bits[7:0]. d) Register 0x54: SED Patt/Err R1H, Bits[13:8]. e) Register 0x55: SED Patt/Err F0L, Bits[7:0]. f) Register 0x56: SED Patt/Err F0H, Bits[13:8]. g) Register 0x57: SED Patt/Err F1L, Bits[7:0]. h) Register 0x58: SED Patt/Err F1H, Bits[13:8]. i) Comparison values can be chosen arbitrarily; however, choosing values that require frequent bit toggling provides the most robust test. Enable the SED error detect flag to assert the IRQ pin. a) Register 0x04: set to 0x10. Begin transmitting the input data pattern. Write three times to Register 0x50 to enable the SED. a) Register 0x50: set to 0x80. b) Register 0x50: set to 0xC0. c) Register 0x50: set to 0x80. If IRQ is asserted, read Register 0x50 and Register 0x51 through Register 0x58 to verify that a SED error is detected and determine which input bits are in error. The bits in Register 0x51 through Register 0x58 are latched. This means that the bits indicate any errors that occur on those bits throughout the test and not just the errors that caused the error detected flag to be set. AED mode activates the AED fail bit and the AED pass bit (Register 0x50, Bit 1 and Bit 2). AED mode changes the behavior of Register 0x51 through Register 0x58. Rev. 0 | Page 48 of 68 Data Sheet AD9119/AD9129 ANALOG INTERFACE CONSIDERATIONS The AD9119/AD9129 use the quad-switch architecture shown in Figure 143. Only one pair of switches is enabled during a half-clock cycle, thus requiring each pair to be clocked on alternative clock edges. A key benefit of the quad-switch architecture is that it masks the code-dependent glitches that occur in the conventional twoswitch DAC architecture. When Mix-Mode is used, the output is effectively chopped at the DAC sample rate. This has the effect of reducing the power of the fundamental signal while increasing the power of the images centered around the DAC sample rate, thus improving the dynamic range of these images. INPUT DATA D1 D2 D3 D4 D5 D6 D8 D7 DACCLK_x D3 DACCLK_x CLK IOUTP V G1 IOUTN –D7 D5 D1 LATCHES V 3 G Px_D[13:0]x –D8 D4 D2 VG 2 VG1 VG2 VG3 FOUR-SWITCH DAC OUTPUT (fS MIX-MODE) VG4 D10 D9 –D9 –D10 –D6 t V G4 D10 –D5 D6 –D1 –D2 –D4 D9 D7 –D3 11149-148 ANALOG MODES OF OPERATION D8 11149-146 Figure 145. Mix-Mode Waveform VSSA Figure 143. Quad-Switch Architecture In two-switch architecture, when a switch transition occurs and D1 and D2 are in different states, a glitch occurs. But, if D1 and D2 happen to be at the same state, the switch transitions, and no glitches occur. This code-dependent glitching causes an increased amount of distortion in the DAC. In quad-switch architecture (no matter what the codes are), there are always two switches that are transitioning at each half-clock cycle, thus eliminating the code-dependent glitches but, in the process, creating a constant glitch at 2 × DACCLK. For this reason, a significant clock spur at 2 × fDACCLK is evident in the DAC output spectrum. INPUT DATA D1 D2 D3 D4 D5 D6 D7 D8 D9 This ability to change modes provides the user the flexibility to place a carrier anywhere in the first three Nyquist zones, depending on the operating mode selected. Switching between baseband and Mix-Mode reshapes the sinc roll-off inherent at the DAC output. In baseband mode, the sinc null appears at fDACCLK because the same sample latched on the rising clock edge is also latched again on the falling clock edge, thus resulting in the same ubiquitous sinc response of a traditional DAC. In MixMode, the complement sample of the rising edge is latched on the falling edge, therefore pushing the sinc null to 2 × fDACCLK. Figure 146 shows the ideal frequency response of both modes with the sinc roll-off included. FIRST NYQUIST ZONE D10 SECOND NYQUIST ZONE 0 THIRD NYQUIST ZONE MIX-MODE DACCLK_x –5 D1 D2 D3 D4 D5 –10 t D6 D7 D8 D9 D10 dBFS TWO-SWITCH DAC OUTPUT –15 BASEBAND MODE –20 D6 D2 D3 D4 D7 D8 D9 D10 t D5 –25 11149-147 FOUR-SWITCH DAC OUTPUT (NORMAL MODE) D1 –30 Figure 144. Two-Switch and Quad-Switch DAC Waveforms –35 0 0.25 0.50 0.75 1.00 1.25 NORMALIZED FREQUENCY RELATIVE TO fDACCLK (Hz) 1.50 11149-149 As a consequence of the quad-switch architecture enabling updates on each half-clock cycle, it is possible to operate that DAC core at 2× the DACCLK rate if new data samples are latched into the DAC core on both the rising and falling edge of the DACCLK. This notion serves as the basis when operating the AD9119/AD9129 in either Mix-Mode or with the 2× interpolation filter enabled. In each case, the DAC core is presented with new data samples on each clock edge, albeit in Mix-Mode; the falling edge sample is simply the complement of the rising edge sample value. Figure 146. Sinc Roll-Off for Baseband Mode and Mix-Mode Operation The quad-switch can be configured via SPI (Register 0x19, Bit 0) to operate in either baseband mode (0b) or Mix-Mode (1b). Rev. 0 | Page 49 of 68 AD9119/AD9129 Data Sheet CLOCK INPUT The AD9119/AD9129 contain a low jitter, differential clock receiver that is capable of interfacing directly to a differential or single-ended clock source. Because the input is self-biased to a nominal midsupply voltage of 1.25 V with a nominal impedance of 10 kΩ//2 pF, it is recommended that the clock source be ac-coupled to the DACCLK_x input pins with an external differential load of 100 Ω. When the nominal differential input span is 1 V p-p, the clock receiver can operate with a span that ranges from 250 mV p-p to 2.0 V p-p. TO DAC AND DLL DACCLK_P DUTY CYCLE RESTORER DACCLK_N 5kΩ 1.25V 11149-150 25µA 50kΩ Figure 147. Clock Input The quality of the clock source, as well as its interface to the AD9119/AD9129 clock input, directly impacts ac performance. Select the phase noise and spur characteristics of the clock source to meet the target application requirements. Phase noise and spurs at a given frequency offset on the clock source are directly translated to the output signal. It can be shown that the phase noise characteristics of a reconstructed output sine wave are related to the clock source by 20 × log10 (fOUT/fCLK) when the DAC clock path contribution is negligible. (The wideband noise is not dominated by the thermal and quantization noise of the DAC.) Figure 148 shows a clock source based on the ADF4350 low phase noise/jitter PLL. The ADF4350 can provide output frequencies from 140 MHz up to 4.4 GHz with jitter as low as 0.5 ps rms. Its squared-up output level can be varied from −4 dBm to +5 dBm, allowing further optimization of the clock drive level. PLL The DACCLK_x input goes to a high frequency PLL to ensure robust locking of the DAC sample clock to the input clock. The PLL is enabled by default such that the PLL locks upon power-up. The PLL (or DAC clock retimer) control registers are located at Register 0x33 and Register 0x34. Register 0x33 enables the user to set the phase detector phase offset level (Bits[7:4]), clear the PLL lost lock status bit (Bit 3), choose the PLL divider for optimum performance (Bit 2), and choose the phase detector mode (Bits[1:0]). These settings are determined during product characterization and are given in the recommended start-up sequence (see the Start-Up Sequence section). It is not normally necessary to change these values, nor is the product characterization data valid on any settings other than the recommended ones. Register 0x34 is used to reset the PLL, should that become necessary. At DACCLK = 2.8 GSPS, the lock time is about 10 µs. In most situations, no action is required with the PLL. If the DACCLK is changed and, especially, if it is changed multiple times, as in a frequency hopping application, a phase slip or glitch may be caused by the change in frequency, and it may become necessary to reset the PLL. This can be checked by reading the PLL retimer lost lock bit (Register 0x35, Bit 6). If that is the case, toggle the PLL reset bit by programming Register 0x34, Bit 3, high and then low. In addition, clear the PLL retimer lost lock bit by writing 0b to Register 0x35, Bit 6. PLL lock can be verified by reading the PLL lock bit at Register 0x35, Bit 7. It is possible to use the IRQ registers to set an interrupt for these events. See the Interrupt Requests section for more details. AD9129 ADF4350 2.4nF DACCLK_P PLL fREF VCO DIV-BY-2N N=0–4 2.4nF 100Ω DACCLK_N 0.8GHz TO 2.8GHz 1V p-p Figure 148. Possible Signal Chain for DACCLK_x Input Rev. 0 | Page 50 of 68 11149-151 5kΩ A clock control register exists at Address 0x30. This register can be used to enable automatic duty cycle correction (Bit 1), enable zero-crossing control (Bit 6), and set the zero-crossing point (Bits[5:2]). Recommended settings for this register are listed in the recommended start-up sequence section (see the Start-Up Sequence section). Data Sheet AD9119/AD9129 VOLTAGE REFERENCE IOUTFS = 9.5mA – 34mA The AD9119/AD9129 output current is set by a combination of digital control bits and the I250U reference current, as shown in Figure 149. (9/17) × IOUTFS IPEAK = (8/17) × IOUTFS AC AD9129 FSC[9:0] – + 4kΩ VSSA CURRENT SCALING Figure 150. Equivalent DAC Output Circuit IFULLSCALE I250 Figure 149. Voltage Reference Circuit The reference current is obtained by forcing the band gap voltage across an external 4.0 kΩ resistor from I250U (Pin A1) to ground. The 1.0 V nominal band gap voltage (VREF) generates a 250 µA reference current in the 4.0 kΩ resistor. Note the following constraints when configuring the voltage reference circuit: • • • • • Both the 4.0 kΩ resistor and 1 nF bypass capacitor are required for proper operation. Adjusting the DAC output full-scale current, IOUTFS, from its default setting of 20 mA should be performed digitally. The AD9119/AD9129 are not multiplying DACs. Modulation of the reference current, I250U, with an ac signal is not supported. The band gap voltage appearing at the VREF pin must be buffered for use with an external circuitry because its output impedance is approximately 7.5 kΩ. An external reference can be used to overdrive the internal reference by connecting it to the VREF pin. As mentioned, the IOUTFS can be adjusted digitally over a 9.4 mA to 34.2 mA range by the FSC_x[9:0] bits (Register 0x20, Bits[7:0] and Register 0x21, Bits[1:0]). The following equation relates IOUTFS to the FSC_x[9:0] bits, which can be set from 0 to 1023. IOUTFS = 24.21875 mA × FSC_x[9:0]/1000 + 9.4 mA The example shown in Figure 150 can be modeled as a pair of dc current sources that source a current of 9/17 × IOUTFS to each output. A differential ac current source, IPEAK, is used to model the signal (that is, a digital code) dependent nature of the DAC output. The polarity and signal dependency of this ac current source is related to the digital code (F) by the following equation: ANALOG OUTPUTS Equivalent DAC Output and Transfer Function The AD9119/AD9129 provide complementary current outputs, IOUTP and IOUTN, that sink current from an external load that is referenced to the 1.8 V VDDA supply. Figure 150 shows an equivalent output circuit for the DAC. Compared to most current output DACs of this type, the outputs of the AD9119/ AD9129 exhibit a slight offset current (that is, IOUTFS/17), and the peak differential ac current is slightly below IOUTFS/2 (that is, 8/17 × IOUTFS). (2) −1 < F (code) < +1 (3) Because IPEAK can swing ±(8/17) × IOUTFS, the output currents that are measured at IOUTP and IOUTN can span from IOUTFS/17 to IOUTFS. However, because the ac signal-dependent current component is complementary, the sum of the two outputs is always constant (that is, IOUTP + IOUTN = (18/17) × IOUTFS). The code-dependent current that is measured at the IOUTP (and IOUTN) output is as follows: IOUTP = (9/17) × IOUTFS (mA) + (8/17) × IOUTFS (mA) × F (code) (4) IOUTN = (9/17) × IOUTFS (mA) − (8/17) × IOUTFS (mA) × F (code) Figure 151 shows the IOUTP vs. DACCODE transfer function when IOUTFS is set to 19.65 mA. 20 18 (1) Note that the default value of 0x200 generates 21.937 mA full scale, but most of the characterization presented in this datasheet uses 33 mA, unless noted otherwise. F (code) = (DACCODE − 8192)/8192 where DACCODE = 0 to 16,383 (decimal). 16 OUTPUT CURRENT (mA) I250U 11149-153 1nF 11149-154 VREF (9/17) × IOUTFS DAC Rev. 0 | Page 51 of 68 14 12 10 8 6 4 2 0 0 4096 8192 DAC CODE 12,288 16,384 11149-155 VBG 1.0V Figure 151. Gain Curve for FSC_x[9:0] = 512, DAC Offset = 1.228 mA AD9119/AD9129 Data Sheet The maximum peak power capability of a differential current output DAC is dependent on its peak differential ac current, IPEAK, and the equivalent load resistance it sees. In the case of a 1:1 balun with 50 Ω source termination, the equivalent load that is seen by the DAC ac current source is 25 Ω. If the AD9119/ AD9129 is programmed for an IOUTFS = 20 mA, its peak ac current is 9.375 mA and its peak power, delivered to the equivalent load, is 2.2 mW (that is, P = I2R). Because the source and load resistance seen by the 1:1 balun are equal, this power is shared equally. Hence, the output load receives 1.1 mW, or 0.4 dBm peak power. Figure 152 shows the AD9119/AD9129 interfacing to the JTX-210T transformer. This transformer provides excellent amplitude/ phase balance (that is, <1 dB/1°) up to 1 GHz while providing a 0 Ω D dc bias path to VDDA. If filtering of the DAC images and clock components is required, applying an analog LC filter on the single-ended side has the advantage of preserving the balance of the transformer. JTX-2-10T+ MINI-CIRCUITS IOUTP VDDA 50Ω To calculate the rms power delivered to the load, consider the following: IOUTN Figure 152. Recommended Transformer for Wideband Applications with Upper Bandwidths of up to 2.2 GHz Peak-to-rms of digital waveform Any digital backoff from digital full scale DAC sinc response and nonideal losses in the external network For example, a reconstructed sine wave with no digital backoff ideally measures −2.6 dBm because it has a peak-to-rms ratio of 3 dB. If a typical balun loss of 0.4 dBm is included, the user would expect to measure −3 dBm of actual power in the region where the sinc response of the DAC has negligible influence. Increasing the output power is best accomplished by increasing IOUTFS. Figure 153 shows an interface that can be considered when interfacing the DAC output to a self-biased differential gain block. The inductors (L) shown serve as RF chokes that provide the dc bias path to AGND. Its value, along with the dc blocking capacitors, determines the lower cut-off frequency of the composite pass-band response. (The dc blocking capacitors form a high-pass response with the input resistance of the RF differential gain stage.) C Output Stage Configuration IOUTP The AD9119/AD9129 are intended to serve high dynamic range applications that require wide signal reconstruction bandwidth (that is, a DOCSIS cable modem termination system (CMTS)) and/or high IF/RF signal generation. Optimum ac performance can be realized only if the DAC output is configured for differential (that is, balanced) operation with its output common-mode voltage biased to a stable, low noise 1.8 V nominal analog supply (VDDA). The ADP150 LDO can be used to generate a clean 1.8 V supply. The output network used to interface to the DAC should provide a near 0 Ω dc bias path to VDDA. Any imbalance in the output impedance over frequency between the IOUTP and IOUTN pins degrades the distortion performance (mostly even order) and noise performance. Component selection and layout are critical in realizing the performance potential of the AD9119/AD9129. L 100Ω VDDA L RF DIFF_ AMP C IOUTN 11149-157 • • • 2:1 50Ω 11149-156 Peak DAC Output Power Capability Figure 153. Interfacing the DAC Output to Self-Biased, Differential Gain Stage Many RF differential amplifiers consist of two single-ended amplifiers with matched gain, thus providing no common-mode rejection while possibly degrading the balance, due to poor matching characteristics. Also, depending on the component tolerances, differential LC filters can further degrade the balance in a differential signal path. In both cases, the use of a balun could be advantageous in rejecting the common-mode distortion and noise components from the RF DAC prior to filtering or further amplification. Most applications that require balanced-to-unbalanced conversion from 10 MHz to 1 GHz can take advantage of the Mini-Circuits JTX series of transformers that offer impedance ratios of both 2:1 and 1:1. Rev. 0 | Page 52 of 68 Data Sheet AD9119/AD9129 For applications that operate the AD9119/AD9129 in Mix-Mode with output frequencies extending beyond 2.2 GHz, the user may want to consider the circuit shown in Figure 154. This circuit uses a wideband balun (for example, −3 dB at 4.0 GHz), with a configuration that is similar to the example shown in Figure 152, to provide a dc bias path for the DAC outputs. This circuit was implemented on an evaluation board, and the frequency response was measured to compare it with the ideal curve in Figure 146. The result is shown in Figure 155. C IOUTP L 50Ω L 50Ω MINI-CIRCUITS TCI-1-13M+ TCI-1-33M+ To assist in matching the AD9119/AD9129 output, a Smith chart is provided in Figure 156. The plot was taken using the circuit in Figure 154, with the balun and the coupling capacitors removed, and L = 270 nH. For the measured vs. ideal response of the DAC output, see Figure 155, which illustrates that a nonideal response occurs in the second half of the second Nyquist zone. This area corresponds to the low impedance area between 2 GHz and 3 GHz, as shown in the Smith chart in Figure 156. Output matching can be used to compensate for this nonideal response; the possible reduction in signal bandwidth must be considered if such matching is used. 11149-158 VDDA IOUTN C Figure 154. Recommended Mix-Mode Configuration Offering Extended RF Bandwidth Using TC1-1-13M+ Balun 4 1 3 NORMAL MODE MIX-MODE MEASURED NORMAL MEASURED MIX-MODE 0 –3 3 –6 2 –12 –15 –18 –21 –24 1. 2. 3. 4. –27 –30 –36 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 FREQUENCY (MHz) 11149-257 –33 300kHz 1GHz 2GHz 3GHz 3.1341Ω 54.333Ω 13.113Ω 13.022Ω 710.55mΩ –44.210Ω –11.207Ω –14.259Ω 376.96nH 3.5999pF 7.1006pH 756.48pF 11149-256 POWER (dBc) –9 Figure 156. Measured Smith Chart Showing the DAC Output Impedance; fDAC = 2.6 GSPS Figure 155. Measured vs. Ideal DAC Output Response; fDAC = 2.6 GSPS Rev. 0 | Page 53 of 68 AD9119/AD9129 Data Sheet START-UP SEQUENCE A small number of steps is required to program the AD9119/AD9129 to the proper operating state after the device is powered up. This sequence is listed in Table 16, along with an explanation of the purpose of each step. Table 16. Start-Up Sequence After Power-Up Register 0x00 0x30 0x0C 0x0B 0x01 0x34 0x01 0x33 0x33 Value 0x00 0x5C 0x64 0x39 0x68 0x6D or 0x5D 0x48 0x13 0xF8 or 0xD8 0x33 0x0D 0x0A 0x18 0x20 0x21 0x30 0x12 0x11 0x11 0x01 0xF0 or 0xD0 0x06 0xC0 0xm0 0xC6 0x03 0x46 0x20 0x81 0x01 0x00 Description 4-wire SPI, MSB-first packing, short addressing mode Enable cross control, cross location = 7 dec, duty cycle correction off Set DLL minimum delay = 4 dec, enable DCO Set clock divider to DCI/512 Set bias power-down Set PLL mode for normal or 2× mode; normal mode or FIR25 on = 0x6D, FIR40 on = 0x5D Enable bias Initialize PLL to phase step = 1 dec Select PFD, set PLL phase step, keep PLL lost bit cleared; phase step is as follows: normal mode or FIR25 on = 0xF8, FIR40 on = 0xD8 Deassert the PLL lost bit, keeping the phase step; normal mode or FIR25 on = 0xF0, FIR40 on = 0xD0 Set duty correction bandwidth to lowest Enable DLL Select data mode, filter mode to set value of m; for example: 0x40, unsigned data, interpolator off Set full-scale current (FSC) to 33 mA Complete the setting of FSC Enable cross control, cross location = 1 dec, enable duty cycle correction Set the FIFO pointers Assert FIFO reset Deassert FIFO reset Enable IREF (DAC output) Rev. 0 | Page 54 of 68 Data Sheet AD9119/AD9129 DEVICE CONFIGURATION REGISTERS DEVICE CONFIGURATION REGISTER MAP The blank bits in Table 17 are reserved and should be programmed to their default values. A setting of 1 or 0 indicates the required programming for the bit. Table 17. Device Configuration Register Map Address Register Name Mode Hex 0x00 Dec 0 Type R/W Bit 7 SDIO_DIR Bit 6 LSB/MSB Bit 5 SoftReset Power-Down IRQ Enable 0 IRQ Enable 1 0x01 0x03 0x04 1 3 4 R/W R/W R/W BG_PD FIFO_Warn2 IREF_PD FIFO_Warn1 AED pass BIAS_PD SPIFrmAck AED fail IRQ Request 0 0x05 5 R/W FIFO_Warn2 FIFO_Warn1 SPIFrmAck IRQ Request 1 0x06 6 R/W AED pass AED fail Frame Pin Usage 0x07 Reserved_0 0x08 Data Ctrl 0 0x0A 7 8 10 R/W R/W R/W DLL enable Data Ctrl 1 0x0B 11 R/W Warn clear Data Ctrl 2 Data Ctrl 3 0x0C 0x0D 12 13 R/W R/W Data Status 0 0x0E 14 R DLL lock FIFO Ctrl 0x11 17 R/W SPIFrmReq FIFO Offset FIFO Ph0 Thrm FIFO Ph1 Thrm FIFO Ph2 Thrm FIFO Ph3 Thrm Data Mode Ctrl Decode Ctrl Sync 0x12 0x13 0x14 0x15 0x16 0x18 0x19 0x1A 18 19 20 21 22 24 25 26 R/W R R R R R/W R/W R/W FSC_1 FSC_2 ANA_CNT1 ANA_CNT2 CLK REG1 Retimer Ctrl 0 Retimer Ctrl 1 Retimer Stat 0 0x20 0x21 0x22 0x23 0x30 0x33 0x34 0x35 32 33 34 35 48 51 52 53 R/W R/W R/W R/W R/W R/W R/W R SED Control SED Patt/Err R0L SED Patt/Err R0H SED Patt/Err R1L SED Patt/Err R1H SED Patt/Err F0L SED Patt/Err F0H SED Patt/Err F1L SED Patt/Err F1H Parity Control 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x5C 80 81 82 83 84 85 86 87 88 92 R/W R R R R R R R R R/W Parity Err Rising Parity Err Falling Delay Ctrl 0 Delay Ctrl 1 Drive Strength Part ID 0x5D 0x5E 0x70 0x71 0x7C 0x7F 93 94 112 113 124 127 R R R/W R/W R/W R ParUsage Duty cycle correction enable Lock delay divider DCO enable Bit 4 0 Bit 3 0 Bit 2 SoftReset Bit 1 LSB/MSB Bit 0 SDIO_DIR Default 0x81 CLKPATH_PD DLL lock Parity err rise Retimer_PD Retimer lost DLL_PD Retimer lock SED fail 1 DLL warn Parity err fall 0x48 0x00 0x00 DLL warn DLL lock Retimer lost Retimer lock 0x00 Parity err fall Parity err rise SED fail FrmUsage Must maintain default (reset) value of 0x58 Controller clock divider, Bits[1:0] Maximum delay set, Bits[2:0] Delay line middle set, Bits[3:0] 0x29 Minimum delay set, Bits[2:0] Duty correction BW, Bits[1:0] 0x23 0x04 DLL warn Filter enable DLL delay line DLL delay line DLL correct DCI on start warning end warning phase SPIFrmAck Enable pin framing RdPtrOff, Bits[2:0] Phz0Thrm, Bits[6:0] Phz1Thrm, Bits[6:0] Phz2Thrm, Bits[6:0] Phz3Thrm, Bits[6:0] Binary select FILT_SEL Inc latency Dec latency Sync enable 0x00 FRM_x pin usage mode, Bits[1:0] 0x00 0x58 Phase offset, Bits[3:0] 0x40 DLL lock phase DLL running N/A Phase report enable WtPtrOff, Bits[2:0] 0x00 Mix-Mode en Phase readback, Bits[2:0] Sync done Full-scale current, Bits[7:0] Full-scale current, Bits[9:8] 0 Cross enable Phase step, Bits[3:0] PLL lock PLL lost SED enable SED error clear Parity enable Parity even Cross location, Bits[3:0] Clear lost PLL reset_Z PLL divider Duty enable 0 Retimer mode, Bits[1:0] AED enable 0 0 AED pass AED fail SED fail SED Data Port 0 rising edge low part error, Bits[7:0] SED Data Port 0 rising edge high part error, Bits[13:8] SED Data Port 1 rising edge low part error, Bits[7:0] SED Data Port 1 rising edge high part error, Bits[13:8] SED Data Port 0 falling edge low part error, Bits[7:0] SED Data Port 0 falling edge high part error, Bits[13:8] SED Data Port 1 falling edge low part error, Bits[7:0] SED Data Port 1 falling edge high part error, Bits[13:8] Parity error Parity error Parity error clear falling edge rising edge Parity rising edge error count, Bits[7:0] Parity falling edge error count, Bits[7:0] Enable delay cell, Bits[7:0] Enable delay cell, Bits[10:8] DCO drive strength, Bits[1:0] Part ID, Bits[7:0] Rev. 0 | Page 55 of 68 0x04 N/A N/A N/A N/A 0x00 0x00 0x00 0x00 0x02 0x00 0x0C 0x00 0x30 0x55 N/A 0x00 N/A N/A N/A N/A N/A N/A N/A N/A 0x00 N/A N/A 0xFF 0x67 0x7C 0x07 or 0x87 AD9119/AD9129 Data Sheet DEVICE CONFIGURATION REGISTER DESCRIPTIONS SPI Communications Control Register Address: 0x00, Reset: 0x81, Name: Mode Table 18. Bit Descriptions for Mode Bits 7 Bit Name SDIO_DIR 6 LSB/MSB 5 4 3 2 1 0 SoftReset Reserved Reserved SoftReset LSB/MSB SDIO_DIR Description Selects 3-wire or 4-wire mode 1: 3-wire bidirectional 0: 4-wire unidirectional LSB/MSB data packing 1: LSB-first packing 0: MSB-first packing 1: performs a software-based reset Must be set to 0; reserved (short addressing mode) Mirror Bit 4 for safety Mirror Bit 5 for safety Mirror Bit 6 for safety Mirror Bit 7 for safety Reset 1 Access R/W 0 R/W 0 0 0 0 0 1 R/W R/W R R R R Reset 0 Access R/W 1 R/W 0 R/W 0 1 0 R/W R/W R/W 0 0 R/W R/W Power Control Register Address: 0x01, Reset: 0x48, Name: Power-Down Table 19. Bit Descriptions for Power-Down Bits 7 Bit Name BG_PD 6 IREF_PD 5 BIAS_PD 4 3 2 Reserved Reserved CLKPATH_PD 1 0 Retimer_PD DLL_PD Description Band gap power-down 1: band gap is powered down 0: band gap is active IREF power-down 1: FSC is 0 mA 0: FSC is as programmed Bias power-down 1: all bias currents are off 0: all bias currents are on Reserved Must be set to 1; reserved Clock path power-down 1: DAC clock is powered down 0: DAC clock is active 1: PLL is powered down DLL (data receiver) power-down 1: DLL (data receiver) is powered down Rev. 0 | Page 56 of 68 Data Sheet AD9119/AD9129 Interrupt Enable Register 0 Address: 0x03, Reset: 0x00, Name: IRQ Enable 0 Table 20. Bit Descriptions for IRQ Enable 0 Bits 7 6 5 Bit Name FIFO_Warn2 interrupt enable FIFO_Warn1 interrupt enable SPIFrmAck interrupt enable 4 3 2 1 0 Reserved DLL warn interrupt enable DLL lock interrupt enable Retimer lost interrupt enable Retimer lock interrupt enable Description Enables the FIFO warning within two slots of overwrite interrupt Enables the FIFO warning within one slot of overwrite interrupt Enables the FIFO SPI-based calibration acknowledgement of SPIFrmReq (Address 0x11, Bit 7) going from 0b to1b Reserved Enables the DLL warning flag that the data receiver is no longer locked Enables the DLL warning flag that the data receiver is now locked Enables the retimer lost interrupt indication Enables the retimer lock interrupt indication Reset 0 0 0 Access R/W R/W R/W 0 0 0 0 0 R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R R Reset 0 0 0 0 0 Access R R R R R 0 0 0 R R R Interrupt Enable Register 1 Address: 0x04, Reset: 0x00, Name: IRQ Enable 1 Table 21. Bit Descriptions for IRQ Enable 1 Bits 7 6 5 4 3 2 1 0 Bit Name Reserved AED pass interrupt enable AED fail interrupt enable SED fail interrupt enable Parity error falling edge enable Parity error rising edge enable Reserved Reserved Description Reserved Enables the AED pass interrupt reporting saying that eight valid samples captured Enables the AED fail interrupt reporting that a miscompare occurred Enables the SED fail interrupt reporting that a miscompare occurred Enables the parity fail due to a falling edge-based parity detected error Enables the parity fail due to a rising edge-based parity detected error Reserved Reserved Interrupt Status Register 0 Address: 0x05, Reset: 0x00, Name: IRQ Request 0 Table 22. Bit Descriptions for IRQ Request 0 Bits 7 6 5 4 3 Bit Name FIFO_Warn2 interrupt status FIFO_Warn1 interrupt status SPIFrmAck interrupt status Reserved DLL warn interrupt status 2 1 0 DLL lock interrupt status Retimer lost interrupt status Retimer lock interrupt status Description Indicates that the FIFO is within two slots of overwrite Indicates that the FIFO is within one slot of overwrite Indicates acknowledgement of SPIFrmReq has changed from 0b to1b Reserved Indicates that the DLL (data receiver) is close to coming unlocked and action is needed Indicates that the DLL (data receiver) is now locked Indicates that the retimer PLL is no longer locked Indicates that the retimer PLL is now locked Rev. 0 | Page 57 of 68 AD9119/AD9129 Data Sheet Interrupt Status Register1 Address: 0x06, Reset: 0x00, Name: IRQ Request 1 Table 23. Bit Descriptions for IRQ Request 1 Bits 7 6 5 4 3 2 1 0 Bit Name Reserved AED pass interrupt status AED fail interrupt status SED fail interrupt status Parity error falling edge status Parity error rising edge status Reserved Reserved Description Reserved Indicates that the AED logic has captured eight valid samples Indicates that the AED logic has detected a miscompare Indicates that the SED logic has detected a miscompare Indicates a parity fault due to data captured on the falling edge Indicates a parity fault due to data captured on the rising edge Reserved Reserved Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 Access R/W R/W R 0 R 0 0 0x0 R R R/W Reset 0x58 Access R Reset 0 Access R/W 1 R/W 0 0 0x0 R/W R/W R/W Frame Pin Usage Register Address: 0x07, Reset: 0x00, Name: Frame Pin Usage Table 24. Bit Descriptions for Frame Pin Usage Bits 7 6 5 Bit Name Reserved Reserved ParUsage 4 FrmUsage 3 2 [1:0] Reserved Reserved FRM_x pin usage mode Description Reserved Reserved 1: FRM_x pin is in parity mode, and parity is enabled Note that parity must be enabled, and the type must be chosen in Register 0x5C[7:6] 1: FRM_x pin is in frame mode and enable pin framing (Register 0x11[5] = 1b) is enabled Reserved Reserved 3: reserved 2: frame 1: parity 0: no effect Reserved_0 Register Address: 0x08, Reset: 0x58, Name: Reserved_0 Table 25. Bit Descriptions for Reserved_0 Bits [7:0] Bit Name Reserved Description Must keep default (reset) value; reserved Data Receiver Control 0 Register Address: 0x0A, Reset: 0x40, Name: Data Ctrl 0 Table 26. Bit Descriptions for Data Ctrl 0 Bits 7 Bit Name DLL enable 6 Duty cycle correction enable 5 4 [3:0] Reserved Reserved Phase offset Description 1: enables DLL 0: disables DLL 1: enables duty cycle correction 0: disables duty cycle correction Reserved Reserved Locked phase = 90° ± n × 11.25°, where n is the 4-bit signed magnitude number Rev. 0 | Page 58 of 68 Data Sheet AD9119/AD9129 Data Receiver Control 1 Register Address: 0x0B, Reset: 0x29, Name: Data Ctrl 1 Table 27. Bit Descriptions for Data Ctrl 1 Bits 7 6 Bit Name Warn clear Lock delay divider [5:4] Controller clock divider [3:0] Delay line middle set Description 1: clears data receiver warning bit 1: long delay 0: short delay Controller clock divider 00: DCI/4 01: DCI/16 10: DCI/64 11: DCI/512 Sets nominal delay line delay Reset 0 0 Access R/W R/W 0x2 R/W 0x9 R/W Reset 0 0 0x2 0x3 Access R/W R/W R/W R/W Reset 0x00 0x2 Access R R/W 0 R/W Reset 0 0 0 0 0 Access R R R R R 0 0 R R 0 R Data Receiver Control 2 Register Address: 0x0C, Reset: 0x23, Name: Data Ctrl 2 Table 28. Bit Descriptions for Data Ctrl 2 Bits 7 6 [5:3] [2:0] Bit Name Reserved DCO enable Maximum delay set Minimum delay set Description Reserved 1: enables DCO output driver Sets maximum delay line delay (larger number = longer delay line) Sets minimum delay line delay (larger number = smaller delay line) Data Receiver Control 3 Register Address: 0x0D, Reset: 0x04, Name: Data Ctrl 3 Table 29. Bit Descriptions for Data Ctrl 3 Bits [7:3] [2:1] Bit Name Reserved Duty correction BW set 0 Reserved Description Reserved. Controller clock divider. 00: highest BW. 01: higher BW. 10: lower BW. 11: lowest BW. Reserved Data Receiver Status 0 Register Address: 0x0E, Reset: 0x00, Name: Data Status 0 Table 30. Bit Descriptions for Data Status 0 Bits 7 6 5 4 3 Bit Name DLL lock DLL warning DLL delay line start warning DLL delay line end warning DLL correct phase 2 1 DCI on DLL lock phase 0 DLL running Description 1: DLL lock 1: DLL near beginning/end of delay line 1: DLL at beginning of delay line 1: DLL at end of delay line 1: data is sampled on correct phase 0: data is sampled on incorrect phase. 1: user has provided a clock > 100 MHz 1: DLL is locked on negative half of DCI. 0: DLL is locked on positive half of DCI 1: closed loop DLL attempting to lock 0: delay fixed at middle of delay line Rev. 0 | Page 59 of 68 AD9119/AD9129 Data Sheet FIFO Control Register Address: 0x11, Reset: 0x00, Name: FIFO Ctrl Table 31. Bit Descriptions for FIFO Ctrl Bits 7 6 5 [4:1] 0 Bit Name SPIFrmReq SPIFrmAck Enable pin framing Reserved Phase report enable Description Requests a SPI-based FIFO alignment (FIFO reset) Acknowledges SPIFrmReq change (tracks SPIFrmReq setting) 1: enables hardware pin-based FIFO framing Reserved 1: enables FIFO phase reporting Reset 0 0 0 0x0 0 Access R/W R/W R/W R R/W Reset 0 0x0 0 0x4 Access R R/W R R/W Reset 0 0x00 Access R R Reset 0 0x00 Access R R Reset 0 0x00 Access R R Reset 0 0x00 Access R R FIFO Offset Register Address: 0x12, Reset: 0x04, Name: FIFO Offset Table 32. Bit Descriptions for FIFO Offset Bits 7 [6:4] 3 [2:0] Bit Name Reserved RdPtrOff[2:0] Reserved WtPtrOff[2:0] Description Reserved FIFO read pointer offset Reserved FIFO write pointer offset FIFO Thermometer for Phase 0 Status Register Address: 0x13, Reset: 0x00, Name: FIFO PH0 THRM Table 33. Bit Descriptions for FIFO PH0 THRM Bits 7 [6:0] Bit Name Reserved Phz0Thrm Description Reserved Phase 0-based FIFO thermometer status. Phase 0 relative FIFO phasing, as 0000000b to 1111111b, where 0000011b is considered the middle of the FIFO storage space. FIFO Thermometer for Phase 1 Status Register Address: 0x14, Reset: 0x00, Name: FIFO PH1 THRM Table 34. Bit Descriptions for FIFO PH1 THRM Bits 7 [6:0] Bit Name Reserved Phz1Thrm Description Reserved Phase 1-based FIFO thermometer status. Phase 1 relative FIFO phasing, as 0000000b to 1111111b, where 0000011b is considered the middle of the FIFO storage space. FIFO Thermometer for Phase 2 Status Register Address: 0x15, Reset: 0x00, Name: FIFO PH2 THRM Table 35. Bit Descriptions for FIFO PH2 THRM Bits 7 [6:0] Bit Name Reserved Phz2Thrm Description Reserved Phase 2-based FIFO thermometer status. Phase 2 relative FIFO phasing, as 0000000b to 1111111b, where 0000011b is considered the middle of the FIFO storage space. FIFO Thermometer for Phase 3 Status Register Address: 0x16, Reset: 0x00, Name: FIFO PH3 THRM Table 36. Bit Descriptions for FIFO PH3 THRM Bits 7 [6:0] Bit Name Reserved Phz3Thrm Description Reserved Phase 3-based FIFO thermometer status. Phase 3 relative FIFO phasing, as 0000000b to 1111111b, where 0000011b is considered the middle of the FIFO storage space. Rev. 0 | Page 60 of 68 Data Sheet AD9119/AD9129 Data Mode Control Register Address: 0x18, Reset: 0x00, Name: Data Mode Ctrl Table 37. Bit Descriptions for Data Mode Ctrl Bits 7 Bit Name Filter enable 6 Binary select 5 FILT_SEL [4:0] Reserved Description 1: enables 2× interpolation filter 0: bypasses 2× interpolation filter Selects input data format 1: unsigned 0: signed 2× interpolator filter select 1: 40 dB OOB rejection 0: 25 dB out-of-band (OOB) rejection Reserved Reset 0 Access R/W 0 R/W 0 R 0 R Reset 0x00 0 Access R R/W Reset 0 0 0 0 Access R/W R/W R R/W 0 0 R R Reset 0x00 Access R/W Reset 0 0 0x02 Access R/W R R/W Decoder Control (Program Thermometer Type) Register Address: 0x19, Reset: 0x00, Name: Decode Ctrl Table 38. Bit Descriptions for Decode Ctrl Bits [7:1] 0 Bit Name Reserved Mix-Mode enable Description Reserved 1: Mix-Mode 0: normal Sync Control Register Address: 0x1A, Reset: 0x00, Name: Sync Table 39. Bit Descriptions for Sync Bits 7 6 5 4 Bit Name Inc latency Dec latency Reserved Sync enable 3 [2:0] Sync done Phase readback Description Increment delay by 1 Decrement delay by 1 Reserved 1: multi-DAC sync output pin enabled 0: multi-DAC sync output pin disabled 1: last increment or decrement request is complete Readback of existing SYNC phase delay value Full-Scale Current Adjust (Lower) Register Address: 0x20, Reset: 0x00, Name: FSC_1 Table 40. Bit Descriptions for FSC_1 Bits [7:0] Bit Name Full-scale current, Bits[7:0] Description DAC gain adjust; DAC full-scale current (LSB) Full-Scale Current Adjust (Upper) Register Address: 0x21 Reset: 0x02, Name: FSC_2 Table 41. Bit Descriptions for FSC_2 Bits 7 [6:2] [1:0] Bit Name Reserved Reserved Full-scale current, Bits[9:8] Description Reserved Reserved DAC gain adjust; DAC full-scale current (MSB) Rev. 0 | Page 61 of 68 AD9119/AD9129 Data Sheet Analog Control 1 Register Address: 0x22, Reset: 0x00, Name: ANA_CNT1 Table 42. Bit Descriptions for ANA_CNT1 Bits [7:0] Bit Name Reserved Description Reserved Reset 0x0 Access R/W Reset 0x0C Access R/W Reset 0 0 0 0 0 Access R/W R/W R/W R/W R/W Reset 0x3 0 0 Access R/W Analog Control 2 Register Address: 0x23, Reset: 0x0C, Name: ANA_CNT2 Table 43. Bit Descriptions for ANA_CNT2 Bits [7:0] Bit Name Reserved Description Reserved Clock Control 1 Register Address: 0x30, Reset: 0x00, Name: CLK REG1 Table 44. Bit Descriptions for CLK REG1 Bits 7 6 [5:2] 1 0 Bit Name Reserved Cross enable Cross location Duty enable Select internal Description Must be set to 0; reserved Enables zero-crossing control Adjusts zero-crossing control location (signed magnitude) Enables duty cycle correction Must be set to 0 Retimer Control 0 Register Address: 0x33, Reset: 0x30, Name: Retimer Ctrl 0 Table 45. Bit Descriptions for Retime Ctrl 0 Bits [7:4] 3 2 Bit Name Phase step Clear lost PLL divider [1:0] Retimer mode Description 4-bit signed magnitude; PFD phase step = n × 30° Clear lost status bit 1: divide-by-4 0: divide-by-8 0: enable PFD, normal mode 1: reserved 2: reserved 3: reserved 0x0 Retimer Control 1 Register Address: 0x34, Reset: 0x55, Name: Retimer Ctrl 1 Table 46. Bit Descriptions for Retimer Ctrl 1 Bits [7:4] 3 Bit Name Reserved PLL reset_Z [2:0] Reserved Description Reserved 1: normal operation for DAC clock PLL 0: resets the DAC clock PLL Reserved Reset 0x5 0 Access R/W R/W 0x5 R/W Reset 0 0 0x0 0x0 Access R R R R Retimer Status 0 Register Address: 0x35, Reset: 0x00, Name: Retimer Stat 0 Table 47. Bit Descriptions for Retimer Stat 0 Bits 7 6 [5:4] [3:0] Bit Name PLL lock PLL lost Reserved Reserved Description 1: retimer PLL locked 1: retimer PLL lost (can be sticky) Reserved Reserved Rev. 0 | Page 62 of 68 Data Sheet AD9119/AD9129 Sample Error Detection (SED) Control Register Address: 0x50, Reset: 0x00, Name: SED Control Table 48. Bit Descriptions for SED Control Bits 7 6 5 4 3 2 1 0 Bit Name SED enable SED error clear AED enable Reserved Reserved AED pass AED fail SED fail Description 1: setting this bit to 1 enables the SED compare logic 1: clears all SED reported error bits below 1: enables the AED function (SED with autoclear after eight passing sets) Must be set to 0; reserved Must be set to 0; reserved 1: signals eight true compare cycles 1: signals a miscompare 1: signals an SED miscompare (with SED or AED enabled) Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R R R/W R R Reset 0x00 Access R Reset 0x0 0x00 Access R R Reset 0x00 Access R Reset 0x0 0x00 Access R R Sample Error Detection (SED) Data Port 0 Rising Edge Status Low Register Address: 0x51, Reset: 0x00, Name: SED Patt/Err R0L Table 49. Bit Descriptions for SED Patt/Err R0L Bits [7:0] Bit Name SED Data Port 0 rising edge low part error bits Description SED Data Port 0 rising edge error, Bits[7:0] Sample Error Detection (SED) Data Port 0 Rising Edge Status High Register Address: 0x52, Reset: 0x000, Name: SED Patt/Err R0H Table 50. Bit Descriptions for SED Patt/Err R0H Bits [7:6] [5:0] Bit Name Reserved SED Data Port 0 rising edge high part error bits Description Reserved SED Data Port 0 rising edge error, Bits[13:8] Sample Error Detection (SED) Data Port 1 Rising Edge Status Low Register Address: 0x53, Reset: 0x00, Name: SED Patt/Err R1L Table 51. Bit Descriptions for SED Patt/Err R1L Bits [7:0] Bit Name SED Data Port 1 rising edge low part error bits Description SED Data Port 1 rising edge error, Bits[7:0] Sample Error Detection (SED) Data Port 1 Rising Edge Status High Register Address: 0x54, Reset: 0x00, Name: SED Patt/Err R1H Table 52. Bit Descriptions for SED Patt/Err R1H Bits [7:6] [5:0] Bit Name Reserved SED Data Port 1 rising edge high part error bits Description Reserved SED Data Port 1 rising edge error, Bits[13:8] Rev. 0 | Page 63 of 68 AD9119/AD9129 Data Sheet Sample Error Detection (SED) Data Port 0 Falling Edge Status Low Register Address: 0x55, Reset: 0x00, Name: SED Patt/Err F0L Table 53. Bit Descriptions for SED Patt/Err F0L Bits [7:0] Bit Name SED Data Port 0 falling edge low part error bits Description SED Data Port 0 falling edge error, Bits[7:0] Reset 0x00 Access R Reset 0x0 0x00 Access R R Reset 0x00 Access R Description Reserved SED Data Port 1 falling edge error, Bits[13:8] Reset 0x0 0x00 Access R R Description 1: enables parity 1: even parity; if the parity bit from the FRM_x pin = 1, the number of 1s in the word is even 0: odd parity; if the parity bit from the FRM_x pin = 1, the number of 1s in the word is odd Note that the parity bit must be enabled in Register 0x07 1: clears parity error counters Reserved 1: signals detection of a falling edge parity error 1: signals detection of a rising edge parity error Reset 0x00 0 Access R/W R/W 0 0x0 0 0 R/W R R R Description Number of rising edge-based errors detected, clipped to 256 Reset 0x00 Access R Description Number of falling edge-based errors detected, clipped to 256 Reset 0x00 Access R Sample Error Detection (SED) Data Port 0 Falling Edge Status High Register Address: 0x56, Reset: 0x000, Name: SED Patt/Err F0H Table 54. Bit Descriptions for SED Patt/Err F0H Bits [7:6] [5:0] Bit Name Reserved SED Data Port 0 falling edge high part error bits Description Reserved SED Data Port 0 falling edge error, Bits[13:8] Sample Error Detection (SED) Data Port 1 Falling Edge Status Low Register Address: 0x57, Reset: 0x00, Name: SED Patt/Err F1L Table 55. Bit Descriptions for SED Patt/Err F1L Bits [7:0] Bit Name SED Data Port 1 falling edge low part error bits Description SED Data Port 1 falling edge error, Bits[7:0] Sample Error Detection (SED) Data Port 1 Falling Edge Status High Register Address: 0x58, Reset: 0x00, Name: SED Patt/Err F1H Table 56. Bit Descriptions for SED Patt/Err F1H Bits [7:6] [5:0] Bit Name Reserved SED Data Port 1 falling edge high part error bits Parity Control Register Address: 0x5C, Reset: 0x00, Name: Parity Control Table 57. Bit Descriptions for Parity Control Bits 7 6 Bit Name Parity enable Parity even 5 [4:2] 1 0 Parity error clear Reserved Parity error falling edge Parity error rising edge Parity Rising Edge Count Register Address: 0x5D, Reset: 0x00, Name: Parity Err Rising Table 58. Bit Descriptions for Parity Err Rising Bits [7:0] Bit Name Parity rising edge error count Parity Falling Edge Count Register Address: 0x5E, Reset: 0x00, Name: Parity Err Falling Table 59. Bit Descriptions for Parity Err Falling Bits [7:0] Bit Name Parity falling edge error count Rev. 0 | Page 64 of 68 Data Sheet AD9119/AD9129 Delay Control Register 0 Address: 0x70, Reset: 0xFF, Name: Delay Ctrl 0 Table 60. Bit Descriptions for Delay Ctrl 0 Bits [7:0] Bit Name Enable delay cell Description Sets each bit to enable or disable the delay cell, Bits[7:0]; delay cell number corresponds to bit number 1: enables delay cell (default) 0: disables delay cell Reset 0xFF Access R/W Reset 0x60 0x7 Access R/W R/W Reset 0x1 Access R/W 0x3C R/W Reset 0x07 or 0x87 Access R Delay Control Register 1 Address: 0x71, Reset: 0x67, Name: Delay Ctrl 1 Table 61. Bit Descriptions for Delay Ctrl 1 Bits [7:3] [2:0] Bit Name Reserved Enable delay cell Description Reserved Sets each bit to enable or disable the delay cell, Bits[10:8]; delay cell numbers are 10, 9, and 8, which correspond to Bit 2, Bit 1, and Bit 0, respectively 1: enables delay cell (default) 0: disables delay cell Drive Strength Register Address: 0x7C, Reset: 0x7C, Name: Drive Strength Table 62. Bit Descriptions for Drive Strength Bits [7:6] Bit Name DCO drive strength [5:0] Reserved Description Sets DCO drive strength 00: 2 mA 01: 2.8 mA (default) 10: 3.4 mA 11: 4 mA Reserved Part ID Register Address: 0x7F, Reset: 0x03 or 0x83, Name: Part ID Table 63. Bit Descriptions for Part ID Bits [7:0] Bit Name Part ID Description Version information 0x07 = the AD9129 (14-bit version) 0x87 = the AD9119 (11-bit version) Rev. 0 | Page 65 of 68 AD9119/AD9129 Data Sheet OUTLINE DIMENSIONS 12.10 12.00 SQ 11.90 14 13 12 11 10 9 8 7 6 5 4 3 2 A B C D E F G H J K L M N P 10.40 BSC SQ 0.80 BSC BOTTOM VIEW TOP VIEW DETAIL A DETAIL A 0.43 MAX 0.25 MIN 1.40 MAX A1 BALL CORNER 1 SEATING PLANE 1.00 MAX 0.85 MIN 0.55 0.50 0.45 BALL DIAMETER COPLANARITY 0.12 COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1. 11-18-2011-A A1 BALL CORNER Figure 157. 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-160-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9119BBCZ AD9119BBCZRL AD9119-EBZ AD9119-MIX-EBZ AD9119-CBLTX-EBZ AD9129BBCZ AD9129BBCZRL AD9129BBC AD9129BBCRL AD9129-EBZ AD9129-MIX-EBZ AD9129-CBLTX-EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board for Normal Mode Evaluation Evaluation Board for Mix-Mode Evaluation Evaluation Board for Cable Transmitter Evaluation 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board for Normal Mode Evaluation Evaluation Board for Mix-Mode Evaluation Evaluation Board for Cable Transmitter Evaluation Z = RoHS Compliant Part. Rev. 0 | Page 66 of 68 Package Option BC-160-1 BC-160-1 BC-160-1 BC-160-1 BC-160-1 BC-160-1 Data Sheet AD9119/AD9129 NOTES Rev. 0 | Page 67 of 68 AD9119/AD9129 Data Sheet NOTES ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11149-0-1/13(0) Rev. 0 | Page 68 of 68