CY2303 Phase-Aligned Clock Multiplier Features Functional Description ■ 3-multiplier configuration (1x, 2x, 4x Ref) ■ 10 MHz to 166.67 MHz operating range (reference input from 10 MHz to 41.67 MHz) The CY2303 is a 3 output 3.3V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. ■ Phase Alignment ■ 80 ps typical period jitter ■ Output enable pin ■ 3.3V operation ■ 5V Tolerant input ■ 8-pin 150-mil SOIC package ■ Commercial and Industrial Temperature available The part allows user to obtain 1x, 2x, and 4x Ref output frequencies on respective output pins. The CY2303 has an on-chip PLL, which locks to an input clock presented on the REFIN pin. The PLL feedback is internally connected to the REF output. The input-to-output skew is guaranteed to be less than ±200 ps, and output-to-output skew is guaranteed to be less than 200 ps. Multiple CY2303 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 400 ps. The CY2303 is available in commercial and industrial temperature ranges. Selector Guide Part Number Outputs Input Frequency Range Output Frequency Range Specifics CY2303SXC 3 10 MHz–41.67 MHz 10 MHz–166.67 MHz Commercial Temperature CY2303SXI 3 10 MHz–41.67 MHz 10 MHz–166.67 MHz Industrial Temperature Logic Block Diagram FBK x1 REF PLL REFIN x2 x4 REFx2 REFx4 OE Cypress Semiconductor Corporation Document #: 38-07249 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 23, 2008 [+] Feedback CY2303 Pinouts Figure 1. CY2303 - 8-pin SOIC Top View 1 2 3 4 REF GND REFIN N/C 8 7 6 5 OE VDD REFx4 REFx2 Pin Description Signal[1] Pin Description 1 REF REF output (1x Reference input) 2 GND Ground 3 REFIN Input reference frequency, 5V tolerant input 4 N/C No Connect 5 REFx2 2x Reference input 6 REFx4 4x Reference input 7 VDD 3.3V Supply 8 OE Output Enable (weak pull up) Maximum Ratings Supply Voltage to Ground Potential................–0.5V to +7.0V Storage Temperature ................................. –65°C to +150°C DC Input Voltage (Except Ref) .............. –0.5V to VDD + 0.5V Junction Temperature ................................................. 150°C DC Input Voltage REFIN........................................ –0.5 to 7V Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions for CY2303SC Commercial Temperature Devices Parameter Description Min Max Unit 3.0 3.6 V 0 70 °C VDD Supply Voltage TA Operating Temperature (Ambient Temperature) CL Load Capacitance, Fout < 133.33 MHz – 18 pF Load Capacitance, 133.33 MHz < Fout < 166.67 MHz – 12 pF CIN Input Capacitance tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) – 7 pF 0.05 50 ms Min. Max. Unit – 0.8 V Electrical Characteristics for CY2303SC Commercial Temperature Devices Parameter Description VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current IIH Input HIGH Current VOL Test Conditions [2] Output LOW Voltage 2.0 – V VIN = 0V – 100 μA VIN = VDD – 50 μA IOL = 8 mA – 0.4 V Notes 1. Weak pull-down on all outputs. 2. Parameter is guaranteed by design and characterization. It is not 100% tested in production. Document #: 38-07249 Rev. *C Page 2 of 7 [+] Feedback CY2303 Electrical Characteristics for CY2303SC Commercial Temperature Devices VOH Output HIGH Voltage[2] IOH = –8 mA IDD Supply Current 2.4 – V Unloaded outputs, REFIN = 41.67 MHz – 45 mA Unloaded outputs, REFIN = 25 MHz – 32 mA Unloaded outputs, REFIN = 10 MHz – 18 mA Switching Characteristics for CY2303SC Commercial Temperature Devices Parameter 1/t1 Name Output Frequency [3] Duty Cycle t3 Test Conditions Rise = t2 ÷ t1 Time[3] Time[3] Min Typ. Max Unit 18-pF load 10 – 133.33 MHz 12-pF load – – 166.67 MHz Measured at VDD/2 40 50 60 % Measured between 0.8V and 2.0V – – 1.20 ns Measured between 0.8V and 2.0V – – 1.20 ns All outputs equally loaded Measured at VDD/2 – – 200 ps t4 Fall t5 Output to Output Skew on rising edges[3] t6 Delay, REFIN Rising Edge to Measured at VDD/2 from REFIN to any output REF Rising Edge[3] – – ±200 ps t7 Device to Device Skew[3] Measured at VDD/2 on the REF pin of the device (pin 1) – – 400 ps tJ Period Jitter[3] Measured at Fout < 133.33 MHz, loaded outputs, 18-pF load – 80 ±175 ps tLOCK PLL Lock Time[3] Stable power supply, valid clocks presented on REFIN – – 1.0 ms Operating Conditions for CY2303SI Industrial Temperature Devices Min. Max. Unit VDD Parameter Supply Voltage Description 3.0 3.6 V TA Operating Temperature (Ambient Temperature) –40 85 °C CL Load Capacitance, Fout <133.33 MHz – 15 pF – 10 pF 0.05 50 ms Min Max. Unit – 0.8 V Load Capacitance, 133.33 MHz < Fout < 166.67 MHz, tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Electrical Characteristics for CY2303SI Industrial Temperature Devices Parameter Description Test Conditions VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current IIH Input HIGH Current VIN = VDD VOL Output LOW Voltage[2] IOL = 8 mA VOH [2] Output HIGH Voltage IOH = –8 mA IDD Supply Current 2.0 – V – 100 μA – 50 μA – 0.4 V 2.4 – V Unloaded outputs, REFIN = 41.67 MHz – 48 mA Unloaded outputs, REFIN = 25 MHz – 35 mA Unloaded outputs, REFIN = 10 MHz – 20 mA VIN = 0V Note 3. All parameters are specified with loaded outputs. Document #: 38-07249 Rev. *C Page 3 of 7 [+] Feedback CY2303 Switching Characteristics for CY2303SI Industrial Temperature Devices Parameter 1/t1 Name Output Frequency Duty Cycle[3] = t2 ÷ t1 [3] Test Conditions Min Typ. Max Unit 15-pF load 10 – 133.33 MHz 10-pF load – – 166.67 MHz Measured at VDD/2 40 50 60 % – – 1.20 ns t3 Rise Time Measured between 0.8V and 2.0V t4 Fall Time[3] Measured between 0.8V and 2.0V – – 1.20 ns t5 Output to Output Skew on rising edges[3] All outputs equally loaded Measured at VDD/2 – – 200 ps t6 Delay, REFIN Rising Edge to Measured at VDD/2 from REFIN to any output REF Rising Edge[3] – – ±200 ps t7 Device to Device Skew[3] Measured at VDD/2 on the REF pin of the device (pin 1) – – 400 ps tJ Period Jitter[3] Measured at Fout < 133.33 MHz, loaded outputs, 15-pF load – 80 ±175 ps tLOCK PLL Lock Time[3] Stable power supply, valid clocks presented on REFIN – – 1.0 ms Switching Waveforms Figure 2. Duty Cycle Timing t1 t2 VDD/2 Figure 3. All Outputs Rise/Fall Time OUTPUT 2.0V 0.8V 2.0V 0.8V t3 3.3V 0V t4 Figure 4. Output-Output Skew OUTPUT VDD/2 VDD/2 OUTPUT t5 Document #: 38-07249 Rev. *C Page 4 of 7 [+] Feedback CY2303 Switching Waveforms (continued) Figure 5. Input-Output Propagation Delay INPUT VDD/2 VDD/2 FBK t6 Figure 6. Device-Device Skew FBK, Device 1 VDD/2 VDD/2 FBK, Device 2 t7 Test Circuits Test Circuit # 1 VDD 0.1 μF OUTPUTS CLK OUT C LOAD GND Ordering Information Ordering Code Package Type Operating Range Pb-free CY2303SXC 8-Pin 150-mil SOIC Commercial CY2303SXCT 8-Pin 150-mil SOIC - Tape and Reel Commercial CY2303SXI 8-Pin 150-mil SOIC Industrial CY2303SXIT 8-Pin 150-mil SOIC - Tape and Reel Industrial Document #: 38-07249 Rev. *C Page 5 of 7 [+] Feedback CY2303 Package Diagram Figure 7. 8-Pin (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C Document #: 38-07249 Rev. *C Page 6 of 7 [+] Feedback CY2303 Document History Page Document Title: CY2303 Phase-Aligned Clock Multiplier Document Number: 38-07249 REV. ECN Orig. of Change Submission Date ** 110514 SZV 01/07/02 *A 121852 RBI 12/14/02 Power up requirements added to Operating Conditions Information *B 390413 RGL 08/10/05 Added Lead-free devices Added typical values for jitter *C 2568533 AESA 09/23/08 Updated template. Removed part number CY2303SC and CY2303SI from Selector Guide table. Removed part number CY2303SC, CY2303SCT, CY2303SI, and CY2303SIT. Description of Change Change from Spec number: 38-01036 to 38-07249 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07249 Rev. *C Revised September 23, 2008 Page 7 of 7 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback