Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 ADS868x 16-Bit, High-Speed, Single-Supply, SAR ADC Data Acquisition System with Programmable, Bipolar Input Ranges 1 Features 3 Description • • The ADS8681, ADS8685, and ADS8689 devices belong to a family of integrated data acquisition system based on a successive approximation (SAR) analog-to-digital converter (ADC). The devices feature a high-speed, high-precision SAR ADC, integrated analog front-end (AFE) input driver circuit, overvoltage protection circuit up to ±20 V, and an onchip 4.096-V reference with extremely low temperature drift. 1 • • • • • • • • • 16-Bit ADC with Integrated Analog Front-End High Speed: – ADS8681: 1 MSPS – ADS8685: 500 kSPS – ADS8689: 100 kSPS Software Programmable Input Ranges: – Bipolar Ranges: ±12.288 V, ±10.24 V, ±6.144 V, ±5.12 V, and ±2.56 V – Unipolar Ranges: 0 V–12.288 V, 0 V–10.24 V, 0 V–6.144 V, and 0 V–5.12 V 5-V Analog Supply: 1.65-V to 5-V I/O Supply Constant Resistive Input Impedance ≥ 1 MΩ Input Overvoltage Protection: Up to ±20 V On-Chip, 4.096-V Reference with Low Drift Excellent Performance: – DNL: ±0.4 LSB; INL: ±0.5 LSB – SNR: 92 dB; THD: –107 dB ALARM → High, Low Thresholds per Channel multiSPI™ Interface with Daisy-Chain Extended Industrial Temperature Range: –40°C to +125°C The devices operate on a single 5-V analog supply, but support true bipolar input ranges of ±12.288 V, ±6.144 V, ±10.24 V, ±5.12 V, and ±2.56 V, as well as unipolar input ranges of 0 V to 12.288 V, 0 V to 10.24 V, 0 V to 6.144 V, and 0 V to 5.12 V. The gain and offset errors are accurately trimmed within the specified values for each input range to ensure high dc precision. The input range selection is done by software programming of the device internal registers. The devices offer a high resistive input impedance (≥ 1 MΩ) irrespective of the selected input range. The multiSPI digital interface is backward-compatible to the traditional SPI protocol. Additionally, configurable features simplify interface to a wide range of host controllers. Device Information(1) PART NUMBER 2 Applications • • • ADS868x Channel-Isolated PLC Analog Input Modules Test and Measurement Battery Pack Monitoring PACKAGE BODY SIZE (NOM) TSSOP (16) 5.00 mm × 4.40 mm WQFN (16) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Block Diagram DVDD AVDD REFIO ADS868x 4.096-V Reference REFCAP CONVST/CS 1 M: SCLK OVP AIN_P PGA AIN_GND OVP 2nd-Order LPF ADC Driver 16-Bit SAR ADC Digital Logic and Interface SDI SDO 1 M: VBIAS AGND Oscillator DGND REFGND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Electrical Characteristics........................................... 6 Timing Requirements: Conversion Cycle................ 10 Timing Requirements: Asynchronous Reset........... 10 Timing Requirements: SPI-Compatible Serial Interface ................................................................... 10 6.9 Timing Requirements: Source-Synchronous Serial Interface (External Clock) ........................................ 11 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock).......................................... 11 6.11 Typical Characteristics .......................................... 15 7 Detailed Description ............................................ 22 7.1 Overview ................................................................. 22 7.2 Functional Block Diagram ....................................... 22 7.3 7.4 7.5 7.6 8 Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 23 35 40 48 Application and Implementation ........................ 56 8.1 Application Information............................................ 56 8.2 Typical Application ................................................. 56 9 Power Supply Recommendations...................... 60 9.1 Power Supply Decoupling ....................................... 60 9.2 Power Saving .......................................................... 60 10 Layout................................................................... 61 10.1 Layout Guidelines ................................................. 61 10.2 Layout Example .................................................... 62 11 Device and Documentation Support ................. 63 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 63 63 63 63 63 63 64 12 Mechanical, Packaging, and Orderable Information ........................................................... 64 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (March 2016) to Revision B Page • Added ADS8685 and ADS8689 devices to document .......................................................................................................... 1 • Changed Features bullets: added High Speed bullet, deleted Aggregate Throughput sub-bullet from Excellent Performance bullet, added Extended to Industrial Temperature Range bullet, and deleted Packages bullet ....................... 1 • Changed Description section ................................................................................................................................................. 1 • Deleted Device Comparison Table ........................................................................................................................................ 4 • Added maximum throughput to conditions statement of Electrical Characteristics table and all Timing Requirements tables ..................................................................................................................................................................................... 6 • Changed Power-Supply Requirements sub-section parameter names in Electrical Characteristics table for clarity (specification values did not change) ..................................................................................................................................... 8 • Changed conditions of Timing Requirements tables ........................................................................................................... 10 • Changed Typical Characteristics section: added maximum throughput to conditions statement and deleted redundant plots for the ADS868x ........................................................................................................................................ 15 • Changed Input Alarm section: corrected alarm reset configuration in last two paragraphs and both images ..................... 34 • Added fifth paragraph of Multiple Devices: Daisy-Chain Topology section.......................................................................... 37 • Added RST (Falling Edge) to Device Functional States figure ............................................................................................ 38 • Changed bulleted list in Data Transfer Frame section pertaining to the end of the data transfer frame F .......................... 41 • Changed Output Data Word section..................................................................................................................................... 43 • Changed several value after reset notations from h to b throughout bit registers of the Register Maps section ............... 48 • Changed ALARM_H_TH_REG Register Field Descriptions table ...................................................................................... 55 • Changed ALARM_L_TH_REG Register Field Descriptions table ....................................................................................... 55 • Changed Application and Implementation section for clarity and improved description of device functionality ................. 56 • Changed first sentence of Power Saving section................................................................................................................. 60 2 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 Revision History (continued) Changes from Original (February 2016) to Revision A • Page Released to production .......................................................................................................................................................... 1 Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 3 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 5 Pin Configuration and Functions PW Package 16-Pin TSSOP Top View (Not to Scale) 2 15 RVS AGND 3 14 ALARM/SDO-1/GPO REFIO 4 13 SDO-0 REFGND 5 12 SCLK REFCAP 6 11 CONVST/CS AIN_P 7 10 SDI AIN_GND 8 9 RST RVS AVDD AGND ALARM/SDO-1/GPO REFIO SDO-0 REFGND SCLK REFCAP CONVST/CS SDI DVDD RST 16 AIN_GND 1 AIN_P DGND DVDD AVDD DGND RUM Package 16-Pin WQFN Top View (Not to Scale) Pin Functions NO. NAME TYPE (1) DESCRIPTION TSSOP WQFN AGND 3 1 P Analog ground pin. Decouple with the AVDD pin. AIN_GND 8 6 AI Analog input: negative. Decouple with the AIN_P pin. AIN_P 7 5 AI Analog input: positive. Decouple with the AIN_GND pin. ALARM/SDO-1/GPO 14 12 DO Multi-function output pin. Active high alarm. Data output 1 for serial communication. General-purpose output pin. AVDD 2 16 P Analog supply pin. Decouple with the AGND pin. 11 9 DI Dual-functionality pin. Active high logic: conversion start input pin; a CONVST rising edge brings the device from acquisition phase to conversion phase. Active low logic: chip-select input pin; the device takes control of the data bus when CS is low; the SDO-x pins go to tri-state when CS is high. DGND 1 15 P Digital ground pin. Decouple with the DVDD pin. DVDD 16 14 P Digital supply pin. Decouple with the DGND pin. REFCAP 6 4 AO REFGND 5 3 P REFIO 4 2 AIO RST 9 7 DI Active low logic input to reset the device. RVS 15 13 DO Multi-function output pin for serial interface; see the RESET State section. With CS held high, RVS reflects the status of the internal ADCST signal. With CS low, the status of RVS depends on the output protocol selection. SCLK 12 10 DI Serial communication: clock input pin for the serial interface. All system-synchronous data transfer protocols are timed with respect to the SCLK signal. SDI 10 8 DI Dual function: data input pin for serial communication. Chain data input during serial communication in daisy-chain mode. SDO-0 13 11 DO Serial communication: data output 0 CONVST/CS (1) 4 ADC reference buffer decoupling capacitor pin. Decouple with the REFGND pin. Reference ground pin; short to the analog ground plane. Decouple with the REFIO and REFCAP pins. Internal reference output and external reference input pin. Decouple with REFGND. AI = analog input, AIO = analog input/output, DI = digital input, DO = digital output, and P = power supply. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) AIN_P, AIN_GND to GND MIN MAX AVDD = 5 V (2) –20 20 AVDD = floating (3) –11 11 UNIT V AVDD to GND or DVDD to GND –0.3 7 V REFCAP to REFGND or REFIO to REFGND –0.3 5.7 V GND to REFGND –0.3 0.3 V Digital input pins to GND –0.3 DVDD + 0.3 V Digital output pins to GND –0.3 DVDD + 0.3 V Operating, TA –40 125 Storage, Tstg –65 150 Temperature (1) (2) (3) °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. AVDD = 5 V offers a low impedance of < 30 kΩ. AVDD = floating with an impedance > 30 kΩ. 6.2 ESD Ratings VALUE V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) Analog input pins (AIN_P, AIN_GND) ±4000 All other pins ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101 (1) (2) (2) UNIT V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD Analog supply voltage 4.75 5 5.25 V DVDD Digital supply voltage 1.65 3.3 AVDD V 6.4 Thermal Information ADS8681, ADS8685, ADS8689 THERMAL METRIC (1) PW (TSSOP) RUM (WQFN) 16 PINS 16 PINS UNIT RθJA Junction-to-ambient thermal resistance 95.7 31.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29.3 27.9 °C/W RθJB Junction-to-board thermal resistance 41.5 7.4 °C/W ψJT Junction-to-top characterization parameter 1.5 0.3 °C/W ψJB Junction-to-board characterization parameter 40.8 7.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 1.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 5 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 6.5 Electrical Characteristics all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Input range = ±3 × VREF Full-scale input span (1) (AIN_P to AIN_GND) VIN –12.288 12.288 Input range = ±2.5 × VREF –10.24 10.24 Input range = ±1.5 × VREF –6.144 6.144 Input range = ±1.25 × VREF –5.12 5.12 Input range = ±0.625 × VREF –2.56 2.56 Input range = 3 × VREF 0 12.288 Input range = 2.5 × VREF 0 10.24 Input range = 1.5 × VREF 0 6.144 Input range = 1.25 × VREF 0 5.12 –12.288 12.288 Input range = ±2.5 × VREF –10.24 10.24 Input range = ±1.5 × VREF –6.144 6.144 Input range = ±1.25 × VREF –5.12 5.12 Input range = ±0.625 × VREF –2.56 2.56 Input range = 3 × VREF 0 12.288 Input range = 2.5 × VREF 0 10.24 Input range = 1.5 × VREF 0 6.144 Input range = 1.25 × VREF 0 Input range = ±3 × VREF AIN_P Operating input range AIN_GND RIN Operating input range All input ranges Input impedance At TA = 25°C IIN With voltage at the AIN_P pin = VIN Input current V 5.12 –0.1 0 0.1 Input range = ±3 × VREF 1.02 1.2 1.38 Input range = ±1.5 × VREF 1.02 1.2 1.38 Input range = 3 × VREF 1.02 1.2 1.38 Input range = 1.5 × VREF 1.02 1.2 1.38 Input range = ±2.5 × VREF 0.85 1 1.15 Input range = ±1.25 × VREF 0.85 1 1.15 Input range = ±0.625 × VREF 0.85 1 1.15 Input range = 2.5 × VREF 0.85 1 1.15 Input range = 1.25 × VREF 0.85 1 1.15 7 25 Input impedance drift V Input range = ±3 × VREF (VIN – 2.5) / RIN Input range = ±2.5 × VREF (VIN – 2.2) / RIN Input range = ±1.5 × VREF (VIN – 2.0) / RIN Input range = ±1.25 × VREF (VIN – 2.0) / RIN Input range = ±0.625 × VREF (VIN – 1.6) / RIN Input range = 3 × VREF (VIN – 2.6) / RIN Input range = 2.5 × VREF (VIN – 2.5) / RIN Input range = 1.5 × VREF (VIN – 2.7) / RIN Input range = 1.25 × VREF (VIN – 2.5) / RIN V MΩ ppm/°C µA INPUT OVERVOLTAGE PROTECTION CIRCUIT VOVP All input ranges AVDD = 5 V or offers low impedance < 30 kΩ, all input ranges –20 20 AVDD = floating with impedance > 30 kΩ, all input ranges –11 11 V INPUT BANDWIDTH f–3 dB f–0.1 dB (1) 6 Small-signal Input bandwidth –3 dB All input ranges 15 –0.1 dB All input ranges 2.5 kHz Ideal input span, does not include gain or offset error. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 Electrical Characteristics (continued) all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYSTEM PERFORMANCE Resolution 16 NMC No missing codes 16 DNL Differential nonlinearity (2) All input ranges All bipolar ranges (3) INL Integral nonlinearity EO EG (2) All unipolar ranges (4) Bits Bits –0.7 ±0.4 0.7 –1.2 ±0.5 1.2 ADS8681 –1.5 ±0.5 1.5 ADS8685, ADS8689 –1.2 ±0.5 1.2 All bipolar ranges (3) –1 ±0.2 1 All unipolar ranges (4) –2 ±0.2 2 Offset error (5) At TA = 25°C Offset error drift with temperature All input ranges Gain error (6) At TA = 25°C, all input ranges Gain error drift with temperature (7) All input ranges LSB LSB mV –3 ±0.75 3 –0.025 ±0.01 0.025 ppm/°C %FSR –5 ±1 5 ppm/°C 90.25 92 90.5 92 90.25 92 DYNAMIC CHARACTERISTICS Input range = ±3 × VREF ADS8681 Input range = ±2.5 × VREF ADS8681 ADS8685, ADS8689 ADS8685, ADS8689 90.5 92 89.5 91.5 Input range = ±1.25 × VREF 89.5 91.5 Input range = ±0.625 × VREF 87.75 90 Input range = 3 × VREF Input range = ±1.5 × VREF Signal-to-noise ratio (8) SNR 89.25 91 Input range = 2.5 × VREF 89 91 Input range = 1.5 × VREF 88 90 Input range = 1.25 × VREF Total harmonic distortion (9) (8) THD Signal-to-noise + distortion (8) All input ranges –107 ADS8685, ADS8689 –112 Input range = ±3 × VREF ADS8681 Input range = ±2.5 × VREF ADS8681 ADS8685, ADS8689 ADS8685, ADS8689 (2) (3) (4) (5) (6) (7) (8) (9) Spurious-free dynamic range (8) 90.15 92 90.4 92 90.15 92 90.4 92 89.4 91.5 Input range = ±1.25 × VREF 89.4 91.5 Input range = ±0.625 × VREF 87.65 90 Input range = 3 × VREF SFDR 90 ADS8681 Input range = ±1.5 × VREF SINAD 87.5 89 91 Input range = 2.5 × VREF 88.75 91 Input range = 1.5 × VREF 87.75 90 Input range = 1.25 × VREF 87.25 All input ranges dB dB dB 90 ADS8681 109 ADS8685, ADS8689 114 dB This specification indicates the endpoint INL, not best-fit INL. Bipolar ranges are ±12.288 V, ±10.24 V, ±6.144 V, ±5.12 V, and ±2.56 V. Unipolar ranges are 0 V–12.288 V, 0 V–10.24 V, 0 V–6.144 V, and 0 V–5.12 V. Measured relative to actual measured reference. Excludes internal reference accuracy error. Excludes internal reference temperature drift. All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with a 1-kHz input signal 0.25 dB below full-scale, unless otherwise specified. Calculated on the first nine harmonics of the input frequency. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 7 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com Electrical Characteristics (continued) all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SAMPLING DYNAMICS tCONV Conversion time tACQ Acquisition time Maximum throughput rate without latency fcycle ADS8681 665 ADS8685 1000 ADS8689 5000 ADS8681 335 ADS8685 1000 ADS8689 5000 ns ns ADS8681 1000 ADS8685 500 ADS8689 100 kSPS INTERNAL REFERENCE OUTPUT VREFIO On the REFIO pin (configured as an output) dVREFIO/dTA Internal reference temperature drift COUT_REFIO Decoupling capacitor on REFIO pin VREFCAP Reference voltage to the ADC (on the REFCAP pin) TSSOP (PW) 4.095 4.096 4.097 WQFN (RUM) 4.094 4.096 4.098 TSSOP (PW) 4 7 WQFN (RUM) 5 At TA = 25°C 4.7 At TA = 25°C 4.095 REFCAP temperature drift COUT_REFCAP Decoupling capacitor on REFCAP pin Turn-on time ppm/°C µF 4.096 4.097 0.5 2 10 COUT_REFCAP = 10 µF, COUT_REFIO = 10 µF V V ppm/°C μF 20 ms EXTERNAL REFERENCE INPUT VREFIO_EXT External reference voltage on REFIO REFIO pin configured as an input 4.046 4.096 4.146 V AVDD COMPARATOR VTH_HIGH High threshold voltage 5.3 V VTH_LOW Low threshold voltage 4.7 V POWER-SUPPLY REQUIREMENTS AVDD Analog power-supply voltage DVDD Digital power-supply voltage IAVDD_DYN IAVDD_STC 5 5.25 1.65 3.3 AVDD 2.7 3.3 AVDD ADS8681 8.2 10.5 ADS8685 5.6 7.25 ADS8689 4 5 ADS8681 7.0 8.75 ADS8685 4.4 5.5 ADS8689 2.7 3.25 Internal reference ADS8681 4.7 6.25 ADS8685, ADS8689 3.5 4.7 External reference ADS8681 3.5 4.5 ADS8685, ADS8689 2.3 3 Supply range for specified performance Analog supply current, device converting at maximum throughput Analog supply current, device not converting 4.75 Operating range Internal reference External reference V mA mA IAVDD_STDBY Analog supply current, device in STANDBY mode Internal reference 2.8 External reference 1.6 IAVDD_PD Analog supply current, device in PD mode Internal reference 10 External reference 10 IDVDD_DYN Digital supply current, maximum throughput IDVDD_STDBY Digital supply current, device in STANDBY mode 1 μA IDVDD_PD Digital supply current, device in PD mode 1 μA 8 Submit Documentation Feedback 0.2 mA μA 0.25 mA Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 Electrical Characteristics (continued) all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (CMOS) VIH VIL DVDD > 2.35 V 0.7 × DVDD DVDD + 0.3 DVDD ≤ 2.35 V 0.8 × DVDD DVDD + 0.3 DVDD > 2.35 V –0.3 0.3 × DVDD DVDD ≤ 2.35 V –0.3 0.2 × DVDD Digital high input voltage logic level Digital low input voltage logic level V V Input leakage current 100 nA Input pin capacitance 5 pF DIGITAL OUTPUTS (CMOS) VOH Digital high output voltage logic level IO = 500-μA source VOL Digital low output voltage logic level IO = 500-μA sink Floating state leakage current Only for digital output pins 0.8 × DVDD DVDD V 0 0.2 × DVDD V Internal pin capacitance 1 µA 5 pF TEMPERATURE RANGE TA Operating free-air temperature Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 –40 125 Submit Documentation Feedback °C 9 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 6.6 Timing Requirements: Conversion Cycle all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) MIN TYP MAX UNIT TIMING REQUIREMENTS fcycle Sampling frequency tcycle ADC cycle time period tacq Acquisition time ADS8681 1000 ADS8685 500 ADS8689 100 kSPS 1/fcycle ADS8681 335 ADS8685 1000 ADS8689 5000 ns TIMING SPECIFICATIONS tconv Conversion time ADS8681 665 ADS8685 1000 ADS8689 5000 ns 6.7 Timing Requirements: Asynchronous Reset all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) MIN TYP MAX UNIT TIMING REQUIREMENTS twl_RST Pulse duration: RST high 100 ns TIMING SPECIFICATIONS tD_RST_POR Delay time for POR reset: RST rising to RVS rising tD_RST_APP Delay time for application reset: RST rising to CONVST/CS rising tNAP_WKUP Wake-up time: NAP mode tPWRUP Power-up time: PD mode 20 ms 1 20 20 µs µs ms 6.8 Timing Requirements: SPI-Compatible Serial Interface all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) MIN TYP MAX UNIT 66.67 MHz TIMING REQUIREMENTS fCLK Serial clock frequency tCLK Serial clock time period tPH_CK SCLK high time 0.45 0.55 tCLK tPL_CK SCLK low time 0.45 0.55 tCLK tSU_CSCK Setup time: CONVST/CS falling to first SCLK capture edge 7.5 ns tSU_CKDI Setup time: SDI data valid to SCLK capture edge 7.5 ns tHT_CKDI Hold time: SCLK capture edge to (previous) data valid on SDI 7.5 ns tHT_CKCS Delay time: last SCLK capture edge to CONVST/CS rising 7.5 ns 1/fCLK TIMING SPECIFICATIONS tDEN_CSDO Delay time: CONVST/CS falling edge to data enable 9.5 ns tDZ_CSDO Delay time: CONVST/CS rising to SDO-x going to 3-state 10 ns tD_CKDO Delay time: SCLK launch edge to (next) data valid on SDO-x 12 ns tD_CSRVS Delay time: CONVST/CS rising edge to RVS falling 14 ns 10 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 6.9 Timing Requirements: Source-Synchronous Serial Interface (External Clock) all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) MIN TYP MAX UNIT 66.67 MHz TIMING REQUIREMENTS fCLK Serial clock frequency tCLK Serial clock time period tPH_CK SCLK high time 0.45 0.55 tCLK tPL_CK SCLK low time 0.45 0.55 tCLK 1/fCLK TIMING SPECIFICATIONS tDEN_CSDO Delay time: CONVST/CS falling edge to data enable 9.5 ns tDZ_CSDO Delay time: CONVST/CS rising to SDO-x going to 3-state 10 ns tD_CKRVS_r Delay time: SCLK rising edge to RVS rising 14 ns tD_CKRVS_f Delay time: SCLK falling edge to RVS falling 14 ns tD_RVSDO Delay time: RVS rising to (next) data valid on SDO-x 2.5 ns tD_CSRVS Delay time: CONVST/CS rising edge to RVS displaying internal device state 15 ns 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock) all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) MIN TYP MAX UNIT TIMING SPECIFICATIONS tDEN_CSDO Delay time: CONVST/CS falling edge to data enable 9.5 ns tDZ_CSDO Delay time: CONVST/CS rising to SDO-x going to 3-state 10 ns tDEN_CSRVS Delay time: CONVST/CS falling edge to first rising edge on RVS 50 ns tD_RVSDO Delay time: RVS rising to (next) data valid on SDO-x 2.5 ns tINTCLK Time period: internal clock 15 tCYC_RVS Time period: RVS signal 15 tWH_RVS RVS high time 0.4 0.6 tINTCLK tWL_RVS RVS low time 0.4 0.6 tINTCLK tD_CSRVS Delay time: CONVST/CS rising edge to RVS displaying internal device state 15 ns Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ns ns Submit Documentation Feedback 11 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com The CS falling edge can be issued after tconv_max or when RVS goes high. tcycle CONVST/CS tconv tacq ADCST (Internal) RVS Figure 1. Conversion Cycle Timing Diagram trst twl_RST RST td_rst RVS Figure 2. Asynchronous Reset Timing Diagram tcycle tconv_max Data Read Time CONVST/CS tD_CSRVS tD_CSRVS RVS tHT_CKCS tSU_CSCK CPOL = 0 SCLK CPOL = 1 tD_CSDO tD_CKDO tDEN_CSDO SDO-0 M M-1 M-2 L+1 L tSU_CKDI tHT_CKDI SDI Figure 3. Standard SPI Interface Timing Diagram for CPHA = 0 12 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 tcycle Data Read Time tconv_max CONVST/CS tD_CSRVS tD_CSRVS RVS tHT_CKCS tSU_CSCK CPOL = 0 SCLK CPOL = 1 tD_CKDO tDEN_CSDO SDO-0 0 M M-1 L+1 tDZ_CSDO L tSU_CKDI tHT_CKDI SDI Figure 4. Standard SPI Interface Timing Diagram for CPHA = 1 tcycle tconv_max Data Read Time CONVST/CS tD_CSRVS tD_CSRVS RVS tHT_CKCS tSU_CSCK CPOL = 0 SCLK CPOL = 1 tD_CSDO tD_CKDO tDEN_CSDO SDO-0 M M-2 M-4 L+3 L+1 SDO-1 M-1 M-3 M-5 L+2 L tSU_CKDI tHT_CKDI SDI Figure 5. multiSPI Interface Timing Diagram for Dual SDO-x and CPHA = 0 Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 13 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com tcycle tconv_max Data Read Time CONVST/CS tD_CSRVS tD_CSRVS RVS tHT_CKCS tSU_CSCK CPOL = 0 SCLK CPOL = 1 tD_CKDO tDEN_CSDO SDO-0 tDZ_CSDO 0 M M-2 L+3 L+1 0 M-1 M-1 L+2 L SDO-1 tSU_CKDI tHT_CKDI SDI Figure 6. multiSPI Interface Timing Diagram for Dual SDO-x and CPHA = 1 tconv Data Read Time CONVST/CS tSU_CSCK SCLK tDEN_CSDO SDO-0 tD_CSRD tDZ_CSDO tD_RVSDO M M-1 M-k M-k-1 L+1 M-k-2 tD_CKRVS_r tD_CKRVS_f L tD_CSRVS RVS Figure 7. multiSPI Source-Synchronous External Clock Serial Interface Timing Diagram tconv_max Data Read Time CONVST/CS SCLK tDEN_CSDO SDO-0 tDZ_CSDO M tDEN_CSRVS M-1 M-k tD_RVSDO M-k-1 M-k-2 tWH_RVS L+1 L tD_CSRVS RVS tCYC_RVS tWL_RVS Figure 8. multiSPI Source-Synchronous Internal Clock Serial Interface Timing Diagram 14 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 6.11 Typical Characteristics at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) 15 ± 12.288 V ± 10.24 V ± 6.144 V ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V 9 3 Analog Input Current (uA) Analog Input Current (uA) 15 -3 -9 -15 -12.288 -8.192 -4.096 0 4.096 Input Voltage (V) 8.192 -40C 25C 125C 9 3 -3 -9 -15 -12.288 12.288 -8.192 D001 -4.096 0 4.096 Input Voltage (V) 8.192 12.288 D002 Range = ±12.288 V Figure 9. Input I-V Characteristic Across Input Ranges Figure 10. Input I-V Characteristic Across Temperature 1600 400 1200 200 Number of Devices Input Impedance Drift (ppm) 1400 0 ±12.288 V ±10.24 V ±6.144 V ±5.12 V ±2.56 V -200 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V 1000 800 600 400 200 0 -400 -40 -7 26 59 Free- Air Temperature (qC) 92 1.02 1.06 125 1.1 D003 1.14 1.18 1.22 1.26 Input Impedance (M:) 1.3 1.34 1.38 D004 Number of samples = 3398 Figure 12. Typical Distribution of Input Impedance 45000 40000 40000 35000 35000 30000 30000 Number of Hits Number of Hits Figure 11. Input Impedance Drift vs Temperature 45000 25000 20000 15000 25000 20000 15000 10000 10000 5000 5000 0 0 32766 32767 32768 32769 Output Codes 32770 32766 32771 32767 D007 Mean = 32768.24, sigma = 0.57, input = 0 V Figure 13. DC Histogram for Mid-Scale Inputs (±12.288 V) 32768 32769 Output Codes 32770 32771 D008 D003 Mean = 32767.24, sigma = 0.56, input = 0 V Figure 14. DC Histogram for Mid-Scale Inputs (±10.24 V) Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 15 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com Typical Characteristics (continued) at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) 40000 45000 Number of Hits Number of Hits 30000 20000 30000 15000 10000 0 0 32766 32767 32768 32769 32770 32771 32772 Output Codes 32766 Mean = 32768.21, sigma = 0.62, input = 0 V Figure 15. DC Histogram for Mid-Scale Inputs (±6.144 V) 32772 D010 Figure 16. DC Histogram for Mid-Scale Inputs (±5.12 V) 40000 24000 Number of Hits Number of Hits 32771 50000 30000 18000 12000 30000 20000 10000 6000 0 0 32765 32765 32766 32767 32768 32769 32770 32771 32772 Output Codes D011 Mean = 32768.22, sigma = 0.75, input = 0 V 32766 32767 32768 32769 Output Codes 32770 32771 D012 Mean = 32767.73, sigma = 0.60, input = 6.144 V Figure 17. DC Histogram for Mid-Scale Inputs (±2.56 V) Figure 18. DC Histogram for Mid-Scale Inputs (0 V–12.288 V) 40000 40000 30000 30000 Number of Hits Number of Hits 32768 32769 32770 Output Codes Mean = 32768.11, sigma = 0.62, input = 0 V 36000 20000 10000 20000 10000 0 0 32766 32767 32768 32769 32770 Output Codes 32771 32772 Mean = 32768.41, sigma = 0.62, input = 5.12 V Figure 19. DC Histogram for Mid-Scale Inputs (0 V–10.24 V) 16 32767 D009 Submit Documentation Feedback 32766 32767 D013 32768 32769 32770 Output Codes 32771 32772 D014 Mean = 32768.42, sigma = 0.76, input = 3.072 V Figure 20. DC Histogram for Mid-Scale Inputs (0 V–6.144 V) Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 Typical Characteristics (continued) at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) 40000 Differential Nonlinearity (LSB) 0.7 Number of Hits 30000 20000 10000 0 0.5 0.3 0.1 -0.1 -0.3 -0.5 -0.7 32766 32767 32768 32769 32770 Output Codes 32771 32772 0 16384 D015 Mean = 32768.32, sigma = 0.78, input = 2.56 V 49152 65535 D016 All input ranges Figure 21. DC Histogram for Mid-Scale Inputs (0 V–5.12 V) Figure 22. Typical DNL for All Codes 1.2 0.7 Maximum Minimum 0.5 0.8 Integral Nonlinearity (LSB) Differential Nonlinearity (LSB) 32768 Codes (LSB) 0.3 0.1 -0.1 -0.3 0.4 0 -0.4 -0.8 -0.5 -0.7 -40 -1.2 -7 26 59 Free-Air Temperature (0C) 92 125 0 16384 D017 32768 Codes (LSB) 49152 65535 D018 All input ranges Figure 23. DNL vs Temperature Figure 24. Typical INL for All Codes (All Bipolar Ranges) 1.5 1.2 Maximum Minimum Integral Nonlinearity (LSB) Integral Nonlinearity (LSB) 1 0.5 0 -0.5 0.6 0 -0.6 -1 -1.5 0 16384 32768 Codes (LSB) 49152 65536 D023 Figure 25. Typical INL for All Codes (All Unipolar Ranges) -1.2 -40 -7 26 59 Free-Air Temperature (0C) 92 125 D027 Figure 26. INL vs Temperature (All Bipolar Ranges) Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 17 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com Typical Characteristics (continued) at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) 1.5 1 ± 12.288 V ± 10.24 V ± 6.144 V 0.75 0.75 ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V 0.5 Offset Error (mV) Integral Nonlinearity (LSB) Maximum Minimum 0 -0.75 0.25 0 -0.25 -0.5 -0.75 -1.5 -40 -7 26 59 Free-Air Temperature (0C) 92 -1 -40 125 Figure 27. INL vs Temperature (All Unipolar Ranges) 92 125 D036 0.025 ± 12.288 V ± 10.24 V ± 6.144 V 0.015 Gain Error (%FSR) 10 Number of Devices 26 59 Free-Air Temperature (0C) Figure 28. Offset Error vs Temperature Across Input Ranges 12.5 7.5 5 ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V 0.005 -0.005 -0.015 2.5 -0.025 -40 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3 Offset Drift (ppm/ºC) -7 26 59 Free-Air Temperature (0C) D037 Figure 29. Typical Histogram for Offset Drift 92 125 D038 Figure 30. Gain Error vs Temperature Across Input Ranges 1.1 25 ± 12.288 V ± 10.24 V ± 6.144 V ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V 1 0.9 20 Gain Error (%FSR) 0.8 Number of Units -7 D032 15 10 0.7 0.6 0.5 0.4 0.3 0.2 5 0.1 0 -0.1 0 0 0.5 1 1.5 2 2.5 3 3.5 Gain Drift (ppm/ºC) 4 4.5 0 5 Figure 31. Typical Histogram for Gain Error Drift 18 Submit Documentation Feedback 2000 4000 6000 Source Resistance (:) D039 8000 10000 D040 Figure 32. Gain Error vs External Resistance (REXT) Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 Typical Characteristics (continued) 0 0 -40 -40 Amplitude (dB) Amplitude (dB) at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) -80 -120 -160 -80 -120 -160 -200 -200 0 100000 200000 300000 Input Frequency (Hz) 400000 500000 0 Number of points = 64k, fIN = 1 kHz 100000 150000 Input Frequency (Hz) 200000 250000 D001 Number of points = 64k, fIN = 1 kHz Figure 33. Typical FFT Plot (All Ranges) for the ADS8681 Figure 34. Typical FFT Plot (All Ranges) for the ADS8685 0 94.5 Signal-to-Noise Ratio (dB) -40 Amplitude (dB) 50000 D041 -80 -120 -160 -200 0 20000 40000 60000 Input Frequency (Hz) 80000 ± 12.288 V ± 10.24 V ± 6.144 V 0-10.24 V 0-6.144 V 0-5.12 V 93 91.5 90 88.5 100 100000 ± 5.12 V ± 2.56 V 0-12.288 V 1000 Input Frequency (Hz) D002 10000 D050 Number of points = 64k, fIN = 1 kHz Figure 35. Typical FFT Plot (All Ranges) for the ADS8689 Figure 36. SNR vs Input Frequency 96 94 Signal-to-Noise Ratio (dB) ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V Signal-to-Noise + Distortion Ratio (dB) ± 12.288 V ± 10.24 V ± 6.144 V 95 94 93 92 91 90 89 88 -40 -7 26 59 Free-Air Temperature (0C) 92 125 93 ± 12.288 V ± 10.24 V ± 6.144 V ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V 92 91 90 89 88 100 1000 Input Frequency (Hz) D051 10000 D052 fIN = 1 kHz Figure 37. SNR vs Temperature Figure 38. SINAD vs Input Frequency Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 19 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com Typical Characteristics (continued) at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) -80 ± 12.288 V ± 10.24 V ± 6.144 V 95 ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V Total Harmonic Distortion Ratio (dB) Signal-to-Noise + Distortion Ratio (dB) 96 94 93 92 91 90 89 88 -40 -7 26 59 Free-AirTemperature (0C) 92 ±12.288 V ±10.24 V ±6.144 V 0-10.24 V 0-6.144 V 0-5.12 V -90 -100 -110 -120 100 125 ±5.12 V ±2.56 V 0-12.288 V 1000 Input Frequency (Hz) D053 10000 D054 fIN = 1 kHz Figure 39. SINAD vs Temperature Figure 40. THD vs Input Frequency 9 ± 12.288 V ± 10.24 V ± 6.144 V ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V 8 -90 IAVDD Dynamic (mA) Total Harmonic Distortion (dB) -80 -100 -110 7 6 5 4 3 ADS8681 ADS8685 ADS8689 2 -120 -40 -7 26 59 Free-Air Temperature (0C) 92 1 -40 125 -7 D055 26 59 Free-Air Temperature (qC) 92 125 D003 fIN = 1 kHz Figure 41. THD vs Temperature Figure 42. AVDD Current vs Temperature 9 5 8 4.5 IAVDD Static (mA) IAVDD Current (mA) 7 6 5 4 4 3.5 3 3 2 1 0 200 400 600 Throughput (ksps) 800 Figure 43. AVDD Current vs Throughput 20 ADS8681 ADS8685 ADS8689 ADS8681 ADS8685 Submit Documentation Feedback 1000 D005 2.5 -40 -7 26 59 Free-Air Temperature (qC) 92 125 D004 Figure 44. AVDD Current vs Temperature (During Sampling) Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 Typical Characteristics (continued) at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted) 3 2.8 ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V ± 12.288 V ± 10.24 V ± 6.144 V 2.5 ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V 2.7 IAVDD PD (uA) IAVDD Standby (mA) ± 12.288 V ± 10.24 V ± 6.144 V 2.6 2 1.5 1 2.5 0.5 2.4 -40 -7 26 59 Free-Air Temperature (0C) 92 Figure 45. AVDD Current vs Temperature (Standby Mode) 125 D067 0 -40 -7 26 59 Free-Air Temperature (0C) 92 125 D068 Figure 46. AVDD Current vs Temperature (Power-Down Mode) Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 21 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 7 Detailed Description 7.1 Overview The ADS868x devices belong to a family of high-speed, high-performance, easy-to-use integrated data acquisition system. This single-channel device supports true bipolar input voltage swings up to ±12.288 V, operating on a single 5-V analog supply. The device features an enhanced SPI interface (multiSPI) that allows the sampling rate to be maximized even with lower speed host controllers. The device consists of a high-precision successive approximation register (SAR) analog-to-digital converter (ADC) and a power-optimized analog front-end (AFE) circuit for signal conditioning that includes: • A high-resistive input impedance (≥ 1 MΩ) that is independent of the sampling rate • A programmable gain amplifier (PGA) with a pseudo-differential input configuration supporting nine softwareprogrammable unipolar and bipolar input ranges • A second-order, low-pass antialiasing filter • An ADC driver amplifier that ensures quick settling of the SAR ADC input for high accuracy • An input overvoltage protection circuit up to ±20 V The device also features a low temperature drift, 4.096-V internal reference with a fast-settling buffer and a multiSPI serial interface with daisy-chain (DAISY) and ALARM features. The integration of the multichannel precision AFE circuit with high input impedance and a precision ADC operating from a single 5-V supply offers a simplified end solution without requiring external high-voltage bipolar supplies and complicated driver circuits. 7.2 Functional Block Diagram DVDD AVDD REFIO ADS868x 4.096-V Reference REFCAP CONVST/CS 1 M: SCLK OVP AIN_P PGA AIN_GND OVP 2nd-Order LPF ADC Driver Digital Logic and Interface 16-Bit SAR ADC SDI SDO 1 M: VBIAS AGND Oscillator DGND REFGND Copyright © 2016, Texas Instruments Incorporated 22 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 7.3 Feature Description 7.3.1 Analog Input Structure The device features a pseudo-differential input structure, meaning that the single-ended analog input signal is applied at the positive input AIN_P and the negative input AIN_GND is tied to GND. Figure 47 shows the simplified circuit schematic for the AFE circuit, including the input overvoltage protection circuit, PGA, low-pass filter (LPF), and high-speed ADC driver. 1 M: OVP AIN_P PGA AIN_GND OVP 2nd-Order LPF ADC Driver ADC 1 M: CONVST/CS SCLK SDI SDO VB Figure 47. Simplified Analog Front-End Circuit Schematic The device can support multiple unipolar or bipolar, single-ended input voltage ranges based on the configuration of the program registers. As explained in the RANGE_SEL_REG register, the input voltage range for each analog channel can be configured to bipolar ±3 × VREF, ±2.5 × VREF, ±1.5 × VREF, ±1.25 × VREF, and ±0.625 × VREF or unipolar 0 to 3 × VREF, 0 to 2.5 × VREF, 0 to 1.5 × VREF and 0 to 1.25 × VREF. With the internal or external reference voltage set to 4.096 V, the input ranges of the device can be configured to bipolar ranges of ±12.288 V, ±10.24 V, ±6.144 V, ±5.12 V, and ±2.56 V or unipolar ranges of 0 V to 12.288 V, 0 V to 10.24 V, 0 V to 6.144 V, and 0 V to 5.12 V. The device samples the voltage difference (AIN_P – AIN_GND) between the analog input and the AIN_GND pin. The device allows a ±0.1-V range on the AIN_GND pin. This feature is useful in modular systems where the sensor or signal-conditioning block is further away from the ADC on the board and when a difference in the ground potential of the sensor or signal conditioner from the ADC ground is possible. In such cases, running separate wires from the AIN_GND pin of the device to the sensor or signal-conditioning ground is recommended. In order to obtain optimum performance, the input currents and impedances along each input path are recommended to be matched. The two single-ended signals to AIN_P and AIN_GND must be routed as symmetrically as possible from the signal source to the ADC input pins. If the analog input pin (AIN_P) to the device is left floating, the output of the ADC corresponds to an internal biasing voltage. The output from the ADC must be considered as invalid if the device is operated with floating input pins. This condition does not cause any damage to the device, which becomes fully functional when a valid input voltage is applied to the pins. 7.3.2 Analog Input Impedance The device presents a resistive input impedance ≥ 1 MΩ on each of the analog inputs. The input impedance is independent of the ADC sampling frequency or the input signal frequency. The primary advantage of such highimpedance inputs is the ease of driving the ADC inputs without requiring driving amplifiers with low output impedance. Bipolar, high-voltage power supplies are not required in the system because this ADC does not require any high-voltage, front-end drivers. In most applications, the signal sources or sensor outputs can be directly connected to the ADC input, thus significantly simplifying the design of the signal chain. In order to maintain the dc accuracy of the system, matching the external source impedance on the AIN_P input pin with an equivalent resistance on the AIN_GND pin is recommended. This matching helps cancel any additional offset error contributed by the external resistance. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 23 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com Feature Description (continued) 7.3.3 Input Protection Circuit The device features an internal overvoltage protection (OVP) circuit on each of the analog inputs. Use the internal protection circuit only as a secondary protection scheme. The external protection devices in the end application are highly recommended to be used to protect against surges, electrostatic discharge (ESD), and electrical fast transient (EFT) conditions. A conceptual block diagram of the internal OVP circuit is shown in Figure 48. AVDD VP+ RFB 0V ESD AVDD VP- RS 1 MŸ AIN_P D1p D2p RS V± AVDD AIN_GND VOUT D1n 1 MŸ V+ + D2n RDC ESD VB GND Figure 48. Input Overvoltage Protection Circuit Schematic As shown in Figure 48, the combination of the 1-MΩ (or, 1.2 MΩ for appropriate input ranges) input resistors along with the PGA gain-setting resistors RFB and RDC limit the current flowing into the input pin. A combination of anti-parallel diodes, D1 and D2 are added to protect the internal circuitry and set the overvoltage protection limits. Table 1 explains the various operating conditions for the device when powered on. This table indicates that when the device is properly powered up (AVDD = 5 V) or offers a low impedance of < 30 kΩ, the internal overvoltage protection circuit can withstand up to ±20 V on the analog input pins. Table 1. Input Overvoltage Protection Limits When AVDD = 5 V or Offers a Low Impedance of < 30 kΩ (1) INPUT CONDITION (VOVP = ±20 V) CONDITION RANGE TEST CONDITION ADC OUTPUT COMMENTS |VIN| < |VRANGE| Within operating range All input ranges Valid |VRANGE| < |VIN| < |VOVP| Beyond operating range but within overvoltage range All input ranges Saturated ADC output is saturated, but device is internally protected (not recommended for extended time). |VIN| > |VOVP| Beyond overvoltage range All input ranges Saturated This usage condition can cause irreversible damage to the device. (1) 24 Device functions as per data sheet specifications. GND = 0 V, AIN_GND = 0 V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the break-down voltage for the internal OVP circuit. Assume that RS is approximately 0 Ω. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 The results indicated in Table 1 are based on an assumption that the analog input pin is driven by a very low impedance source (RS is approximately 0 Ω). However, if the source driving the input has higher impedance, the current flowing through the protection diodes reduces further, thereby increasing the OVP voltage range. Note that higher source impedances result in gain errors and contribute to overall system noise performance. Figure 49 shows the voltage versus current response of the internal overvoltage protection circuit when the device is powered on. According to this current-to-voltage (I-V) response, the current flowing into the device input pin is limited by the 1-MΩ (or 1.2 MΩ for appropriate input ranges) input impedance. However, for voltages beyond ±20 V, the internal node voltages surpass the break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the input pin. The same overvoltage protection circuit also provides protection to the device when the device is not powered on and AVDD is floating with an impedance > 30 kΩ. This condition can arise when the input signals are applied before the ADC is fully powered on. The overvoltage protection limits for this condition are shown in Table 2. Table 2. Input Overvoltage Protection Limits When AVDD = Floating with Impedance > 30 kΩ (1) INPUT CONDITION (VOVP = ±11 V) CONDITION RANGE TEST CONDITION ADC OUTPUT COMMENTS |VIN| < |VOVP| Within overvoltage range All input ranges Invalid Device is not functional but is protected internally by the OVP circuit. |VIN| > |VOVP| Beyond overvoltage range All input ranges Invalid This usage condition can cause irreversible damage to the device. (1) AVDD = floating, GND = 0 V, AIN_GND = 0 V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the break-down voltage for the internal OVP circuit. Assume that RS is approximately 0 Ω. Figure 50 shows the I-V response of the internal overvoltage protection circuit when the device is not powered on. According to this I-V response, the current flowing into the device input pin is limited by the 1-MΩ input impedance. However, for voltages beyond ±11 V, the internal node voltage surpasses the break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the input pin. 30 24 18 20 Input Current (uA) Input Current (uA) 12 10 0 -10 6 0 -6 -12 -20 -30 -30 -18 -24 -18 -12 -6 0 6 Input voltage (V) 12 18 24 Figure 49. I-V Curve for the Input OVP Circuit (AVDD = 5 V) 30 -24 -20 -16 -12 -8 D005 -4 0 4 Input voltage (V) 8 12 16 20 D006 Figure 50. I-V Curve for the Input OVP Circuit (AVDD = Floating) Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 25 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 7.3.4 Programmable Gain Amplifier (PGA) The device features a programmable gain amplifier (PGA) as part of the analog signal-conditioning circuit that converts the original single-ended input signal into a fully-differential signal to drive the internal SAR ADC. The PGA also adjusts the common-mode level of the input signal before feeding it into the SAR ADC to ensure maximum usage of the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can be adjusted by setting the RANGE_SEL[3:0] bits in the configuration register (see the RANGE_SEL_REG register). The default or power-on state for the RANGE_SEL[3:0] bits is 0000, corresponding to an input signal range of ±3 × VREF. Table 3 lists the various configurations of the RANGE_SEL[3:0] bits for the different analog input voltage ranges. The PGA uses a precisely-matched network of resistors for multiple gain configurations. Matching between these resistors is accurately trimmed to keep the overall gain error low across all input ranges. Table 3. Input Range Selection Bits Configuration RANGE_SEL[3:0] ANALOG INPUT RANGE BIT 3 BIT 2 BIT 1 BIT 0 ±3 × VREF 0 0 0 0 ±2.5 × VREF 0 0 0 1 ±1.5 × VREF 0 0 1 0 ±1.25 × VREF 0 0 1 1 ±0.625 × VREF 0 1 0 0 0–3 × VREF 1 0 0 0 0–2.5 × VREF 1 0 0 1 0–1.5 × VREF 1 0 1 0 0–1.25 × VREF 1 0 1 1 7.3.5 Second-Order, Low-Pass Filter (LPF) In order to mitigate the noise of the front-end amplifier and gain resistors of the PGA, the AFE circuit of the device features a second-order, antialiasing LPF at the output of the PGA. The magnitude and phase response of the analog antialiasing filter are shown in Figure 51 and Figure 52, respectively. For maximum performance, the –3-dB cutoff frequency for the antialiasing filter is typically set to 15 kHz. The performance of the filter is consistent across all input ranges supported by the ADC. 45 3 0 Phase (Degree) Magnitude (dB) 0 -3 ±12.288 V ±10.24 V ±6.144 V ±5.12 V ±2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V -6 -9 -12 -15 10 100 -90 1k Input Frequency (Hz) 10k 100k Submit Documentation Feedback -135 10 ± 12.288 V ± 10.24 V ± 6.144 V ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V 100 D058 Figure 51. Second-Order LPF Magnitude Response 26 -45 1k Input Frequency (Hz) 10k 100k D059 Figure 52. Second-Order LPF Phase Response Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 7.3.6 ADC Driver In order to meet the performance of the device at the maximum sampling rate, the sample-and-hold capacitors at the input of the ADC must be successfully charged and discharged during the acquisition time window. This drive requirement at the input of the ADC necessitates the use of a high-bandwidth, low-noise, and stable amplifier buffer. Such an input driver is integrated in the front-end signal path of the analog input channel of the device. 7.3.7 Reference The device can operate with either an internal voltage reference or an external voltage reference using the internal buffer. The internal or external reference selection is determined by programming the INTREF_DIS bit of the RANGE_SEL_REG register. The internal reference source is enabled (INTREF_DIS = 0) by default after reset or when the device powers up. The INTREF_DIS bit must be programmed to logic 1 to disable the internal reference source whenever an external reference source is used. 7.3.7.1 Internal Reference The device features an internal reference source with a nominal output value of 4.096 V. In order to select the internal reference, the INTREF_DIS bit of the RANGE_SEL_REG register must be programmed to logic 0. When the internal reference is used, the REFIO pin becomes an output with the internal reference value. A 4.7-µF (minimum) decoupling capacitor is recommended to be placed between the REFIO pin and REFGND, as shown in Figure 53. The capacitor must be placed as close to the REFIO pin as possible. The output impedance of the internal band-gap circuit creates a low-pass filter with this capacitor to band-limit the noise of the reference. The use of a smaller capacitor value allows higher reference noise in the system that can potentially degrade SNR and SINAD performance. The REFIO pin must not be used to drive external ac or dc loads because of limited current output capability. The REFIO pin can be used as a source if followed by a suitable op amp buffer (such as the OPA320). AVDD 4.096 VREF RANGE_SEL_REG[6] = 0 (INTREF_DIS) REFIO 4.7 PF REFCAP 1 PF 10 PF REFGND ADC AGND Figure 53. Device Connections for Using an Internal 4.096-V Reference Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 27 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com The device internal reference is factory-trimmed to ensure the initial accuracy specification. The histogram in Figure 54 shows the distribution of the internal voltage reference output taken from more than 3420 production devices. 1000 900 Number of Devices 800 700 600 500 400 300 200 100 0 4.094 4.0945 4.095 4.0955 4.096 4.0965 4.097 4.0975 4.098 REFIO Voltage (V) D060 Figure 54. Internal Reference Accuracy Histogram at Room Temperature The initial accuracy specification for the internal reference can be degraded if the die is exposed to any mechanical or thermal stress. Heating the device when being soldered to a printed circuit board (PCB) and any subsequent solder reflow is a primary cause for shifts in the VREF value. The main cause of thermal hysteresis is a change in die stress and is therefore a function of the package, die-attach material, and molding compound, as well as the layout of the device itself. Number of Devices In order to illustrate this effect, 30 devices were soldered using lead-free solder paste with the manufacturer suggested reflow profile, as explained in application report AN-2029 Handling & Process Recommendations (SNOA550). The internal voltage reference output is measured before and after the reflow process and the typical shift in value is shown in Figure 55. Although all tested units exhibit a positive shift in their output voltages, negative shifts are also possible. Note that the histogram in Figure 55 shows the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, which is common on PCBs with surface-mount components on both sides, causes additional shifts in the output voltage. If the PCB is to be exposed to multiple reflows, solder the ADS868x in the second pass to minimize device exposure to thermal stress. 7 6.5 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -7 -6 -5 -4 -3 -2 -1 Error in REFIO Voltage (mV) 0 1 D070 Figure 55. Solder Heat Shift Distribution Histogram 28 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 The internal reference is also temperature compensated to provide excellent temperature drift over an extended industrial temperature range of –40°C to +125°C. Figure 56 and Figure 57 show the variation of the internal reference voltage across temperature for different values of the AVDD supply voltage. Note that the temperature drift of the internal reference is also a function of the package type. Figure 58 and Figure 59 show histogram distribution of the reference voltage drift for the TSSOP (PW) and WQFN (RUM) packages, respectively. 4.1 4.097 AVDD = 5.25 V AVDD = 5 V AVDD = 4.75 V REFIO Voltage (V) - TSSOP 4.099 REFIO Voltage (V) - QFN 4.098 AVDD = 5.25 V AVDD = 5 V AVDD = 4.75 V 4.096 4.097 4.096 4.095 4.094 4.093 4.092 4.095 4.094 4.093 4.092 4.091 4.09 4.091 4.09 -40 -7 26 59 Free-Air Temperature (0C) 92 125 4.089 -40 -7 D061 Figure 56. REFIO Voltage Variation Across AVDD and Temperature (PW Package) 26 59 Free-Air Temperature (0C) 92 125 D612 Figure 57. REFIO Voltage Variation Across AVDD and Temperature (RUM Package) 8 14 6 10 Number of Devices Number of Devices 12 8 6 4 4 2 2 0 0 3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.9 REFIO Drift (ppm/ºC) 6.3 6.7 7.1 D062 AVDD = 5 V, number of devices = 30, ΔT = –40°C to +125°C Figure 58. Internal Reference Temperature Drift Histogram (PW Package) 2.2 3 3.8 4.6 5.4 6.2 7 7.8 8.6 9.4 10.2 11 REFIO Drift (ppm/ºC) D622 AVDD = 5 V, number of devices = 30, ΔT = –40°C to +125°C Figure 59. Internal Reference Temperature Drift Histogram (RUM Package) Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 29 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 7.3.7.2 External Reference For applications that require a better reference voltage or a common reference voltage for multiple devices, the device provides a provision to use an external reference source along with an internal buffer to drive the ADC reference pin. In order to select the external reference mode, the INTREF_DIS bit of the RANGE_SEL_REG register must be programmed to logic 1. In this mode, an external 4.096-V reference must be applied at the REFIO pin, which functions as an input. Any low-power, low-drift, or small-size external reference can be used in this mode because the internal buffer is optimally designed to handle the dynamic loading on the REFCAP pin that is internally connected to the ADC reference input. The output of the external reference must be appropriately filtered to minimize the resulting effect of the reference noise on system performance. A typical connection diagram for this mode is shown in Figure 60. AVDD 4.096 VREF AVDD RANGE_SEL_REG[6] = 1 (INTREF_DIS) OUT REFIO REF5040 (See the device datasheet for a detailed pin configuration.) CREF REFCAP 1 PF 10 PF REFGND ADC AGND Figure 60. Device Connections for Using an External 4.096-V Reference The output of the internal reference buffer appears at the REFCAP pin. A minimum capacitance of 10 µF must be placed between the REFCAP and REFGND pins. Place another capacitor of 1 µF as close to the REFCAP pin as possible for decoupling high-frequency signals. Do not use the internal buffer to drive external ac or dc loads because of the limited current output capability of this buffer. 30 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 The performance of the internal buffer output is very stable across the entire operating temperature range of –40°C to +125°C. Figure 61 (for the PW package) and Figure 63 (for the RUM package) show the variation in the REFCAP output across temperature for different values of the AVDD supply voltage. The typical specified value of the reference buffer drift over temperature is 0.5 ppm/°C, as shown in Figure 62 (for the PW package) and Figure 64 (for the RUM package), and the maximum specified temperature drift is equal to 2 ppm/°C. 24 4.1 AVDD = 5.25 V AVDD = 5 V AVDD = 4.75 V 4.098 20 Number of Devices REFCAP Voltage (V) - TSSOP 4.099 4.097 4.096 4.095 4.094 4.093 4.092 16 12 8 4 4.091 4.09 -40 0 -7 26 59 Free-Air Temperature (0C) 92 0.2 125 0.4 0.6 D063 0.8 1.0 1.2 1.4 1.6 REFCAP Drift (ppm/ºC) 1.8 2.0 D064 AVDD = 5 V, number of devices = 30, ΔT = –40°C to +125°C Figure 61. Reference Buffer Output (REFCAP) Variation vs Supply and Temperature (PW Package) Figure 62. Reference Buffer Temperature Drift Histogram (PW Package) 4.098 18 AVDD = 5.25 V AVDD = 5 V AVDD = 4.75 V 16 14 4.096 Number of Devices REFCAP Voltage (V) - QFN 4.097 4.095 4.094 4.093 4.092 10 8 6 4 4.091 4.09 -40 12 2 0 -7 26 59 Free-Air Temperature (0C) 92 125 0.2 0.4 0.6 D632 0.8 1.0 1.2 1.4 1.6 REFCAP Drift (ppm/ºC) 1.8 2.0 D642 WQFN (RUM) package, AVDD = 5 V, number of devices = 30, ΔT = –40°C to +125°C Figure 63. Reference Buffer Output (REFCAP) Variation vs Supply and Temperature (RUM Package) Figure 64. Reference Buffer Temperature Drift Histogram (RUM Package) Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 31 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 7.3.8 ADC Transfer Function The device supports a pseudo-differential input supporting both bipolar and unipolar input ranges. The output of the device is in straight-binary format for both bipolar and unipolar input ranges. The ideal transfer characteristic for all input ranges is shown in Figure 65. The full-scale range (FSR) for each input signal is equal to the difference between the positive full-scale (PFS) input voltage and the negative fullscale (NFS) input voltage. The LSB size is equal to FSR / 216. For a reference voltage of VREF = 4.096 V, the LSB values corresponding to the different input ranges are listed in Table 4. ADC Output Code FFFFh 8000h 0001h 1 LSB NFS FSR / 2 FSR ± 1 LSB PFS Analog Input (AIN_P ± AIN_GND) Figure 65. Device Transfer Function (Straight-Binary Format) Table 4. ADC LSB Values for Different Input Ranges (VREF = 4.096 V) 32 INPUT RANGE POSITIVE FULL-SCALE (V) NEGATIVE FULL-SCALE (V) FULL-SCALE RANGE (V) LSB ±3 × VREF 12.288 –12.288 24.576 375.0 µV ±2.5 × VREF 10.24 –10.24 20.48 312.5 µV ±1.5 × VREF 6.144 –6.144 12.288 185.5 µV ±1.25 × VREF 5.12 –5.12 10.24 156.25 µV ±0.625 × VREF 2.56 –2.56 5.12 78.125 µV 0 to 3 × VREF 12.288 0 12.288 185.5 µV 0 to 2.5 × VREF 10.24 0 10.24 156.25 µV 0 to 1.5 × VREF 6.144 0 6.144 93.75 µV 0 to 1.25 × VREF 5.12 0 5.12 78.125 µV Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 7.3.9 Alarm Features The device features an active-high alarm output on the ALARM/SDO-1/GPO pin, provided that the pin is configured for alarm functionality. To enable the ALARM output on the multi-function pin, se the SDO1_CONFIG[1:0] bits of the SDO_CTL_REG register to 01b (see the SDO_CTL_REG register). The device features two types of alarm functions: an input alarm and an AVDD alarm. • For the input alarm, the voltage at the input of the ADC is monitored and compared against userprogrammable high and low threshold values. The device sets an active high alarm output when the corresponding digital value of the input signal goes beyond the high or low threshold set by the user; see the Input Alarm section for a detailed explanation of the input alarm feature functionality. • For the AVDD alarm, the analog supply voltage (AVDD) of the ADC is monitored and compared against the specified typical low threshold (4.7 V) and high threshold (5.3 V) values of the AVDD supply. The device sets an active high alarm output if the value of AVDD crosses the specified low (4.7 V) and high threshold (5.3 V) values in either direction. When the alarm functionality is turned on, both the input and AVDD alarm functions are enabled by default. These alarm functions can be selectively disabled by programming the IN_AL_DIS and VDD_AL_DIS bits (respectively) of the RST_PWRCTL_REG register. Each alarm (input alarm or AVDD alarm) has two types of alarm flags associated with it: the active alarm flag and the tripped alarm flag. All the alarm flags can be read in the ALARM_REG register. Both flags are set when the associated alarm is triggered. However while the active alarm is cleared at the end of the current ADC conversion (and set again if the alarm condition persists), the tripped flag is cleared only after ALARM_REG is read. The ALARM output flags are updated internally at the end of every conversion. These output flags can be read during any data frame that the user initiates by bringing the CONVST/CS signal to a low level. The ALARM output flags can be read in three different ways: either via the ALARM output pin, by reading the internal ALARM registers, or by appending the ALARM flags to the data output. • A high level on the ALARM pin indicates an over- or undervoltage condition on AVDD or on the analog input channel of the device. This pin can be wired to interrupt the host input. • The internal ALARM flag bits in the ALARM_REG register are updated at the end of conversion. After receiving an ALARM interrupt on the output pin, the internal alarm flag registers can be read to obtain more details on the conditions that generated the alarm. • The alarm output flags can be selectively appended to the data output bit stream (see the DATAOUT_CTL_REG register for configuration details). Figure 66 shows a functional block diagram for the device alarm functionality. AVDD High Alarm AVDD Low Alarm Input Alarm Threshold +/Hysteresis ALARM Other Input Alarm Input Active Alarm Flag + ADC Output ADCST Rising (End of Conversion) S Q R Q Input Tripped Alarm Flag Alarm Flag Read ADC SDO Figure 66. Alarm Functionality Schematic Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 33 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 7.3.9.1 Input Alarm The device features a high and a low alarm on the analog input. The alarms corresponding to the input signal have independently-programmable thresholds and a common hysteresis setting that can be controlled through the ALARM_H_TH_REG and ALARM_L_TH_REG registers. The device sets the input high alarm when the digital output exceeds the high alarm upper limit [high alarm threshold (T)]. The alarm resets when the digital output is less than or equal to the high alarm lower limit [high alarm (T) – H – 1). This function is shown in Figure 67. Alarm Threshold Alarm Threshold Similarly, the input low alarm is triggered when the digital output falls below the low alarm lower limit [low alarm threshold (T)]. The alarm resets when the digital output is greater than or equal to the low alarm higher limit [low alarm (T) + H + 1]. This function is shown in Figure 68. H_ALARM On H_ALARM Off (T ± H ± 1) (T) Figure 67. High ALARM Hysteresis L_ALARM On L_ALARM Off (T) ADC Output (T + H + 1) ADC Output Figure 68. Low ALARM Hysteresis 7.3.9.2 AVDD Alarm The device features a high and a low alarm on the analog voltage supply, AVDD. Unlike the input signal alarm, the AVDD alarm has fixed trip points that are set by design. The device features an internal analog comparator that constantly monitors the analog supply against the high and low threshold voltages. The high alarm is set if AVDD exceeds a typical value of 5.3 V and the low alarm is asserted if AVDD drops below 4.7 V. This feature is specially useful for debugging unusual device behavior caused by a glitch or brown-out condition on the analog AVDD supply. 34 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 7.4 Device Functional Modes The device features the multiSPI digital interface for communication and data transfer between the device and the host controller. The multiSPI interface supports many data transfer protocols that the host uses to exchange data and commands with the device. The host can transfer data into the device using one of the standard SPI modes. However, the device can be configured to output data in a number of ways to suit the application demands of throughput and latency. The data output in these modes can be controlled either by the host or the device, and the timing can either be system synchronous or source synchronous. For detailed explanation of the supported data transfer protocols, see the Data Transfer Protocols section. This section describes the main components of the digital interface module as well as supported configurations and protocols. As shown in Figure 69, the interface module is comprised of shift registers (both input and output), configuration registers, and a protocol unit. During any particular data frame, data are transferred both into and out of the device. As a result, the host always perceives the device as a 32-bit input-output shift register, as shown in Figure 69. Interface Module SDI Output Register (Data and Flags from Device) D31 D30 D1 D0 Unified Shift Register LSB LSB+1 MSB-1 MSB B31 B30 B1 B0 SDO-0 ADC RST CONVST Input Register Digital Control Logic Command Processor CS SCLK ALARM/SDO-1/GPO Configuration Registers SCLK Counter RVS Figure 69. Device Interface Module The Pin Configuration and Functions section provides descriptions of the interface pins; the Data Transfer Frame section details the functions of shift registers, the SCLK counter, and the command processor; the Data Transfer Protocols section details supported protocols; and the Register Maps section explains the configuration registers and bit settings. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 35 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com Device Functional Modes (continued) 7.4.1 Host-to-Device Connection Topologies The multiSPI interface and device configuration registers offer great flexibility in the ways a host controller can exchange data or commands with the device. This section describes how to select the hardware connection topology to meet different system requirements. 7.4.1.1 Single Device: All multiSPI Options Figure 70 shows the pin connection between a host controller and a stand-alone device to exercise all options provided by the multiSPI interface. DVDD Isolation (Optional) RST CONVST/CS SCLK Device Host Controller SDI SDO-0 ALARM/SDO-1/GPO RVS Figure 70. All multiSPI Protocols Pin Configuration 7.4.1.2 Single Device: Standard SPI Interface Figure 71 shows the minimum pin interface for applications using a standard SPI protocol. DVDD Isolation (Optional) RST (Optional) CONVST/CS SCLK Device Host Controller SDI SDO-0 ALARM/SDO-1/GPO RVS (Optional) Figure 71. Standard SPI Protocol Pin Configuration The CONVST/CS, SCLK, SDI, and SDO-0 pins constitute a standard SPI port of the host controller. The RST pin can be tied to DVDD. The RVS pin can be monitored for timing benefits. The ALARM/SDO-1/GPO pin may not have any external connection. 36 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 Device Functional Modes (continued) 7.4.1.3 Multiple Devices: Daisy-Chain Topology Host Controller RVS SDO-0 SDI SCLK RVS SDO-0 SCLK SDI Device 2 CONVST/CS Device 1 CONVST/CS RVS SDO-0 SDI SCLK CONVST/CS Isolation (Optional) SDI SDO SCLK CONVST/CS A typical connection diagram showing multiple devices in a daisy-chain topology is shown in Figure 72. Device N Figure 72. Daisy-Chain Connection Schematic The CONVST/CS and SCLK inputs of all devices are connected together and controlled by a single CONVST/CS and SCLK pin of the host controller, respectively. The SDI input pin of the first device in the chain (device 1) is connected to the SDO-x pin of the host controller, the SDO-0 output pin of device 1 is connected to the SDI input pin of device 2, and so forth. The SDO-0 output pin of the last device in the chain (device N) is connected to the SDI pin of the host controller. To operate multiple devices in a daisy-chain topology, the host controller must program the configuration registers in each device with identical values. The devices must operate with a single SDO-0 output, using the external clock with any of the legacy, SPI-compatible protocols for data read and data write operations. In the SDO_CTL_REG register, bits 7-0 must be programmed to 00h. All devices in the daisy-chain topology sample their analog input signals on the rising edge of the CONVST/CS signal and the data transfer frame starts with a falling edge of the same signal. At the launch edge of the SCLK signal, every device in the chain shifts out the MSB to the SDO-0 pin. On every SCLK capture edge, each device in the chain shifts in data received on its SDI pin as the LSB bit of the unified shift register; see Figure 69. Therefore, in a daisy-chain configuration, the host controller receives the data of device N, followed by the data of device N-1, and so forth (in MSB-first fashion). On the rising edge of the CONVST/CS signal, each device decodes the contents in its unified and takes appropriate action. For N devices connected in a daisy-chain topology, an optimal data transfer frame must contain 32 × N SCLK capture edges (see Figure 73). A shorter data transfer frame can result in an erroneous device configuration and must be avoided. For a data transfer frame with > 32 × N SCLK capture edges, the host controller must appropriately align the configuration data for each device before bringing CONVST/CS high. Note that the overall throughput of the system is proportionally reduced with the number of devices connected in a daisy-chain topology. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 37 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com Device Functional Modes (continued) A typical timing diagram for three devices connected in a daisy-chain topology and using the SPI-00-S protocol is shown in Figure 73. CONVST/CS SCLK 1 2 31 32 33 Configuration Data: Device 3 {SDO}HOST {SDI}1 B95 B94 34 63 64 65 Configuration Data: Device 2 B65 B64 B63 B62 66 95 96 Configuration Data: Device 1 B33 B32 B31 B30 B1 B0 Configuration Data: Device 2 {SDO-0}1 {SDI}2 {D31}1 {D30}1 {D1}1 {D0}1 B95 B94 B65 B64 B63 B62 B33 B32 Configuration Data: Device 3 {SDO-0}2 {SDI}3 {D31}2 {D30}2 {D1}2 {D0}2 {D31}1 Output Data: Device 3 {SDO-0}3 {SDI}HOST {D31}3 {D30}3 {D30}1 {D1}1 {D0}1 B95 Output Data: Device 2 {D1}3 {D0}3 {D31}2 {D30}2 B94 B65 B64 Output Data: Device 1 {D1}2 {D0}2 {D31}1 {D30}1 {D1}1 {D0}1 Figure 73. Three Devices in Daisy-Chain Mode Timing Diagram 7.4.2 Device Operational Modes As shown in Figure 74, the device supports three functional states: RESET, ACQ, and CONV. The device state is determined by the status of the CONVST/CS and RST control signals provided by the host controller. Power-Up ACQ CS T/ (R isi ng ) ge Ed RS n sio S NV CO d En o o fC RS er nv T (F al lin g T Ed (R ge isi ng Ed ge ) ) RST (Falling Edge) CONV RESET Figure 74. Device Functional States 38 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 Device Functional Modes (continued) 7.4.2.1 RESET State The device features an active-low RST pin that is an asynchronous digital input. In order to enter a RESET state, the RST pin must be pulled low and kept low for the twl_RST duration (as specified in the Timing Requirements: Asynchronous Reset table). The device features two different types of reset functions: an application reset or a power-on reset (POR). The functionality of the RST pin is determined by the state of the RSTn_APP bit in the RST_PWRCTL_REG register. • In order to configure the RST pin to issue an application reset, the RSTn_APP bit in the RST_PWRCTL_REG register must be configured to 1b. In this RESET state, all configuration registers (see the Register Maps section) are reset to their default values, the RVS pins remain low, and the SDO-x pins are tri-stated. • The default configuration for the RST pin is to issue a power-on reset when pulled to a low level. The RSTn_APP bit is set to 0b in this state. When a POR is issued, all internal circuitry of the device (including the PGA, ADC driver, and voltage reference) are reset. When the device comes out of the POR state, the tD_RST_POR time duration must be allowed for (see the Timing Requirements: Asynchronous Reset table) in order for the internal circuitry to accurately settle. In order to exit any of the RESET states, the RST pin must be pulled high with CONVST/CS and SCLK held low. After a delay of tD_RST_POR or tD_RST_APP (see the Timing Requirements: Asynchronous Reset table), the device enters ACQ state and the RVS pin goes high. To operate the device in any of the other two states (ACQ or CONV), the RST pin must be held high. With the RST pin held high, transitions on the CONVST/CS pin determine the functional state of the device. A typical conversion cycle is illustrated in Figure 1. 7.4.2.2 ACQ State In ACQ state, the device acquires the analog input signal. The device enters ACQ state on power-up, after any asynchronous reset, or after the end of every conversion. The falling edge of the RST falling edge takes the device from an ACQ state to a RESET state. A rising edge of the CONVST/CS signal takes the device from ACQ state to a CONV state. The device offers a low-power NAP mode to reduce power consumption in the ACQ state; see the NAP Mode section for more details on NAP mode. 7.4.2.3 CONV State The device moves from ACQ state to CONV state on the rising edge of the CONVST/CS signal. The conversion process uses an internal clock and the device ignores any further transitions on the CONVST/CS signal until the ongoing conversion is complete (that is, during the time interval of tconv). At the end of conversion, the device enters ACQ state. The cycle time for the device is given by Equation 1: t cycle-min tconv tacq-min (1) NOTE The conversion time, tconv, can vary within the specified limits of tconv_min and tconv_max (as specified in the Timing Requirements: Conversion Cycle table). After initiating a conversion, the host controller must monitor for a low-to-high transition on the RVS pin or wait for the tconv_max duration to elapse before initiating a new operation (data transfer or conversion). If RVS is not monitored, substitute tconv in Equation 1 with tconv_max. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 39 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 7.5 Programming The device features nine configuration registers (as described in the Register Maps section) and supports two types of data transfer operations: data write (the host configures the device), and data read (the host reads data from the device). 7.5.1 Data Transfer Frame A data transfer frame between the device and the host controller begins at the falling edge of the CONVST/CS pin and ends when the device starts conversion at the subsequent rising edge. The host controller can initiate a data transfer frame by bringing the CONVST/CS signal low (as shown in Figure 75) after the end of the CONV phase, as described in the CONV State section. Frame F CONVST/CS RVS As per output protocol selection. td_RVS SCLK N SCLKs SDI Valid Command SDO-x Data Output or OSR Contents SCLK Counter SCLK Counter 0 N Output Data Word Input Shift Register (ISR) D31 D0 B31 B0 D31 D0 B31 B0 Output Shift Register (OSR) Command Processor Figure 75. Data Transfer Frame 40 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 Programming (continued) For a typical data transfer frame F: 1. The host controller pulls CONVST/CS low to initiate a data transfer frame. On the falling edge of the CONVST/CS signal: – RVS goes low, indicating the beginning of the data transfer frame. – The internal SCLK counter is reset to 0. – The device takes control of the data bus. As illustrated in Figure 75, the contents of the output data word are loaded into the 32-bit output shift register (OSR). – The internal configuration register is reset to 0000h, corresponding to a NOP command. 2. During the frame, the host controller provides clocks on the SCLK pin: – On each SCLK capture edge, the SCLK counter is incremented and the data bit received on the SDI pin is shifted into the LSB of the input shift register. – On each launch edge of the output clock (SCLK in this case), the MSB of the output shift register data is shifted out on the selected SDO-x pins. – The status of the RVS pin depends on the output protocol selection (see the Protocols for Reading From the Device section). 3. The host controller pulls the CONVST/CS pin high to end the data transfer frame. On the rising edge of CONVST/CS: – The SDO-x pins go to tri-state. – As illustrated in Figure 75, the contents of the input shift register are transferred to the command processor for decoding and further action. – RVS output goes low, indicating the beginning of conversion. After pulling CONVST/CS high, the host controller must monitor for a low-to-high transition on the RVS pin or wait for the tconv_max time (see the Timing Requirements: Conversion Cycle table) to elapse before initiating a new data transfer frame. At the end of the data transfer frame F: • If the SCLK counter = 32, then the device treats the frame F as an optimal data transfer frame for any read or write operation. At the end of an optimal data transfer frame, the command processor treats the 32-bit contents of the input shift register as a valid command word. • If the SCLK counter is < 32, then the device treats the frame F as a short data transfer frame. – The data write operation to the device in invalid and the device treats this frame as an NOP command. – The output data bits transferred during a short frame on the SDO-x pins are still valid data. The host controller can use the short data transfer frame to read only the required number of MSB bits from the 32bit output shift register. • If the SCLK counter is > 32, then the device treats the frame F as a long data transfer frame. At the end of a long data transfer frame, the command processor treats the 32-bit contents of the input shift register as a valid command word. There is no restriction on the maximum number of clocks that can be provided within any data transfer frame F. However, when the host controller provides a long data transfer frame, the last 32 bits shifted into the device prior to the CONVST/CS rising edge must constitute the desired command. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 41 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com Programming (continued) 7.5.2 Input Command Word and Register Write Operation Any data write operation to the device is always synchronous to the external clock provided on the SCLK pin. The device allows either one byte or two bytes (equivalent to half a word) to be read or written during any device programming operation. Table 5 lists the input commands supported by the device. The input commands associated with reading or writing two bytes in a single operation are suffixed as HWORD. For any HWORD command, the LSB of the 9-bit address is always ignored and considered as 0b. For example, regardless whether address 04h or 05h is entered for any particular HWORD command, the device always exercises the command on address 04h. Table 5. List of Input Commands OPCODE B[31:0] COMMAND ACRONYM 00000000_000000000_ 00000000_00000000 11000_xx_<9-bit address>_ <16-bit data> NOP COMMAND DESCRIPTION No operation • • • • Command used to clear any (or a group of) bits of a register. Any bit marked 1 in the data field results in that particular bit of the specified register being reset to 0, leaving the other bits unchanged. Half-word command (that is, the command functions on 16 bits at a time). LSB of the 9-bit address is always ignored and considered as 0b. Command used to perform a 16-bit read operation. Half-word command (that is, the device outputs 16 bits of register data at a time). LSB of the 9-bit address is always ignored and considered as 0b. Upon receiving this command, the device sends out 16 bits of the register in the next frame. CLEAR_HWORD 11001_xx_<9-bit address>_ 00000000_00000000 READ_HWORD • • • • 01001_xx_<9-bit address>_ 00000000_00000000 READ • Same as the READ_HWORD except that only eight bits of the register (byte read) are returned in the next frame. 11010_00_<9-bit address>_ <16-bit data> • • Half-word write command (two bytes of input data are written into the specified address). LSB of the 9-bit address is always ignored and considered as 0b. 11010_01_<9-bit address>_ <16-bit data> • • • Half-word write command. LSB of the 9-bit address is always ignored and considered as 0b. With this command, only the MS byte of the 16-bit data word is written at the specified register address. The LS byte is ignored. • • • Half-word write command. LSB of the 9-bit address is always ignored and considered as 0b. With this command, only the LS byte of the 16-bit data word is written at the specified register address. The MS byte is ignored. • • Command used to set any (or a group of) bits of a register. Any bit marked 1 in the data field results in that particular bit of the specified register being set to 1, leaving the other bits unchanged. Half-word command (that is, the command functions on 16 bits at a time). LSB of the 9-bit address is always ignored and considered as 0b. WRITE 11010_10_<9-bit address>_ <16-bit data> 11011_xx_<9-bit address>_ <16-bit data> SET_HWORD All other input command combinations • • NOP No operation All input commands (including the CLEAR_HWORD, WRITE, and SET_HWORD commands listed in Table 5) used to configure the internal registers must be 32 bits long. If any of these commands are provided in a particular data frame F, that command gets executed at the rising edge of the CONVST/CS signal. 42 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 7.5.3 Output Data Word The data read from the device can be synchronized to the external clock on the SCLK pin or to an internal clock of the device by programming the configuration registers (see the Data Transfer Protocols section for details). In any data transfer frame, the contents of the internal output shift register are shifted out on the SDO-x pins. The output data for any frame (F+1) is determined by the command issued in frame F and the status of DATA_VAL[2:0] bits: • If DATA_VAL[2:0] bits in DATAOUT_CTL_REG register are set to 1xxb, then the output data word for frame (F+1) contains fixed data pattern as described in the DATAOUT_CTL_REG register. • If a valid READ command is issued in frame F, the output data word for frame (F+1) contains 8-bit register data, followed by 0's. • If a valid READ_HWORD command is issued in frame F, the output data word for frame (F+1) contains 16-bit register data, followed by 0's. • For all other combinations, the output data word for frame (F+1) contains the latest 16-bit conversion result. Program the DATAOUT_CTL_REG register to append various data flags to the conversion result. The data flags are appended as per following sequence: 1. DEVICE_ADDR[3:0] bits are appended if the DEVICE_ADDR_INCL bit is set to 1 2. AVDD ALARM FLAGS are appended if the VDD_ACTIVE_ALARM_INCL bit is set to 1 3. INPUT ALARM FLAGS are appended if the IN_ACTIVE_ALARM_INCL bit is set to 1 4. ADC INPUT RANGE FLAGS are appended if the RANGE_INCL bit is set to 1 5. PARITY bits are appended if the PAR_EN bit is set to 1 6. All the remaining bits in the 32-bit output data word are set to 0. Table 6 shows the output data word with all data flags enabled. Table 6. Output Data Word With All Data Flags Enabled DEVICE_ADDR_INCL = 1b, VDD_ACTIVE_ALARM_INCL = 1b, IN_ACTIVE_ALARM_INCL = 1b, RANGE_INCL = 1b, and PAR_EN = 1b D[31:16] D[15:12] D[11:10] D[9:7] D[7:4] D[3:2] D[1:0] Conversion result Device address AVDD alarm flags Input alarm flags ADC input range Parity bits 00b Table 7 shows output data word with only some of the data flags enabled. Table 7. Output Data Word With Only Some Data Flags Enabled DEVICE_ADDR_INCL = 0b, VDD_ACTIVE_ALARM_INCL = 1b, IN_ACTIVE_ALARM_INCL = 0b, RANGE_INCL = 1b, and PAR_EN = 1b D[31:16] D[15:14] D[13:10] D[9:8] D[7:0] Conversion result AVDD alarm flags ADC input range Parity bits 00000000b Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 43 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 7.5.4 Data Transfer Protocols The device features a multiSPI interface that allows the host controller to operate at slower SCLK speeds and still achieve the required cycle time with a faster response time. • For any data write operation, the host controller can use any of the four legacy, SPI-compatible protocols to configure the device, as described in the Protocols for Configuring the Device section. • For any data read operation from the device, the multiSPI interface module offers the following options: – Legacy, SPI-compatible protocol with a single SDO-x (see the Legacy, SPI-Compatible (SYS-xy-S) Protocols with a Single SDO-x section) – Legacy, SPI-compatible protocol with dual SDO-x (see the Legacy, SPI-Compatible (SYS-xy-S) Protocols with Dual SDO-x section) – ADC master clock or source-synchronous (SRC) protocol for data transfer (see the Source-Synchronous (SRC) Protocols section) 7.5.4.1 Protocols for Configuring the Device As described in Table 8, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-S, SPI-01-S, SPI-10-S, or SPI-11-S) to write data into the device. Table 8. SPI Protocols for Configuring the Device PROTOCOL SCLK POLARITY (At CS Falling Edge) SCLK PHASE (Capture Edge) SDI_CTL_REG SDO_CTL_REG DIAGRAM SPI-00-S SPI-01-S Low Rising 00h 00h Figure 76 Low Falling 01h 00h Figure 76 SPI-10-S High Falling 02h 00h Figure 77 SPI-11-S High Rising 03h 00h Figure 77 On power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data read and data write operations. To select a different SPI-compatible protocol, program the SDI_MODE[1:0] bits in the SDI_CNTL_REG register. This first write operation must adhere to the SPI-00-S protocol. Any subsequent data transfer frames must adhere to the newly-selected protocol. Note that the SPI protocol selected by the configuration of the SDI_MODE[1:0] is applicable to both read and write operations. Figure 76 and Figure 77 detail the four protocols using an optimal data frame; see the Timing Requirements: SPI-Compatible Serial Interface table for associated timing parameters. NOTE As explained in the Data Transfer Frame section, a valid write operation to the device requires a minimum of 32 SCLKs to be provided within a data transfer frame. CONVST/CS CONVST/CS RVS RVS CPOL = 0 CPOL = 0 SCLK SCLK CPOL = 1 SDI CPOL = 1 B31 B30 B29 B1 B0 Figure 76. Standard SPI Timing Protocol (CPHA = 0, 32 SCLK Cycles) 44 Submit Documentation Feedback SDI B31 B30 B2 B1 B0 Figure 77. Standard SPI Timing Protocol (CPHA = 1, 32 SCLK Cycles) Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 7.5.4.2 Protocols for Reading From the Device The protocols for the data read operation can be broadly classified into three categories: 1. Legacy, SPI-compatible protocols with a single SDO-x 2. Legacy, SPI-compatible protocols with dual SDO-x 3. ADC master clock or source-synchronous (SRC) protocol for data transfer 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols with a Single SDO-x As shown in Table 9, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-S, SPI01-S, SPI-10-S, or SPI-11-S) to read data from the device. Table 9. SPI Protocols for Reading From the Device PROTOCOL SCLK POLARITY (At CS Falling Edge) SPI-00-S Low SPI-01-S Low SPI-10-S High SPI-11-S High SCLK PHASE (Capture Edge) MSB BIT LAUNCH EDGE SDI_CTL_REG SDO_CTL_REG DIAGRAM Rising CS falling 00h 00h Figure 78 Falling 1st SCLK rising 01h 00h Figure 78 Falling CS falling 02h 00h Figure 79 Rising 1st SCLK falling 03h 00h Figure 79 On power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data read and data write operations. To select a different SPI-compatible protocol for both the data transfer operations: 1. Program the SDI_MODE[1:0] bits in the SDI_CTL_REG register. This first write operation must adhere to the SPI-00-S protocol. Any subsequent data transfer frames must adhere to the newly-selected protocol. 2. Set the SDO_MODE[1:0] bits = 00b in the SDO_CTL_REG register. NOTE The SPI transfer protocol selected by configuring the SDI_MODE[1:0] bits in the SDI_CTL_REG register determines the data transfer protocol for both write and read operations. Either data can be read from the device using the selected SPI protocol by configuring the SDO_MODE[1:0] bits = 00b in the SDO_CTL_REG register, or one of the SRC protocols can be selected for data read, as explained in the Source-Synchronous (SRC) Protocols section. When using any of the SPI-compatible protocols, the RVS output remains low throughout the data transfer frame; see the Timing Requirements: SPI-Compatible Serial Interface table for associated timing parameters. Figure 78 and Figure 79 explain the details of the four protocols. As explained in the Data Transfer Frame section, the host controller can use a short data transfer frame to read only the required number of MSB bits from the 32-bit output data word. If the host controller uses a long data transfer frame with SDO_CNTL_REG[7:0] = 00h, then the device exhibits daisy-chain operation (see the Multiple Devices: Daisy-Chain Topology section). Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 45 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com CONVST/CS CONVST/CS RVS RVS CPOL = 0 CPOL = 0 SCLK SCLK CPOL = 1 CPOL = 1 M SDO-0 M-1 M-2 L+1 L SDO-0 Figure 78. Standard SPI Timing Protocol (CPHA = 0, Single SDO-x) 0 M M-1 L+1 L Figure 79. Standard SPI Timing Protocol (CPHA = 1, Single SDO-x) 7.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols with Dual SDO-x The device provides an option to increase the SDO-x bus width from one bit (default, single SDO-x) to two bits (dual SDO-x) when operating with any of the data transfer protocols. In order to operate the device in dual SDO mode, the SDO1_CONFIG[1:0] bits in the SDO_CTL_REG register must be set to 11b. In this mode, the ALARM/SDO-1/GPO pin functions as SDO-1. In dual SDO mode, two bits of data are launched on the two SDO-x pins (SDO-0 and SDO-1) on every SCLK launch edge, as shown in Figure 80 and Figure 81. CONVST/CS CONVST/CS RVS RVS CPOL = 0 CPOL = 0 SCLK SCLK CPOL = 1 SDO-0 SDO-1 CPOL = 1 M M-1 M-2 M-3 M-4 M-5 L+3 L+2 L+1 SDO-0 0 M M-2 L+3 L+1 0 M-1 M-1 L+2 L L SDO-1 Figure 80. Standard SPI Timing Protocol (CPHA = 0, Dual SDO-x) Figure 81. Standard SPI Timing Protocol (CPHA = 1, Dual SDO-x) NOTE For any particular SPI protocol, the device follows the same timing specifications for single and dual SDO modes. The only difference is that the device requires half as many SCLK cycles to output the same number of bits when in single SDO mode, thus reducing the minimum required SCLK frequency for a certain sampling rate of the ADC. 46 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 7.5.4.2.3 Source-Synchronous (SRC) Protocols The multiSPI interface supports an ADC master clock or source-synchronous mode of data transfer between the device and host controller. In this mode, the device provides an output clock that is synchronous with the output data. Furthermore, the host controller can also select the output clock source and data bus width options in this mode of operation. In all SRC modes of operation, the RVS pin provides the output clock, synchronous to the device data output. The SRC protocol allows the clock source (internal or external) and the width of the output bus to be configured, similar to the SPI protocols. 7.5.4.2.3.1 Output Clock Source Options The device allows the output clock on the RVS pin to be synchronous to either the external clock provided on the SCLK pin or to the internal clock of the device. This selection is done by configuring the SSYNC_CLK bit, as explained in the SDO_CTL_REG register. The timing diagram and specifications for operating the device with an SRC protocol in external CLK mode are provided in Figure 7 and the Timing Requirements: Source-Synchronous Serial Interface (External Clock) table. The timing diagram and specifications for operating the device with an SRC protocol in internal CLK mode are provided in Figure 8 and the Timing Requirements: Source-Synchronous Serial Interface (Internal Clock) table. 7.5.4.2.3.2 Output Bus Width Options The device provides an option to increase the SDO-x bus width from one bit (default, single SDO-x) to two bits (dual SDO-x) when operating with any of the SRC protocols. In order to operate the device in dual SDO mode, the SDO1_CONFIG[1:0] bits in the SDO_CTL_REG register must be set to 11b. In this mode, the ALARM/SDO1/GPO pin functions as SDO-1. NOTE For any particular SRC protocol, the device follows the same timing specifications for single and dual SDO modes. The only difference is that the device requires half as many clock cycles to output the same number of bits when in single SDO mode, thus reducing the minimum required clock frequency for a certain sampling rate of the ADC. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 47 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 7.6 Register Maps 7.6.1 Device Configuration and Register Maps The device features nine configuration registers, mapped as described in Table 10. Each configuration registers is comprised of four registers, each containing a data byte. Table 10. Configuration Registers Mapping ADDRESS REGISTER NAME 00h DEVICE_ID_REG REGISTER FUNCTION 04h RST_PWRCTL_REG 08h SDI_CTL_REG SDI data input control register 0Ch SDO_CTL_REG SDO-x data input control register 10h DATAOUT_CTL_REG 14h RANGE_SEL_REG Device ID register Reset and power control register Output data control register Input range selection control register 20h ALARM_REG 24h ALARM_H_TH_REG ALARM output register ALARM high threshold and hysteresis register 28h ALARM_L_TH_REG ALARM low threshold register 7.6.1.1 DEVICE_ID_REG Register (address = 00h) This register contains the unique identification numbers associated to a device that is used in a daisy-chain configuration involving multiple devices. Figure 82. DEVICE_ID_REG Register 31 30 29 15 14 13 28 27 Reserved R-00h 12 11 26 25 24 23 10 9 8 7 Reserved R-0000h 22 21 Reserved R-0000b 6 5 20 19 4 3 18 17 16 DEVICE_ADDR[3:0] R/W-0000b 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset; LEGEND: -<0>, -<1> = Condition after power-on reset Address for bits 7-0 = 00h Address for bits 15-8 = 01h Address for bits 23-16 = 02h Address for bits 31-24 = 03h Table 11. DEVICE_ID_REG Register Field Descriptions Bit (1) 48 Field Type Reset Description 31-24 Reserved R 00h Reserved. Reads return 00h. 23-20 Reserved R 0000b Reserved. Reads return 0000b. 19-16 DEVICE_ADDR[3:0] (1) R 0000b These bits can be used to identify up to 16 different devices in a system. 15-0 Reserved R 0000h Reserved. Reads return 0000h. These bits are useful in daisy-chain mode. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 7.6.1.2 RST_PWRCTL_REG Register (address = 04h) This register controls the reset and power-down features offered by the converter. Any write operation to the RST_PWRCTL_REG register must be preceded by a write operation with the register address set to 05h and the register data set to 69h. Figure 83. RST_PWRCTL_REG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 4 3 2 1 0 IN_AL_DIS Reserved RSTn_APP NAP_EN PWRDN R/W-0b R-0b R/W-<0>b R/W-<0>b R/W-0b Reserved R-0000h 15 14 13 12 11 10 9 8 7 6 WKEY[7:0] Reserved R/W-00h R-00b 5 VDD_AL_ DIS R/W-0b LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset; LEGEND: -<0>, -<1> = Condition after power-on reset Address for bits 7-0 = 04h Address for bits 15-8 = 05h Address for bits 23-16 = 06h Address for bits 31-24 = 07h Table 12. RST_PWRCTL_REG Register Field Descriptions Field Type Reset Description 31-16 Bit Reserved R 0000h Reserved. Reads return 0000h. 15-8 WKEY[7:0] R/W 00h This value functions as a protection key to enable writes to bits 5-0. Bits are written only if WKEY is set to 69h first. 7-6 (1) (2) Reserved R 00b Reserved. Reads return 00b 5 VDD_AL_DIS R/W 0b 0b = VDD alarm is enabled 1b = VDD alarm is disabled 4 IN_AL_DIS R/W 0b 0b = Input alarm is enabled 1b = Input alarm is disabled 3 Reserved R 0b Reserved. Reads return 0h. R/W 0b 0b = RST pin functions as a POR class reset (causes full device initialization) 1b = RST pin functions as an application reset (only user-programmed modes are cleared) (1) 2 RSTn_APP 1 NAP_EN (2) R/W 0b 0b = Disables the NAP mode of the converter 1b = Enables the converter to enter NAP mode if CONVST/CS is held high after the current conversion completes 0 PWRDN (2) R/W 0b 0b = Puts the converter into active mode 1b = Puts the converter into power-down mode Setting this bit forces the RST pin to function as an application reset until the next power cycle. See the Electrical Characteristics table for details on the latency encountered when entering and exiting the associated low-power mode. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 49 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 7.6.1.3 SDI_CTL_REG Register (address = 08h) This register configures the protocol used for writing data to the device. Figure 84. SDI_CTL_REG Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 Reserved R-0000h 8 7 22 21 20 19 18 17 6 5 4 3 2 1 0 SDI_MODE [1:0] R/W-<00>b Reserved Reserved R-00h R-000000b 16 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset; LEGEND: -<0>, -<1> = Condition after power-on reset Address for bits 7-0 = 08h Address for bits 15-8 = 09h Address for bits 23-16 = 0Ah Address for bits 31-24 = 0Bh Table 13. SDI_CTL_REG Register Field Descriptions Bit 50 Field Type Reset Description 31-16 Reserved R 0000h Reserved. Reads return 0000h. 15-8 Reserved R 00h Reserved. Reads return 00h. 7-2 Reserved R 000000b Reserved. Reads return 000000b. 1-0 SDI_MODE[1:0] R/W 00b These bits select the protocol for reading from or writing to the device. 00b = Standard SPI with CPOL = 0 and CPHASE = 0 01b = Standard SPI with CPOL = 0 and CPHASE = 1 10b = Standard SPI with CPOL = 1 and CPHASE = 0 11b = Standard SPI with CPOL = 1 and CPHASE = 1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 7.6.1.4 SDO_CTL_REG Register (address = 0Ch) This register controls the data protocol used to transmit data out from the SDO-x pins of the device. Figure 85. SDO_CTL_REG Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 8 SDO1_ CONFIG [1:0] R/W-00b Reserved GPO_VAL Reserved R-000b R/W-0b R-00b 24 23 Reserved R-0000h 7 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved SSYNC_CLK Reserved SDO_ MODE[1:0] R-0b R/W-<0>b R-0h R/W-<0>b LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset; LEGEND: -<0>, -<1> = Condition after power-on reset Address for bits 7-0 = 0Ch Address for bits 15-8 = 0Dh Address for bits 23-16 = 0Eh Address for bits 31-24 = 0Fh Table 14. SDO_CTL_REG Register Field Descriptions Bit Field Type Reset Description 31-16 Reserved R 0000h Reserved. Reads return 0h. 15-13 Reserved R 000b Reserved. Reads return 000b. 12 GPO_VAL R/W 0b 1-bit value for the output on the GPO pin. 11-10 Reserved R 00b Reserved. Reads return 00b. SDO1_CONFIG[1:0] R/W 00b Two bits are used to configure ALARM/SDO-1/GPO: 00b = SDO-1 is always tri-stated; 1-bit SDO mode 01b = SDO-1 functions as ALARM; 1-bit SDO mode 10b = SDO-1 functions as GPO; 1-bit SDO mode 11b = SDO-1 combined with SDO-0 offers a 2-bit SDO mode Reserved R 0b Reserved. Reads return 0b. R/W 0b This bit controls the source of the clock selected for source-synchronous transmission. 0b = External SCLK (no division) 1b = Internal clock (no division) R 0000b Reserved. Reads return 0000b. 00b These bits control the data output modes of the device. 0xb = SDO mode follows the same SPI protocol as that used for SDI; see the SDI_CTL_REG register 10b = Invalid configuration 11b = SDO mode follows the ADC master clock or source-synchronous protocol 9-8 7 6 5-2 1-0 (1) SSYNC_CLK (1) Reserved SDO_MODE[1:0] R/W This bit takes effect only in the ADC master clock or source-synchronous mode of operation. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 51 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 7.6.1.5 DATAOUT_CTL_REG Register (address = 10h) This register controls the data output by the device. Figure 86. DATAOUT_CTL_REG Register 31 30 15 14 DEVICE_ Reserved ADDR_ INCL R-0b R/W-0b 29 28 27 26 13 12 11 10 25 Reserved R-0000h 9 24 23 22 21 20 19 18 17 16 8 7 6 5 4 3 2 1 0 VDD_ACTIVE_ ALARM_INCL[1:0] IN_ACTIVE_ ALARM_INCL[1:0] Reserved RANGE_ INCL Reserved PAR_EN R/W-0b R/W-0b R-0b R/W-0b R-0000b R/W<0>b DATA_VAL [2:0] R/W-000b LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset; LEGEND: -<0>, -<1> = Condition after power-on reset Address for bits 7-0 = 10h Address for bits 15-8 = 11h Address for bits 23-16 = 12h Address for bits 31-24 = 13h Table 15. DATAOUT_CTL_REG Register Field Descriptions Bit Field Type Reset Description 31-16 Reserved R 0000h Reserved. Reads return 0000h. 15 Reserved R 0b Reserved. Reads return 0b. 14 DEVICE_ADDR_INCL R/W 0b Control to include the 4-bit DEVICE_ADDR register value in the SDO-x output bit stream. 0b = Do not include the register value 1b = Include the register value 13-12 VDD_ACTIVE_ALARM_INCL[1:0] R/W 00b Control to include the active VDD ALARM flags in the SDO-x output bit stream. 00b = Do not include 01b = Include ACTIVE_VDD_H_FLAG 10b = Include ACTIVE_VDD_L_FLAG 11b = Include both flags 11-10 IN_ACTIVE_ALARM_INCL[1:0] R/W 00b Control to include the active input ALARM flags in the SDO-x output bit stream. 00b = Do not include 01b = Include ACTIVE_IN_H_FLAG 10b = Include ACTIVE_IN_L_FLAG 11b = Include both flags 9 Reserved R 0b Reserved. Reads return 0h. 8 RANGE_INCL R/W 0b Control to include the 4-bit input range setting in the SDO-x output bit stream. 0b = Do not include the range configuration register value 1b = Include the range configuration register value Reserved R 0000b Reserved. Reads return 0000b. 0b = Output data does not contain parity information 1b = Two parity bits (ADC output and output data frame) are appended to the LSBs of the output data The ADC output parity bit reflects an even parity for the ADC output bits only. The output data frame parity bit reflects an even parity signature for the entire output data frame, including the ADC output bits and any internal flags or register settings. 7-4 3 2-0 (1) 52 PAR_EN (1) R/W 0b DATA_VAL[2:0] R/W 000b These bits control the data value output by the converter. 0xxb = Value output is the conversion data 100b = Value output is all 0's 101b = Value output is all 1's 110b = Value output is alternating 0's and 1's 111b = Value output is alternating 00's and 11's Setting this bit increases the length of the output data by two bits. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 7.6.1.6 RANGE_SEL_REG Register (address = 14h) This register controls the configuration of the internal reference and input voltage ranges for the converter. Figure 87. RANGE_SEL_REG Register 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 Reserved R-00h 23 22 Reserved R-0000h 7 6 Reser INTREF_ DIS ved R-0b R/W-0b 21 20 19 18 17 16 5 4 3 2 1 0 Reserved RANGE_SEL[3:0] R-00b R/W-<0000>b LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset; LEGEND: -<0>, -<1> = Condition after power-on reset Address for bits 7-0 = 14h Address for bits 15-8 = 15h Address for bits 23-16 = 16h Address for bits 31-24 = 17h Table 16. RANGE_SEL_REG Register Field Descriptions Field Type Reset Description 31-16 Bit Reserved R 0000h Reserved. Reads return 0000h. 15-8 Reserved R 00h Reserved. Reads return 00h. 7 Reserved R 0b Reserved. Reads return 0b. 6 INTREF_DIS R/W 0b Control to disable the ADC internal reference. 0b = Internal reference is enabled 1b = Internal reference is disabled 5-4 Reserved R 00b Reserved. Reads return 00b. 3-0 RANGE_SEL[3:0] R/W 0000b These bits comprise the 4-bit register that selects the nine input ranges of the ADC. 0000b = ±3 × VREF 0001b = ±2.5 × VREF 0010b = ±1.5 × VREF 0011b = ±1.25 × VREF 0100b = ±0.625 × VREF 1000b = 3 × VREF 1001b = 2.5 × VREF 1010b = 1.5 × VREF 1011b = 1.25 × VREF Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 53 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 7.6.1.7 ALARM_REG Register (address = 20h) This register contains the output alarm flags (active and tripped) for the input and AVDD alarm. Figure 88. ALARM_REG Register 31 30 29 28 27 26 25 24 23 Reserved R-0000h 15 14 13 12 11 10 9 8 7 ACTIVE_ ACTIVE_ ACTIVE_ ACTIVE_ TRP_ VDD_L_ VDD_H_ Reserved IN_L_ IN_H_ Reserved VDD_L_ FLAG FLAG FLAG FLAG FLAG R-0b R-0b R-00b R-0b R-0b R-00b R-0b 22 21 20 19 18 17 16 6 TRP_ VDD_H_ FLAG R-0b 5 4 3 2 1 0 TRP_IN_ TRP_IN_ L_FLAG H_FLAG R-0b Reserved OVW_ ALARM R-000b R-0b R-0b LEGEND: R = Read only; -n = value after reset; -0, -1 = Condition after application reset; -<0>, -<1> = Condition after power-on reset Address for bits 7-0 = 20h Address for bits 15-8 = 21h Address for bits 23-16 = 22h Address for bits 31-24 = 23h Table 17. ALARM_REG Register Field Descriptions Bit 31-16 Type Reset Description Reserved R 0000h Reserved. Reads return 0000h. 15 ACTIVE_VDD_L_FLAG R 0b Active ALARM output flag for low AVDD voltage. 0b = No ALARM condition 1b = ALARM condition exists 14 ACTIVE_VDD_H_FLAG R 0b Active ALARM output flag for high AVDD voltage. 0b = No ALARM condition 1b = ALARM condition exists Reserved R 00b Reserved. Reads return 00b. 11 ACTIVE_IN_L_FLAG R 0b Active ALARM output flag for high input voltage. 0b = No ALARM condition 1b = ALARM condition exists 10 ACTIVE_IN_H_FLAG R 0b Active ALARM output flag for low input voltage. 0b = No ALARM condition 1b = ALARM condition exists 9-8 Reserved R 00b Reserved. Reads return 00b. 7 TRP_VDD_L_FLAG R 0b Tripped ALARM output flag for low AVDD voltage. 0b = No ALARM condition 1b = ALARM condition exists 6 TRP_VDD_H_FLAG R 0b Tripped ALARM output flag for high AVDD voltage. 0b = No ALARM condition 1b = ALARM condition exists 5 TRP_IN_L_FLAG R 0b Tripped ALARM output flag for high input voltage. 0b = No ALARM condition 1b = ALARM condition exists 4 TRP_IN_H_FLAG R 0b Tripped ALARM output flag for low input voltage. 0b = No ALARM condition 1b = ALARM condition exists Reserved R 000b Reserved. Reads return 000b. OVW_ALARM R 0b Logical OR outputs all tripped ALARM flags. 0b = No ALARM condition 1b = ALARM condition exists 13-12 3-1 0 54 Field Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 7.6.1.8 ALARM_H_TH_REG Register (address = 24h) This register controls the hysteresis and high threshold for the input alarm. Figure 89. ALARM_H_TH_REG Register 31 30 15 14 29 28 27 26 INP_ALRM_HYST[7:0] R/W-00h 13 12 11 10 25 9 24 23 22 8 7 6 INP_ALRM_HIGH_TH[15:0] R/W-FFFFh 21 20 19 Reserved R-00h 4 3 5 18 17 16 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset; LEGEND: -<0>, -<1> = Condition after power-on reset Address for bits 7-0 = 24h Address for bits 15-8 = 25h Address for bits 23-16 = 26h Address for bits 31-24 = 27h Table 18. ALARM_H_TH_REG Register Field Descriptions Field Type Reset Description 31-24 Bit INP_ALRM_HYST[7:0] R/W 00h INP_ALRM_HYST[7:2]: 6-bit hysteresis value for the input ALARM. INP_ALRM_HYST[1:0] must be set to 00b. 23-16 Reserved R 00h Reserved. Reads return 00h. 15-0 INP_ALRM_HIGH_TH[15:0] R/W FFFFh Threshold for comparison is INP_ALRM_HIGH_TH[15:0]. 7.6.1.9 ALARM_L_TH_REG Register (address = 28h) This register controls the low threshold for the input alarm. Figure 90. ALARM_L_TH_REG Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 Reserved R-0000h 9 8 7 6 INP_ALRM_LOW_TH[15:0] R/W-0000h 21 20 19 18 17 16 5 4 3 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset; LEGEND: -<0>, -<1> = Condition after power-on reset Address for bits 7-0 = 28h Address for bits 15-8 = 29h Address for bits 23-16 = 2Ah Address for bits 31-24 = 2Bh Table 19. ALARM_L_TH_REG Register Field Descriptions Field Type Reset Description 32:16 Bit Reserved R 0000h Reserved. Reads return 0000h. 15-0 INP_ALRM_LOW_TH[15:0] R/W 0000h Threshold for comparison is INP_ALRM_LOW_TH[15:0]. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 55 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The ADS868x is a fully-integrated data acquisition (DAQ) system based on a 16-bit successive approximation (SAR) analog-to-digital converter (ADC). The device includes an integrated analog front-end (AFE) circuit to drive the inputs of the ADC and an integrated precision reference with a buffer. As such, this device does not require any additional external circuits for driving the reference or analog input pins of the ADC. 8.2 Typical Application Isolation Barrier Local Power Supply System Power Supply x x Isolated DC-DC Converter IGND x GND x VINP Input Signal SAR ADC Digital Isolator Digital Host x VINM IGND x GND GND IGND IGND x GND NOTE: The potential difference between IGND and GND can be as high as the barrier breakdown voltage (often thousands of volts). x Figure 91. 16-Bit Isolated DAQ System for High Common-Mode Rejection 8.2.1 Design Requirements Design a 16-bit DAQ system for processing input signals up to ±12 V superimposed on large dc or ac commonmode offsets relative to the ground potential of the system main power supply. The specific performance requirements are as follows: • Input signal: ±12-V amplitude signal of a 1-kHz frequency superimposed on a ±75-V common-mode with frequency between dc and 15 kHz • CMRR > 100 dB over stipulated common-mode frequency range • SNR > 90 dB • THD < –104 dB 56 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 Typical Application (continued) 8.2.2 Detailed Design Procedure The design uses galvanic isolation between the DAQ system inputs and main power supply to achieve extremely high CMRR, as indicated by Figure 91. The system not only tolerates large common-mode voltages beyond its absolute maximum ratings but also delivers excellent performance largely independent of common-mode amplitude and frequency (within the specified operating limits). The relevant performance characteristics are illustrated in Figure 99, Figure 93, and Figure 94. The system performance requirements by itself can be easily satisfied by using the ADS868x. This device simplifies system design because the ADS868x eliminates the need for designing a discrete high-performance signal chain needed with most other SAR ADCs. In addition, the use of galvanic isolation has the following system design implications: • A local floating supply is needed to power the ADS868x because the device cannot load the system main power supply • A digital isolator is required to facilitate data transfer between the isolated ADS868x serial interface and the digital host controller The floating power supply can be realized as an isolated transformer-based, push-pull converter followed by a rectifier and low-dropout (LDO) regulator to largely eliminate the ADC power-supply ripple by taking advantage of the high PSRR provided by most LDOs. A schematic of this design is shown in Figure 92. xx xx xx xx Isolation Barrier S2 Main Power Supply (> 4.3 V) GND Transformer Driver VIN IGND S1 GND GND Full-Wave Rectifier and Smoothing Capacitor LDO VIN D1 CS M D2 IGND IGND VOUT Isolated 5 V GND IGND LDO VIN VOUT Isolated 3.3 V 1:NS (>1) Isolated Switching Power Supply GND IGND Figure 92. Isolated Power-Supply Design Recommended components for the circuit shown in Figure 92 are given below: • The SN6501 transformer driver is selected for its low input voltage requirement, small form-factor, and the flexibility offered for easily adjusting the system isolation voltage rating by substituting the transformer • A miniature printed circuit board (PCB)-mount, center-tapped transformer with a gain > 1 maintains line regulation at the LDO outputs • Schottky rectifiers for minimal forward voltage drop • Smoothing capacitor for sufficiently low ripple at the LDO input • The TPS7A4901 LDOs for an ultra-low noise contribution relative to the ADS868x and high PSRR over a wide frequency range to attenuate output ripple to levels below the LDO output noise level With regard to the digital isolator, the ISO7640FM is recommended for the following reasons: • Supports > a 50-MHz SCLK and the required logic levels for operating the ADS868x at the full throughput • Quad-channel device that facilitates excellent delay-matching between critical interface signals for reliable operation at high speed Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 57 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com Typical Application (continued) 0 0 -40 -40 Amplitude (dB) Amplitude (dB) 8.2.3 Application Curves -80 -120 -160 -200 0 100 200 300 Frequency (kHz) 400 500 Figure 93. FFT Plot With a DC Common-Mode at 1 MSPS 100 200 300 Frequency (kHz) 0 -40 -40 -120 500 D709 Figure 94. FFT Plot With an AC Common-Mode at 1 MSPS 0 -80 400 fSAMPLE = 1 Msps, VIN = ±12 V, fIN = 1 kHz, VCM = 155 VPP, SINAD = 91.6 dB, THD = –109 dB Amplitude (dB) Amplitude (dB) 0 D708 fSAMPLE = 1 MSPS, VIN = ±12 V, fIN = 1 kHz, VCM = 50 VDC, SINAD = 91.6 dB, THD = –109 dB -80 -120 -160 -160 -200 -200 0 50 100 150 Frequency (kHz) 200 0 250 50 100 150 Frequency (kHz) D710 fSAMPLE = 500 kSPS, VIN = ±12 V, fIN = 1 kHz, VCM = 50 VDC, SINAD = 92 dB, THD = –109 dB -40 -40 Amplitude (dB) 0 -120 -160 250 D711 Figure 96. FFT Plot With an AC Common-Mode at 500 kSPS 0 -80 200 fSAMPLE = 500 kSPS, VIN = ±12 V, fIN = 1 kHz, VCM = 155 VPP, SINAD = 91.5 dB, THD = –109 dB Figure 95. FFT Plot With a DC Common-Mode at 500 kSPS Amplitude (dB) -120 -160 -200 -80 -120 -160 -200 -200 0 10 20 30 Frequency (kHz) 40 50 Figure 97. FFT Plot With a DC Common-Mode at 100 kSPS Submit Documentation Feedback 0 10 20 30 Frequency (kHz) D712 fSAMPLE = 100 kSPS, VIN = ±12 V, fIN = 1 kHz, VCM = 50 VDC, SINAD = 91.8 dB, THD = –110 dB 58 -80 40 50 D713 fSAMPLE = 100 kSPS, VIN = ±12 V, fIN = 1 kHz, VCM = 155 VPP, SINAD = 91.2 dB, THD = –110 dB Figure 98. FFT Plot With an AC Common-Mode at 100 kSPS Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 Typical Application (continued) 160 150 CMRR (dB) 140 130 120 110 100 90 80 20 100 1000 1000020000 Common-Mode Signal Frequency (Hz) D200 Figure 99. Common-Mode Rejection Ratio vs Frequency Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 59 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 9 Power Supply Recommendations The device uses two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on AVDD and DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value within the permissible range. 9.1 Power Supply Decoupling The AVDD supply pins must be decoupled with AGND by using a minimum 10-µF and 1-µF capacitor on each supply. Place the 1-µF capacitor as close to the supply pins as possible. Place a minimum 10-µF decoupling capacitor very close to the DVDD supply to provide the high-frequency digital switching current. The effect of using the decoupling capacitor is illustrated in the difference between the power-supply rejection ratio (PSRR) performance of the device. Figure 100 shows the PSRR of the device without using a decoupling capacitor. The PSRR improves when the decoupling capacitors are used, as shown in Figure 101. -50 ± 12.288 V ± 10.24 V ± 6.144 V ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V -40 -50 Power Supply Rejection Ratio Power Supply Rejection Ratio -30 -60 -70 -80 100 1k 10k Input Frequency (Hz) 100k ± 12.288 V ± 10.24 V ± 6.144 V ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V -60 -70 -80 -90 -100 100 1k 10k Input Frequency (Hz) D057 Figure 100. PSRR Without a Decoupling Capacitor 100k D056 Figure 101. PSRR With a Decoupling Capacitor 9.2 Power Saving In normal mode of operation, the device does not power down between conversions, and therefore achieves high throughput.However, the device offers two programmable low-power modes: NAP and power-down (PD) to reduce power consumption when the device is operated at lower throughput rates. 9.2.1 NAP Mode In NAP mode, the internal blocks of the device are placed into a low-power mode to reduce the overall power consumption of the device in the ACQ state. To enable NAP mode: • Write 69h to register address 05h to unlock the RST_PWRCTL_REG register. • The NAP_EN bit in the RST_PWRCTL_REG register must be set to 1b. The CONVST/CS pin must be kept high at the end of the conversion process. The device then enters NAP mode at the end of conversion and remains in NAP mode as long as the CONVST/CS pin is held high. A falling edge on the CONVST/CS brings the device out of NAP mode; however, the host controller can initiate a new conversion (CONVST/CS rising edge) only after the tNAP_WKUP time has elapsed (see the Timing Requirements: Asynchronous Reset table). 60 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 Power Saving (continued) 9.2.2 Power-Down (PD) Mode The device also features a deep power-down mode (PD) to reduce the power consumption at very low throughput rates. The following steps must be taken to enter PD mode: 1. Write 69h to register address 05h to unlock the RST_PWRCTL_REG register. 2. Set the PWRDN bit in the RST_PWRCTL_REG register to 1b. The device enters PD mode on the rising edge of the CONVST/CS signal. In PD mode, all analog blocks within the device are powered down; however, the interface remains active and the register contents are also retained. The RVS pin is high, indicating that the device is ready to receive the next command. In order to exit PD mode: 1. Clear the PWRDN bit in the RST_PWRCTL_REG register to 0b. 2. The RVS pin goes high, indicating that the device has started coming out of PD mode. However, the host controller must wait for the tPWRUP time (see the Timing Requirements: Asynchronous Reset table) to elapse before initiating a new conversion. 10 Layout 10.1 Layout Guidelines Figure 102 illustrates a PCB layout example for the ADS868x. • Partition the PCB into analog and digital sections. Care must be taken to ensure that the analog signals are kept away from the digital lines. This layout helps keep the analog input and reference input signals away from the digital noise. In this layout example, the analog input and reference signals are routed on the lower side of the board and the digital connections are routed on the top side of the board. • Using a single dedicated ground plane is strongly encouraged. • Power sources to the ADS868x must be clean and well-bypassed. Using a 1-μF, X7R-grade, 0603-size ceramic capacitor with at least a 10-V rating in close proximity to the analog (AVDD) supply pins is recommended. For decoupling the digital supply pin (DVDD), a 1-μF, X7R-grade, 0603-size ceramic capacitor with at least a 10-V rating is recommended. Placing vias between the AVDD, DVDD pins and the bypass capacitors must be avoided. All ground pins must be connected to the ground plane using short, lowimpedance paths. • There are two decoupling capacitors used for the REFCAP pin. The first is a small, 1-μF, 0603-size ceramic capacitor placed close to the device pins for decoupling the high-frequency signals and the second is a 10-μF, 0805-size ceramic capacitor to provide the charge required by the reference circuit of the device. A capacitor with an ESR less than 0.2 Ω is recommended for the 10-μF capacitor. Both of these capacitors must be directly connected to the device pins without any vias between the pins and capacitors. • The REFIO pin also must be decoupled with a minimum of 4.7-μF ceramic capacitor if the internal reference of the device is used. The capacitor must be placed close to the device pins. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 61 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 10.2 Layout Example GND External Reference DVDD AVDD 1µF 1µF GND DVDD 4.7 µF 16 AVDD 2 GND RVS ALARM/SDO-1/GPO GND REFIO 1µF 4 SDO-0 REFGND 5 SCLK REFCAP 6 CONVST/CS SDI 10 µF GND Analog Input RST GND Optional Figure 102. Board Layout for the ADS868x 62 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 ADS8681, ADS8685, ADS8689 www.ti.com SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • OPA320 Precision, 20MHz, 0.9pA, Low-Noise, RRIO, CMOS Operational Amplifier with Shutdown (SBOS513) • SN6501 Transformer Driver for Isolated Power Supplies (SLLSEA0) • TPS7A49 36-V, 150-mA, Ultralow-Noise, Positive Linear Regulator (SBVS121) • ISO764xFM Low-Power Quad-Channel Digital Isolators (SLLSE89) • AN-2029 Handling and Process Recommendations Application Report (SNOA550) 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 20. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ADS8681 Click here Click here Click here Click here Click here ADS8685 Click here Click here Click here Click here Click here ADS8689 Click here Click here Click here Click here Click here 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks E2E is a trademark of Texas Instruments. multiSPI is a trademark of Motorola Mobility LLC. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback 63 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com 11.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 64 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ADS8681 ADS8685 ADS8689 PACKAGE OPTION ADDENDUM www.ti.com 16-Dec-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADS8681IPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS8681 ADS8681IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS8681 ADS8681IRUMR ACTIVE WQFN RUM 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS8681 ADS8681IRUMT ACTIVE WQFN RUM 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS8681 ADS8685IPW PREVIEW TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS8685 ADS8685IPWR PREVIEW TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS8685 ADS8685IRUMR PREVIEW WQFN RUM 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS8685 ADS8685IRUMT PREVIEW WQFN RUM 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS8685 ADS8689IPW PREVIEW TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS8689 ADS8689IPWR PREVIEW TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS8689 ADS8689IRUMR PREVIEW WQFN RUM 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS8689 ADS8689IRUMT PREVIEW WQFN RUM 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS8689 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 16-Dec-2016 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Dec-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8681IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS8681IRUMR WQFN RUM 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS8681IRUMT WQFN RUM 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS8685IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS8689IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Dec-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8681IPWR ADS8681IRUMR TSSOP PW 16 2000 367.0 367.0 35.0 WQFN RUM 16 3000 367.0 367.0 35.0 ADS8681IRUMT WQFN RUM 16 250 210.0 185.0 35.0 ADS8685IPWR TSSOP PW 16 2000 367.0 367.0 35.0 ADS8689IPWR TSSOP PW 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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