Cypress CY62148BLL-70ZC 4-mbit (512k x 8) static ram Datasheet

CY62148B MoBL™
4-Mbit (512K x 8) Static RAM
Features
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. This device
has an automatic power-down feature that reduces power
consumption by more than 99% when deselected.
• High Speed: 70 ns
• 4.5V–5.5V operation
• Low active power
— Typical active current: 2.5 mA @ f = 1 MHz
— Typical active current: 12.5 mA @ f = fmax(70 ns)
• Low standby current
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• CMOS for optimum speed/power
• Available in standard 32-lead (450-mil) SOIC, 32-lead
TSOP II and 32-lead Reverse TSOP II packages
Functional Description
The CY62148B is a high-performance CMOS static RAM
organized as 512K words by 8 bits. Easy memory expansion
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH for read. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY62148B is available in a standard 32-pin 450-mil-wide
body width SOIC, 32-pin TSOP II, and 32-pin Reverse TSOP
II packages.
Logic Block Diagram
Pin Configuration
Top View
SOIC
TSOP II
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O0
INPUT BUFFER
CE
I/O1
I/O2
SENSE AMPS
ROW DECODER
A0
A1
A4
A5
A6
A7
A12
A14
A16
A17
512 K x 8
ARRAY
I/O3
I/O4
POWER
DOWN
A2
A3
A15
A18
A13
A8
A9
A11
A10
OE
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
A4
A5
A6
A7
A12
A14
A16
A17
I/O6
I/O7
WE
Cypress Semiconductor Corporation
Document #: 38-05039 Rev. *C
•
198 Champion Court
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Top View
Reverse
TSOP II
I/O5
COLUMN
DECODER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
•
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
OE
A11
A9
A8
A13
WE
A18
A15
Vcc
San Jose, CA 95134-1709
•
408-943-2600
Revised August 2, 2006
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CY62148B MoBL™
Product Portfolio
Power Dissipation
Operating, Icc
VCC Range
Standby (ISB2)
f = fmax
Product
Min.
Typ.
Max.
Speed
CY62148BLL
4.5 V
5.0V
5.5V
70 ns
Temp.
Com’l
Typ.
[3]
12.5 mA
Max.
Typ.[3]
Max.
20 mA
4 µA
20 µA
Ind’l
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage...............................................2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-Up Current ..................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND........ –0.5V to +7.0V
Operating Range
DC Voltage Applied to Outputs
in High Z State[1] .....................................–0.5V to VCC +0.5V
Range
Commercial
DC Input Voltage[1] ..................................–0.5V to VCC +0.5V
Industrial
Ambient
Temperature[2]
VCC
0°C to +70°C
4.5V–5.5V
–40°C to +85°C
Electrical Characteristics Over the Operating Range
CY62148B-70
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = – 1 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 2.1 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Leakage Current
GND ≤ VI ≤ VCC
IOZ
Output Leakage
Current
GND ≤ VI ≤ VCC, Output Disabled
ICC
VCC Operating
Supply Current
f = fMAX = 1/tRC
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC,
CE ≥ VIH
VIN ≥ VIH or
VIN ≤ VIL, f = fMAX
Com/Ind’l
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE ≥ VCC – 0.3V,
VIN ≥ VCC – 0.3V,
or VIN ≤ 0.3V, f =0
Com/Ind’l
f = 1 MHz
Com/Ind’l
IOUT =0 mA
VCC = Max.,
Min.
Typ.[3]
Max.
2.4
Unit
V
0.4
V
2.2
VCC +0.3
V
–0.3
0.8
V
–1
+1
µA
–1
+1
µA
20
mA
12.5
2.5
4
mA
1.5
mA
20
µA
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “Instant On” case temperature.
3. Typical values are measured at VCC = 5V, TA = 25°C, and are included for reference only and are not tested or guaranteed.
Document #: 38-05039 Rev. *C
Page 2 of 11
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CY62148B MoBL™
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
6
pF
8
pF
AC Test Loads and Waveforms
R1 1800 Ω
R1 1800Ω
5V
ALL INPUT PULSES
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
(a)
OUTPUT
R2
5 pF
990 Ω
INCLUDING
JIG AND
SCOPE
(b)
3.0V
90%
R2
990 Ω
GND
10%
≤ 3 ns
90%
10%
≤ 3 ns
Equivalent to:
THEVENIN EQUIVALENT
639 Ω
1.77V
OUTPUT
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05039 Rev. *C
Page 3 of 11
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CY62148B MoBL™
Switching Characteristics[5] Over the Operating Range
62148BLL-70
Parameter
Description
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
70
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
70
ns
tDOE
OE LOW to Data Valid
35
ns
[6]
tLZOE
OE LOW to Low Z
10
[6]
CE LOW to Low Z
tHZCE
CE HIGH to High Z[6, 7]
tPU
CE LOW to Power-Up
tPD
ns
25
10
ns
ns
25
0
CE HIGH to Power-Down
ns
ns
5
OE HIGH to High Z
tLZCE
WRITE
70
[6, 7]
tHZOE
ns
ns
ns
70
ns
CYCLE[8]
tWC
Write Cycle Time
70
ns
tSCE
CE LOW to Write End
60
ns
tAW
Address Set-Up to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
55
ns
tSD
Data Set-Up to Write End
30
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low Z[6]
5
ns
tHZWE
WE LOW to High
Z[6, 7]
25
ns
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05039 Rev. *C
Page 4 of 11
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CY62148B MoBL™
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
Conditions
Typ.[3]
Max.
2.0
Com’l LL
Ind’l
tCDR[4]
tR[9]
Min.
No input may exceed
VCC + 0.3V
VCC = VDR = 3.0V
CE > VCC – 0.3V
VIN > VCC – 0.3V or
VIN < 0.3V
LL
Chip Deselect to Data Retention Time
Operation Recovery Time
Unit
V
20
µA
20
µA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
3.0V
VDR > 2V
tR
tCDR
CE
Switching Waveforms
Read Cycle No.1[10, 11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tHZCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ISB
Notes:
9. Full Device operatin requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at Vcc(min) > 100 µs.
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05039 Rev. *C
Page 5 of 11
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CY62148B MoBL™
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[13]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
tWC
ADDRESS
tSCE
CE
tHZCE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 15
tHZOE
Notes:
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
14. Data I/O is high-impedance if OE = VIH.
15. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05039 Rev. *C
Page 6 of 11
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CY62148B MoBL™
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)[13, 14]
tWC
ADDRESS
tSCE
CE
tHZCE
tAW
tSA
tHA
tPWE
WE
tSD
NOTE 15
DATAI/O
tHD
DATA VALID
tLZWE
tHZWE
Truth Table
CE
OE
WE
I/O0 – I/O7
Mode
Power
H
X
X
High Z
Power-Down
Standby (ISB)
L
L
H
Data Out
Read
Active (ICC)
L
X
L
Data In
Write
Active (ICC)
L
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
70
Ordering Code
Package
Diagram
Package Type
CY62148BLL-70SC
51-85081
32-lead (450-Mil) Molded SOIC
CY62148BLL-70ZC
51-85095
32-lead TSOP II
CY62148BLL-70ZRC
51-85138
32-lead RTSOP II
CY62148BLL-70SI
51-85081
32-lead (450-Mil) Molded SOIC
CY62148BLL-70ZI
51-85095
32-lead TSOP II
CY62148BLL-70ZRI
51-85138
32-lead RTSOP II
Operating
Range
Commercial
Industrial
Please contact your local Cypress sales representative for availability of these parts
Document #: 38-05039 Rev. *C
Page 7 of 11
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CY62148B MoBL™
Package Diagrams
32-lead (450 MIL) Molded SOIC (51-85081)
51-85081-A
Document #: 38-05039 Rev. *C
Page 8 of 11
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CY62148B MoBL™
Package Diagrams (continued)
32-lead Thin Small Outline Package Type II (51-85095)
51-85095-**
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05039 Rev. *C
Page 9 of 11
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CY62148B MoBL™
Package Diagrams (continued)
32-lead Reverse Thin Small Outline Package Type II (51-85138)
51-85138-**
Document #: 38-05039 Rev. *C
Page 10 of 11
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62148B MoBL™
Document History Page
Document Title: CY62148B 4-Mbit (512K x 8) Static RAM
Document Number: 38-05039
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
106833
05/01/01
SZV
Description of Change
Change from Spec number 38-01104 to 38-05039
*A
106970
07/16/01
GAV
Modified annotations on Pin Configurations; tSD = 30 ns
*B
109766
10/09/01
MGN
Remove 55-ns devices
*C
485639
See ECN
VKN
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Corrected the typo in the Array size in the Logic Block Diagram on page# 1
Renamed Package Name column with Package Diagram in the Ordering
Information Table
Document #: 38-05039 Rev. *C
Page 11 of 11
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