Low Power, 350 MHz Voltage Feedback Amplifiers AD8038/AD8039 FUNCTIONAL BLOCK DIAGRAM Low power: 1 mA supply current/amp High speed 350 MHz, −3 dB bandwidth (G = +1) 425 V/μs slew rate Low cost Low noise 8 nV/√Hz @ 100 kHz 600 fA/√Hz @ 100 kHz Low input bias current: 750 nA maximum Low distortion −90 dB SFDR @ 1 MHz −65 dB SFDR @ 5 MHz Wide supply range: 3 V to 12 V Small packaging: 8-lead SOT-23, 5-lead SC70, and 8-lead SOIC AD8038 8 DISABLE –IN 2 NC 1 7 +VS +IN 3 6 VOUT –VS 4 5 NC 02951-001 FEATURES NC = NO CONNECT Figure 1. 8-lead SOIC (R) VOUT 1 AD8038 5 +VS 4 –IN +IN 3 02951-002 –VS 2 Figure 2. 5-Lead SC70 (KS) AD8039 Battery-powered instrumentation Filters A/D drivers Level shifting Buffering Photo multipliers 8 +VS –IN1 2 7 VOUT2 +IN1 3 6 –IN2 –VS 4 5 +IN2 02951-003 APPLICATIONS VOUT1 1 NC = NO CONNECT Figure 3. 8-Lead SOIC (R) and 8-Lead SOT-23 (RJ) GENERAL DESCRIPTION The AD8038 and AD8039 amplifiers have a wide input commonmode range of 1 V from either rail and swing to within 1 V of each rail on the output. These amplifiers are optimized for driving capacitive loads up to 15 pF. If driving larger capacitive loads, a small series resistor is needed to avoid excessive peaking or overshoot. 24 G = +10 21 18 15 G = +5 12 9 G = +2 6 3 G = +1 0 –3 –6 0.1 1 10 FREQUENCY (MHz) 100 1000 02951-004 The Analog Devices, Inc., proprietary XFCB process allows low noise operation (8 nV/√Hz and 600 fA/√Hz) at extremely low quiescent currents. Given a wide supply voltage range (3 V to 12 V), wide bandwidth, and small packaging, the AD8038 and AD8039 amplifiers are designed to work in a variety of applications where power and space are at a premium. The AD8039 amplifier is available in a 8-lead SOT-23 package, and the single AD8038 is available in both an 8-lead SOIC and a 5-lead SC70 package. These amplifiers are rated to work over the industrial temperature range of −40°C to +85°C. GAIN (dB) The AD8038 (single) and AD8039 (dual) amplifiers are high speed (350 MHz) voltage feedback amplifiers with an exceptionally low quiescent current of 1.0 mA/amplifier typical (1.5 mA maximum). The AD8038 single amplifier in the 8-lead SOIC package has a disable feature. Despite being low power and low cost, the amplifier provides excellent overall performance. Additionally, it offers a high slew rate of 425 V/μs and a low input offset voltage of 3 mV maximum. Figure 4. Small Signal Frequency Response for Various Gains, VOUT = 500 mV p-p, VS = ±5 V Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Powered by TCPDF (www.tcpdf.org) IMPORTANT LINKS for the AD8038_8039* Last content update 08/19/2013 03:00 am DOCUMENTATION PARAMETRIC SELECTION TABLES AN-649: Using the Analog Devices Active Filter Design Tool AN-581: Biasing and Decoupling Op Amps in Single Supply Applications AN-402: Replacing Output Clamping Op Amps with Input Clamping Amps AN-417: Fast Rail-to-Rail Operational Amplifiers Ease Design Constraints in Low Voltage High Speed Systems MT-060: Choosing Between Voltage Feedback and Current Feedback Op Amps MT-059: Compensating for the Effects of Input Capacitance on VFB and CFB Op Amps Used in Current-to-Voltage Converters MT-058: Effects of Feedback Capacitance on VFB and CFB Op Amps MT-056: High Speed Voltage Feedback Op Amps MT-053: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR MT-052: Op Amp Noise Figure: Don’t Be Mislead MT-050: Op Amp Total Output Noise Calculations for Second-Order System MT-049: Op Amp Total Output Noise Calculations for Single-Pole System MT-048: Op Amp Noise Relationships: 1/f Noise, RMS Noise, and Equivalent Noise Bandwidth MT-047: Op Amp No MT-033: Voltage Feedback Op Amp Gain and Bandwidth MT-032: Ideal Voltage Feedback (VFB) Op Amp A Stress-Free Method for Choosing High-Speed Op Amps FOR THE AD8038 Find Similar Products By Operating Parameters High Speed Amplifiers Selection Table UG-112: Universal Evaluation Board for Single, High Speed Op Amps Offered in SC-70 Packages UG-101: Evaluation Board User Guide FOR THE AD8039 AD8039-EP: Low Power, 350 MHz Voltage Feedback Amplifier AD8039-DSCC: Microcircuit, Linear, Low Power, 350 MHz Voltage Feedback Amplifier, Monolithic Silicon Military Data sheet AN-348: Avoiding Passive-Component Pitfalls AN-356: User’s Guide to Applying and Measuring Operational Amplifier Specifications UG-019: Universal Evaluation Board for Dual, High Speed Op Amps Offered in 8-Lead SOT-23 Packages DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE dBm/dBu/dBv Calculator Analog Filter Wizard 2.0 Power Dissipation vs Die Temp ADIsimOpAmp™ OpAmp Stability AD8038/AD8039 SPICE Macro-Model DESIGN COLLABORATION COMMUNITY Collaborate Online with the ADI support team and other designers about select ADI products. Follow us on Twitter: www.twitter.com/ADI_News Like us on Facebook: www.facebook.com/AnalogDevicesInc DESIGN SUPPORT Submit your support request here: Linear and Data Converters Embedded Processing and DSP Telephone our Customer Interaction Centers toll free: Americas: Europe: China: India: Russia: 1-800-262-5643 00800-266-822-82 4006-100-006 1800-419-0108 8-800-555-45-90 Quality and Reliability Lead(Pb)-Free Data SAMPLE & BUY EVALUATION KITS & SYMBOLS & FOOTPRINTS View the Evaluation Boards and Kits page for the AD8038 View the Evaluation Boards and Kits page for the AD8039 Symbols and Footprints for the AD8038 Symbols and Footprints for the AD8039 AD8038 AD8039 View Price & Packaging Request Evaluation Board Request Samples Check Inventory & Purchase Find Local Distributors * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page (labeled 'Important Links') does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. AD8038/AD8039 TABLE OF CONTENTS Features .............................................................................................. 1 Disable ......................................................................................... 13 Applications ....................................................................................... 1 Power Supply Bypassing ............................................................ 13 Functional Block Diagram .............................................................. 1 Grounding ................................................................................... 13 General Description ......................................................................... 1 Input Capacitance ...................................................................... 13 Revision History ............................................................................... 2 Output Capacitance ................................................................... 13 Specifications..................................................................................... 3 Input-to-Output Coupling ........................................................ 13 Absolute Maximum Ratings............................................................ 5 Applications Information .............................................................. 14 Maximum Power Dissipation ..................................................... 5 Low Power ADC Driver ............................................................ 14 Output Short Circuit .................................................................... 5 Low Power Active Video Filter ................................................. 14 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 15 Typical Performance Characteristics ............................................. 6 Ordering Guide .......................................................................... 16 Layout, Grounding, and Bypassing Considerations .................. 13 REVISION HISTORY 8/09—Rev. F to Rev. G 5/02—Rev. A to Rev. B Changes to Applications Section and General Description Section ................................................................................................ 1 Changes to Disable Section and Grounding Section ................. 13 Changes to Low Power ADC Driver Section and Low Power Active Video Filter Section ............................................................ 14 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 16 Add Part Number AD8038 ............................................... Universal Changes to Product Title ..................................................................1 Changes to Features ..........................................................................1 Changes to Product Description .....................................................1 Changes to Connection Diagram ....................................................1 Update to Specifications ...................................................................2 Update to Maximum Power Dissipation ........................................4 Update to Output Short Circuit.......................................................4 Update to Ordering Guide ...............................................................4 Change to Figure 2 ............................................................................4 Change to TPC 2 ...............................................................................5 Change to TPC 18 .............................................................................6 Change to TPC 27 .............................................................................7 Change to TPC 29 .............................................................................8 Change to TPC 30 .............................................................................8 Change to TPC 31 .............................................................................8 Added TPC 36....................................................................................8 Added TPC 37....................................................................................9 Edits to Low Power Active Video Filter....................................... 10 Change to Figure 4 ......................................................................... 10 8/04—Rev. E to Rev. F Changes to Figure 4 ........................................................................ 10 8/03—Rev. D to Rev. E Change to TPC 34............................................................................. 8 7/03—Rev. C to Rev. D Changes to Ordering Guide ............................................................ 4 Updated TPC 35 Caption ................................................................ 8 6/03—Rev. B to Rev. C Updated Connection Diagrams ...................................................... 1 Updated Ordering Guide ................................................................. 4 Updated Outline Dimensions ....................................................... 11 4/02—Rev. 0 to Rev. A Changes to Features ..........................................................................1 Update Specifications ................................................................... 2, 3 Edits to TPC 19 ..................................................................................7 Rev. G | Page 2 of 16 AD8038/AD8039 SPECIFICATIONS TA = 25°C, VS = ±5 V, RL = 2 kΩ, Gain = +1, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Overdrive Recovery Time Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE SFDR Second Harmonic Third Harmonic Second Harmonic Third Harmonic Crosstalk, Output-to-Output (AD8039) Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS DC Output Voltage Swing Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio POWER-DOWN DISABLE 1 Turn-On Time Turn-Off Time Disable Voltage—Part is Off Disable Voltage—Part is On Disabled Quiescent Current Disabled In/Out Isolation 1 Conditions Min Typ G = +1, VO = 0.5 V p-p G = +2, VO = 0.5 V p-p G = +1, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, VO = 2 V step, RL = 2 kΩ G = +2, 1 V overdrive G = +2, VO = 2 V step 300 350 175 100 45 425 50 18 MHz MHz MHz MHz V/μs ns ns fC = 1 MHz, VO = 2 V p-p, RL = 2 kΩ fC = 1 MHz, VO = 2 V p-p, RL = 2 kΩ fC = 5 MHz, VO = 2 V p-p, RL = 2 kΩ fC = 5 MHz, VO = 2 V p-p, RL = 2 kΩ f = 5 MHz, G = +2 f = 100 kHz f = 100 kHz −90 −92 −65 −70 −70 8 600 dBc dBc dBc dBc dB nV/√Hz fA/√Hz VO = ±2.5 V 0.5 4.5 400 3 ±25 70 RL = 1 kΩ VCM = ±2.5 V 10 2 ±4 67 MΩ pF V dB ±4 20 V pF 400 61 RL = 2 kΩ, saturated output 30% overshoot, G = +2 3.0 −Supply +Supply f = 1 MHz Only available in AD8038 8-lead SOIC package. Rev. G | Page 3 of 16 −71 −64 1.0 −77 −70 180 700 +VS − 4.5 +VS − 2.5 0.2 −60 Max 3 750 12 1.5 Unit mV μV/°C nA nA/°C nA dB V mA dB dB ns ns V V mA dB AD8038/AD8039 TA = 25°C, VS = 5 V, RL = 2 kΩ to VS/2, Gain = +1, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Overdrive Recovery Time Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE SFDR Second Harmonic Third Harmonic Second Harmonic Third Harmonic Crosstalk, Output-to-Output Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS DC Output Voltage Swing Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio POWER-DOWN DISABLE 1 Turn-On Time Turn-Off Time Disable Voltage—Part is Off Disable Voltage—Part is On Disabled Quiescent Current Disabled In/Out Isolation 1 Conditions Min Typ G = +1, VO = 0.2 V p-p G = +2, VO = 0.2 V p-p G = +1, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, VO = 2 V step, RL = 2 kΩ G = +2, 1 V overdrive G = +2, VO = 2 V step 275 300 150 30 45 365 50 18 MHz MHz MHz MHz V/μs ns ns fC = 1 MHz, VO = 2 V p-p, RL = 2 kΩ fC = 1 MHz, VO = 2 V p-p, RL = 2 kΩ fC = 5 MHz, VO = 2 V p-p, RL = 2 kΩ fC = 5 MHz, VO = 2 V p-p, RL = 2 kΩ f = 5 MHz, G = +2 f = 100 kHz f = 100 kHz −82 −79 −60 −67 −70 8 600 dBc dBc dBc dBc dB nV/√Hz fA/√Hz VO = ±2.5 V 0.8 3 400 3 ±30 70 RL = 1 kΩ VCM = ±1 V 10 2 1.0 − 4.0 65 MΩ pF V dB 0.9 − 4.1 20 V pF 340 59 RL = 2 kΩ, saturated output 30% overshoot 3 −65 f = 1 MHz Only available in AD8038 8-lead SOIC package. Rev. G | Page 4 of 16 0.9 −71 210 700 +VS − 4.5 +VS − 2.5 0.2 −60 Max 3 750 12 1.5 Unit mV μV/°C nA nA/°C nA dB V mA dB ns ns V V mA dB AD8038/AD8039 ABSOLUTE MAXIMUM RATINGS 2.0 Rating 12.6 V See Figure 5 ±VS ±4 V −65°C to +125°C −40°C to +85°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8038/AD8039 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8038/AD8039. Exceeding a junction temperature of 175°C for an extended time can result in changes in the silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (θJA), ambient temperature (TA), and total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated as 1.5 SOIC-8 SOT-23-8 1.0 SC70-5 0.5 0 –55 –25 5 35 65 95 AMBIENT TEMPERATURE (°C) 125 02951-005 Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) MAXIMUM POWER DISSIPATION (W) Table 3. Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board RMS output voltages should be considered. If RL is referenced to VS−, as in single-supply operation, then the total drive power is VS × IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS /4 for RL to midsupply PD = (VS × IS) + (VS/4)2/RL In single-supply operation with RL referenced to VS−, worst case is VOUT = VS /2. Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads from metal traces, throughholes, ground, and power planes reduce the θJA. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in the Layout, Grounding, and Bypassing Considerations section. Figure 5 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead SOIC (125°C/W), 5-lead SC70 (210°C/W), and 8-lead SOT-23 (160°C/W) packages on a JEDEC standard 4-layer board. θJA values are approximations. OUTPUT SHORT CIRCUIT TJ = TA + (PD × θJA) The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) multiplied by the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, then the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. Shorting the output to ground or drawing excessive current from the AD8038/AD8039 will likely cause a catastrophic failure. ESD CAUTION PD = quiescent power + (total drive power − load power) PD = [VS × IS] + [(VS/2) × (VOUT/RL)] − [VOUT2/RL] Rev. G | Page 5 of 16 AD8038/AD8039 TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions: ±5 V, CL = 5 pF, G = +2, RG = RF = 1 kΩ, RL = 2 kΩ, VO = 2 V p-p, Frequency = 1 MHz, TA = 25°C. 24 21 7 G = +10 RL = 2kΩ 6 18 5 G = +5 RL = 500Ω 12 GAIN (dB) 9 6 G = +2 3 0 3 RL = 1kΩ 2 G = +1 1 –3 1 100 10 1000 FREQUENCY (MHz) 0 0.1 02951-006 –6 0.1 4 1 10 100 1000 FREQUENCY (MHz) Figure 6. Small Signal Frequency Response for Various Gains, VOUT = 500 mV p-p 02951-009 GAIN (dB) 15 Figure 9. Small Signal Frequency Response for Various RL, VS = 5 V, VOUT = 500 mV p-p 7 8 VS = ±1.5V 6 RL = 2kΩ 7 VS = ±2.5V 5 6 RL = 500Ω 5 4 GAIN (dB) GAIN (dB) VS = ±5V 3 2 4 3 RL = 1kΩ 2 1 10 100 1000 FREQUENCY (MHz) 0 0.1 100 Figure 10. Large Signal Frequency Response for Various RL, VOUT = 3 V p-p, VS = 5 V 7 8 6 RL = 2kΩ 7 RL = 2kΩ 6 5 RL = 500Ω 5 GAIN (dB) 4 3 RL = 500Ω 2 RL = 1kΩ 4 3 RL = 1kΩ 2 1 1 10 100 1000 FREQUENCY (MHz) Figure 8. Small Signal Frequency Response for Various RL, VS = ±5 V, VOUT = 500 mV p-p 0 0.1 1 10 100 FREQUENCY (MHz) Figure 11. Large Signal Frequency Response for Various RL, VOUT = 4 V p-p, VS = ±5 V Rev. G | Page 6 of 16 02951-011 1 02951-008 GAIN (dB) 10 FREQUENCY (MHz) Figure 7. Small Signal Frequency Response for Various Supplies, VOUT = 500 mV p-p 0 0.1 1 02951-010 1 02951-007 1 0 0.1 AD8038/AD8039 5 70 OPEN-LOOP GAIN (dB) GAIN (dB) 2 1 0 –1 CL = 5pF –2 50 PHASE 30 FREQUENCY (MHz) 02951-012 –4 1000 45 10 0 100 GAIN 20 –10 10 90 40 –3 1 135 60 CL = 10pF PHASE (Degrees) 3 0 –20 0.01 1 0.1 10 –45 1000 100 02951-015 4 –5 180 80 CL = 15pF FREQUENCY (MHz) Figure 15. Open-Loop Gain and Phase, VS = ±5 V Figure 12. Small Signal Frequency Response for Various CL, VOUT = 500 mV p-p, VS = ±5 V, G = +1 9 7 CL = 15pF 5 6 –40°C CL = 10pF GAIN (dB) GAIN (dB) 3 1 –1 +25°C 3 +85°C CL = 5pF 0 1 10 100 1000 FREQUENCY (MHz) –3 0.1 02951-013 100 1000 Figure 16. Frequency Response vs. Temperature, Gain = +2, VS = ±5 V, VOUT = 2 V p-p –50 2 VOUT = 200mV 1 HARMONIC DISTORTION (dBc) VOUT = 1V –1 –2 VOUT = 500mV –3 VOUT = 2V –4 RL = 500Ω HD2 –55 0 RL = 500Ω HD3 –60 –65 –70 RL = 2kΩ HD3 –75 RL = 2kΩ HD2 –80 –85 –5 –90 1 10 100 1000 FREQUENCY (MHz) 02951-014 GAIN (dB) 10 FREQUENCY (MHz) Figure 13. Small Signal Frequency Response for Various CL, VOUT = 500 mV p-p, VS = 5 V, G = +1 –6 0.1 1 1 2 3 4 5 6 7 8 9 10 FREQUENCY (MHz) Figure 17. Harmonic Distortion vs. Frequency for Various Loads, VS = ±5 V, VOUT = 2 V p-p, G = +2 Figure 14. Frequency Response for Various Output Voltage Levels Rev. G | Page 7 of 16 02951-017 –5 02951-016 –3 AD8038/AD8039 –40 –45 10MHz HD2 RL = 500Ω HD2 –55 –50 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) –50 RL = 500Ω HD3 –60 –65 –70 RL = 2kΩ HD3 –75 RL = 2kΩ HD2 –80 5MHz HD2 10MHz HD3 –60 5MHz HD3 –70 1MHz HD3 –80 1MHz HD2 –90 1 2 3 4 5 6 7 8 9 10 FREQUENCY (MHz) –100 02951-018 –90 2 1 3 4 AMPLITUDE (V p-p) Figure 18. Harmonic Distortion vs. Frequency for Various Loads, VS = 5 V, VOUT = 2 V p-p, G = +2 02951-021 –85 Figure 21. Harmonic Distortion vs. VOUT Amplitude for Various Frequencies, VS = ±5 V, G = +2 –45 –50 G = +2 HD2 –70 G = +2 HD3 –80 G = +1 HD3 –90 –100 1 2 3 4 5 6 7 8 9 10 FREQUENCY (MHz) –55 10MHz HD3 5MHz HD2 –65 5MHz HD3 –75 1MHz HD3 1MHz HD2 –85 –95 1.0 1.5 2.0 2.5 3.0 AMPLITUDE (V p-p) Figure 19. Harmonic Distortion vs. Frequency for Various Gains, VS = ±5 V, VOUT = 2 V p-p 02951-022 HARMONIC DISTORTION (dBc) –60 02951-019 HARMONIC DISTORTION (dBc) 10MHz HD2 G = +1 HD2 Figure 22. Harmonic Distortion vs. Amplitude for Various Frequencies, VS = 5 V, G = +2 1000 VOLTAGE NOISE (nV/ Hz) G = +1 HD2 –60 G = +2 HD2 –70 G = +2 HD3 –80 10 1 10 1 2 3 4 5 6 7 8 9 10 FREQUENCY (MHz) Figure 20. Harmonic Distortion vs. Frequency for Various Gains, VS = 5 V, VOUT = 2 V p-p Rev. G | Page 8 of 16 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 23. Input Voltage Noise vs. Frequency 100M 02951-023 –100 100 G = +1 HD3 –90 02951-020 HARMONIC DISTORTION (dBc) –50 AD8038/AD8039 NOISE (fA/√Hz) 100k CL = 25pF WITH RSNUB = 19.6Ω 10k CL = 5pF 1k 1k 100 10k 100k 1M FREQUENCY (Hz) 50mV/DIV 02951-024 100 10 Figure 27. Small Signal Transient Response for Various CL, VS = 5 V Figure 24. Input Current Noise vs. Frequency RL = 500Ω 5ns/DIV 02951-027 CL = 10pF CL = 25pF WITH RSNUB = 19.6Ω RL = 2kΩ CL = 5pF 5ns/DIV 50mV/DIV Figure 25. Small Signal Transient Response for Various RL, VS = 5 V RL = 500Ω 5ns/DIV 02951-028 50mV/DIV 02951-025 CL = 10pF Figure 28. Small Signal Transient Response for Various CL, VS = ±5 V RL = 2kΩ RL = 500Ω RL = 2kΩ 5ns/DIV 500mV/DIV 02951-026 50mV/DIV Figure 26. Small Signal Transient Response for Various RL, VS = ±5 V 5ns/DIV 02951-029 2.5V Figure 29. Large Signal Transient Response for Various RL, VS = 5 V Rev. G | Page 9 of 16 AD8038/AD8039 IN RL = 2kΩ RL = 500Ω 5ns/DIV 2V/DIV 02951-033 1V/DIV 02951-030 OUT 50ns/DIV Figure 33. Input Overdrive Recovery, Gain = +1 Figure 30. Large Signal Transient Response for Various RL, VS = ±5 V CL = 25pF IN OUT CL = 5pF 5ns/DIV INPUT 1V/DIV OUTPUT 2V/DIV Figure 31. Large Signal Transient Response for Various CL, VS = 5 V 50ns/DIV 02951-034 500mV/DIV 02951-031 2.5V Figure 34. Output Overdrive Recovery, Gain = +2 CL = 10pF VS = ±5V G = +2 VOUT = 2V p-p 2mV/DIV CL = 5pF ERROR VOLTAGE +0.1% 0 –0.1% t=0 5ns/DIV 0.5V/DIV 5ns/DIV Figure 35. 0.1% Settling Time VOUT = 2 V p-p Figure 32. Large Signal Transient Response for Various CL, VS = ±5 V Rev. G | Page 10 of 16 02951-035 500mV/DIV 02951-032 VIN –10 10 –20 0 –30 –10 –20 –40 PSRR (dB) –50 SIDE B –60 SIDE A –70 –PSRR –30 –40 +PSRR –50 –60 –80 –70 –90 100 1000 –90 0.01 0.1 1 10 100 1000 400 500 02951-040 10 FREQUENCY (MHz) 02951-036 1 12 FREQUENCY (MHz) Figure 36. AD8039 Crosstalk, VIN = 1 V p-p, Gain = +1 02951-039 –80 –100 0.1 02951-041 CROSSTALK (dB) AD8038/AD8039 Figure 39. PSRR vs. Frequency 9 –10 8 –20 6 VOUT (p-p) CMRR (dB) –30 –40 VS = +5V VS = ±5V –50 5 4 VS = +5V 3 –60 2 –70 1 1 10 100 1000 FREQUENCY (MHz) 0 100 02951-037 0 –80 VS = ±5V 7 200 300 RLOAD (Ω) Figure 40. Output Swing vs. Load Resistance Figure 37. CMRR vs. Frequency, VIN = 1 V p-p 1.25 1000 1.00 SUPPLY CURRENT (mA) 10 1 0.75 0.50 0.25 VS = ±5V VS = +5V 0.1 0.01 0.1 1 10 100 FREQUENCY (MHz) 1000 02951-038 IMPEDANCE Ω) 100 0 0 2 4 6 8 10 SUPPLY VOLTAGE (V) Figure 41. AD8038 Supply Current vs. Supply Voltage Figure 38. Output Impedance vs. Frequency Rev. G | Page 11 of 16 AD8038/AD8039 0 –10 ISOLATION (dB) –20 –30 –40 –50 –60 –70 –90 0.1 1 10 FREQUENCY (MHz) 100 1000 02951-042 –80 Figure 42. AD8038 Input-Output Isolation (G = +2, RL = 2 kΩ, VS = ±5 V) Rev. G | Page 12 of 16 AD8038/AD8039 LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS DISABLE INPUT CAPACITANCE The AD8038 in the 8-lead SOIC package provides a disable feature. This feature disables the input from the output (see Figure 42 for input-output isolation) and reduces the quiescent current from typically 1 mA to 0.2 mA. When the DISABLE node is pulled below 4.5 V from the positive supply rail, the part becomes disabled. To enable the part, the DISABLE node needs to be pulled to greater than (VS – 2.5). Along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. A few picofarads of capacitance reduces the input impedance at high frequencies, in turn increasing the gain of the amplifiers, causing peaking of the frequency response, or even oscillations if severe enough. It is recommended that the external passive components that are connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. The ground and power planes must be kept at a distance of at least 0.05 mm from the input pins on all layers of the board. POWER SUPPLY BYPASSING Power supply pins are actually inputs, and care must be taken so that a noise-free stable dc voltage is applied. The purpose of bypass capacitors is to create low impedances from the supply to ground at all frequencies, thereby shunting or filtering a majority of the noise. Decoupling schemes are designed to minimize the bypassing impedance at all frequencies with a parallel combination of capacitors. The 0.01 μF or 0.001 μF (X7R or NPO) chip capacitors are critical and should be placed as close as possible to the amplifier package. Larger chip capacitors, such as 0.1 μF capacitors, can be shared among a few closely spaced active components in the same signal path. A 10 μF tantalum capacitor is less critical for high frequency bypassing and, in most cases, only one per board is needed at the supply inputs. GROUNDING A ground plane layer is important in densely packed PC boards to spread the current minimizing parasitic inductances. However, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. The length of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the high frequency impedance of the path. High speed currents in an inductive ground return create an unwanted voltage noise. OUTPUT CAPACITANCE To a lesser extent, parasitic capacitances on the output can cause peaking of the frequency response. Two methods to minimize this effect include the following: • • Put a small value resistor in series with the output to isolate the load capacitor from the output stage of the amplifier, see Figure 12, Figure 13, Figure 27, and Figure 28. Increase the phase margin with higher noise gains or add a pole with a parallel resistor and capacitor from −IN to the output. INPUT-TO-OUTPUT COUPLING The input and output signal traces should not be parallel to minimize capacitive coupling between the inputs and outputs, avoiding any positive feedback. The length of the high frequency bypass capacitor leads is most critical. A parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. Because load currents flow from the supplies as well, the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. For the larger value capacitors, which are intended to be effective at lower frequencies, the current return path distance is less critical. Rev. G | Page 13 of 16 AD8038/AD8039 APPLICATIONS INFORMATION LOW POWER ADC DRIVER LOW POWER ACTIVE VIDEO FILTER 2.5V 0.1µF Some composite video signals derived from a digital source contain clock feedthrough that can limit picture quality. Active filters made from op amps can be used in this application, but they consume 25 mW to 30 mW for each channel. In powersensitive applications, this can be too much, requiring the use of passive filters that can create impedance matching problems when driving any significant load. 10µF 3V 0.1µF 0V 3 8 REF 50Ω 1 VIN 2 1kΩ 1kΩ AD9203 AD8039 1kΩ 6 1kΩ 50Ω 7 5 1kΩ VINP VINN 4 0.1µF –5V 10µF 02951-043 1kΩ 10µF 1kΩ The AD8038 can be used to make an effective low-pass active filter that consumes one-fifth of the power consumed by an active filter made from an op amp. Figure 44 shows a circuit that uses a AD8038 with ±2.5 V supplies to create a three-pole Sallen-Key filter. This circuit uses a single RC pole in front of a standard 2-pole active section. RF 1Ω 680pF Figure 43. Schematic to Drive AD9203 with the AD8039 +2.5V The AD9203 is a low power (125 mW on a 5 V supply), 40 MSPS 10-bit converter. As such, the low power, high performance AD8039 is an appropriate amplifier choice to drive it. The AD9203 works best when the common-mode voltage at the input is at the midsupply or 2.5 V. The output stage design of the AD8039 makes it ideal for driving these types of ADCs. In this circuit, one of the op amps is configured in the inverting mode, and the other is in the noninverting mode. However, to provide better bandwidth matching, each op amp is configured for a noise gain of +2. The inverting op amp is configured for a gain of −1, and the noninverting op amp is configured for a gain of +2. Each has a very similar ac response. The input signal to the noninverting op amp is divided by 2 to normalize its voltage level and make it equal to the inverting output. R1 200Ω VIN R4 49.9Ω R2 499Ω C1 100pF R3 49.9Ω AD8038 C3 33pF –2.5V R5 75Ω 0.1µF VOUT 10µF Figure 44. Low-Pass Filter for Video Figure 45 shows the frequency response of this filter. The response is down 3 dB at 6 MHz; therefore, it passes the video band with little attenuation. The rejection at 27 MHz is 45 dB, which provides more than a factor of 100 in suppression of the clock components at this frequency. 10 0 –10 GAIN (dB) In low supply voltage applications, differential analog inputs are needed to increase the dynamic range of the ADC inputs. Differential driving can also reduce second and other even-order distortion products. The AD8039 can be used to make a dccoupled, single-ended-to-differential driver for driving these ADCs. Figure 43 is a schematic of such a circuit for driving the AD9203, 10-bit, 40 MSPS ADC. 10µF 0.1µF 02951-044 +5V The outputs of the op amps are centered at 2.5 V, which is the midsupply level of the ADC. This is accomplished by first taking the 2.5 V reference output of the ADC and dividing it by 2 with a pair of 1 kΩ resistors. The resulting 1.25 V is applied to the positive input of each op amp. This voltage is then multiplied by the gain of the op amps to provide a 2.5 V level at each output. Rev. G | Page 14 of 16 –20 –30 –40 –50 –60 0.1 1 10 FREQUENCY (MHz) Figure 45. Video Filter Response 100 02951-045 1kΩ AD8038/AD8039 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 5 1 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 46. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 2.20 2.00 1.80 1.35 1.25 1.15 5 1 4 2 3 PIN 1 2.40 2.10 1.80 0.65 BSC 1.00 0.90 0.70 1.10 0.80 0.10 MAX 0.30 0.15 0.40 0.10 SEATING PLANE 0.22 0.08 0.46 0.36 0.26 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203-AA Figure 47. 5-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-5) Dimensions shown in millimeters Rev. G | Page 15 of 16 012407-A 8 4.00 (0.1574) 3.80 (0.1497) AD8038/AD8039 3.00 2.90 2.80 1.70 1.60 1.50 8 7 6 5 1 2 3 4 PIN 1 INDICATOR 3.00 2.80 2.60 0.65 BSC 1.95 BSC 1.45 MAX 0.95 MIN 0.15 MAX 0.05 MIN 0.38 MAX 0.22 MIN 0.22 MAX 0.08 MIN SEATING PLANE 8° 4° 0° 0.60 BSC 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-BA 121608-A 1.30 1.15 0.90 Figure 48. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE Model AD8038AR AD8038AR-REEL AD8038AR-REEL7 AD8038ARZ 1 AD8038ARZ-REEL1 AD8038ARZ-REEL71 AD8038AKSZ-R21 AD8038AKSZ-REEL1 AD8038AKSZ-REEL71 AD8039AR AD8039AR-REEL AD8039AR-REEL7 AD8039ARZ1 AD8039ARZ-REEL1 AD8039ARZ-REEL71 AD8039ART-R2 AD8039ART-REEL AD8039ART-REEL7 AD8039ARTZ-R21 AD8039ARTZ-REEL1 AD8039ARTZ-REEL71 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 5-Lead Thin Shrink Small Outline Transistor Package [SC70] 5-Lead Thin Shrink Small Outline Transistor Package [SC70] 5-Lead Thin Shrink Small Outline Transistor Package [SC70] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Small Outline Transistor Package [SOT-23] 8-Lead Small Outline Transistor Package [SOT-23] 8-Lead Small Outline Transistor Package [SOT-23] 8-Lead Small Outline Transistor Package [SOT-23] 8-Lead Small Outline Transistor Package [SOT-23] 8-Lead Small Outline Transistor Package [SOT-23] Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked.. ©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02951-0-8/09(G) Rev. G | Page 16 of 16 Package Option R-8 R-8 R-8 R-8 R-8 R-8 KS-5 KS-5 KS-5 R-8 R-8 R-8 R-8 R-8 R-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 Branding H1C H1C H1C HYA HYA HYA HYA# HYA# HYA#