AD AD9262BCPZ-5 30 msps to 160 msps dual continuous time sigma-delta adc Datasheet

16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to
160 MSPS Dual Continuous Time Sigma-Delta ADC
AD9262
FEATURES
APPLICATIONS
Baseband quadrature receivers: CDMA2000, W-CDMA,
multicarrier GSM/EDGE, 802.16x, and LTE
Quadrature sampling instrumentation
Medical equipment
Radio detection and ranging (RADAR)
GENERAL DESCRIPTION
The AD9262 is a dual channel, 16-bit analog-to-digital converter (ADC) based on a continuous time (CT) sigma-delta (Σ-Δ)
architecture that achieves −87 dBc of dynamic range over a
10 MHz input bandwidth. The integrated features and characteristics unique to the continuous time Σ-Δ architecture significantly
simplify its use and minimize the need for external components.
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
ORA
VIN+A
VIN–A
CT Σ-Δ
MODULATOR
VREF
CFILT
VIN–B
VIN+B
CLK+
CLK–
SAMPLE
RATE
CONVERTER
LOW-PASS
DECIMATION
FILTER
AD9262
DC
CORRECT
CMOS
BUFFER
D15A
D0A
QUADRATURE
ERROR
ESTIMATE
GAIN
ADJ
PHASE
ADJ
DCO
CT Σ-Δ
MODULATOR
LOW-PASS
DECIMATION
FILTER
SAMPLE
RATE
CONVERTER
PHASELOCKED
LOOP
DC
CORRECT
CMOS
BUFFER
SERIAL
INTERFACE
AGND
SDIO SCLK CSB
D15B
D0B
ORB
DGND
07772-001
SNR: 83 dB (85 dBFS) to 10 MHz input
SFDR: −87 dBc to 10 MHz input
Noise figure: 15 dB
Input impedance: 1 kΩ
Power: 600 mW
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Selectable bandwidth
2.5 MHz/5 MHz/10 MHz real
5 MHz/10 MHz/20 MHz complex
Output data rate: 30 MSPS to 160 MSPS
Integrated dc and quadrature correction
Integrated decimation filters
Integrated sample rate converter
On-chip PLL clock multiplier
On-chip voltage reference
Offset binary, Gray code, or twos complement data format
Serial control interface (SPI)
Figure 1
The AD9262 incorporates an integrated dc correction and
quadrature estimation block that corrects for gain and phase
mismatch between the two channels. This functional block
proves invaluable in complex signal processing applications
such as direct conversion receivers.
The digital output data is presented in offset binary, Gray code,
or twos complement format. A data clock output (DCO) is
provided to ensure proper timing with the receiving logic. The
AD9262 has the added feature of interleaving Channel A and
Channel B data onto one 16-bit bus, simplifying on-board routing.
The ADC is available in three different bandwidth options of
2.5 MHz, 5 MHz, and 10 MHz, and operates on a 1.8 V analog
supply and a 1.8 V to 3.3 V digital supply, consuming 600 mW.
The AD9262 is available in a 64-lead LFCSP and is specified
over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1.
The AD9262 has a resistive input impedance that relaxes the
requirements of the driver amplifier. In addition, a 32× oversampled fifth-order continuous time loop filter significantly attenuates
out-of-band signals and aliases, reducing the need for external
filters at the input.
2.
An external clock input or the integrated integer-N PLL provides
the 640 MHz internal clock needed for the oversampled continuous time Σ-Δ modulator. On-chip decimation filters and sample
rate converters reduce the modulator data rate from 640 MSPS to a
user-defined output data rate between 30 MSPS and 160 MSPS,
enabling a more efficient and direct interface.
4.
3.
5.
6.
Continuous time Σ-Δ architecture efficiently achieves high
dynamic range and wide bandwidth.
Passive input structure reduces or eliminates the requirements for a driver amplifier.
An oversampling ratio of 32× and high order loop filter
provide excellent alias rejection reducing or eliminating the
need for antialiasing filters.
An integrated decimation filter, sample rate converter, PLL
clock multiplier, and voltage reference provide ease of use.
Integrated dc correction and quadrature error correction.
Operates from a single 1.8 V analog power supply and
1.8 V to 3.3 V output supply.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
AD9262* PRODUCT PAGE QUICK LINKS
Last Content Update: 09/27/2017
COMPARABLE PARTS
TOOLS AND SIMULATIONS
View a parametric search of comparable parts.
• AD9262 IBIS Model
EVALUATION KITS
REFERENCE MATERIALS
• AD9262 Evaluation Board
Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
DOCUMENTATION
Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
• Understanding Continuous-Time, Discrete-Time SigmaDelta ADCs And Nyquist ADCs
• AN-282: Fundamentals of Sampled Data Systems
DESIGN RESOURCES
• AN-283: Sigma-Delta ADCs and DACs
• AD9262 Material Declaration
• AN-807: Multicarrier WCDMA Feasibility
• PCN-PDN Information
• AN-808: Multicarrier CDMA2000 Feasibility
• Quality And Reliability
• AN-812: MicroController-Based Serial Port Interface (SPI)
Boot Circuit
• Symbols and Footprints
• AN-835: Understanding High Speed ADC Testing and
Evaluation
DISCUSSIONS
View all AD9262 EngineerZone Discussions.
• AN-878: High Speed ADC SPI Control Software
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• Interfacing the ADL5382 Quadrature I/Q Demodulator to
the AD9262 16-Bit Continuous Time Sigma-Delta ADC as
an RF-to-Bits Solution
Data Sheet
• AD9262: 16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160
MSPS Dual Continuous Time Sigma-Delta ADC Data Sheet
User Guides
• UG-051: Evaluating the AD9262, 16-Bit, Dual Continuous
Time Sigma Delta ADC and Demonstrating Direct
Conversion
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AD9262
TABLE OF CONTENTS
Features .............................................................................................. 1
AD9262BCPZ-10 ....................................................................... 12
Applications ....................................................................................... 1
Equivalent Circuits ......................................................................... 15
General Description ......................................................................... 1
Theory of Operation ...................................................................... 16
Functional Block Diagram .............................................................. 1
Analog Input Considerations ................................................... 16
Product Highlights ........................................................................... 1
Clock Input Considerations ...................................................... 18
Revision History ............................................................................... 2
Power Dissipation and Standby Mode .................................... 20
Specifications..................................................................................... 3
Digital Engine ............................................................................. 21
DC Specifications ......................................................................... 3
DC and Quadrature Error Correction (QEC) ........................ 23
AC Specifications.......................................................................... 4
Digital Outputs ........................................................................... 24
Digital Decimation Filtering Characteristics ............................ 5
Timing ......................................................................................... 25
Digital Specifications ................................................................... 6
Serial Port Interface (SPI) .............................................................. 26
Switching Specifications .............................................................. 7
Configuration Using the SPI ..................................................... 26
Absolute Maximum Ratings............................................................ 8
Hardware Interface..................................................................... 27
Thermal Resistance ...................................................................... 8
Applications Information .............................................................. 28
ESD Caution .................................................................................. 8
Filtering Requirement ................................................................ 28
Pin Configuration and Function Descriptions ............................. 9
Memory Map .................................................................................. 30
Typical Performance Characteristics ........................................... 10
Memory Map Definitions ......................................................... 30
AD9262BCPZ ............................................................................. 10
Outline Dimensions ....................................................................... 32
AD9262BCPZ-5.......................................................................... 11
Ordering Guide .......................................................................... 32
REVISION HISTORY
2/10—Rev. 0 to Rev. A
Changes to Figure 61 ...................................................................... 28
1/10—Revision 0: Initial Version
Rev. A | Page 2 of 32
AD9262
SPECIFICATIONS
DC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN1 = −2.0 dBFS,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ANALOG INPUT BANDWIDTH
ACCURACY
No Missing Codes
Offset Error
Gain Error
Integral Nonlinearity (INL)2
MATCHING CHARACERISTICS
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
ANALOG INPUT
Input Span, VREF = 0.5 V
Common-Mode Voltage
Input Resistance
POWER SUPPLIES
Supply Voltage
AVDD
CVDD
DVDD
DRVDD
Supply Current
IAVDD2
ICVDD2 PLL Enabled
ICVDD2 PLL Disabled
IDVDD2
IDRVDD2 (1.8 V)
IDRVDD2 (3.3 V)
POWER CONSUMPTION
Sine Wave Input2 PLL Disabled
Sine Wave Input2 PLL Enabled
Power-Down Power
Standby Power2
Sleep Power
1
2
Temp
Full
Min
Full
Full
Full
25°C
AD9262BCPZ
Typ
Max
16
2.5
AD9262BCPZ-5
Min
Typ
Max
16
5
AD9262BCPZ-10
Min
Typ
Max
16
10
Guaranteed
±0.025 ±0.2
±0.7
±3.0
±1.5
Guaranteed
±0.025 ±0.2
±0.7
±3.0
±1.5
Guaranteed
±0.025 ±0.2
±0.7
±3.0
±1.5
Full
Full
±0.035
±0.3
Full
Full
±1.5
±50
500
490
±0.2
±1.3
±0.035
±0.3
510
490
±1.5
±50
500
±0.2
±1.3
±0.035
±0.3
510
490
±1.5
±50
500
Unit
Bits
MHz
% FSR
% FSR
LSB
±0.2
±1.3
% FSR
% FSR
510
ppm/°C
ppm/°C
mV
Full
Full
Full
1.7
2
1.8
1
1.9
1.7
2
1.8
1
1.9
1.7
2
1.8
1
1.9
V p-p diff
V
kΩ
Full
Full
Full
Full
1.7
1.7
1.7
1.7
1.8
1.8
1.8
1.8
1.9
1.9
1.9
3.6
1.7
1.7
1.7
1.7
1.8
1.8
1.8
1.8
1.9
1.9
1.9
3.6
1.7
1.7
1.7
1.7
1.8
1.8
1.8
1.8
1.9
1.9
1.9
3.6
V
V
V
V
Full
Full
Full
Full
Full
Full
146
57
8.1
108
8.3
17
165
65
8.8
117
8.6
146
57
8.1
141
8.7
18
165
65
8.8
152
9.1
146
57
8.1
169
10
22
165
65
8.8
182
12.7
mA
mA
mA
mA
mA
mA
Full
Full
Full
Full
Full
487
576
23
10
3
538.5
640
547
636
23
10
3
601.5
703
600
688
23
10
3
660
762
mW
mW
mW
mW
mW
4
4
Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted.
Measured with a low input frequency, full-scale sine wave.
Rev. A | Page 3 of 32
4
AD9262
AC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,
unless otherwise noted.
Table 2.
AD9262BCPZ
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 600 kHz2
fIN = 1.2 MHz3
fIN = 2.4 MHz4
fIN = 4.2 MHz
fIN = 8.4 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 600 kHz
fIN = 1.2 MHz
fIN = 2.4 MHz
fIN = 4.2 MHz
fIN = 8.4 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 600 kHz2
fIN = 1.2 MHz3
fIN = 2.4 MHz4
fIN = 4.2 MHz
fIN = 8.4 MHz
NOISE SPECTRAL DENSITY (NSD)
AIN = −2 dBFS
AIN = −40 dBFS
NOISE FIGURE5
TWO-TONE SFDR
fIN1 = 1.8 MHz @ −8 dBFS, fIN2 = 2.1 MHz @ −8 dBFS
fIN1 = 2.1 MHz @ −8 dBFS, fIN2 = 2.4 MHz @ −8 dBFS
fIN1 = 3.7 MHz @ −8 dBFS, fIN2 = 4.2 MHz @ −8 dBFS
fIN1 = 7.2 MHz @ −8 dBFS, fIN2 = 8.4 MHz @ −8 dBFS
CROSSTALK6
ANALOG INPUT BANDWIDTH
APERTURE JITTER
Temp
Min
Typ
Full
Full
Full
25°C
25°C
86
89
89
89
25°C
25°C
25°C
25°C
25°C
Max
14.5
14.5
AD9262BCPZ-5
Min
Typ
83
86
86
86
Max
AD9262BCPZ-10
Min
81
14
14
Full
Full
Full
25°C
25°C
−87
−87
<−120
−80
Full
Full
25°C
−154.3
−155.4
15.6
−152
−154
25°C
25°C
25°C
25°C
25°C
25°C
25°C
−92
−87
−87
<−120
−80
−155
−156
15
−152
−154.5
−93
−110
1
5
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Data guaranteed over the full temperature range for the AD9262BCPZ only.
3
Data guaranteed over the full temperature range for the AD9262BCPZ-5 only.
4
Data guaranteed over the full temperature range for the AD9262BCPZ-10 only.
5
Noise figure with respect to 50 Ω. AD9262 internal impedance is 1000 Ω differential. See the AN-835 Application Note for a definition.
6
Crosstalk measured with an input signal on both channels at different frequencies and the leakage of one on to the other.
2
Rev. A | Page 4 of 32
Max
Unit
83
83
83
dB
dB
dB
dB
dB
13.5
13.5
Bits
Bits
Bits
Bits
Bits
−87
−87
<−120
−80
dBc
dBc
dBc
dBc
dBc
−155
−156
15
−153
−154.5
−93
−92.5
−92.5
−110
−110
2.5
1
Typ
10
1
dBFS/Hz
dBFS/Hz
dB
dBc
dBc
dBc
dBc
dB
MHz
ps rms
AD9262
DIGITAL DECIMATION FILTERING CHARACTERISTICS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,
unless otherwise noted.
Table 3.
Parameter1
Pass-Band Transition
Pass-Band Ripple
Stop Band
Stop Band Attenuation
1
Min
2.5
AD9262BCPZ
Typ
<0.1
3.75 MHz − fS/2
>85
Max
3.75
Min
5
AD9262BCPZ-5
Typ
Max
6.5
Min
10
<0.1
6.5 MHz − fS/2
>85
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Rev. A | Page 5 of 32
AD9262BCPZ-10
Typ
Max
13
<0.1
13 MHz − fS/2
>85
Unit
MHz
dB
MHz
dB
AD9262
DIGITAL SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,
unless otherwise noted.
Table 4.
Parameter1
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SCLK)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO, CSB, RESET)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage (VOH, IOH = 50 μA)
High Level Output Voltage (VOH, IOH = 0.5 mA)
Low Level Output Voltage (VOL, IOL = 1.6 mA)
Low Level Output Voltage (VOL, IOL = 50 μA)
DRVDD = 1.8 V
High Level Output Voltage (VOH, IOH = 50 μA)
High Level Output Voltage (VOH, IOH = 0.5 mA)
Low Level Output Voltage (VOL, IOL = 1.6 mA)
Low Level Output Voltage (VOL, IOL = 50 μA)
1
Temp
Min
Full
Full
Full
Full
Full
Full
0.4
0.3
−60
−60
Full
Full
Full
Full
Full
Full
1.2
0
−50
−10
Full
Full
Full
Full
Full
Full
1.2
0
−10
+40
Full
Full
Full
Full
3.29
3.25
Full
Full
Full
Full
1.79
1.75
Typ
CMOS/LVPECL
0.8
2
0.450
0.5
+60
+60
20
1
Unit
V p-p
V
μA
μA
kΩ
pF
DRVDD + 0.3
0.8
−75
+10
V
V
μA
μA
kΩ
pF
DRVDD + 0.3
0.8
+10
+135
V
V
μA
μA
kΩ
pF
30
2
26
5
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Rev. A | Page 6 of 32
Max
0.2
0.05
V
V
V
V
0.2
0.05
V
V
V
V
AD9262
SWITCHING SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS
unless otherwise noted.
Table 5.
Parameter1
CLOCK INPUT (USING CLOCK MULTIPLIER)
Conversion Rate
CLK± Period
CLK± Duty Cycle
CLOCK INPUT (DIRECT CLOCKING)
Conversion Rate
CLK± Period
CLK± Duty Cycle
DATA OUTPUT PARAMETERS
Output Data Rate
DCO to Data Skew (tSKEW)2
Sample Latency3
WAKE-UP TIME5
Power-Down Power
Standby Power
Sleep Power
OUT-OF-RANGE RECOVERY TIME3
SERIAL PORT INTERFACE6
SCLK Period
SCLK Pulse Width High Time (tSHIGH)
SCLK Pulse Width Low Time (tSLOW)
SDIO to SCLK Setup Time (tSDS)
SDIO to SCLK Hold Time (tSDH)
CSB to SCLK Setup Time (tSS)
CSB to SCLK Hold Time (tSH)
Temp
Min
Typ
Max
Unit
Full
Full
Full
30
6.25
40
50
160
33
60
MSPS
ns
%
Full
Full
Full
608
1.49
40
640
1.5625
50
672
1.64
60
MSPS
ns
%
Full
Full
Full
20
3
160
960
MSPS
ns
Cycles4
3
9
15
960
μs
μs
μs
Cycles4
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
40
16
16
5
2
5
2
ns
ns
ns
ns
ns
ns
ns
1
See the AN-83 5 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Data skew is measured from DCO 50% transition to data (D0x to D15x) 50% transition, with 5 pF load.
3
Typical measured value for the AD9262BCPZ-10. For the AD9262BCPZ-5 and the AD9262BCPZ, typical values double and quadruple the number of cycles, respectively.
4
Cycles refers to modulator clock cycles.
5
Wake-up time is dependent on the value of the decoupling capacitor, value shown with 10uF capacitor on VREF and CFILT.
6
See Figure 60 and the Serial Port Interface (SPI) section.
2
Timing Diagram
DCO
07772-002
tSKEW
D0x TO D15x
Figure 2. Timing Diagram
Rev. A | Page 7 of 32
AD9262
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 6.
Parameter
Electrical
AVDD to AGND
DVDD to DGND
DRVDD to DGND
AGND to DGND
AVDD to DRVDD
CVDD to CGND
CGND to DGND
D0A to D15A to DGND
D0B to D15B to DGND
DCO to DGND
ORA, ORB to DGND
SDIO to DGND
CSB to AGND
SCLK to AGND
VIN+A/VIN−A, VIN+B/VIN−B to AGND
CLK+, CLK− to CGND
Environmental
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 Sec)
Junction Temperature
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints, maximizing the
thermal capability of the package.
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−3.9 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +0.3 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +2.5 V
−0.3 V to +2.0 V
Table 7. Thermal Resistance
Package Type
64-Lead LFCSP (CP-64-4)
θJA
21.2
θJC
1.1
Unit
°C/W
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, metal in direct contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θJA.
ESD CAUTION
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 8 of 32
AD9262
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CLK+
CGND
AGND
AVDD
VIN–B
VIN+B
AVDD
CFILT
VREF
AVDD
VIN–A
VIN+A
AVDD
AGND
RESET
CSB
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
AD9262
CMOS OUTPUTS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK
SDIO
ORA
D15A
D14A
DVDD
DGND
DRVDD
D13A
D12A
D11A
D10A
D9A
D8A
D7A
D6A
NOTES
1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE
LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB
INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING
THE THERMAL CAPACITY OF THE PACKAGE.
07772-003
D11B
D12B
D13B
D14B
D15B
ORB
DRVDD
DGND
DVDD
DCO
D0A
D1A
D2A
D3A
D4A
D5A
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CLK–
CVDD
D0B
D1B
D2B
DVDD
DGND
DRVDD
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1
2
3 to 5, 9 to 21
6, 25, 43
7, 24, 42
8, 23, 41
22
26
27 to 40, 44, 45
46
47
48
49
50
51, 62
52, 55, 58, 61
53
54
56
57
59
60
63
64
65 (EPAD)
Mnemonic
CLK−
CVDD
D0B to D15B
DVDD
DGND
DRVDD
ORB
DCO
D0A to D15A
ORA
SDIO
SCLK
CSB
RESET
AGND
AVDD
VIN+A
VIN−A
VREF
CFILT
VIN+B
VIN−B
CGND
CLK+
Exposed pad (EPAD)
Description
Clock Input (−).
Clock Supply (1.8 V).
Channel B Data Output Pins. D0B is the LSB and D15B is the MSB.
Digital Supply (1.8 V).
Digital Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Channel B Overrange Indicator.
Data Clock Output.
Channel A Data Output Pins. D0A is the LSB and D15A is the MSB.
Channel A Overrange Indicator.
Serial Port Interface Data Input/Output.
Serial Port Interface Clock.
Serial Port Interface Chip Select Active Low.
Chip Reset.
Analog Ground.
Analog Supply (1.8 V).
Channel A Analog Input (+).
Channel A Analog Input (−).
Voltage Reference Input.
Noise Limiting Filter Capacitor.
Channel B Analog Input (+).
Channel B Analog Input (−).
Clock Ground.
Clock Input (+).
Analog Ground. (Pin 65 is the exposed thermal pad on the bottom of the package.) The
exposed pad must be soldered to ground.
Rev. A | Page 9 of 32
AD9262
TYPICAL PERFORMANCE CHARACTERISTICS
All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS,
TA = 25°C, output data rate 40 MSPS, unless otherwise noted.
AD9262BCPZ
0
120
BANDWIDTH: 2.5MHz
DATA RATE: 40MSPS
fIN: 600kHz AT –2dBFS
SNR: 87.9dB
SFDR: 88.2dBc
–20
80
–60
SNR/SFDR
–80
–100
SNR (dBFS)
60
SFDR (dBc)
40
–120
SNR (dB)
–140
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–100
–140
8
10
12
14
16
18
20
FREQUENCY (MHz)
–160
0
2
4
6
8
10
12
14
16
18
20
–20
–40
SFDR
–80
–100
SFDR (dBc)
–60
–80
–120
SFDR (dBFS)
–100
–140
0
2
4
6
8
10
12
14
16
18
FREQUENCY (MHz)
20
07772-063
AMPLITUDE (dBFS)
BANDWIDTH: 2.5MHz
DATA RATE: 40MSPS
fIN1: 1.8MHz AT –8dBFS
fIN2: 2.1MHz AT –8dBFS
SFDR: –91.7dBc
0
BANDWIDTH: 2.5MHz
DATA RATE: 40MSPS
fIN: 2.4MHz AT –2dBFS
SNR: 87.8dB
SFDR: 106.6dBc
–60
–160
0
Figure 8. AD9262BCPZ Two-Tone FFT with fIN1 = 1.8 MHz, fIN2 = 2.1 MHz
0
–40
–10
FREQUENCY (MHz)
Figure 5. AD9262BCPZ Single-Tone FFT with fIN = 1.2 MHz
–20
–20
–100
–140
6
–30
–80
–120
4
–40
–60
–120
2
–50
–40
–80
0
–60
–20
–60
–160
–70
0
07772-062
AMPLITUDE (dBFS)
–40
–80
INPUT AMPLITUDE (dBFS)
BANDWIDTH: 2.5MHz
DATA RATE: 40MSPS
fIN: 1.2MHz AT –2dBFS
SNR: 87.7dB
SFDR: 87.1dBc
–20
–90
Figure 7. AD9262BCPZ Single-Tone SNR and SFDR vs. Input Amplitude
with fIN = 600 kHz
Figure 4. AD9262BCPZ Single-Tone FFT with fIN = 600 kHz
0
0
–100
07772-070
0
07772-061
–160
07772-087
20
Figure 6. AD9262BCPZ Single-Tone FFT with fIN = 2.4 MHz
–120
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
INPUT AMPLITUDE (dBFS)
Figure 9. AD9262BCPZ Two-Tone SFDR/IMD3 vs. Input Amplitude
with fIN1 = 1.8 MHz, fIN2 = 2.1 MHz
Rev. A | Page 10 of 32
07772-077
AMPLITUDE (dBFS)
–40
SFDR (dBFS)
100
AD9262
AD9262BCPZ-5
120
0
BANDWIDTH: 5MHz
DATA RATE: 40MSPS
fIN: 1.2MHz AT –2dBFS
SNR: 85.3dB
SFDR: 87.1dBc
–20
80
–60
SNR/SFDR
AMPLITUDE (dBFS)
–40
SFDR (dBFS)
100
–80
–100
SNR (dBFS)
60
SFDR (dBc)
SNR (dB)
40
–120
20
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
Figure 10. AD9262BCPZ-5 Single-Tone FFT with fIN = 1.2 MHz
0
AMPLITUDE (dBFS)
–140
10
12
14
16
18
20
FREQUENCY (MHz)
–20
–10
BANDWIDTH: 5MHz
DATA RATE: 40MSPS
fIN1: 1.8MHz AT –8dBFS
fIN2: 2.1MHz AT –8dBFS
SFDR: –92.8dBc
–100
–140
8
–30
–80
–120
6
–40
–60
–120
4
–50
–40
–100
2
–60
–20
–80
0
–70
0
–60
–160
–80
Figure 13. AD9262BCPZ-5 Single-Tone SNR and SFDR vs. Input Amplitude with
fIN = 1.2 MHz
–160
07772-065
Figure 11. AD9262BCPZ-5 Single-Tone FFT with fIN = 2.4 MHz
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
Figure 14. AD9262BCPZ-5 Two-Tone FFT with fIN1 = 1.8 MHz, fIN2 = 2.1 MHz
0
0
BANDWIDTH: 5MHz
DATA RATE: 40MSPS
fIN: 4.2MHz AT –2dBFS
SNR: 85.7dB
SFDR: 104.9dBc
–20
–40
–20
SFDR (dBc)
–40
SFDR
–60
–80
–100
–60
–80
–120
SFDR (dBFS)
–100
–160
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
07772-066
–140
–120
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
INPUT AMPLITUDE (dBFS)
Figure 15. AD9262BCPZ-5 Two-Tone SFDR/IMD3 vs. Input Amplitude
with fIN1 = 2.1 MHz, fIN2 = 2.4 MHz
Figure 12. AD9262BCPZ-5 Single-Tone FFT with fIN = 4.2 MHz
Rev. A | Page 11 of 32
07772-078
AMPLITUDE (dBFS)
–40
–90
INPUT AMPLITUDE (dBFS)
BANDWIDTH: 5MHz
DATA RATE: 40MSPS
fIN: 2.4MHz AT –2dBFS
SNR: 85.7dB
SFDR: 87.4dBc
–20
AMPLITUDE (dBFS)
0
–100
07772-057
0
07772-064
–160
07772-092
–140
AD9262
AD9262BCPZ-10
0
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–100
–120
–140
–140
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
–160
Figure 16. AD9262BCPZ-10 Single-Tone FFT with fIN = 2.4 MHz
0
–140
12
14
16
18
20
FREQUENCY (MHz)
–160
07772-068
10
Figure 17. AD9262BCPZ-10 Single-Tone FFT with fIN = 4.2 MHz
16
18
20
BANDWIDTH: 10MHz
DATA RATE: 40MSPS
fIN1: 3.6MHz AT –8dBFS
fIN2: 4.2MHz AT –8dBFS
SFDR: –92.5dBc
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
Figure 20. AD9262BCPZ-10 Two-Tone FFT with fIN1 = 3.6 MHz, fIN2 = 4.2 MHz
0
BANDWIDTH: 10MHz
DATA RATE: 40MSPS
fIN: 8.4MHz AT –2dBFS
SNR: 82.6dB
SFDR: 104.1dBc
–20
–40
AMPLITUDE (dBFS)
–40
–60
–80
–100
–60
–80
–100
–120
–120
–140
–140
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
Figure 18. AD9262BCPZ-10 Single-Tone FFT with fIN = 8.4 MHz
–160
07772-069
0
BANDWIDTH: 10MHz
DATA RATE: 40MSPS
fIN1: 7.2MHz AT –8dBFS
fIN2: 8.4MHz AT –8dBFS
SFDR: –92.5dBc
–20
0
2
4
6
8
10
12
FREQUENCY (MHz)
14
16
18
20
07772-060
0
–160
14
–100
–140
8
12
–80
–120
6
10
–60
–120
4
8
–40
–100
2
6
–20
–80
0
4
0
–60
–160
2
Figure 19. AD9262BCPZ-10 Two-Tone FFT with fIN1 = 2.1 MHz, fIN2 = 2.4 MHz
AMPLITUDE (dBFS)
–40
0
FREQUENCY (MHz)
BANDWIDTH: 10MHz
DATA RATE: 40MSPS
fIN: 4.2MHz AT –2dBFS
SNR: 82.7dB
SFDR: 86.7dBc
–20
AMPLITUDE (dBFS)
–80
–120
–160
AMPLITUDE (dBFS)
–60
07772-067
AMPLITUDE (dBFS)
–40
BANDWIDTH: 10MHz
DATA RATE: 40MSPS
fIN1: 2.1MHz AT –8dBFS
fIN2: 2.4MHz AT –8dBFS
SFDR: –93dBc
–20
07772-058
BANDWIDTH: 10MHz
DATA RATE: 40MSPS
fIN: 2.4MHz AT –2dBFS
SNR: 82.8dB
SFDR: 87.7dBc
07772-059
0
Figure 21. AD9262BCPZ-10 Two-Tone FFT with fIN1 = 7.2 MHz, fIN2 = 8.4 MHz
Rev. A | Page 12 of 32
AD9262
110
120
SFDR (dBFS)
100
105
100
SFDR (dBc)
40
SNR (dB)
20
–90
–80
–70
–60
–50
–40
–30
–20
–10
INPUT AMPLITUDE (dBFS)
90
SFDR (dBc)
85
SNR (dB)
80
07772-093
0
–100
95
0
2
3
4
5
6
7
8
10
100
9
FREQUENCY (MHz)
Figure 22. AD9262BCPZ-10 Single-Tone SNR/SFDR vs. Input Amplitude
with fIN = 2.4 MHz
Figure 25. AD9262BCPZ-10 SNR/SFDR vs. Input Frequency
92
0
91
–20
1.9 V
SNR (dB)/SFDR (dBc)
90
–40
SFDR
1
07772-081
60
07772-090
SNR (dBFS)
SNR/SFDR
SNR/SFDR
80
SFDR (dBc)
–60
–80
SFDR (dBFS)
89
88
SFDR
1.8V
1.7V
87
86
85
84
SNR
1.9V
1.8V
1.7V
83
–100
82
–90
–80
–70
–60
–50
–40
–30
–20
81
–60
07772-076
–120
–100
–10
INPUT AMPLITUDE (dBFS)
Figure 23. AD9262BCPZ-10 Two-Tone SFDR/IMD3 vs. Input Amplitude
with fIN1 = 2.1 MHz, fIN2 = 2.4 MHz
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 26. AD9262BCPZ-10 SFDR/SNR vs. Temperature with fIN = 2.4 MHz
89
84.0
83.8
SFDR (dBc)
88
83.6
83.4
86
SNR (dB)
SNR/SFDR
87
85
83.2
83.0
82.8
82.6
84
SNR (dB)
82.4
83
20
40
60
80
100
120
OUTPUT DATA RATE (MSPS)
140
160
180
Figure 24. AD9262BCPZ-10 SNR/SFDR vs. Output Data Rate with fIN = 2.4 MHz
Rev. A | Page 13 of 32
82.0
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1.875
1.900
COMMON-MODE VOLTAGE (V)
Figure 27. AD9262BCPZ-10 SNR vs. Input Common-Mode Voltage
with fIN = 2.4 MHz
07772-091
0
07772-079
82.2
82
AD9262
0.5
83.0
fIN = 2.4MHz
82.5
0
82.0
INL ERROR (LSB)
81.0
80.5
80.0
79.5
–1.0
–1.5
–2.0
79.0
–2.5
78.0
–3.0
1.0
4.0
4.5
5.0
6.0
7.0
7.5
8.5 10.0 12.0 14.0 16.0 21.0
8.0
9.0 10.5 12.5 15.0 17.0
PLL DIVIDE RATIO
Figure 28. AD9262BCPZ-10 Single-Tone SNR vs. PLL Divide Ratio
0
8192
16,384 24,576 32,768 40,960 49,152 57,344 65,536
OUTPUT CODE
Figure 29. AD9262BCPZ-10 INL
Rev. A | Page 14 of 32
07772-096
78.5
07772-080
SNR (dB)
–0.5
fIN = 8.4MHz
81.5
AD9262
EQUIVALENT CIRCUITS
AVDD
26kΩ 1kΩ
CSB
500Ω
07772-004
07772-009
2V p-p DIFFERENTIAL
1.8V CM
500Ω
Figure 30. Equivalent Analog Input Circuit
Figure 34. Equivalent CSB Input Circuit
CVDD
DRVDD
10kΩ
10kΩ
90kΩ
30kΩ
07772-007
CVDD
CLK–
07772-005
CLK+
DGND
Figure 35. Equivalent Digital Output Circuit
Figure 31. Equivalent Clock Input Circuit
DRVDD
2.85kΩ
10kΩ
3.5kΩ
07772-006
10µF
TO CURRENT
GENERATOR
Figure 36. Equivalent VREF Circuit
Figure 32. Equivalent SDIO Input Circuit
1kΩ
SCLK
07772-008
30kΩ
Figure 33. Equivalent SCLK Input Circuit
Rev. A | Page 15 of 32
07772-010
1kΩ
SDIO
8.5kΩ
0.5V
AD9262
THEORY OF OPERATION
Figure 40. Digital Filter Cutoff Frequency
fOUT/2
DECIMATION SAMPLE RATE
FILTER
CONVERTER
fOUT
fMOD/16
BAND OF INTEREST
QUANTIZER
ADC
H(f)
fMOD/16
Figure 41. Sample Rate Converter
SRC
–
07772-033
DAC
ANALOG INPUT CONSIDERATIONS
Figure 37. Σ-Δ Modulator Overview
The quantizer produces a nine-level digital word. The quantization
noise is spread uniformly over the Nyquist band (see Figure 38),
but the feedback loop causes the quantization noise present in
the nine-level output to have a nonuniform spectral shape. This
noise-shaping technique (see Figure 39) pushes the in-band
noise out of band; therefore, the amount of quantization noise
in the frequency band of interest is minimal.
The digital decimation filter that follows the modulator removes
the large out-of-band quantization noise (see Figure 40), while
also reducing the data rate from fMOD to fMOD/16. If the internal
PLL is enabled, the sample rate converter generates samples at
the same frequency as the input clock frequency. If the internal
PLL is disabled, the sample rate converter can be programmed
to give an output frequency that is a divide ratio of the modulator
clock. The sample rate converter is designed to attenuate images
outside the band of interest (see Figure 41).
fMOD/2
BAND OF INTEREST
07772-034
QUANTIZATION NOISE
The continuous time modulator removes the need for an antialias filter at the input to the AD9262. A discrete time converter
aliases signals around the sample clock frequency and its multiples
to the band of interest (see Figure 42). Therefore, an external
antialias filter is needed to reject these signals.
DESIRED
INPUT
UNDESIRED
SIGNAL
fS
fS/2
ADC
07772-038
+
fMOD/32
07772-037
MODULATOR
LOOP FILTER
BAND OF INTEREST
07772-036
DIGITAL FILTER CUTOFF FREQUENCY
The AD9262 uses a continuous time Σ-Δ modulator to convert
the analog input to a digital word. The digital word is processed
by the decimation filter and rate-adjusted by the sample rate
converter (see Figure 37). The modulator consists of a continuous
time loop filter preceding a quantizer that samples at fMOD =
640 MSPS. This produces an oversampling ratio (OSR) of 32 for
a 10 MHz input bandwidth. The output of the quantizer is fed
back to a DAC that ideally cancels the input signal. The incomplete input cancellation residue is filtered by the loop filter and
is used to form the next quantizer sample.
Figure 42. Discrete Time Converter
In contrast, the continuous time Σ-Δ modulator used within the
AD9262 has inherent antialiasing. The antialiasing property
results from sampling occurring at the output of the loop filter
(see Figure 43), and thus aliasing occurs at the same point in the
loop as quantization noise is injected; aliases are shaped by the
same mechanism as quantization noise. The quantization noise
transfer function, NTF(f), has zeros in the band of interest and in
all alias bands because NTF(f) is a discrete time transfer function,
whereas the loop filter transfer function, LF(f), is a continuous
time transfer function, which introduces poles only in the band
of interest. The signal transfer function, being the product of
NTF(f) and LF(f), only has zeros in alias bands and therefore
suppresses all aliases.
L F (f)
Figure 38. Quantization Noise
LOOP FILTER
INP UT
LF(f)
fMOD QUANTIZATION
NOISE
BAND OF INTEREST
fMOD/2
07772-035
NOISE SHAPING
H(z)
fMOD
OUTPUT
NTF(f)
f
fMOD
Figure 43. Continuous Time Converter
Rev. A | Page 16 of 32
07772-039
Figure 39. Noise Shaping
AD9262
VIN+x
1:1
RT
50Ω
VS
AD9262
SIGNAL
SOURCE
VIN–x
AVDD
0.1µF
Figure 46. Differential Transformer Configuration
Voltage Reference
AVDD – 0.5V
500Ω
TO LOOP FILTER
STAGE 2
500Ω
FROM QUANTIZER
07772-040
DAC
Figure 44. Input Common Mode
Differential Input Configurations
A stable and accurate 0.5 V voltage reference is built into the
AD9262. The reference voltage should be decoupled to minimize
the noise bandwidth using a 10 μF capacitor. The reference is
used to generate a bias current into a matched resistor such that,
when used to bias the current in the feedback DAC, a voltage
of AVDD − 0.5 V is developed at the internal side of the input
resistors (see Figure 47). The current bias circuit should also be
decoupled on the CFILT pin with a 10 μF capacitor. For this
reason, the VREF voltage should always be 0.5 V.
AVDD – 0.5V
The AD9262 can also be configured for differential inputs. The
ADA4937-2 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the ADA4937-2 is easily set by connecting AVDD to
the VOCM2 pin of the ADA4937-2 (see Figure 45). The noise and
linearity of the ADA4937-2 need important consideration because
the system performance may be limited by the ADA4937-2.
+5V
VCM = AVDD
VIN p-p = 2V
VIN+x
500Ω
500Ω
VIN–x
0.5V
VREF 10kΩ
REF
TO LOOP
FILTER
STAGE 2
AVDD
10µF
500Ω
AVDD – 0.5V
+1.8V
0.1µF
CFILT
0.1µF
07772-043
VIN+x
VCM = AVDD
VIN p-p = 2V
VIN–x
2V p-p
50Ω
The analog inputs of the AD9262 are not internally dc biased. In
ac-coupled applications, the user must provide this bias externally.
Setting the device such that VCM = AVDD is recommended for
optimum performance. The analog inputs are 500 Ω resistors,
and the internal reference loop aims to develop 0.5 V across
each input resistor (see Figure 44). With 0 V differential input,
the driver sources 1 mA into each analog input.
07772-042
Input Common Mode
10µF
200Ω
200Ω 6
VOCM2 11
RT
60.4
VS
SIGNAL
SOURCE
7
AVDD
9
ADA4937-2
0.1µF
Internal Reference Connection
AD9262
12
15
200Ω
49.9Ω
Figure 47. Voltage Reference Loop
13
60.4Ω
VIN+x
0.1µF
–5V
07772-041
2V p-p
50Ω
VIN–x
To minimize thermal noise, the internal reference on the AD9262
is an unbuffered 0.5 V. It has an internal 10 kΩ series resistor,
which, when externally decoupled with a 10 μF capacitor, limits
the noise (see Figure 48). The unbuffered reference should not
be used to drive any external circuitry. The internal reference is
used by default and when Serial Register 0x18[6] is reset.
Figure 45. Differential Input Configuration Using the ADA4937-2
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a couple of megahertz (MHz), and excessive signal power
can cause core saturation, which leads to distortion.
Rev. A | Page 17 of 32
2.85kΩ
10kΩ
8.5kΩ
0.5V
3.5kΩ
10µF
TO CURRENT
GENERATOR
Figure 48. Internal Reference Configuration
07772-044
For frequencies offset from dc, where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 46. The center
tap of the secondary winding of the transformer is connected to
AVDD to bias the analog input.
AD9262
External Reference Operation
If an external reference is desired, the internal reference can be
disabled by setting Serial Register 0x18[6] high. Figure 49 shows
an application using the ADR130B as a stable external reference.
10kΩ
Direct Clocking
Figure 49. External Reference Configuration
CLOCK INPUT CONSIDERATIONS
The AD9262 offers two modes of sourcing the ADC sample
clock (CLK+ and CLK−). The first mode uses an on-chip clock
multiplier that accepts a reference clock operating at the lower
input frequency. The on-chip phase-locked loop (PLL) then
multiplies the reference clock to a higher frequency, which is
then used to generate all the internal clocks required by the ADC
The clock multiplier provides a high quality clock that meets
the performance requirements of most applications. Using the
on-chip clock multiplier removes the burden of generating and
distributing the high speed clock.
The second mode bypasses the clock multiplier circuitry and
allows the clock to be directly sourced. This mode enables the
user to source a very high quality clock directly to the Σ-Δ
modulator. Sourcing the ADC clock directly may be necessary
in demanding applications that require the lowest possible ADC
output noise. See Figure 28, which shows the degradation in
SNR performance for the various PLL settings.
In either case, when using the on-chip clock multiplier or sourcing
the high speed clock directly, it is necessary that the clock
source have low jitter to maximize the ADC noise performance.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. As jitter increases, the SNR performance of the
AD9262 degrades from that specified in Table 2. The jitter
inherent in the part due to the PLL root sum squares with any
external clock jitter, thereby degrading performance. To prevent
jitter from dominating the performance of the AD9262, the input
clock source should be no greater than 1 ps rms of jitter.
The CLK± inputs are self-biased to 450 mV (see Figure 31);
if the inputs are dc-coupled, it is important to maintain the
specified 450 mV input common-mode voltage. Each input pin
can safely swing from 200 mV p-p to 1 V p-p single-ended
about the 450 mV common-mode voltage. The recommended
clock inputs are CMOS or LVPECL.
The specified clock rate of the Σ-Δ modulator, fMOD, is 640 MHz.
The clock rate possesses a direct relationship to the available
input bandwidth of the ADC.
The default configuration of the AD9262 is for direct clocking
where the PLL is bypassed. Figure 50 shows one preferred method
for clocking the AD9262. A low jitter clock source is converted
from a single-ended signal to a differential signal using an RF
transformer. The back-to-back Schottky diodes across the
secondary side of the transformer limits clock excursions into the
AD9262 to approximately 0.8 V p-p differential. This helps
prevent the large voltage swings of the clock from feeding
through to other portions of the AD9262 while preserving the
fast rise and fall times of the signal, which are critical to
achieving low jitter.
0.1µF
CLOCK
INPUT
CLK+
0.1µF
CLK–
50Ω
0.1µF
ADC
AD9262
SCHOTTKY
DIODES:
HSM2812
Figure 50. Transformer-Coupled Differential Clock
If a differential clock is not available, the AD9262 can be driven
by a single-ended signal into the CLK+ terminal with the CLK−
terminal ac-coupled to ground. Figure 51 shows the circuit
configuration.
0.1µF
CLOCK
INPUT
CLK+
50Ω
CLK–
ADC
AD9262
SCHOTTKY
DIODES:
0.1µF HSM2812
Figure 51. Single-Ended Clock
Another option is to ac couple a differential LVPECL signal to
the sample clock input pins, as shown in Figure 52. The AD951x
family of clock drivers is recommended because it offers excellent
jitter performance.
0.1µF
CLOCK
INPUT
0.1µF
50Ω1
150Ω
Rev. A | Page 18 of 32
0.1µF
CLK
AD951x
LVPECL
DRIVER
CLOCK
INPUT
Bandwidth = fMOD ÷ 64
In either case, using the on-chip clock multiplier to generate the
Σ-Δ modulator clock rate or directly sourcing the clock, any
deviation from 640 MHz results in a change in input band-
MINI-CIRCUITS
TC1-1-13M+, 1:1
0.1µF
XFMR
07772-046
TO CURRENT
GENERATOR
100Ω
CLK
240Ω
240Ω
CLK+
CLK–
ADC
AD9262
0.1µF
50Ω1
RESISTORS ARE OPTIONAL.
Figure 52. Differential LVPECL Sample Clock
07772-048
10µF
07772-047
0.1µF
0.5V
07772-045
ADR130B
AVDD
width. The input range of the clock is limited to 640 MHz ± 5%.
In situations where the AD9262 loses its clock and then later
regains it, it is important that the sample rate converter be reset
and reprogrammed before the desired output data rate is
achieved.
AD9262
Internal PLL Clock Distribution
PLL Autoband Select
The alternative clocking option available on the AD9262 is to apply
a low frequency reference clock and use the on-chip clock multiplier to generate the high frequency fMOD rate. The internal clock
architecture is shown in Figure 53.
The PLL VCO has a wide operating range that is covered by
overlapping frequency bands. For any desired VCO output
frequency, there are multiple valid PLL band select values. The
AD9262 possesses an automatic PLL band select feature on chip
that determines the optimal PLL band setting. This feature can
be enabled by writing to Register 0x0A[6]and is the recommended
configuration with the PLL clocking option. When the device is
taken out of sleep or standby mode, Register 0x0A[6] must be
toggled to reinitiate the autoband detect. See Table 9 for information about enabling the autoband select along with configuring
the PLL.
CLK+/CLK–
LOOP
FILTER
PHASE
DETECTOR
VCO
PLL
DIVIDER
÷N
÷2
MODULATOR
CLOCK
640MSPS
Table 10. PLL Multiplication Factors
07772-049
PLL MULT
0x0A[5:0]
PLLENABLE
0x09[2]
Figure 53. Internal Clock Architecture
The clock multiplication circuit operates such that the VCO
outputs a frequency, fVCO, equal to the reference clock input
multiplied by N.
fVCO = (CLK±) × (N)
where N is the PLL multiplication (PLLMULT) factor.
The Σ-Δ modulator clock frequency, fMOD, is equal to
fMOD = fVCO ÷ 2
The reference clock, CLK±, is limited to 30 MHz to 160 MHz
when configured to use the on-chip clock multiplier. Given the
input range of the reference clock and the available multiplication
factors, the fVCO is approximately 1280 MHz. This results in the
desired fMOD rate of 640 MHz with a 50% duty cycle.
Before the PLL enable register bit (PLLENABLE) is set, the PLL
multiplication factor should be programmed into Register
0x0A[5:0]. After setting the PLLENABLE bit, the PLL locks and
reports a locked state in Register 0x0A[7]. If the PLL multiplication factor is changed, the PLL enable bit should be reset and set
again. Some common clock multiplication factors are shown in
Table 11.
The recommended sequence for enabling and programming the
on-chip clock multiplier is shown in Table 9.
Table 9. Sequence for Enabling and Programming the PLL
Step
1
2
3
4
5
6
Procedure
Apply a reference clock to the CLK± pins.
Program the PLL multiplication factor in
Register 0x0A[5:0]. See Table 10.
Enable the PLL; Register 0x09 = 04 (decimal).
Enable PLL autoband select.
Initiate an SRC reset; Register 0x101[5:0] = 0.
Set SRC to desired value via Register 0x101[5:0].
0x0A[5:0]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Rev. A | Page 19 of 32
PLLMULT (N)
8
8
8
8
8
8
8
8
9
10
10
12
12
14
15
16
17
18
18
20
21
21
21
24
25
25
25
28
28
30
30
32
0x0A[5:0]
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PLLMULT (N)
32
34
34
34
34
34
34
34
34
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
AD9262
Table 11. Common Modulator Clock Multiplication Factors
CLK±
(MHz)
30.72
39.3216
52.00
61.44
76.80
78.00
78.6432
89.60
92.16
122.88
134.40
153.60
157.2864
0x0A[5:0]
(PLLMULT)
42
32
25
21
17
17
16
15
14
10
10
8
8
fVCO
(MHz)
1290.24
1258.29
1300.00
1290.24
1305.60
1326.00
1258.29
1344.00
1290.24
1228.80
1344.00
1228.80
1258.29
fMOD
(MHz)
645.12
629.15
650.00
645.12
652.80
663.00
629.15
672.00
645.12
614.40
672.00
614.40
629.15
BW
(MHz)
10.08
9.83
10.16
10.08
10.20
10.36
9.83
10.50
10.08
9.60
10.50
9.60
9.83
Jitter Considerations
The aperture jitter requirements for continuous time Σ-Δ converters may be more forgiving than Nyquist rate converters. The
continuous time Σ-Δ architecture is an oversampled system
and to accurately represent the analog input signal to the ADC,
a large number of output samples must be averaged together. As
a result, the jitter contribution from each sample is root sum
squared, resulting in a more subtle impact on noise performance as compared to Nyquist converters where aperture
jitter has a direct impact on each sampled output.
POWER DISSIPATION AND STANDBY MODE
The AD9262 power consumption can be further reduced by
configuring the chip in channel power-down, standby, or sleep
mode. The low power modes turn off internal blocks of the chip,
including the reference. As a result, the wake-up time is dependent on the amount of circuitry that is turned off. Fewer internal
circuits that are powered down result in proportionally shorter
wake-up time. The low power modes are shown in Table 12.
In the standby mode, all clock related activity and the output
channels are disabled. Only the references and CMOS outputs
remain powered up to ensure a short recovery and link integrity. During sleep mode, all internal circuits are powered down,
putting the device into its lowest power mode, and the CMOS
outputs are disabled.
Each ADC channel can be independently powered down or
both channels can be set simultaneously by writing to the
channel index, Register 0x05[1:0].
Table 12. Low Power Modes
Mode
Normal
Power-Down
Standby
Sleep
In the block diagram of the continuous time Σ-Δ modulator
(see Figure 37), the two building blocks most susceptible to
jitter are the quantizer and the DAC. The error introduced
through the sampling process is reduced by the loop gain and
shaped in the same way as the quantization noise and, therefore,
its effect can be neglected. On the contrary, the jitter error
associated with the DAC directly adds to the input signal, thus
increasing the in-band noise power and degrading the modulator
performance. The SNR degradation due to jitter can be
represented by the following equation.
SNR = −20 log (2πfanalogtjitter_rms) dB
where fanalog is the analog input frequency and tjitter_rms is the jitter.
The SNR performance of the AD9262 remains constant within
the input bandwidth of the converter, from DC to 10 MHz.
Therefore, the minimal jitter specification is determined at the
highest input frequency. From the calculation, the aperture
jitter of the input clock must be no greater than 1 ps to achieve
optimal SNR performance.
Rev. A | Page 20 of 32
0x08[1:0]
0x0
0x1
0x2
0x3
Analog Circuitry
On
Off
Off
Off
Clock
On
On
Off
Off
Ref
On
On
On
Off
AD9262
DIGITAL ENGINE
Table 14. DEC4 Filter Coefficients
Bandwidth Selection
Coefficient
Number
C0, C22
C1, C21
C2, C20
C3, C19
C4, C18
C5, C17
The digital engine (see Figure 54) selects the decimation signal
bandwidth by cascading third-order sinc (sinc3) decimate-by-2
filters. For a 10 MHz signal band, no filters are cascaded; for a
5 MHz signal band, a single filter is used; and for a 2.5 MHz
signal band, the 5 MHz filter is cascaded with a second filter.
Depending on the signal bandwidth, this drops the data rate
into the fixed decimation filter. As a result, lower signal bandwidth
options result in lower power. Bandwidth selection is determined
by setting Serial Register 0x0F[6:5]. Table 13 summarizes the
available bandwidth options.
AD9262BCPZ-5
5 MHz
5 MHz
2.5 MHz
2.5 MHz
Coefficient
Number
C0, C62
C1, C61
C2, C60
C3, C59
C4, C58
C5, C57
C6, C56
C7, C55
C8, C54
C9, C53
C10, C52
C11, C51
C12, C50
C13, C49
C14, C48
C15, C47
AD9262BCPZ-10
10 MHz
5 MHz
2.5 MHz
2.5 MHz
Decimation Filters
The fixed decimation filters reduce the sample rate from 640 MSPS
to 40 MSPS. A fixed frequency low-pass filter is used to define
the signal band. This filter incorporates magnitude equalization
for the droop of the preceding sinc decimation filters and the
sinc filters of the sample rate converter. Table 14 and Table 15
detail the coefficients for the DEC4 and LPF/EQZ filters. Sinc filter
implementation for all sinc filters is standard.
BANDWIDTH SELECTION
10MHz
4
Σ-Δ
OUTPUT
5MHz
DEC01
SINC3 2
2.5MHz
10MHz
5MHz
Coefficient
1121
0
−2796
0
10,184
16,384
Coefficient
17
31
−15
−52
36
78
−84
−98
170
97
−291
−42
441
−98
−592
353
Coefficient
Number
C16, C46
C17, C45
C18, C44
C19, C43
C20, C42
C21, C41
C22, C40
C23, C39
C24, C38
C25, C37
C26, C36
C27, C35
C28, C34
C29, C33
C30, C32
C31
Coefficient
694
−744
−677
1271
450
−1909
103
2612
−1147
−3326
3022
4051
−6870
−5305
21,141
38,956
DECIMATION FILTERS
DEC1
DEC2
DEC3
DEC4
LPF/EQZ
SINC4 2
SINC4 2
SINC6 2
HB 2
FIR
INT1
INT2
INT3
HB 2
HB 2
SINC5 4
2.5MHz
DEC02
SINC3 2
2
10MHz
INT4
5MHz
SINC5 8
2.5MHz
SAMPLE RATE CONVERTER
Figure 54. Digital Engine
Rev. A | Page 21 of 32
NCO
16
DATA
OUTPUT
07772-050
AD9262BCPZ
2.5 MHz
2.5 MHz
2.5 MHz
2.5 MHz
Coefficient
Number
C6, C16
C7, C15
C8, C14
C9, C13
C10, C12
C11
Table 15. LPF/EQZ Filter Coefficients
Table 13. Output Bandwidth Options
BW[1:0]
0x0
0x1
0x2
0x3
Coefficient
−21
0
122
0
−418
0
AD9262
Sample Rate Converter
If the main clocking source of the AD9262 is provided by the
PLL, it is important, once the PLL has been programmed and
locked, to initiate an SRC reset before programming the desired
KOUT factor. This is done by first writing 0x101[5:0] = 0 and
then rewriting to the same register with the appropriate KOUT
value. In addition, if the AD9262 loses its clock source and then
later regains it, an SRC reset should be initiated.
The sample rate converter (SRC) allows the flexibility of a
user-defined output sample rate, enabling a more efficient
and direct interface to the digital receiver blocks.
The sample rate converter performs an interpolation and
resampling procedure to provide an output data rate of
20 MSPS to 168 MSPS. Table 16 and Table 17 detail the
coefficients for the INT1 and INT2 filters. The sinc filters
are a standard implementation.
Table 18. SRC Conversion Factors
The relationship between the output sample rate and the Σ-Δ
modulator clock rate is expressed as follows:
fOUT = fMOD ÷ KOUT
Table 18 shows the available KOUT conversion factors.
Table 16. INT1 Filter Coefficients
Coefficient
Number
C0, C26
C1, C25
C2, C24
C3, C23
C4, C22
C5, C21
C6, C20
Coefficient
15
0
−97
0
361
0
−1017
Coefficient
Number
C7, C19
C8, C18
C9, C17
C10, C16
C11, C15
C12, C14
C13
Coefficient
0
2450
0
−5761
0
20,433
32,768
Table 17. INT2 Filter Coefficients
Coefficient
Number
C0, C14
C1, C13
C2, C12
C3, C11
Coefficient
−27
0
227
0
Coefficient
Number
C4, C10
C5, C9
C6, C8
C7
Coefficient
−1032
0
4928
8192
0x101[5:0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Rev. A | Page 22 of 32
KOUT
SRC reset
4
4
4
4
4
4
4
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
0x101[5:0]
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
KOUT
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
16
16.5
17
17.5
18
18.5
19
19.5
20
20.5
21
21.5
0x101[5:0]
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
KOUT
22
22.5
23
23.5
24
24.5
25
25.5
26
26.5
27
27.5
28
28.5
29
29.5
30
30.5
31
31.5
AD9262
Cascaded Filter Responses
DC AND QUADRATURE ERROR CORRECTION (QEC)
The cascaded filter responses for the three signal bandwidth
settings are for a 160 MSPS output data rate, as shown in Figure 55,
Figure 56, and Figure 57.
In direct conversion or other quadrature systems, mismatches
between the real (I) and imaginary (Q) signal paths cause
frequencies in the positive spectrum to image into the negative
spectrum and vice versa. From an RF point of view, this is
equivalent to information above the LO frequency interfering
with information below the LO frequency, and vice versa. These
mismatches may occur from gain and/or phase mismatches in
the analog quadrature demodulator or in any components in
the ADC signal chain itself. In a single-carrier zero-IF system
where the carrier has been placed symmetrically around dc, this
causes self-distortion of the carrier as the two sidebands fold
onto one another and degrade the EVM of the signal.
0
0.08
AMPLITUDE (dBFS)
–20
0.04
–40
0
–60
–0.04
–80
–0.08
0
2
–100
4
6
FREQUENCY (MHz)
8
10
–120
–140
0
10
20
30
40
50
FREQUENCY (MHz)
60
70
80
07772-051
–160
Figure 55. 10 MHz Signal Bandwidth, 160 MSPS
The integrated quadrature error correction (QEC) algorithm of
the AD9262 attempts to measure and correct the amplitude and
phase imbalances of the I and Q signal paths to achieve higher
levels of image suppression than is achievable by analog means
alone. These errors can be corrected in an adapted manner
where the I and Q gain and quadrature phase mismatches are
constantly estimated and corrected. This allows changes in the
mismatches due to slow supply and temperature changes to be
constantly tracked.
0
0.08
AMPLITUDE (dBFS)
–20
0.04
–40
0
–60
–0.04
–80
–0.08
0
1
–100
2
3
FREQUENCY (MHz)
4
5
–120
–140
10
20
30
40
50
FREQUENCY (MHz)
60
70
80
07772-052
–160
0
Figure 56. 5 MHz Signal Bandwidth, 160 MSPS
0.08
0
–60
–0.04
–80
–0.08
LO Leakage (DC) Correction
0.5
–100
1.5
FREQUENCY (MHz)
2.5
–120
–140
–160
0
10
20
30
40
50
FREQUENCY (MHz)
60
70
80
07772-053
AMPLITUDE (dBFS)
0.04
–40
The quadrature errors are corrected in a frequency independent
manner on the AD9262; therefore, systems with significant
mismatch in the baseband chain may have reduced image
suppression. The AD9262 QEC still corrects the systematic
imbalances.
The convergence time of the QEC algorithm is dependent on
the statistics of the input signal. For large signals and large
imbalance errors, this convergence time is typically less than
two million samples of the AD9262 output data rate.
0
–20
In a multicarrier communication system, this can be even more
problematic because carriers of widely different power levels
can interfere with one another. For example, a large carrier
centered at +f1 can have an image appear at –f1 that can be
larger than the desired carrier at this frequency.
In a direct conversion receiver subsystem, LO to RF leakage of
the quadrature modulator shows up as dc offsets at baseband.
These offsets are added to dc offsets in the baseband signal
paths, and both contribute to a carrier at dc. In a zero-IF receiver,
this dc energy can cause problems because it appears in band of
a desired channel. As part of the AD9262 QEC function, the dc
offset is suppressed by applying a low frequency notch filter to
form a null around dc. The 3 dB bandwidth of this notch filter
vs. the AD9262 output data rates is shown in Figure 58.
Figure 57. 2.5 MHz Signal Bandwidth, 160 MSPS
Rev. A | Page 23 of 32
AD9262
60
Interleaved Outputs
The AD9262 has the added feature of interleaving Channel A
and Channel B data onto one 16-bit bus. This feature is available for integer values of KOUT greater than 8 and does not apply
to half values of KOUT. The interleave function can be accessed
by writing to Register 0x14[5]. The data from both Channel A
and Channel B are interleaved and presented on the Channel A
bus, whereas the Channel B bus is internally grounded. Channel
A is sampled on the falling edge of DCO and Channel B on the
rising edge. The output of Channel A and Channel B can be
interchanged by inverting the DCO clock, Register 0x16[7]. In this
case, Channel B is sampled on the falling edge and Channel A
on the rising edge.
3dB BANDWIDTH (Hz)
50
40
30
20
0
30
50
70
90
110
130
150
OUTPUT DATA RATE (MSPS)
07772-072
10
Figure 58. DC Correction Low Frequency Notch Filter 3 dB Bandwidth vs.
Output Data Rate
DCO
The quadrature gain, quadrature phase, and dc correction
algorithms can also be disabled independently for system
debugging or to save power by setting Register 0x112[2:0].
The default configuration on the AD9262 has the QEC and dc
correction blocks disabled, and Register 0x101[6] must be
pulled high to enable the correction blocks. After the QEC is
enabled and a correction value has been calculated, the value
remains active as long as any one of the QEC functions (DC,
gain, or phase correction) is used.
QEC and DC Correction Range
Table 19 gives the minimum and maximum correction ranges
of the algorithms on the AD9262 If the mismatches are greater
than these ranges, an imperfect correction results.
Table 19. QEC and DC Correction Range
Parameter
Gain
Phase
DC
Min
−1.1 dB
−1.79 degrees
−6 %
Max
+1.0 dB
+1.79 degrees
+6%
DIGITAL OUTPUTS
Digital Output Format
The AD9262 offers a variety of digital output formats for ease of
system integration. The digital output on each channel consists
of 16 data bits and an output clock signal (DCO) for data latching.
The data bits can be configured for offset binary, twos complement, or Gray code by writing to Register 0x14[1:0]. In addition,
the voltage swing of the digital outputs can be configured to 3.3 V
TTL levels or a reduced voltage swing of 1.8 V by accessing
Register 0x14[7]. When 3.3 V voltage levels are desirable, the
DRVDD power supply must be set to 3.3 V.
BUS A
A
B
A
B
BUS B
A
07772-094
DCO
In applications where constant tracking of the dc offsets and
quadrature errors are not needed, the algorithms can be
independently frozen to save power. When frozen, the image
and LO leakage (dc) correction are still performed, but changes
are no longer tracked. Register 0x112[5:3] disables the
respective correction when frozen.
Figure 59. Interleaved Output Mode
Overrange (OR) Condition
The ORA and ORB (ORx) pins serve as indicators for an overrange
condition. The ORx pins are triggered by in-band signals that
exceed the full-scale range of the ADC. In addition, the AD9262
possesses out-of-band gain above 10 MHz. Therefore, a large
out-of-band signal may trip an overrange condition.
The ORx pins are synchronous outputs that are updated at the
output data rate. Ideally, ORx should be latched on the falling
edge of DCO to ensure proper setup-and-hold time. However,
because an overrange condition typically extends well beyond one
clock cycle (that is, it does not toggle at the DCO rate) data can
usually be successfully detected on the rising edge of DCO or
monitored asynchronously.
The AD9262 has two trip points that can trigger an overrange
condition: analog and digital. The analog trip point is located in
the modulator ,and the second trip point is in the digital engine.
In normal operation, it is possible for the analog trip point to
toggle the ORx pin for a number of clock cycles as the analog
input approaches full scale. Because the ORx pin is a pulse-width
modulated (PWM) signal, as the analog input increases in amplitude, the duration of overrange pin toggling increases. Eventually,
when the ORx pin is high for an extended period of time, the
ADC is overloaded, whereby there is little correspondence
between analog input and digital output.
The second trip point is in the digital block. If the input signal is
large enough to cause the data bits to clip to its maximum fullscale level, an overrange condition occurs. The overrange trip
point can be adjusted by specifying a threshold level.
Rev. A | Page 24 of 32
AD9262
occurs, the modulator resets itself after 16 consecutive clock
cycles of overrange.
Table 20 shows the corresponding threshold level in dBFS vs.
register setting. If the input signal crosses this level, the ORx pin
is set. In the case where 0x111[5:0] is set to all 0s, the threshold
level is set to the maximum code of 32,76710. This feature provides a means of reporting the instantaneous amplitude as it
crosses a user-provided threshold. This gives the user a sense
of the signal level without needing to perform a full power
measurement.
If the AD9262 is used in a system that incorporates automatic
gain control (AGC), the ORx signal can be used to indicate that
the signal amplitude should be reduced. This may be particularly
effective for use in maximizing the signal dynamic range if the
signal includes high occurrence components that occasionally
exceed full scale by a small amount.
The user has the ability to select how the overrange conditions
are reported, and this is controlled through Register 0x111 via
AUTORST, OR_IND, and ORTHRESH (see Table 21). By
enabling the AUTORST bit, Register 0x111[7], if an overrange
occurs, the ADC automatically resets itself. The ORx pins remain
high until the automatic reset has completed. If an analog trip
TIMING
The AD9262 provides a data clock out (DCO) pin to assist in
capturing the data in an external register. The data outputs are
valid on the rising edge of DCO, unless changed by setting
Serial Register 0x16[7] (see the Serial Port Interface (SPI)
section). See Figure 2 for a graphical timing description.
Table 20. OR Threshold Levels
0x111[5:0]
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
Threshold (dBFS)
−36.12
−30.10
−26.58
−24.08
−22.14
−20.56
−19.22
−18.06
−17.04
−16.12
−15.29
−14.54
−13.84
−13.20
−12.60
−12.04
−11.51
−11.02
−10.56
−10.10
−9.68
0x111[5:0]
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
Threshold (dBFS)
−9.28
−8.89
−8.52
−8.16
−7.82
−7.50
−7.18
−6.88
−6.58
−6.30
−6.02
−5.75
−5.49
−5.24
−5.00
−4.76
−4.53
−4.30
−4.08
−3.87
−3.66
ORTHRESH[4:0]
00000
0x111[5:0]
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Threshold (dBFS)
−3.45
−3.25
−3.06
−2.87
−2.68
−2.50
−2.32
−2.14
−1.97
−1.80
−1.64
−1.48
−1.32
−1.16
−1.00
−0.86
−0.71
−0.56
−0.42
−0.28
−0.14
Table 21. ORx Conditions
ORx Conditions
Normal, Reset Off
Digital Threshold,
Reset Off
Full Overrange,
Reset Off
Data Valid, No Reset
Normal, Reset On
Digital Threshold,
Reset On
Full Overrange,
Reset On
Data Valid,
Reset On
AUTORST
0
0
OR_IND
0
0
ORTHRESH[5:0]
0
0
1
0
X
0
1
1
1
0
0
1
0
X
00000
1
1
0
X
If analog trip or digital trip or calibration, ORx = 0, else ORx = 1
Digital trip: if 16-bit output > 32,767, ORx = 1, else ORx = 0
Digital threshold: if 16-bit output > ORTHRESH, ORx = 1,
else ORx = 0
If analog trip or digital trip ORx = 1 else ORx = 0
1
1
1
X
If analog trip or digital trip or calibration, ORx = 0 else ORx = 1
>0
>0
Rev. A | Page 25 of 32
Description
Digital trip: if 16-bit output > 32,767, ORx = 1, else ORx = 0
Digital threshold: if 16-bit output > ORTHRESH, ORx = 1,
else ORx = 0
If analog trip or digital trip, ORx = 1, else ORx = 0
AD9262
SERIAL PORT INTERFACE (SPI)
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and the length is determined
by the W0 bit and the W1 bit. All data is composed of 8-bit words.
The first bit of each individual byte of serial data indicates whether
a read or write command is issued. This allows the serial data
input/output (SDIO) pin to change direction from an input to
an output.
The AD9262 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. This provides
the user added flexibility and customization depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that are further divided into fields, as documented in
the Memory Map section. For detailed operational information,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and to read the contents
of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output
(SDIO) pin to change direction from an input to an output at the
appropriate point in the serial frame.
CONFIGURATION USING THE SPI
As summarized in Table 22, three pins define the SPI of this ADC.
The SCLK pin synchronizes the read and write data presented
to the ADC. The SDIO pin allows data to be sent and read from
the internal ADC memory map registers. The CSB pin is an active
low control that enables or disables the read and write cycles.
Table 22. Serial Port Interface Pins
Data can be sent in MSB-first or in LSB-first mode. MSB first is
the default setting on power-up and can be changed via the
configuration register. For more information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Pin Name
SCLK
Table 23. SPI Timing Diagram Specifications
SDIO
CSB
Description
SCLK (serial clock) is the serial shift clock. SCLK
synchronizes serial interface reads and writes.
SDIO (serial data input/output) is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB (chip select bar) is an active low control that
gates the read and write cycles.
Parameter
tSDS
tSDH
tSCLK
tSS
tSH
tSHIGH
The falling edge of CSB in conjunction with the rising edge of
SCLK determines the start of the framing. Figure 60 and Table 23
provide an example of the serial timing and its definitions.
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic
high state
Minimum period that SCLK should be in a logic
low state
tSLOW
Other modes involving CSB are available. CSB can be held low
indefinitely to permanently enable the device (this is called
streaming). CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are
placed in a high impedance mode.
tSDS
tSS
tSHIGH
tSDH
tSCLK
tSH
tSLOW
CSB
SCLK DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
07772-054
SDIO DON’T CARE
DON’T CARE
Figure 60. Serial Port Interface Timing Diagram
Rev. A | Page 26 of 32
AD9262
HARDWARE INTERFACE
The pins described in Table 22 comprise the physical interface
between the programming device of the user and the serial port
of the AD9262. The SCLK and CSB pins function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
PROM or PIC microcontrollers. This provides the user with the
ability to use an alternate method to program the ADC. One
such method is described in detail in the AN-812 Application
Note, MicroController-Based Serial Port Interface (SPI) Boot
Circuit.
Rev. A | Page 27 of 32
AD9262
APPLICATIONS INFORMATION
Depending on the application and the system architecture, this
low order filter may or may not be necessary. The signal transfer function (STF) of a continuous time feedforward ADC
usually contains out-of-band peaks. Because these STF peaks
are typically one or two octaves above the pass-band edge, they
are not problematic in applications where the bulk of the signal
energy is in or near the pass band. However, in applications
with large far-out interferers, it is necessary to either add a filter
to attenuate these problematic signals or to allocate some of the
ADC dynamic range to accommodate them.
Figure 61 shows the normalized STF of the AD9262 CT Σ-Δ
converter. The figure shows out-of-band peaking beyond the
band edge of the ADC. Within the 10 MHz band of interest, the
STF is maximally flat with less than 0.1 dB of gain. Maximum
peaking occurs at 60 MHz with 10 dB of gain. To put this into
perspective, for a fixed input power, a 5 MHz in-band signal
appears at −5 dBFS, a 25 MHz tone appears at −2 dBFS and
60 MHz tone at +5 dBFS. Because the maximum input to the
ADC is −2 dBFS, large out-of-band signals can quickly saturate
the system. This implies that, under these conditions, the digital
outputs of the ADC no longer accurately represent the input.
See the Overrange (OR) Condition section for details on overrange detection and recovery.
15
13
The noise performance is normalized to a −2 dBFS in-band
signal. The AD9262 STF and NTF are flat within the band of
interest and should result in almost no change in input level
and IBN. Beyond the bandwidth of the AD9262, out-of-band
peaking adds gain to the system, therefore requiring the input
power to be scaled back to prevent in-band noise degradation.
The input power is scaled back to a point where only 3 dB of
noise degradation is allowed, therefore resulting in the response
shown in Figure 62.
5
0
–5
–40°C
–10
–15
+85°C
+25°C
CHEBYSHEVII
FILTER RESPONSE
–20
–25
0
10
20
30
40
50
80
90
100
An example third-order, low-pass Chebyshev II type filter is
shown in Figure 63. Table 24 summarizes the components
and manufacturers used to build the circuit.
L1
180nH
9
C1
18pF
5
C2
390pF
L1
180nH
3
1
VIN+
C3
150pF
1kΩ
AD9262
CT-Σ-Δ
VIN–
C2
390pF
–1
Figure 63. Third-Order, Low-Pass Chebyshev II Filter
–3
0
10
20
30
40
50
60
FREQUENCY (MHz)
70
80
90
100
Figure 61. STF
Rev. A | Page 28 of 32
07772-095
7
07772-073
GAIN (dB)
70
Figure 62. Maximum Input Level for 3 dB Noise Degradation
11
–5
60
FREQUENCY (MHz)
07772-074
The need for antialias protection often requires one or two
octaves for a transition band, which reduces the usable bandwidth of a Nyquist converter to between 25% and 50% of the
available bandwidth. A CT Σ-Δ converter maximizes the available signal bandwidth by forgoing the need for an anti-aliasing
filter because the architecture possesses inherent anti-aliasing.
Although a high order, sharp cutoff antialiasing filter may not
be necessary because of the unique characteristics of the
architecture, a low order filter may still be required to precede
the ADC for out-of-band signal handling.
Figure 61 shows the gain profile of the AD9262, and this can be
interpreted as the level at which the signal power should be
scaled back to prevent an overload condition. This is the ultimate trip point and before this point is reached, the in-band
noise (IBN) slowly degrades. As a result, it is recommended that
the low-pass filter be designed to match the profile of Figure 62,
which shows the maximum input signal for a 3 dB degradation
of in-band noise. The input signal is attenuated to allow only
3 dB of noise degradation over frequency.
AMPLITUDE (dB)
FILTERING REQUIREMENT
AD9262
Table 24. Chebyshev II Filter Components
Parameter
C1
L1
C2
C3
Value
18
180
390
150
Unit
pF
nH
pF
pF
Manufacturer
Murata GRM188 series, 0603
Coil Craft 0603 LS, 2%
Murata GRM188 series, 0603
Murata GRM188 series, 0603
In addition to matching the profile of Figure 62, group delay
and channel matching are important filter design criteria. Low
tolerance components are highly recommended for improved
channel matching, which translates to minimal degradation in
image rejection for quadrature systems.
Rev. A | Page 29 of 32
AD9262
MEMORY MAP
Table 25. Memory Map
Register Name
SPI Port Config
Chip ID
Chip Grade
Channel Index
Power Modes
PLLENABLE
PLL
Analog Input
Output Modes
Output Adjust
Output Clock
Reference
Output Data
Overrange
QEC1
QEC2
Address
0x00
0x01
0x02
0x05
0x08
0x09
0x0A
0x0F
0x14
0x15
0x16
0x18
0x101
0x111
0x112
0x113
Bit 7
0
Bit 6
LSBFIRST
Bit 5
SOFTRESET
Bit 4
Bit 3
1
1
CHIPID[7:0]
CHILDID[2:0]
1
Bit 2
SOFTRESET
Bit 1
LSBFIRST
Channel[1:0]
PWRDWN[1:0]
PLLLOCKED
DRVSTD
PLLENABLE
PLLMULT[5:0]
PLLAUTO
BW[1:0]
Interleave
OUTENB
OUTINV
DRVSTR33[1:0]
Format[1:0]
DRVSTR18[1:0]
DCOINV
AUTORST
EXTREF
QEC
OR_IND
DCFRZ
PHASEFRZ
KOUT[5:0]
ORTHRESH[5:0]
GAINFRZ
DCENB
DCFRC
PHASEENB
PHASEFRC
MEMORY MAP DEFINITIONS
Table 26. Memory Map Definitions
Register
SPI Port Config
Address
0x00
Bit(s)
6, 1
Mnemonic
LSBFIRST
Default
0
Chip ID
Chip Grade
0x01
0x02
5, 2
[7:0]
[5:4]
SOFTRESET
CHIPID
CHILDID
0
0x22
0
Channel Index
0x05
[1:0]
Channel
0
Power Modes
0x08
[1:0]
PWRDWN
0
PLLENABLE
PLL
0x09
0x0A
2
7
PLLENABLE
PLLLOCKED
0
0
0x0F
6
[5:0]
[6:5]
PLLAUTO
PLLMULT
BW
0
0
0
Analog Input
Bit 0
0
Description
0: serial interface uses MSB first format
1: serial interface uses LSB first format
1: default all serial registers except 0x00, 0x09, and 0x0A
0x22: AD9262
0x00: 10 MHz bandwidth
0x10: 5 MHz bandwidth
0x20: 2.5 MHz bandwidth
0: both channels addressed simultaneously
1: Channel A only addressed
2: Channel B only addressed
3: both channels addressed simultaneously
0x0: normal operation
0x1: power-down (local)
0x2: standby (everything except reference circuits)
0x3: sleep
1: enable PLL
0: PLL is not locked
1: PLL is locked
1: PLL autoband enabled
See Table 10
See Table 13
Rev. A | Page 30 of 32
GAINENB
GAINFRC
AD9262
Register
Output Modes
Output Adjust
Address
0x14
0x15
Output Clock
Reference
Output Data
0x16
0x18
0x101
Overrange
0x111
QEC1
0x112
QEC2
0x113
Bit(s)
7
Mnemonic
DRVSTD
Default
0
5
4
2
[1:0]
Interleave
OUTENB
OUTINV
Format
0
0
0
0
[3:2]
DRVSTR33
0
[1:0]
DRVSTR18
2
7
6
6
[5:0]
7
6
[5:0]
5
4
3
2
1
0
2
1
0
DCOINV
EXTREF
QEC
KOUT
AUTORST
OR_IND
ORTHRESH
DCFRZ
PHASEFRZ
GAINFRZ
DCENB
PHASEENB
GAINENB
DCFRC
PHASEFRC
GAINFRC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
0: 3.3 V
1: 1.8 V
1: interleave both channels onto D[15:0]A
1: data outputs tristated
1: data outputs bitwise inverted
0: offset binary
1: twos complement
2: Gray code
3: offset binary
Typical output sink current to DGND
0: 33 mA
1: 63 mA
2: 93 mA
3: 120 mA
Typical output sink current to DGND
0: 10 mA
1: 20 mA
2: 30 mA
3: 39 mA
1: invert DCO
1: use external reference
1: enable quadrature error correction
Output data rate, see Table 18
1: enable loop filter reset indicator on ORx pin
Refer to Table 21
Refer to Table 20
1: freeze dc correction coefficients
1: freeze phase correction coefficients
1: freeze gain correction coefficients
1: disable dc correction
1: disable phase correction
1: disable gain correction
1: force dc correction coefficients to initial static values
1: force phase correction coefficients to initial static values
1: force gain correction coefficients to initial static values
Rev. A | Page 31 of 32
AD9262
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
48
64
49
PIN 1
INDICATOR
1
PIN 1
INDICATOR
0.50
BSC
0.50
0.40
0.30
1.00
0.85
0.80
SEATING
PLANE
33
32
16
17
0.05 MAX
0.02 NOM
0.30
0.23
0.18
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
6.35
6.20 SQ
6.05
EXPOSED PAD
(BOTTOM VIEW)
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
091707-C
8.75
BSC SQ
TOP VIEW
Figure 64. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9262BCPZ-10
AD9262BCPZ-5
AD9262BCPZ
AD9262EBZ
AD9262-5EBZ
AD9262-10EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07772-0-2/10(A)
Rev. A | Page 32 of 32
Package Option
CP-64-4
CP-64-4
CP-64-4