CAT24WC33/65 32K/64K-Bit I2C Serial CMOS EEPROM FEATURES ■ 400 KHz I2C Bus Compatible* ■ Commercial, Industrial and Automotive Tem- perature Ranges ■ 1.8 to 5.5 Volt Read and Write Operation ■ Write Protection ■ Cascadable for up to Eight Devices ■ 1,000,000 Program/Erase Cycles ■ Self-Timed Write Cycle with Auto-Clear ■ Schmitt Trigger Inputs for Noise Protection DESCRIPTION d e The CAT24WC33/65 is a 32K/64K-bit Serial CMOS E2PROM internally organized as 4096/8192 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The VSS 1 2 3 4 it n o 8 7 6 5 c s VCC WP SCL SDA SOIC Package (J, W, K, X) A0 A1 A2 i D VSS 1 2 3 4 8 7 6 5 CAT24WC33/65 features a 32-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin DIP or 8-pin SOIC packages. u n BLOCK DIAGRAM DIP Package (P, L) A0 A1 A2 a P ■ 100 Year Data Retention ■ 8-Pin DIP or 8-Pin SOIC PIN CONFIGURATION s t r –Bottom 1/4 Array Protected When WP at VIH ■ 32/64-Byte Page Write Buffer VCC WP SCL SDA EXTERNAL LOAD SENSE AMPS SHIFT REGISTERS DOUT ACK VCC WORD ADDRESS BUFFERS VSS COLUMN DECODERS 256 SDA START/STOP LOGIC E2PROM XDEC 128/256 128/256 X 256 CONTROL LOGIC WP PIN FUNCTIONS Pin Name Function A0, A1, A2 Device Address Inputs SDA Serial Data/Address SCL Serial Clock WP Write Protect VCC +1.8V to +5.5V Power Supply VSS Ground DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL SCL A0 A1 A2 STATE COUNTERS SLAVE ADDRESS COMPARATORS * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1049, Rev. D CAT24WC33/65 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100mA RELIABILITY CHARACTERISTICS Symbol Parameter Min. NEND(3) Endurance TDR(3) Data Retention 100 ESD Susceptibility 2000 Latch-up 100 VZAP (3) ILTH(3)(4) VCC = +1.8V to +5.5V, unless otherwise specified. it n o Parameter ICC Power Supply Current ISB(5) Standby Current (VCC = 5V) ILI Input Leakage Current ILO Output Leakage Current VIL Input Low Voltage VIH Input High Voltage c s i D Cycles/Byte d e u n Limits Min. a P Units 1,000,000 D.C. OPERATING CHARACTERISTICS Symbol Max. s t r Typ. Years Volts mA Max. Units Test Conditions 3 mA fSCL = 100 KHz 1 µA VIN = GND or VCC 10 µA VIN = GND to VCC 10 µA VOUT = GND to VCC –1 VCC x 0.3 V VCC x 0.7 VCC + 0.5 V VOL1 Output Low Voltage (VCC = +3.0V) 0.4 V IOL = 3.0 mA VOL2 Output Low Voltage (VCC = +1.8V) 0.5 V IOL = 1.5 mA CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O(3) CIN (3) Test Max. Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (A0, A1, A2, SCL, WP) 6 pF VIN = 0V Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range. Doc. No. 1049, Rev. D 2 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC33/65 A.C. CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified Output Load is 1 TTL Gate and 100pF Read & Write Cycle Limits CAT24WCXX-1.8 1.8V-5.5V Min. Symbol Parameter FSCL Clock Frequency tBUF Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start tHD:STA Start Condition Hold Time tLOW (1) TI tAA (1) CAT24WCXX 2.5V-5.5V Max. Min. 100 200 200 3.5 3.5 4.7 4 4 Clock Low Period 4.7 4.7 tHIGH Clock High Period 4 tSU:STA Start Condition Setup Time (for a Repeated Start Condition) tHD:DAT Data In Hold Time tSU:DAT Data In Setup Time SDA and SCL Rise Time (1) SDA and SCL Fall Time tR tF it n o tSU:STO Stop Condition Setup Time tDH Data Out Hold Time Power-Up Timing (1)(2) c s Symbol tPUR i D tPUW d e 1.2 u n 50 1 0 100 Parameter Units 400 kHz 200 ns 1 µs µs µs µs 0.6 µs 0.6 µs 0 ns 50 30 0 s t r Max. a P 0.6 4.7 0 Min. 1.2 4 4.7 4 Max. 10 0 4.7 (1) 4.5V-5.5V 50 ns 1 0.3 300 300 µs ns 4 0.6 µs 100 100 ns Max. Units Power-Up to Read Operation 1 ms Power-Up to Write Operation 1 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Write Cycle Limits Symbol Parameter tWR Write Cycle Time Min. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Typ. Max Units 10 ms interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. 3 Doc No. 1049, Rev. D CAT24WC33/65 FUNCTIONAL DESCRIPTION transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. The CAT24WC33/65 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC33/65 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. A0, A1, A2: Device Address Inputs These pins are hardwired or left unconnected (for hardware compatibility with CAT24WC16). When hardwired, up to eight CAT24WC33/65s may be addressed on a single bus system (refer to Device Addressing ). When the pins are left unconnected, the default values are zeros. PIN DESCRIPTIONS SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. d e SDA: Serial Data/Address The bidirectional serial data/address pin is used to Figure 1. Bus Timing tF tHIGH tR tLOW it n o tSU:STA tHD:STA SDA IN tHD:DAT tAA SDA OUT c s Figure 2. Write Cycle Timing SCL i D SDA 8TH BIT BYTE n u n tLOW SCL s t r WP: Write Protect This input, when tied to GND, allows write operations to the entire memory. For CAT24WC33/65 when this pin is tied to Vcc, the bottom 1/4 array of memory (locations 000H to 7FFH for the 24WC65 and locations 000H to 3FFH for 24WC33) is write protected . When left floating, memory is unprotected. a P tSU:DAT tSU:STO tBUF tDH 5020 FHD F03 ACK tWR STOP CONDITION START CONDITION ADDRESS 5020 FHD F04 Figure 3. Start/Stop Timing SDA SCL START BIT Doc. No. 1049, Rev. D STOP BIT 4 5020 FHD F05 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC33/65 I2C BUS PROTOCOL compare to the hardwired input pins, A2, A1 and A0. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. After the Master sends a START condition and the slave address byte, the CAT24WC33/65 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24WC33/65 then performs a Read or Write operation depending on the state of the R/W bit. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition Acknowledge The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24WC33/65 monitors the SDA and SCL lines and will not respond until this condition is met. The CAT24WC33/65 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. d e STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING u n When the CAT24WC33/65 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24WC33/65 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a stop condition to return the CAT24WC33/65 to the standby power mode and place the device in a known state. The bus Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 (Fig. 5). The next three bits (A2, A1, A0) are the device address bits; up to eight 32K/64K devices may to be connected to the same bus. These bits must it n o c s a P s t r After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. Figure 4. Acknowledge Timing i D SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START 5020 FHD F06 Figure 5. Slave Address Bits 1 0 1 0 A2 A1 A0 R/W 5027 FHD F07 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc No. 1049, Rev. D CAT24WC33/65 If the Master transmits more than 32/64 bytes before sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwritten. WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address words that are to be written into the address pointers of the CAT24WC33/65. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT24WC33/65 acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. When all 32/64 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT24WC33/65 in a single write cycle. Acknowledge Polling Page Write d e The CAT24WC33/65 writes up to 32/64 bytes of data, in a single write cycle, using the Page Write operation. CAT24WC33/65, Die Revision B = 32 Byte page. CAT24WC65, Die Revision D = 64 Byte page. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 31/63 additional bytes. After each byte has been transmitted, CAT24WC33/65 will respond with an acknowledge, and internally increment the five low order address bits by one. The high order bits remain unchanged. it n o Figure 6. Byte Write Timing S T A R T c s BUS ACTIVITY: MASTER i D SDA LINE S SLAVE ADDRESS s t r Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, CAT24WC33/65 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If CAT24WC33/65 is still busy with the write operation, no ACK will be returned. If CAT24WC33/65 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. WRITE PROTECTION u n a P The Write Protection feature allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to VCC, the bottom 1/4 of the memory array (locations 000H to 7FFH for the 24WC65 and locations 000H to 3FFH for 24WC33) is protected and becomes read only. The CAT24WC33/65 will accept both slave and byte addresses, but the memory location BYTE ADDRESS A15–A8 A7–A0 S T O P DATA P X XX * A C K A C K A C K A C K 24WC33/65 F08 Figure 7. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS A15–A8 A7–A0 S DATA DATA n S T O P DATA n+31 P X XX * A C K A C K A C K * = Don't care bit for 24WC33 A C K A C K A C K A C K 24WC33/65 F09 X= Don't care bit Doc. No. 1049, Rev. D 6 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC33/65 READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After CAT24WC33/65 acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT24WC33/65 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. READ OPERATIONS The READ operation for the CAT24WC33/65 is initiated in the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. Sequential Read The CAT24WC33/65’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N=E (where E=4095 for 24WC33 and E=8191 for 24WC65), then the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT24WC33/65 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. it n o Selective/Random Read s t r The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24WC33/65 sends the initial 8bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24WC33/65 will continue to output an 8bit byte for each acknowledge sent by the Master. The operation will terminate when the Master fails to respond with an acknowledge, thus sending the STOP condition. Immediate/Current Address Read d e a P The data being transmitted from CAT24WC33/65 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24WC33/65 address bits so that the entire memory array can be read during one operation. If more than E (where E=4095 for 24WC33 and E=8191 for 24WC65) bytes are read out, the counter will ‘wrap around’ and continue to clock out data bytes. u n Selective/Random READ operations allow the Master device to select at random any memory location for a Figure 8. Immediate Address Read Timing c s i D SCL SDA BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S T O P DATA S P A C K 8 N O A C K 9 8TH BIT DATA OUT NO ACK STOP 24WC33/65 F10 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc No. 1049, Rev. D CAT24WC33/65 Figure 9. Selective Read Timing S T A R T BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS S T A R T BYTE ADDRESS A15–A8 A7–A0 S SLAVE ADDRESS S T O P DATA S XXX * A C K A C K P A C K A C K N O A C K * = Don't care for 24WC33 X= Don't care bit Figure 10. Sequential Read Timing BUS ACTIVITY: MASTER s t r 24WC33/65 F11 SLAVE ADDRESS DATA n DATA n+1 d e DATA n+2 SDA LINE A C K A C K it n o A C K u n A C K a P DATA n+x S T O P P N O A C K 5020 FHD F12 c s i D Doc. No. 1049, Rev. D 8 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC33/65 8-LEAD 300 MIL WIDE PLASTIC DIP (P, L) 0.245 (6.17) 0.295 (7.49) 0.300 (7.62) 0.325 (8.26) 0.355 (9.02) 0.400 (10.16) 0.120 (3.05) 0.150 (3.81) 0.180 (4.57) MAX 0.015 (0.38) 0.110 (2.79) 0.150 (3.81) d e 0.100 (2.54) BSC 0.045 (1.14) 0.060 (1.52) 0.014 (0.36) 0.022 (0.56) u n a P s t r 0.310 (7.87) 0.380 (9.65) Notes: 1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. it n o 8-LEAD 150 MIL WIDE SOIC (J, W) c s i D 0.1497 (3.80) 0.1574 (4.00) 0.1890 (4.80) 0.1968 (5.00) 0.2284 (5.80) 0.2440 (6.20) 0.0099 (0.25) X 45 0.0196 (0.50) 0.0075 (0.19) 0.0098 (0.25) 0.0532 (1.35) 0.0688 (1.75) 0 —8 0.050 (1.27) BSC 0.013 (0.33) 0.020 (0.51) 0.0040 (0.10) 0.0098 (0.25) 0.016 (0.40) 0.050 (1.27) Notes: 1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc No. 1049, Rev. D CAT24WC33/65 8-LEAD 210 MIL WIDE SOIC (K, X) 0.205 (5.20) 0.213 (5.40) 0.303 (7.70) 0.318 (8.10) 0.0267 (0.68) 0.0303 (0.77) 0.205 (5.15) 0.210 (5.35) a P 0.008 (0.20) 0.080 (2.03) MAX 4 REF 0.046 (1.17) 0.054 (1.37) 0.025 (0.65) d e 0.0137 (0.35) 0.0177 (0.45) u n s t r Note: 1. All linear dimensions are in inches and parenthetically in millimeters. it n o c s i D Doc. No. 1049, Rev. D 10 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC33/65 ORDERING INFORMATION Prefix Device # Suffix CAT 24WC33 Optional Company ID Product Number 24WC33: 32K 24WC65: 64K K -1.8 I Temperature Range Blank = Commercial (0˚ to 70˚C) I = Industrial (-40˚ to 85˚C) A = Automotive (-40˚ to 105˚C) * E = Extended (-40˚ to 125˚C) Package P: PDIP K: SOIC (EIAJ) J: SOIC (JEDEC) L: PDIP (Lead free, Halogen free) X: SOIC (EIAJ, Lead free, Halogen free) W: SOIC (JEDEC, Lead free, Halogen free) Tape & Reel a P Operating Voltage Blank: 2.5V - 5.5V 1.8: 1.8V - 5.5V u n d e Rev D(2) TE13 s t r Die Revision 24WC33: B, D 24WC65: B, D Notes: (1) The device used in the above example is a CAT24WC33KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, Tape & Reel) (2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWB). For additional information, please contact your Catalyst sales office. it n o c s i D © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc No. 1049, Rev. D REVISION HISTORY Date Rev. Reason 7/8/2004 B Added die revision to Ordering Information 7/30/2004 C Updated DC Operating Charactristics and notes 10/31/2005 D Update Ordering Information d e Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ u n a P s t r Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION and SPECIFICALLY DISCLAIMS ANY and ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. it n o Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. c s Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. i D Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1049 D 10/31/05