AD AD824 Single supply, rail-to-rail low power, fet-input op amp Datasheet

Single Supply, Rail-to-Rail
Low Power, FET-Input Op Amp
AD824
FEATURES
Single Supply Operation: 3 V to 30 V
Very Low Input Bias Current: 2 pA
Wide Input Voltage Range
Rail-to-Rail Output Swing
Low Supply Current: 500 A/Amp
Wide Bandwidth: 2 MHz
Slew Rate: 2 V/s
No Phase Reversal
APPLICATIONS
Photo Diode Preamplifier
Battery Powered Instrumentation
Power Supply Control and Protection
Medical Instrumentation
Remote Sensors
Low Voltage Strain Gage Amplifiers
DAC Output Amplifier
PIN CONFIGURATIONS
14-Lead Epoxy SOIC
(R Suffix)
14 OUT D
OUT A 1
13 –IN D
–IN A 2
+IN A 3
AD824
12 +IN D
+IN B 5
11 V–
TOP VIEW
(Not to Scale)
10 +IN C
–IN B 6
9 –IN C
OUT B 7
8 OUT C
V+ 4
16-Lead Epoxy SOIC
(R Suffix)
16 OUT D
OUT A 1
–IN A
2
+IN A
3
V+
4
+IN B
5
12 +IN C
–IN B
6
11 –IN C
OUT B 7
NC 8
15 –IN D
14 +IN D
AD824
13 V–
10 OUT C
9 NC
NC = NO CONNECT
The AD824 is a quad, FET input, single supply amplifier, featuring rail-to-rail outputs. The combination of FET inputs and
rail-to-rail outputs makes the AD824 useful in a wide variety of
low voltage applications where low input current is a primary
consideration.
The FET input combined with laser trimming provides an input
that has extremely low bias currents with guaranteed offsets
below 1 mV. This enables high accuracy designs even with
high source impedances. Precision is combined with low
noise, making the AD824 ideal for use in battery powered
medical equipment.
The AD824 is guaranteed to operate from a 3 V single supply
up to ± 15 V dual supplies. AD824AR-3V Parametric Performance at 3 V is fully guaranteed.
Applications for the AD824 include portable medical equipment,
photo diode preamplifiers and high impedance transducer
amplifiers.
Fabricated on ADI’s complementary bipolar process, the AD824
has a unique input stage that allows the input voltage to safely
extend beyond the negative supply and to the positive supply
without any phase inversion or latchup. The output voltage
swings to within 15 mV of the supplies. Capacitive loads to
350 pF can be handled without oscillation.
The ability of the output to swing rail-to-rail enables designers
to build multistage filters in single supply systems and maintain
high signal-to-noise ratios.
GENERAL DESCRIPTION
The AD824 is specified over the extended industrial (–40∞C to
+85∞C) temperature range and is available in narrow 14-lead
and 16-lead SOIC packages.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD824–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = 5.0 V, V
S
Parameter
Symbol
INPUT CHARACTERISTICS
Offset Voltage AD824A
VOS
CM
= 0 V, VOUT = 0.2 V, TA = 25C unless otherwise noted)
Conditions
Min
Typ
Max
Unit
0.1
1.0
1.5
12
4000
10
1013储3.3
mV
mV
pA
pA
pA
pA
V
dB
dB
dB
W储pF
TMIN to TMAX
Input Bias Current
2
300
2
300
IB
TMIN to TMAX
Input Offset Current
IOS
TMIN to TMAX
Input Voltage Range
Common-Mode Rejection Ratio
Input Impedance
Large Signal Voltage Gain
Offset Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage High
CMRR
AVO
DVOS/DT
VOH
Output Voltage Low
VOL
Short Circuit Limit
ISC
Open-Loop Impedance
ZOUT
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
PSRR
ISY
VCM = 0 V to 2 V
VCM = 0 V to 3 V
TMIN to TMAX
–0.2
66
60
60
VO = 0.2 V to 4.0 V
RL = 2 kW
RL = 10 kW
RL = 100 kW
TMIN to TMAX, RL = 100 kW
20
50
250
180
40
100
1000
400
2
V/mV
V/mV
V/mV
V/mV
mV/∞C
ISOURCE = 20 mA
TMIN to TMAX
ISOURCE = 2.5 mA
TMIN to TMAX
ISINK = 20 mA
TMIN to TMAX
ISINK = 2.5 mA
TMIN to TMAX
Sink/Source
TMIN to TMAX
f = 1 MHz, AV = 1
4.975
4.97
4.80
4.75
4.988
4.985
4.85
4.82
15
20
120
140
± 12
± 10
100
V
V
V
V
mV
mV
mV
mV
mA
mA
W
VS = 2.7 V to 12 V
TMIN to TMAX
TMIN to TMAX
70
66
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
SR
BWP
tS
GBP
fo
CS
RL = 10 kW, AV = 1
1% Distortion, VO = 4 V p-p
VOUT = 0.2 V to 4.5 V, to 0.01%
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion
en p-p
en
in
THD
3.0
80
74
25
30
150
200
80
500
600
dB
dB
mA
No Load
f = 1 kHz, RL = 2 kW
2
150
2.5
2
50
–123
V/ms
kHz
ms
MHz
Degrees
dB
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
f = 10 kHz, RL = 0, AV = +1
2
16
0.8
0.005
mV p-p
nV/÷Hz
fA/÷Hz
%
–2–
REV. C
AD824
ELECTRICAL SPECIFICATIONS (@ V = 15.0 V, V
S
Parameter
Symbol
INPUT CHARACTERISTICS
Offset Voltage AD824A
VOS
Input Bias Current
IB
Input Offset Current
IB
IOS
OUT =
0 V, TA = 25C unless otherwise noted)
Conditions
Min
TMIN to TMAX
VCM = 0 V
TMIN to TMAX
VCM = –10 V
TMIN to TMAX
Input Voltage Range
Common-Mode Rejection Ratio
Input Impedance
Large Signal Voltage Gain
Offset Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage High
CMRR
AVO
DVOS/DT
VOH
Output Voltage Low
VOL
Short Circuit Limit
Open-Loop Impedance
ISC
ZOUT
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
PSRR
ISY
Max
Unit
0.5
0.6
4
500
25
3
500
2.5
4.0
35
4000
1013储3.3
mV
mV
pA
pA
pA
pA
pA
V
dB
dB
W储pF
20
VCM = –15 V to 13 V
TMIN to TMAX
–15
70
66
Vo = –10 V to +10 V;
RL = 2 kW
RL = 10 kW
RL = 100 kW
TMIN to TMAX, RL = 100 kW
12
50
300
200
50
200
2000
1000
2
V/mV
V/mV
V/mV
V/mV
mV/∞C
ISOURCE = 20 mA
TMIN to TMAX
ISOURCE = 2.5 mA
TMIN to TMAX
ISINK = 20 mA
TMIN to TMAX
ISINK = 2.5 mA
TMIN to TMAX
Sink/Source, TMIN to TMAX
f = 1 MHz, AV = 1
14.975
14.970
14.80
14.75
14.988
14.985
14.85
14.82
–14.985
–14.98
–14.88
–14.86
± 20
100
V
V
V
V
V
V
V
V
mA
W
VS = 2.7 V to 15 V
TMIN to TMAX
VO = 0 V
TMIN to TMAX
70
68
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
SR
BWP
tS
GBP
fo
CS
RL = 10 kW, AV = 1
1% Distortion, VO = 20 V p-p
VOUT = 0 V to 10 V, to 0.01%
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion
en p-p
en
in
THD
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
f =10 kHz, VO = 3 V rms,
RL = 10 kW
REV. C
Typ
f = 1 kHz, RL =2 kW
–3–
±8
13
80
–14.975
–14.97
–14.85
–14.8
80
560
625
675
dB
dB
mA
mA
2
33
6
2
50
–123
V/ms
kHz
ms
MHz
Degrees
dB
2
16
1.1
mV p-p
nV/÷Hz
fA/÷Hz
0.005
%
AD824–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
(@ VS = 3.0 V, VCM = 0 V, VOUT = 0.2 V, TA = 25C unless otherwise noted)
Parameter
Symbol
INPUT CHARACTERISTICS
Offset Voltage AD824A -3 V
VOS
Conditions
Min
Typ
Max
Unit
0.2
1.0
1.5
12
4000
10
1013储3.3
mV
mV
pA
pA
pA
pA
V
dB
dB
W储pF
TMIN to TMAX
Input Bias Current
IB
2
250
2
250
TMIN to TMAX
Input Offset Current
IOS
TMIN to TMAX
Input Voltage Range
Common-Mode Rejection Ratio
Input Impedance
Large Signal Voltage Gain
Offset Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage High
CMRR
AVO
DVOS/DT
VOH
Output Voltage Low
VOL
Short Circuit Limit
ISC
ISC
ZOUT
Open-Loop Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
PSRR
ISY
VCM = 0 V to 1 V
TMIN to TMAX
0
58
56
VO = 0.2 V to 2.0 V
RL = 2 kW
RL = 10 kW
RL = 100 kW
TMIN to TMAX, RL = 100 kW
10
30
180
90
20
65
500
250
2
V/mV
V/mV
V/mV
V/mV
mV/∞C
ISOURCE = 20 mA
TMIN to TMAX
ISOURCE = 2.5 mA
TMIN to TMAX
ISINK = 20 mA
TMIN to TMAX
ISINK = 2.5 mA
TMIN to TMAX
Sink/Source
Sink/Source, TMIN to TMAX
f = 1 MHz, AV = 1
2.975
2.97
2.8
2.75
2.988
2.985
2.85
2.82
15
20
120
140
±8
±6
100
V
V
V
V
mV
mV
mV
mV
mA
mA
W
VS = 2.7 V to 12 V,
TMIN to TMAX
VO = 0.2 V, TMIN to TMAX
70
66
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
SR
BWP
tS
GBP
fo
CS
RL =10 kW, AV = 1
1% Distortion, VO = 2 V p-p
VOUT = 0.2 V to 2.5 V, to 0.01%
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion
en p-p
en
in
THD
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz, RL = 2 kW
f = 10 kHz, RL = 0, AV = +1
–4–
1
74
500
25
30
150
200
600
dB
dB
mA
2
300
2
2
50
–123
V/ms
kHz
ms
MHz
Degrees
dB
2
16
0.8
0.01
mV p-p
nV/÷Hz
fA/÷Hz
%
REV. C
AD824
WAFER TEST LIMITS (@ V = 5.0 V, V
S
CM
= 0 V, TA = 25C unless otherwise noted)
Parameter
Symbol
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage High
Output Voltage Low
Supply Current/Amplifier
VOS
IB
IOS
VCM
CMRR
PSRR
AVO
VOH
VOL
ISY
Conditions
Limit
Unit
VCM = 0 V to 2 V
V = + 2.7 V to +12 V
RL = 2 kW
ISOURCE = 20 mA
ISINK = 20 mA
VO = 0 V, RL = •
1.0
12
20
–0.2 to 3.0
66
70
15
4.975
25
600
mV max
pA max
pA
V min
dB min
mV/V
V/mV min
V min
mV max
mA max
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS 1
VCC
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . –VS – 0.2 V to +VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 30 V
Output Short Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range
R-14, R-16 Packages . . . . . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range
AD824A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
Junction Temperature Range
R-14, R-16 Packages . . . . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300∞C
Package Type
14-Lead SOIC (R)
16-Lead SOIC (R)
qJA2
qJC
Unit
120
92
36
27
∞C/W
∞C/W
I5
R1
Package
Description
AD824AR-14
AD824AR-14-3V
AD824AR-16
–40∞C to +85∞C 14-Pin SOIC
–40∞C to +85∞C 14-Pin SOIC
–40∞C to +85∞C 16-Pin SOIC
+IN
J1
Q6
C3
Q5
J2
R13
Q20
Q19
R7
Q7
R15
Q23
Q22
C2
–IN
C4
VOUT
Q24 Q25
Q8
C1
Q2
Q3
Q31
R12
I1
R14
I2
R17
I3
Q28
Q26
I4
VEE
Figure 1. Simplified Schematic of 1/4 AD824
Package
Option
R-14
R-14
R-16
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD824 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. C
Q29
Q21 Q27
Q4
ORDERING GUIDE
Temperature
Range
Q18
R9
NOTES
1
Absolute maximum ratings apply to packaged parts unless otherwise noted.
2
qJA is specified for the worst case conditions, i.e., qJA is specified for device in socket
for P-DIP packages; qJA is specified for device soldered in circuit board for SOIC
package.
Model
I6
R2
–5–
WARNING!
ESD SENSITIVE DEVICE
AD824 –Typical Performance Characteristics
VS = 15V
NO LOAD
80
40
45
90
20
135
180
0
100
1k
10k
100k
1M
40
45
90
20
135
180
0
10M
100
100
90
1k
10k
100k
1M
PHASE – Degrees
GAIN – dB
60
PHASE – Degrees
10M
100
90
10
10
0%
0%
50mV
1µs
50mV
TPC 1. Open-Loop Gain/Phase and Small Signal
Response, VS = ± 15 V, No Load
TPC 3. Open-Loop Gain/Phase and Small Signal
Response, VS = 5 V, No Load
VS = 15V
CL = 100pF
80
1µs
VS = 5V
CL = 220pF
60
60
GAIN – dB
40
45
90
20
135
180
0
100
1k
10k
100k
1M
PHASE – Degrees
40
45
90
20
135
180
0
PHASE – Degrees
GAIN – dB
60
GAIN – dB
VS = 5V
NO LOAD
80
–20
10M
1k
10k
100k
1M
10M
100
90
100
90
10
10
0%
0%
50mV
50mV
1µs
TPC 2. Open-Loop Gain/Phase and Small Signal
Response, VS = ± 15 V, CL = 100 pF
1µs
TPC 4. Open-Loop Gain/Phase and Small Signal
Response, VS = 5 V, CL = 220 pF
–6–
REV. C
AD824
VS = 3V
NO LOAD
60
t
45
90
20
135
180
0
9.950µs
100
90
PHASE – Degrees
GAIN – dB
40
10
0%
–20
5V
1k
10k
100k
1M
2µs
10M
t
100
90
10.810µs
100
90
10
10
0%
0%
50mV
1µs
5V
TPC 5. Open-Loop Gain/Phase and Small Signal
Response, VS = 3 V, No Load
TPC 7. Slew Rate, RL = 10k
VS = 3V
CL = 220pF
60
2µs
100
90
45
90
20
135
180
0
PHASE – Degrees
GAIN – dB
40
VOUT
10
0%
5V
100µs
TPC 8. Phase Reversal with Inputs Exceeding Supply by 1 V
–20
1k
10k
100k
1M
10M
0.8
OUTPUT TO RAIL – Volts
0.7
100
90
10
0.6
0.5
SOURCE
0.4
0.3
0.2
SINK
0%
50mV
0.1
1µs
0
1
TPC 6. Open-Loop Gain/Phase and Small Signal
Response, VS = 3 V, CL = 220 pF
REV. C
5
10
50 100
500
LOAD CURRENT – A
1m
5m
10m
TPC 9. Output Voltage to Supply Rail vs. Sink and Source
Load Currents
–7–
AD824
14
COUNT = 60
3V
VS
15V
10
60
NUMBER OF UNITS
NOISE DENSITY – nV/ Hz
12
40
20
8
6
4
2
5
10
15
FREQUENCY – kHz
20
0
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0 1.5
OFFSET VOLTAGE DRIFT
2.0
2.5
TPC 13. TC VOS Distribution, –55∞C to +125∞C, VS = 5, 0
TPC 10. Voltage Noise Density
150
0.1
VS = 5, 0
RL = 0
AV = +1
INPUT OFFSET CURRENT – pA
125
VS = +3
THD+N – %
0.010
VS = +5
0.001
VS = 15
100
75
50
25
0
0.0001
20
100
1k
FREQUENCY – Hz
10k
–25
–60
20k
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE – C
TPC 14. Input Offset Current vs. Temperature
TPC 11. Total Harmonic Distortion
280
100k
VS = 5, 0
COUNT = 860
10k
INPUT BIAS CURRENT – pA
NUMBER OF UNITS
240
200
160
1k
100
120
80
40
0
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1 0.2
OFFSET VOLTAGE – mV
0.3
0.4
0.5
10
1
20
40
60
80
100
TEMPERATURE – C
120
140
TPC 15. Input Bias Current vs. Temperature
TPC 12. Input Offset Distribution, VS = 5, 0
–8–
REV. C
AD824
1k
100
INPUT VOLTAGE NOISE – nV/÷Hz
COMMON-MODE REJECTION – dB
120
80
60
40
20
0
10
100
1k
10k
100k
FREQUENCY – Hz
1M
POWER SUPPLY REJECTION – dB
–80
–100
–120
100
1k
10k
FREQUENCY – Hz
100
1k
FREQUENCY – Hz
10k
100k
100
80
60
40
20
0
10
100k
TPC 17. THD vs. Frequency, 3 V rms
30
80
80
25
60
60
40
3, 0V
20
20
0
0
100
1k
10k
100k
FREQUENCY – Hz
1M
OUTPUT VOLTAGE – Volts
15V
PHASE MARGIN – Degrees
100
40
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
TPC 20. Power Supply Rejection vs. Frequency
100
20
15
10
5
–20
10M
0
1k
TPC 18. Open-Loop Gain and Phase vs. Frequency
REV. C
10
120
–60
–20
10
1
TPC 19. Input Voltage Noise Spectral Density vs.
Frequency
–40
THD – dB
10
1
10M
TPC 16. Common-Mode Rejection vs. Frequency
OPEN-LOOP GAIN – dB
100
3k
10k
30k
100k
INPUT FREQUENCY – Hz
300k
1M
TPC 21. Large Signal Frequency Response
–9–
AD824
–80
–90
CROSSTALK – dB
5V
–100
5µs
100
90
–110
1 TO 4
–120
1 TO 3
1 TO 2
10
0%
–130
–140
10
1k
FREQUENCY – Hz
100
10k
100k
TPC 22. Crosstalk vs. Frequency
TPC 25. Large Signal Response
2750
10k
2500
1k
SUPPLY CURRENT – µA
OUTPUT IMPEDANCE –
VS = 15V
100
10
1
2250
2000
VS = 3, 0
1750
1500
.1
1250
.01
10
1k
100
10k
100k
FREQUENCY – Hz
1M
1000
–60
10M
TPC 23. Output Impedance vs. Frequency, Gain = +1
–40
–20
0
20
40
60
80
TEMPERATURE – C
100
120
140
TPC 26. Supply Current vs. Temperature
20mV
OUTPUT SATURATION VOLTAGE – mV
1000
500ns
100
90
10
0%
VS = 15V
VS = 3, 0
100
VOL – VS
10
0
0.01
TPC 24. Small Signal Response, Unity Gain Follower,
10k储100 pF Load
VS – VOH
0.10
1.0
LOAD CURRENT – mA
10.0
TPC 27. Output Saturation Voltage
–10–
REV. C
AD824
APPLICATION NOTES
INPUT CHARACTERISTICS
In the AD824, n-channel JFETs are used to provide a low
offset, low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below –VS to 1 V less
than +VS. Driving the input voltage closer to the positive rail will
cause a loss of amplifier bandwidth.
The AD824 does not exhibit phase reversal for input voltages
up to and including +VS. Figure 2a shows the response of an
AD824 voltage follower to a 0 V to 5 V (+VS) square wave input.
The input and output are superimposed. The output tracks the
input up to +VS without phase reversal. The reduced bandwidth
above a 4 V input causes the rounding of the output wave form.
For input voltages greater than +VS, a resistor in series with
the AD824’s noninverting input will prevent phase reversal at
the expense of greater input voltage noise. This is illustrated in
Figure 2b.
1V
2µs
100
90
0%
(a)
1V
The AD824’s unique bipolar rail-to-rail output stage swings
within 15 mV of the positive and negative supply voltages. The
AD824’s approximate output saturation resistance is 100 W for
both sourcing and sinking. This can be used to estimate output
saturation voltage when driving heavier current loads. For
instance, the saturation voltage will be 0.5 V from either supply
with a 5 mA current load.
Direct capacitive loads will interact with the amplifier’s effective
output impedance to form an additional pole in the amplifier’s
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. TPC 4 and 6 show the AD824’s
pulse response as a unity gain follower driving 220 pF. Configurations with less loop gain, and as a result less loop bandwidth,
will be much less sensitive to capacitance load effects. Noise
gain is the inverse of the feedback attenuation factor provided
by the feedback network in use.
10µs
1V
100
90
10
GND
OUTPUT CHARACTERISTICS
If the AD824’s output is overdriven so as to saturate either of
the output devices, the amplifier will recover within 2 ms of its
input returning to the amplifier’s linear operating region.
1V
+VS
Input voltages less than –VS are a completely different story.
The amplifier can safely withstand input voltages 20 V below
the minus supply voltage as long as the total voltage from the
positive supply to the input terminal is less than 36 V. In addition,
the input stage typically maintains picoamp level input currents
across that input voltage range.
For load resistances over 20 kW, the AD824’s input error
voltage is virtually unchanged until the output voltage is driven
to 180 mV of either supply.
10
GND
A current-limiting resistor should be used in series with the
input of the AD824 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV or if an
input voltage will be applied to the AD824 when ± VS = 0. The
amplifier will be damaged if left in that condition for more than
10 seconds. A 1 kW resistor allows the amplifier to withstand up
to 10 V of continuous overvoltage and increases the input voltage noise by a negligible amount.
0%
1V
(b)
Figure 3 shows a method for extending capacitance load drive
capability for a unity gain follower. With these component values, the circuit will drive 5,000 pF with a 10% overshoot.
+5V
RP
VIN
VOUT
+VS
0.01F
8
VIN
Figure 2. (a) Response with RP = 0; VIN from 0 to +VS
(b) VIN = 0 to + VS + 200 m V
VOUT = 0 to + VS
RP = 49.9 kW
Since the input stage uses n-channel JFETs, input current
during normal operation is positive; the current flows out from
the input terminals. If the input voltage is driven more positive
than +VS – 0.4 V, the input current will reverse direction as
internal device junctions become forward biased. This is
illustrated in TPC 8.
REV. C
100
1/4
AD824
VOUT
0.01F
4
CL
–VS
20pF
20k
Figure 3. Extending Unity Gain Follower Capacitive Load
Capability Beyond 350 pF
–11–
AD824
APPLICATIONS
Single Supply Voltage-to-Frequency Converter
Table I. AD824 In Amp Performance
The circuit shown in Figure 4 uses the AD824 to drive a low
power timer, which produces a stable pulse of width t1. The
positive going output pulse is integrated by R1-C1 and used as
one input to the AD824, which is connected as a differential
integrator. The other input (nonloading) is the unknown voltage,
VIN. The AD824 output drives the timer trigger input, closing
the overall feedback loop.
10V
C5
0.1F
U4
REF02
2
6
VREF = 5V
5
3
RSCALE**
10k
4
CMOS
74HCO4
U3B
4
3
U1
C1
499k, 1%
0V TO 2.5V
FULL SCALE
C2
0.01F, 2%
VS = 5 V
CMRR
Common-Mode
Voltage Range
3 dB BW, G = 10
G = 100
tSETTLING
2 V Step (VS = 0 V, 3 V)
5 V (VS = ± 5 V)
Noise @ f = 1 kHz, G = 10
G = 100
74 dB
80 dB
–0.2 V to +2 V –5.2 V to +4 V
180 kHz
180 kHz
18 kHz
18 kHz
2 ms
5 ms
270 nV/÷Hz
2.2 mV/÷Hz
270 nV/÷Hz
2.2 mV/÷Hz
OUT2
U3A
2
1
5µs
100
90
OUT1
U2
CMOS 555
R3*
116k
1/4
R1
VS = 3 V, 0 V
C3
0.1F
0.01F, 2%
R2
499k, 1%
Parameters
4
R
6 THR
8
V+
OUT 3
2 TR
AD824
10
CV 5
7 DIS
C6
390pF
5%
(NPO)
0%
1V
GND
1
C4
0.1F
Figure 5a. Pulse Response of In Amp to a 500 mV p-p
Input Signal; VS = 5 V, 0 V; Gain = 10
NOTES
fOUT = V IN/(VREF t1), t1 = 1.1 R3 C6
= 25kHz fS AS SHOWN.
* = 1% METAL FILM, <50ppm/C TC
VREF
** = 10%, 20T FILM, <100ppm/C TC
R1
R2
R3
R4
R5
R6
90k
9k
1k
1k
9k
90k
OHMTEK
PART # 1043
t1 = 33s FOR fOUT = 20kHz @ V IN = 2.0V
G = 10
Figure 4. Single Supply Voltage-to-Frequency Converter
Typical AD824 bias currents of 2 pA allow megaohm-range
source impedances with negligible dc errors. Linearity errors on
the order of 0.01% full scale can be achieved with this circuit.
This performance is obtained with a 5 V single supply, which
delivers less than 3 mA to the entire circuit.
G = 100
G = 100
G = 10
+VS
0.1F
2
6
1/4
VIN1
RP
1k
Single Supply Programmable Gain Instrumentation Amplifier
VIN2
The AD824 can be configured as a single supply instrumentation amplifier that is able to operate from single supplies down
to 5 V or dual supplies up to ± 15 V. AD824 FET inputs’ 2 pA
bias currents minimize offset errors caused by high unbalanced
source impedances.
3
1/4
1
AD824
5
AD824
11
7
VOUT
RP
1k
(G = 10) V OUT = (VIN1 – V IN2) (1+
R6
R4 + R5
(G = 100) V OUT = (VIN1 – V IN2) (1+
) + V REF
R5 + R6
R4
) + V REF
FOR R1 = R6, R2 = R5 AND R3 = R4
An array of precision thin-film resistors sets the in amp gain to
be either 10 or 100. These resistors are laser-trimmed to ratio
match to 0.01% and have a maximum differential TC of 5 ppm/∞C.
Figure 5b. A Single Supply Programmable
Instrumentation Amplifier
–12–
REV. C
AD824
3 Volt, Single Supply Stereo Headphone Driver
The AD824 exhibits good current drive and THD+N performance, even at 3 V single supplies. At 1 kHz, total harmonic
distortion plus noise (THD+N) equals –62 dB (0.079%) for a
300 mV p-p output signal. This is comparable to other single
supply op amps that consume more power and cannot run on 3 V
power supplies.
In Figure 6, each channel’s input signal is coupled via a 1 mF
Mylar capacitor. Resistor dividers set the dc voltage at the
noninverting inputs so that the output voltage is midway between
the power supplies (1.5 V). The gain is 1.5. Each half of the
AD824 can then be used to drive a headphone channel. A 5 Hz
high-pass filter is realized by the 500 mF capacitors and the
headphones, which can be modeled as 32 ohm load resistors to
ground. This ensures that all signals in the audio frequency
range (20 Hz–20 kHz) are delivered to the headphones.
3V
0.1F
0.1F
95.3k
1F
CHANNEL 1
1/4
MYLAR
AD824
AD824
47.5k
95.3k
500F
L
4.99k
10k
HEADPHONES
32 IMPEDANCE
10k
of 4.5 V can be used to drive an A/D converter front end. The
other half of the AD824 is configured as a unity-gain inverter
and generates the other bridge input of –4.5 V. Resistors R1 and
R2 provide a constant current for bridge excitation. The AD620
low power instrumentation amplifier is used to condition the
differential output voltage of the bridge. The gain of the AD620
is programmed using an external resistor RG and determined by:
G=
A 3.3 V/5 V Precision Sample-and-Hold Amplifier
In battery-powered applications, low supply voltage operational
amplifiers are required for low power consumption. Also, low
supply voltage applications limit the signal range in precision
analog circuitry. Circuits like the sample-and-hold circuit shown
in Figure 8, illustrate techniques for designing precision analog
circuitry in low supply voltage applications. To maintain high
signal-to-noise ratios (SNRs) in a low supply voltage application
requires the use of rail-to-rail, input/output operational amplifiers. This design highlights the ability of the AD824 to operate
rail-to-rail from a single 3 V/5 V supply, with the advantages of
high input impedance. The AD824, a quad JFET-input op amp,
is well suited to S/H circuits due to its low input bias currents
(3 pA, typical) and high input impedances (3 ¥ 1013 W, typical).
The AD824 also exhibits very low supply currents so the total
supply current in this circuit is less than 2.5 mA.
3.3/5V
3.3/5V
R
R1
50k
4.99k
1/4
47.5k
1F
AD824
AD824
CHANNEL 2
49.4 kW
+1
RG
R2
50k
500F
MYLAR
AD824A
3
0.1F
4
1
A1
2 A1
FALSE GROUND (FG)
11
R4
2k
3.3/5V
13
Figure 6. 3 Volt Single Supply Stereo Headphone Driver
Low Dropout Bipolar Bridge Driver
R5
2k
The AD824 can be used for driving a 350 ohm Wheatstone
bridge. Figure 7 shows one half of the AD824 being used to
buffer the AD589—a 1.235 V low power reference. The output
+VS
6
1
350
350
3
1/4
1/4
12
SAMPLE/
HOLD
5
VREF
–4.5V
+VS
0.1F
+5V
1F
GND
–VS
0.1F
–VS
A4
A4
14
4
5
8
AD824C
+
V
– OUT
C
500pF
FG
Figure 8. 3.3 V/5.5 V Precision Sample and Hold
4
–VS
R2
20
13
FG
A3
6
AD824
AD620
RG
6
8
7
1%
AD824
AD824
7
AD824D
2
1F
–5V
In many single supply applications, the use of a false ground
generator is required. In this circuit, R1 and R2 divide the
supply voltage symmetrically, creating the false ground voltage
at one-half the supply. Amplifier A1 then buffers this voltage
creating a low impedance output drive. The S/H circuit is configured in an inverting topology centered around this false
ground level.
Figure 7. Low Dropout Bipolar Bridge Driver
REV. C
3
10
+VS
10k
1%
2
TO A/D CONVERTER
REFERENCE INPUT
26.4k, 1%
350
CH
500pF
FG
7
9
1/4
1/4
AD824
AD824
350
10k
A2
A2
ADG513
9
R1
20
+1.235V
1%
10
\
49.9k
10k
14
16
11
AD824B
5
AD589
15
–13–
AD824
A design consideration in sample-and-hold circuits is voltage
droop at the output caused by op amp bias and switch leakage
currents. By choosing a JFET op amp and a low leakage CMOS
switch, this design minimizes droop rate error to better than
0.1 mV/ms in this circuit. Higher values of CH will yield a lower
droop rate. For best performance, CH and C2 should be polystyrene, polypropylene or Teflon capacitors. These types of
capacitors exhibit low leakage and low dielectric absorption. Additionally, 1% metal film resistors were used throughout the design.
In the sample mode, SW1 and SW4 are closed, and the output
is VOUT = –VIN. The purpose of SW4, which operates in parallel
with SW1, is to reduce the pedestal, or hold step, error by
injecting the same amount of charge into the noninverting input
of A3 that SW1 injects into the inverting input of A3. This
creates a common-mode voltage across the inputs of A3 and is
then rejected by the CMR of A3; otherwise, the charge injection
from SW1 would create a differential voltage step error that
would appear at VOUT. The pedestal error for this circuit is
less than 2 mV over the entire 0 V to 3.3 V/5 V signal range.
Another method of reducing pedestal error is to reduce the pulse
amplitude applied to the control pins. In order to control the
ADG513, only 2.4 V are required for the “ON” state and
0.8 V for the “OFF” state. If possible, use an input control
signal whose amplitude ranges from 0.8 V to 2.4 V instead of a
full range 0 V to 3.3 V/5 V for minimum pedestal error.
Other circuit features include an acquisition time of less than
3 ms to 1%; reducing CH and C2 will speed up the acquisition
time further, but an increased pedestal error will result. Settling
time is less than 300 ns to 1%, and the sample-mode signal BW
is 80 kHz.
The ADG513 was chosen for its ability to work with 3 V/5 V
supplies and for having normallyopen and normallyclosed precision CMOS switches on a dielectrically isolated process. SW2 is
not required in this circuit; however, it was used in parallel with
SW3 to provide a lower RON analog switch.
–14–
REV. C
AD824
* AD824 SPICE Macro-model
9/94, Rev. A *
ARG/ADI
*
* Copyright 1994 by Analog Devices, Inc.
*
* Refer to “README.DOC” file for License Statement.
Use of this model indicates your acceptance with
the terms and provisions in the License Statement. *
* Node assignments
*
noninverting input
*
| inverting input
*
| | positive supply
*
| | | negative supply
*
| | | | output
*
| | | | |
.SUBCKT AD824
1 2 99 50 25
*
* INPUT STAGE & POLE AT 3.1 MHz
*
R3 5
99
1.193E3
R4 6
99
1.193E3
CIN 1
2
4E-12
C2 5
6
19.229E-12
I1 4 50
108E-6
IOS 1
2
1E-12
EOS 7
1
POLY(1) (12,98) 100E-6 1
J1 4 2
5
JX
J2 4 7
6
JX
*
* GAIN STAGE & DOMINANT POLE
*
EREF
98
0 (30,0) 1
R5 9
98
2.205E6
C3 9
25
54E-12
G1 98
9
(6,5) 0.838E-3
V1 8
98
-1
V2 98
10
-1
D1 9
10
DX
D2 8
9
DX
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHz *
R21 11
12
1E6
R22 12
98
100
C14 11
12
159E-12
E13 11
98
POLY(2) (2,98) (1,98) 0 0.5 0.5
*
* POLE AT 10 MHz
*
R23 18
98
1E6
C15 18
98
15.9E-15
REV. C
G15 98
18
(9,98) 1E-6
*
* OUTPUT STAGE
*
ES 26
98
(18,98) 1
RS 26
22
500
IB1 98
21
2.404E-3
IB2 23
98
2.404E-3
D10 21
98
DY
D11 98
23
DY
C16 20
25
2E-12
C17 24
25
2E-12
DQ1 97
20
DQ
Q2 20
21
22 NPN
Q3 24
23
22 PNP
DQ2 24
51
DQ
Q5 25
20
97 PNP 20
Q6 25
24
51 NPN 20
VP 96
97
0
VN 51
52
0
EP 96
0
(99,0) 1
EN 52
0
(50,0) 1
R25 30
99
5E6
R26 30
50
5E6
FSY1
99
0 VP 1
FSY2
0
50VN 1
DC1 25
99
DX
DC2 50
25
DX
*
* MODELS USED
*
.MODEL JX NJF(BETA=3.2526E-3 VTO=-2.000 IS=2E-12) .MODEL
NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3
+ RE=4 RC=550 IS=1E-16)
.MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 + RE=4
RC=750 IS=1E-16)
.MODEL DX D(IS=1E-15)
.MODEL DY D()
.MODEL DQ D(IS=1E-16)
.ENDS AD824
–15–
AD824
14-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-14)
16-Lead Standard Small Outline Package [SOIC]
Wide Body
(R-16)
Dimensions shown in millimeters and (inches)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
4.00 (0.1575)
3.80 (0.1496)
10.50 (0.4134)
10.10 (0.3976)
14
8
1
7
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
C00875–0–2/03(C)
OUTLINE DIMENSIONS
1.27 (0.0500)
BSC
0.51 (0.0201)
0.33 (0.0130)
6.20 (0.2441)
5.80 (0.2283)
7.60 (0.2992)
7.40 (0.2913)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
9
16
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.40 (0.0157)
0.19 (0.0075)
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COMPLIANT TO JEDEC STANDARDS MS-012AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
8
1
0.50 (0.0197)
ⴛ 45ⴗ
0.25 (0.0098)
0.51 (0.0201)
0.33 (0.0130)
0.75 (0.0295)
ⴛ 45ⴗ
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
0.32 (0.0126)
0.23 (0.0091)
8ⴗ
0ⴗ
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location
Page
2/03–Data Sheet changed from REV. B to REV. C.
Deleted N Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to Figure 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Edits to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Edits to ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
–16–
REV. C
PRINTED IN U.S.A.
1/02–Data Sheet changed from REV. A to REV. B.