CY7C1347G 4-Mbit (128 K × 36) Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description ■ Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD) ■ 2.5- / 3.3-V I/O power supply (VDDQ) ■ Fast clock to output times: 2.6 ns (for 250 MHz device) ■ User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self timed writes ■ Asynchronous output enable ■ Offered in Pb-free 100-pin TQFP, Pb-free and non Pb-free 119-ball BGA package, and 165-ball FBGA package ■ “ZZ” sleep mode option and stop clock option ■ Available in Industrial and commercial temperature ranges The CY7C1347G[1] is a 3.3 V, 128 K × 36 synchronous pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G I/O pins can operate at either the 2.5 V or the 3.3 V level. The I/O pins are 3.3 V tolerant when VDDQ = 2.5 V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 2.6 ns (250 MHz device). CY7C1347G supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the address strobe from processor (ADSP) or the address strobe from controller (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the four Byte Write Select (BW[A:D]) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous chip Selects (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tristate control. To provide proper data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state. Selection Guide Description 250 MHz 200 MHz 166 MHz 133 MHz Unit Maximum access time 2.6 2.8 3.5 4.0 ns Maximum operating current 325 265 240 225 mA Maximum CMOS standby current 40 40 40 40 mA Note 1. For best practice recommendations, refer to the Cypress application note, SRAM System Guidelines – AN1064. Cypress Semiconductor Corporation Document #: 38-05516 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 29, 2011 [+] Feedback CY7C1347G Logic Block Diagram A0, A1, A ADDRESS REGISTER 2 A [1:0] MODE ADV CLK Q1 BURST COUNTER CLR AND LOGIC ADSC Q0 ADSP BW D DQ D ,DQP D BYTE WRITE REGISTER DQ D ,DQPD BYTE WRITE DRIVER BW C DQ C ,DQP C BYTE WRITE REGISTER DQ C ,DQP C BYTE WRITE DRIVER DQ B ,DQP B BYTE WRITE REGISTER DQ B ,DQP B BYTE WRITE DRIVER BW B BW A BWE ZZ ENABLE REGISTER SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQP A DQP B DQP C DQP D DQ A ,DQP A BYTE WRITE DRIVER DQ A ,DQP A BYTE WRITE REGISTER GW CE 1 CE 2 CE 3 OE MEMORY ARRAY PIPELINED ENABLE INPUT REGISTERS SLEEP CONTROL Document #: 38-05516 Rev. *I Page 2 of 24 [+] Feedback CY7C1347G Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 6 Functional Overview ........................................................ 7 Single Read Accesses ................................................ 7 Single Write Accesses Initiated by ADSP ................... 7 Single Write Accesses Initiated by ADSC ................... 7 Burst Sequences ......................................................... 8 Sleep Mode ................................................................. 8 Interleaved Burst Sequence ............................................ 8 Linear Burst Sequence .................................................... 8 ZZ Mode Electrical Characteristics ................................. 8 Truth Table ........................................................................ 8 Partial Truth Table for Read/Write ................................ 10 Maximum Ratings ........................................................... 11 Operating Range ............................................................. 11 Document #: 38-05516 Rev. *I Neutron Soft Error Immunity ......................................... 11 Electrical Characteristics ............................................... 11 Capacitance .................................................................... 13 Thermal Resistance ........................................................ 13 Switching Characteristics .............................................. 14 Switching Waveforms .................................................... 15 Ordering Information ...................................................... 19 Ordering Code Definitions ......................................... 19 Package Diagrams .......................................................... 20 Acronyms ........................................................................ 22 Document History Page ................................................. 23 Sales, Solutions, and Legal Information ...................... 24 Worldwide Sales and Design Support ....................... 24 Products .................................................................... 24 PSoC Solutions ......................................................... 24 Page 3 of 24 [+] Feedback CY7C1347G Pin Configurations BYTE C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1347G 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA BYTE B BYTE A MODE A A A A A1 A0 NC/72M NC/36M VSS VDD NC/18M NC/9M A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 BYTE D DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A Figure 1. 100-pin TQFP Pinout Document #: 38-05516 Rev. *I Page 4 of 24 [+] Feedback CY7C1347G Pin Configurations (continued) Figure 2. 119-ball BGA Pinout 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B C NC/288 M NC/144 M CE2 A A A ADSC VDD A A CE3 A NC/576 M NC/1G D DQC DQPC VSS NC VSS DQPB DQB E F DQC VDDQ DQC DQC VSS VSS CE1 DQB DQB DQB VDDQ G H J DQC DQC VDDQ DQC DQC VDD BWC VSS NC OE ADV GW VDD VSS VSS BWB VSS NC DQB DQB VDD DQB DQB VDDQ K DQD DQD VSS CLK VSS DQA DQA L DQD DQD BWD NC BWA DQA DQA M N VDDQ DQD DQD DQD VSS VSS BWE A1 VSS VSS DQA DQA VDDQ DQA P DQD DQPD VSS A0 VSS DQPA DQA R T NC NC A NC/72M MODE A VDD A NC A A NC/36M NC ZZ U VDDQ NC NC NC NC NC VDDQ Figure 3. 165-ball FBGA Pinout 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/288 M A CE1 BWC BWB CE3 BWE ADSC ADV A NC NC/144 M A CE2 BWD BWA CLK GW OE ADSP A NC/576 M DQPC DQC NC DQC VDDQ VDDQ VSS VDD VSS VSS VSS VSS VSS VSS VDD VDDQ NC/1G DQB DQPB DQB R VSS VDDQ DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC NC DQD DQC VSS DQD VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS NC/18M VSS VSS VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC NC/72 M A A NC A1 NC A A A NC/9 M MODE NC/36 M A A NC A0 NC A A A A Document #: 38-05516 Rev. *I Page 5 of 24 [+] Feedback CY7C1347G Pin Definitions Name I/O Description A0,A1,A InputSynchronous Address Inputs Used to Select One of the 128 K Address Locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feeds the 2-bit counter. BWA, BWB, BWC, BWD InputSynchronous Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW InputSynchronous Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). BWE InputSynchronous Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputSynchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputSynchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. CE3 InputSynchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. OE InputAsynchronous Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputSynchronous Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically increments the address in a burst cycle. ADSP InputSynchronous Address Strobe from Processor, Sampled on the Rising Edge of CLK. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputSynchronous Address Strobe from Controller, Sampled on the Rising Edge of CLK. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ InputAsynchronous ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull-down. DQA, DQB, DQC, DQD, DQPA, DQPB, DQPC, DQPD I/OSynchronous Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs are placed in a tristate condition. VDD Power Supply Power Supply Inputs to the Core of the Device. VSS Ground VDDQ VSSQ MODE Ground for the Core of the Device. I/O Power Supply Power Supply for the I/O circuitry. I/O Ground InputStatic Document #: 38-05516 Rev. *I Ground for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull-up. Page 6 of 24 [+] Feedback CY7C1347G Pin Definitions (continued) Name NC, NC/9M, NC/18M, NC/36M, NC/72M, NC/144M, NC/288M, NC/576M, NC/1G I/O Description – No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M, NC/288M, NC/576M, and NC/1G are address expansion pins that are not internally connected to the die. Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250 MHz device). The CY7C1347G supports secondary cache in systems using either a linear or interleaved burst sequence. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Address Strobe from Processor (ADSP) or the Address Strobe from Controller (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tristate control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A[16:0]) is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the Output Register and onto the data bus within 2.6 ns (250 MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tristated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. After the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output tristates immediately. Document #: 38-05516 Rev. *I Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A[16:0] is loaded into the Address Register and the address advancement logic while being delivered to the RAM core. The write signals (GW, BWE, and BW[A:D]) and ADV inputs are ignored during this first cycle. ADSP-triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs and DQPs inputs is written into the corresponding address location in the RAM core. If GW is HIGH, then the write operation is controlled by BWE and BW[A:D] signals. The CY7C1347G provides byte write capability that is described in Partial Truth Table for Read/Write on page 10. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW[A:D]) input selectively writes to only the desired bytes. Bytes not selected during a byte write operation remain unaltered. A synchronous self timed write mechanism is provided to simplify the write operations. Because the CY7C1347G is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs and DQPs inputs. Doing so tristates the output drivers. As a safety precaution, DQs and DQPs are automatically tristated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BW[A:D]) are asserted active to conduct a write to the desired byte(s). ADSC-triggered write accesses require a single clock cycle to complete. The address presented to A[16:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQs and DQPs is written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation remain unaltered. A synchronous self timed write mechanism has been provided to simplify the write operations. Because the CY7C1347G is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs and DQPs inputs. Doing so tristates the output Page 7 of 24 [+] Feedback CY7C1347G drivers. As a safety precaution, DQs and DQPs are automatically tristated whenever a write cycle is detected, regardless of the state of OE. Interleaved Burst Sequence First Address Burst Sequences The CY7C1347G provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user-selectable through the MODE input. Asserting ADV LOW at clock rise automatically increments the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Third Address Fourth Address A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Sequence First Address Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Second Address Second Address Third Address Fourth Address A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Snooze mode standby current ZZ > VDD 0.2 V – 40 mA tZZS Device operation to ZZ ZZ > VDD 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC – ns tZZI ZZ Active to snooze current This parameter is sampled – 2tCYC ns tRZZI ZZ Inactive to exit snooze current This parameter is sampled 0 – ns Truth Table The truth table for part number CY7C1347G follow. [2, 3, 4, 5, 6] Add. Used CE1 CE2 CE3 ZZ Deselect cycle, power-down None H X X L X L X X X L-H Tristate Deselect cycle, power-down None L L X L L X X X X L-H Tristate Deselect cycle, power-down None L X H L L X X X X L-H Tristate Deselect cycle, power-down None L L X L H L X X X L-H Tristate Deselect cycle, power-down None L X H L H L X X X L-H Tristate Next Cycle ADSP ADSC ADV WRITE OE CLK DQ Notes 2. X = “Do not Care.” H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA, BWB, BWC, BWD), BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow the outputs to tristate. OE is a do not care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05516 Rev. *I Page 8 of 24 [+] Feedback CY7C1347G Truth Table (continued) The truth table for part number CY7C1347G follow. [2, 3, 4, 5, 6] Next Cycle Snooze mode, power-down Add. Used CE1 CE2 CE3 ZZ None X X X H ADSP ADSC ADV WRITE X X X X OE CLK X X DQ Tristate Read Cycle, Begin Burst External L H L L L X X X L L-H Q Read Cycle, Begin Burst External L H L L L X X X H L-H Tristate Write Cycle, Begin Burst External L H L L H L X L X L-H D Read Cycle, Begin Burst External L H L L H L X H L L-H Q Read Cycle, Begin Burst External L H L L H L X H H L-H Tristate Read Cycle, Continue Burst Next X X X L H H L H H L-H Tristate Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H Tristate Write cycle, continue burst Next X X X L H H L L X L-H D Write cycle, continue burst Next H X X L X H L L X L-H D Read cycle, suspend burst Current X X X L H H H H L L-H Q Read cycle, suspend burst Current X X X L H H H H H L-H Tristate Read cycle, suspend burst Current H X X L X H H H L L-H Q Read cycle, suspend burst Current H X X L X H H H H L-H Tristate Write cycle, suspend burst Current X X X L H H H L X L-H D Write cycle, suspend burst Current H X X L X H H L X L-H D Document #: 38-05516 Rev. *I Page 9 of 24 [+] Feedback CY7C1347G Partial Truth Table for Read/Write The partial truth table for read/write for part number CY7C1347G follow. [7, 8] Function GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write byte A – DQA H L H H H L Write byte B – DQB H L H H L H Write bytes B, A H L H H L L Write byte C – DQC H L H L H H Write bytes C, A H L H L H L Write bytes C, B H L H L L H Write bytes C, B, A H L H L L L Write byte D – DQD H L L H H H Write bytes D, A H L L H H L Write bytes D, B H L L H L H Write bytes D, B, A H L L H L L Write bytes D, C H L L L H H Write bytes D, C, A H L L L H L Write bytes D, C, B H L L L L H Write all bytes H L L L L L Write all bytes L X X X X X Notes 7. X = “Do not Care.” H = Logic HIGH, L = Logic LOW. 8. This table is only a partial listing of the byte write combinations. Any combination of BWx is valid. Appropriate write is based on which byte write is active. Document #: 38-05516 Rev. *I Page 10 of 24 [+] Feedback CY7C1347G Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Neutron Soft Error Immunity Test Conditions Typ Max* Unit Logical single-bit upsets 25 °C 361 394 FIT/ Mb LMBU Logical multi-bit upsets 25 °C 0 0.01 FIT/ Mb SEL Single event latch-up 85 °C 0 0.1 FIT/ Dev Storage temperature 65 C to +150 C Parameter Description Ambient temperature with power applied55 C to +125 C LSBU Supply voltage on VDD relative to GND 0.5 V to +4.6 V Supply voltage on VDDQ relative to GND0.5 V to +VDD DC voltage applied to outputs in high Z State 0.5 V to VDD + 0.5 V DC input voltage 0.5 V to VDD + 0.5 V Current into outputs (LOW) ......................................... 20 mA Static discharge voltage.......................................... > 2001 V (MIL-STD-883, Method 3015) * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note, Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates – AN54908. Latch-up Current.................................................... > 200 mA Operating Range Ambient Temperature Range Commercial 0 °C to +70 °C Industrial –40 °C to +85 °C VDD VDDQ 3.3 V5% / 2.5 V + 10% 5% to VDD Electrical Characteristics Over the Operating Range[9, 10] Parameter Description Test Conditions Min Max Unit VDD Power supply voltage 3.135 3.6 V VDDQ I/O supply voltage 2.375 VDD V VOH Output HIGH voltage For 3.3 V I/O, IOH = –4.0 mA 2.4 – V For 2.5 V I/O, IOH = –1.0 mA 2.0 – V For 3.3 V I/O, IOL = 8.0 mA – 0.4 V For 2.5 V I/O, IOL = 1.0 mA – 0.4 V VOL VIH VIL IX Output LOW voltage Input HIGH voltage[9] Input LOW voltage [9] Input leakage current except ZZ and MODE Input current of MODE Input current of ZZ IOZ Output leakage current For 3.3 V I/O 2.0 VDD + 0.3 V V For 2.5 V I/O 1.7 VDD + 0.3 V V For 3.3 V I/O –0.3 0.8 V For 2.5 V I/O –0.3 0.7 V GND < VI < VDDQ 5 5 A Input = VSS 30 – A Input = VDD – 5 A Input = VSS 5 – A Input = VDD – 30 A GND VI VDDQ, output disabled 5 5 A Notes 9. Overshoot: VIH(AC) < VDD +1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2). 10. tpower-up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05516 Rev. *I Page 11 of 24 [+] Feedback CY7C1347G Electrical Characteristics (continued) Over the Operating Range[9, 10] Parameter IDD ISB1 Description VDD operating supply current Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Min Max Unit 4 ns cycle, 250 MHz – 325 mA 5 ns cycle, 200 MHz – 265 mA 6 ns cycle, 166 MHz – 240 mA 7.5 ns cycle, 133 MHz – 225 mA 4 ns cycle, 250 MHz – 120 mA 5 ns cycle, 200 MHz – 110 mA 6 ns cycle, 166 MHz – 100 mA Automatic CE power-down current—TTL inputs Max. VDD, device deselected, VIN > VIH or VIN < VIL f = fMAX = 1/tCYC – 90 mA ISB2 Automatic CE power-down current—CMOS inputs All speeds Max. VDD, device deselected, VIN < 0.3 V or VIN > VDDQ – 0.3 V, f=0 – 40 mA ISB3 Automatic CE power-down current—CMOS inputs Max. VDD, device deselected, or 4 ns cycle, 250 MHz VIN < 0.3 V or VIN > VDDQ – 0.3 V 5 ns cycle, 200 MHz f = fMAX = 1/tCYC 6 ns cycle, 166 MHz – 105 mA – 95 mA – 85 mA – 75 mA – 45 mA 7.5 ns cycle, 133 MHz 7.5 ns cycle, 133 MHz ISB4 Automatic CE power-down current—TTL inputs Document #: 38-05516 Rev. *I Max. VDD, device deselected, VIN VIH or VIN VIL, f = 0 Page 12 of 24 [+] Feedback CY7C1347G Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description 100-pin TQFP 119-ball BGA 165-ball FBGA Unit Max Max Max Test Conditions CIN Input capacitance CCLK Clock input capacitance CIO I/O capacitance TA = 25 C, f = 1 MHz, VDD = 3.3 V. VDDQ = 3.3 V 5 5 5 pF 5 5 5 pF 5 7 7 pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description 100-pin TQFP 119-ball BGA 165-ball FBGA Unit Package Package Package Test Conditions JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 30.32 34.1 20.3 C/W 6.85 14.0 4.6 C/W Figure 4. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317 3.3 V OUTPUT OUTPUT RL = 50 Z0 = 50 All input pulses VDDQ GND 5 pF R = 351 10% 90% 10% 90% 1 ns 1 ns VT = 1.5 V Including JIG and scope (a) (c) (b) 2.5 V I/O Test Load R = 1667 2.5 V OUTPUT OUTPUT RL = 50 Z0 = 50 VT = 1.25 V (a) Document #: 38-05516 Rev. *I All input pulses VDDQ GND 5 pF Including JIG and scope R = 1538 (b) 10% 90% 10% 90% 1 ns 1 ns (c) Page 13 of 24 [+] Feedback CY7C1347G Switching Characteristics Over the Operating Range[11, 12] Parameter tPOWER Description VDD(Typical) to the first Access[13] –250 –200 –166 –133 Unit Min Max Min Max Min Max Min Max 1 – 1 – 1 – 1 – ms 4.0 – 5.0 – 6.0 – 7.5 – ns Clock tCYC Clock cycle time tCH Clock HIGH 1.7 – 2.0 – 2.5 – 3.0 – ns tCL Clock LOW 1.7 – 2.0 – 2.5 – 3.0 – ns Output Times tCO Data output valid after CLK rise – 2.6 – 2.8 – 3.5 – 4.0 ns tDOH Data output hold after CLK rise 1.0 – 1.0 – 1.5 – 1.5 – ns 0 – 0 – 0 – 0 – ns tCLZ Clock to low tCHZ Clock to high Z[14, 15, 16] – 2.6 – 2.8 – 3.5 – 4.0 ns tOEV OE LOW to output valid – 2.6 – 2.8 – 3.5 – 4.5 ns tOELZ OE LOW to output low Z[14, 15, 16] 0 – 0 – 0 – 0 – ns tOEHZ OE HIGH to output high Z[14, 15, 16] – 2.6 – 2.8 – 3.5 – 4.0 ns Z[14, 15, 16] Setup Times tAS Address setup before CLK rise 1.2 – 1.2 – 1.5 – 1.5 – ns tADS ADSC, ADSP setup before CLK rise 1.2 – 1.2 – 1.5 – 1.5 – ns tADVS ADV setup before CLK rise 1.2 – 1.2 – 1.5 – 1.5 – ns tWES GW, BWE, BWX setup before CLK rise 1.2 – 1.2 – 1.5 – 1.5 – ns tDS Data input setup before CLK rise 1.2 – 1.2 – 1.5 – 1.5 – ns tCES Chip enable setup before CLK rise 1.2 – 1.2 – 1.5 – 1.5 – ns Hold Times tAH Address hold after CLK rise 0.3 – 0.5 – 0.5 – 0.5 – ns tADH ADSP, ADSC hold after CLK rise 0.3 – 0.5 – 0.5 – 0.5 – ns tADVH ADV hold after CLK Rise 0.3 – 0.5 – 0.5 – 0.5 – ns tWEH GW, BWE, BWX hold after CLK rise 0.3 – 0.5 – 0.5 – 0.5 – ns tDH Data input hold after CLK rise 0.3 – 0.5 – 0.5 – 0.5 – ns tCEH Chip enable hold after CLK rise 0.3 – 0.5 – 0.5 – 0.5 – ns Notes 11. Timing references level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V on all datasheets. 12. Test conditions shown in (a) of Figure 4 on page 13 unless otherwise noted. 13. This part has an internal voltage regulator; tPOWER is the time that the power must be supplied above VDD(min) initially before a read or write operation can be initiated. 14. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 13. Transition is measured ±200 mV from steady-state voltage. 15. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z before Low Z under the same system conditions. 16. This parameter is sampled and not 100% tested. Document #: 38-05516 Rev. *I Page 14 of 24 [+] Feedback CY7C1347G Switching Waveforms Figure 5. Read Cycle Timing[17] t CYC CLK t t CH t CL t ADH ADS ADSP t ADS tADH ADSC t AS ADDRESS tAH A1 A2 t WES A3 Burst continued with new base address tWEH GW, BWE, BW [A:D] t CES Deselect cycle tCEH CE t ADVS tADVH ADV ADV suspends burst. OE t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t OEV t CO t OELZ t DOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) t CO Single READ BURST READ DON’T CARE Burst wraps around to its initial state UNDEFINED Note 17. In this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW, or CE3 is HIGH. Document #: 38-05516 Rev. *I Page 15 of 24 [+] Feedback CY7C1347G Switching Waveforms (continued) Figure 6. Write Cycle Timing[18, 19] t CYC CLK tCH t ADS tCL tADH ADSP t ADS ADSC extends burst tADH t ADS tADH ADSC t AS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst t WES tWEH BWE, BW[A :B] t WES tWEH GW t CES tCEH CE t t ADVS ADVH ADV ADV suspends burst OE t DS Data In (D) High-Z t OEHZ tDH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Notes 18. In this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW, or CE3 is HIGH. 19. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BWx LOW. Document #: 38-05516 Rev. *I Page 16 of 24 [+] Feedback CY7C1347G Switching Waveforms (continued) Figure 7. Read/Write Cycle Timing[20, 21, 22] tCYC CLK tCL tCH t ADS tADH ADSP ADSC t AS ADDRESS A1 tAH A2 A3 A4 t WES tWEH t DS tDH A5 A6 BWE, BW[A:D] t CES tCEH CE ADV OE tCO t OELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ D(A5) D(A3) Q(A2) Q(A4) Single WRITE Q(A4+1) Q(A4+2) Q(A4+3) BURST READ DON’T CARE D(A6) Back-to-Back WRITEs UNDEFINED Notes 20. In this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW, or CE3 is HIGH. 21. The data bus (Q) remains in High Z following a write cycle, unless a new read access is initiated by ADSP or ADSC. 22. GW is HIGH. Document #: 38-05516 Rev. *I Page 17 of 24 [+] Feedback CY7C1347G Switching Waveforms (continued) Figure 8. ZZ Mode Timing[23, 24] CLK t ZZ I t t ZZ ZZREC ZZI SUPPLY I DDZZ t RZZI A LL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes 23. Device must be deselected when entering ZZ mode. See Truth Table on page 8 for all possible signal conditions to deselect the device. 24. DQs are in High Z when exiting ZZ sleep mode. Document #: 38-05516 Rev. *I Page 18 of 24 [+] Feedback CY7C1347G Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices Speed (MHz) 133 Ordering Code Package Diagram Package Type Operating Range CY7C1347G-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free CY7C1347G-133BGXC 51-85115 119-ball Ball Grid Array (14 × 22 × 2.4 mm) Pb-free Commercial 166 CY7C1347G-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Commercial 200 CY7C1347G-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Commercial 250 CY7C1347G-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Commercial Ordering Code Definitions CY 7C 1347 G - XXX XXX C Temperature range: C = Commercial Package Type: AX = 100-pin TQFP (Pb-free) BGX = 119-ball BGA (Pb-free) Speed Grade: XXX = 133 MHz or 166 MHz or 200 MHz or 250 MHz Process Technology 90 nm 1347 = SCD, 128 K × 36 (4 Mb) Marketing Code: 7C = SRAMs Company ID: CY = Cypress Document #: 38-05516 Rev. *I Page 19 of 24 [+] Feedback CY7C1347G Package Diagrams Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) 51-85050 *D Document #: 38-05516 Rev. *I Page 20 of 24 [+] Feedback CY7C1347G Package Diagrams (continued) Figure 10. 119-ball BGA (14 × 22 × 2.4 mm) 51-85115 *C Document #: 38-05516 Rev. *I Page 21 of 24 [+] Feedback CY7C1347G Package Diagrams (continued) Figure 11. 165-ball FBGA (13 × 15 × 1.4 mm) 51-85180 *C Acronyms Acronym Description DDR double data rate FBGA fine-pitch ball grid array HSTL high-speed transceiver logic JEDEC joint electron device engineering council JTAG joint test action group ODT on-die termination PLL phase-locked loop QDR quad data rate TAP test access port TCK test clock TDO test data out TDI test data in TMS test mode select Document #: 38-05516 Rev. *I Page 22 of 24 [+] Feedback CY7C1347G Document History Page Document Title: CY7C1347G 4-Mbit (128 K × 36) Pipelined Sync SRAM Document Number: 38-05516 Revision ECN Orig. of Change Submission Description of Change Date ** 224364 RKF See ECN New datasheet *A 276690 VBL See ECN Changed TQFP package in Ordering Information section to Pb-Free TQFP Added comment of BG and BZ Pb-Free package availability *B 333625 SYT See ECN Removed 225 MHz and 100 MHz speed grades Modified Address Expansion balls in the pinouts for 100 TQFP Package as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Replaced TBDs for JA and JC to their respective values on the Thermal Resistance table Changed the package name for 100 TQFP from A100RA to A101 Removed comment on the availability of BG Pb-Free package Updated the Ordering Information by shading and unshading MPNs as per availability *C 419256 RXU See ECN Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Swapped typo CE2 and CE3 in the Truth Table column heading on Page #6 Modified test condition from VIH < VDD to VIH VDD. Modified test condition from VDDQ < VDD to VDDQ < VDD Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table. Replaced Package Name column with Package Diagram in the Ordering Information table. Replaced Package Diagram of 51-85050 from *A to *B Replaced Package Diagram of 51-85180 from ** to *A Updated the Ordering Information. *D 480124 VKN See ECN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Updated the Ordering Information table. *E 1078184 VKN See ECN Corrected write timing diagram on page 12 *F 2633279 NXR/AESA 01/15/09 Updated Ordering Information and data sheet template. *G 2756998 VKN 08/28/09 Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. Updated Package Diagram for spec 51-85180. *H 2998771 NJY 08/02/10 Template update. Updated package diagrams to latest revision. 51-85050 – *B to *C 51-85115 – *B to *C 51-85180 – *B to *C *I 3208774 NJY 03/29/2011 Document #: 38-05516 Rev. *I Updated Ordering Information and added Ordering Code Definitions. Updated Package Diagrams. Page 23 of 24 [+] Feedback CY7C1347G Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05516 Rev. *I Revised March 29, 2011 Page 24 of 24 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback