[ /Title (CD74 HC283 , CD74 HCT28 3) /Subject (High Speed CMOS Logic 4-Bit Binary Full Adder CD54HC283, CD74HC283, CD54HCT283, CD74HCT283 Data sheet acquired from Harris Semiconductor SCHS176D November 1997 - Revised October 2003 High-Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry Features Description • Adds Two Binary Numbers The ’HC283 and ’HCT283 binary full adders add two 4-bit binary numbers and generate a carry-out bit if the sum exceeds 15. • Full Internal Lookahead • Fast Ripple Carry for Economical Expansion Because of the symmetry of the add function, this device can be used with either all active-high operands (positive logic) or with all active-low operands (negative logic). When using positive logic the carry-in input must be tied low if there is no carry-in. • Operates with Both Positive and Negative Logic • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Ordering Information • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times PART NUMBER • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH TEMP. RANGE (oC) PACKAGE CD54HC283F3A -55 to 125 16 Ld CERDIP CD54HCT283F3A -55 to 125 16 Ld CERDIP CD74HC283E -55 to 125 16 Ld PDIP CD74HC283M -55 to 125 16 Ld SOIC CD74HC283MT -55 to 125 16 Ld SOIC CD74HC283M96 -55 to 125 16 Ld SOIC CD74HCT283E -55 to 125 16 Ld PDIP CD74HCT283M -55 to 125 16 Ld SOIC CD74HCT283MT -55 to 125 16 Ld SOIC CD74HCT283M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout Functional Diagram CD54HC283, CD54HCT283 (CERDIP) CD74HC283, CD74HCT283 (PDIP, SOIC) TOP VIEW A0 B0 A1 B1 S1 1 16 VCC B1 2 15 B2 A1 3 14 A2 S0 4 13 S2 B2 A0 5 12 A3 A3 B0 6 11 B3 CIN 7 10 S3 GND 8 A2 B3 CIN 9 COUT 5 4 S0 6 3 1 S1 2 14 13 S2 15 12 10 S3 11 7 9 COUT GND = 8 VCC = 16 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC283, CD74HC283, CD54HCT283, CD74HCT283 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 2 CD54HC283, CD74HC283, CD54HCT283, CD74HCT283 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH High Level Output Voltage TTL Loads 25oC VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VIL or VIH -0.02 4.5 4.4 - - 4.4 - 4.4 - V VOH VIL or VIH -4 4.5 3.98 - - 3.84 - 3.7 - V Low Level Output Voltage CMOS Loads VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Low Level Output Voltage TTL Loads VOL VIH or VIL 4 4.5 - - 0.26 - 0.33 - 0.4 V II VCC to GND - 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND - 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC - 2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA PARAMETER HCT Types Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS CIN 1.5 B1, A1, A0 1 B0 0.4 B3, A3, A2, B2 0.5 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. Switching Specifications Input tr, tf = 6ns PARAMETER HC TYPES Propagation Delay -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - 160 - 200 - 240 ns CIN to S0 4.5 - - 32 - 40 - 48 ns CL = 15pF 5 - 13 - - - - - ns CL = 50pF 6 - - 27 - 34 - 41 ns 3 CD54HC283, CD74HC283, CD54HCT283, CD74HCT283 Switching Specifications Input tr, tf = 6ns PARAMETER CIN to S1 CIN to S2, CIN to COUT CIN to S3 An, Bn to COUT An, Bn to Sn Output Transition Time (Continued) -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - 180 - 225 - 270 ns 4.5 - - 36 - 45 - 54 ns CL = 15pF 5 - 15 - - - - - ns CL = 50pF 6 - - 31 - 38 - 46 ns CL = 50pF 2 - - 195 - 245 - 295 ns 4.5 - - 39 - 49 - 59 ns CL = 15pF 5 - 16 - - - - - ns CL = 50pF 6 - - 33 - 42 - 50 ns CL = 50pF 2 - - 230 - 290 - 345 ns 4.5 - - 46 - 58 - 69 ns CL = 15pF 5 - 19 - - - - - ns CL = 50pF 6 - - 39 - 49 - 59 ns CL = 50pF 2 - - 195 - 245 - 295 ns 4.5 - - 39 - 49 - 59 ns CL = 15pF 5 - 16 - - - - - ns CL = 50pF 6 - - 33 - 42 - 50 ns CL = 50pF 2 - - 210 - 265 - 315 ns 4.5 - - 42 - 53 - 63 ns CL = 15pF 5 - 18 - - - - - ns CL = 50pF 6 - - 36 - 45 - 54 ns CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance, (Notes 3, 4) CPD - 5 - 70 - - - - - pF tPLH, tPHL CL = 15pF 5 - 13 - - - - - ns CL = 50pF 4.5 - - 31 - 39 - 47 ns CL = 15pF 5 - 18 - - - - - ns CL = 50pF 4.5 - 43 - 54 - 65 ns CL = 15pF 5 - - - - - - ns CL = 50pF 4.5 - 46 - 58 - 69 ns CL = 15pF 5 - - - - - - ns CL = 50pF 4.5 - 53 - 66 - 80 ns CL = 15pF 5 - - - - - - ns CL = 50pF 4.5 - 48 - 60 - 72 ns CL = 15pF 5 - - - - - - ns CL = 50pF 4.5 - 49 - 61 - 74 ns CL = 50pF 4.5 - 15 - 19 - 22 ns HCT TYPES Propagation Delay CIN to S0 CIN to S1 tPLH, tPHL CIN to S2, CIN to COUT tPLH, tPHL CIN to S3 tPLH, tPHL An, Bn to COUT tPLH, tPHL An, Bn to Sn Output Transition Time tPLH, tPHL tTLH, tTHL 4 19 22 20 21 CD54HC283, CD74HC283, CD54HCT283, CD74HCT283 Switching Specifications Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Input Capacitance CIN - - - - 10 - 10 - 10 pF Power Dissipation Capacitance, (Notes 3, 4) CPD - 5 - 82 - - - - - pF PARAMETER NOTES: 3. CPD is used to determine the dynamic power consumption, per package. 4. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns VCC tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-8976501EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8976501EA CD54HC283F3A CD54HC283F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8976501EA CD54HC283F3A CD54HCT283F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HCT283F3A CD74HC283E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC283E CD74HC283EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC283E CD74HC283M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC283M CD74HC283M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC283M CD74HC283M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC283M CD74HC283ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC283M CD74HC283MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC283M CD74HC283MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC283M CD74HCT283E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT283E CD74HCT283EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT283E CD74HCT283M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT283M CD74HCT283M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT283M CD74HCT283M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT283M CD74HCT283MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT283M Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Jun-2014 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CD74HCT283MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT283M CD74HCT283MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT283M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 OTHER QUALIFIED VERSIONS OF CD54HC283, CD54HCT283, CD74HC283, CD74HCT283 : • Catalog: CD74HC283, CD74HCT283 • Military: CD54HC283, CD54HCT283 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC283M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT283M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC283M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT283M96 SOIC D 16 2500 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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