CY8C21345 CY8C22345 CY8C22545 PSoC® Programmable System-on-Chip Features ■ ■ ■ Powerful Harvard-architecture processor: ❐ M8C processor speeds up to 24 MHz ❐ 8 × 8 multiply, 32-bit accumulate ❐ Low power at high speed ❐ 3.0 V to 5.25 V operating voltage ❐ Industrial temperature range: –40 °C to +85 °C ■ Programmable pin configurations: ❐ 25 mA sink, 10 mA source on all GPIOs ❐ Pull-up, pull-down, high Z, Strong, or open-drain drive modes on all GPIOs ❐ Up to 38 analog inputs on GPIOs ❐ Configurable interrupt on all GPIOs ■ Additional system resources: 2 ❐ I C slave, master, and multimaster to 400 kHz ❐ Supports hardware addressing feature ❐ Watchdog and sleep timers ❐ User configurable low voltage detection ❐ Integrated supervisory circuit ❐ On-Chip precision voltage reference ❐ Supports RTC block into digital peripheral logic Advanced peripherals (PSoC® Blocks) ❐ Six analog type “E” PSoC blocks provide: • Single or dual 8-Bit ADC • Comparators (up to four) ❐ Up to eight digital PSoC blocks provide: • 8- to 32-bit timers and counters, 8- and 16-bit pulse-width modulators (PWMs) • One shot, multi-shot mode support in timers and PWMs • PWM with deadband support in one digital block • Shift register, CRC, and PRS modules • Full duplex UART • Multiple SPI masters or slaves, variable data length Support: 8- to 16-Bit • Can be connected to all GPIO pins ❐ Complex peripherals by combining blocks ❐ Shift function support for FSK detection ❐ Powerful synchronize feature support. Analog module operations can be synchronized by digital blocks or external signals. Top Level Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC Core Global Digital Interconnect SRAM 1K SROM Flash 16K CPU Core (M8C) Interrupt Controller High speed 10-bit SAR ADC with sample and hold optimized for Global Analog Interconnect Sleep and Watchdog embedded control ■ ■ Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) Precision, programmable clocking: ❐ Internal ± 5% 24/48 MHz oscillator across the industrial temperature range ❐ High accuracy 24 MHz with optional 32 kHz crystal and PLL ❐ Optional external oscillator, up to 24 MHz ❐ Internal/external oscillator for watchdog and sleep Flexible on-chip memory: ❐ Up to 16 KB flash program storage 50,000 erase/write cycles ❐ Up to 1-KB SRAM data storage ❐ In-system serial programming (ISSP) ❐ Partial flash updates ❐ Flexible protection modes ❐ EEPROM emulation in flash ® Optimized CapSense resource: ❐ Two IDAC support up to 640 µA source current to replace external resistor ❐ Two dedicated clock resources for CapSense: • CSD_CLK: 1/2/4/8/16/32/128/256 derive from SYSCLK • CNT_CLK: 1/2/4/8 Derive from CSD_CLK ❐ Dedicated 16-bit timers/counters for CapSense scanning ❐ Support dual CSD channels simultaneous scanning Cypress Semiconductor Corporation Document Number: 001-43084 Rev. *Q • 198 Champion Court ANALOG SYSTEM DIGITAL SYSTEM Digital Block Array Analog Ref Analog Input Muxing(L,R) DBC DBC DCC DCC = ROW 1 Analog Block Array DBC DBC DCC DCC ROW 2 System Bus ■ CTE CTE SCE SCE CapSense Digital Resource Digital Clocks MACs CTE CTE 10-bit SAR ADC I2C POR and LVD System Resets Internal Voltage Ref. SYSTEM RESOURCES • San Jose, CA 95134-1709 • 408-943-2600 Revised April 9, 2013 CY8C21345 CY8C22345 CY8C22545 Contents PSoC Functional Overview .............................................. 3 PSoC Core .................................................................. 3 Digital System ............................................................. 3 Analog System ............................................................ 4 Additional System Resources ..................................... 4 PSoC Device Characteristics ...................................... 5 Getting Started .................................................................. 5 Application Notes ........................................................ 5 Development Kits ........................................................ 5 Training ....................................................................... 5 CYPros Consultants .................................................... 5 Solutions Library .......................................................... 5 Technical Support ....................................................... 5 Development Tools .......................................................... 6 PSoC Designer Software Subsystems ........................ 6 Designing with PSoC Designer ....................................... 7 Select User Modules ................................................... 7 Configure User Modules .............................................. 7 Organize and Connect ................................................ 7 Generate, Verify, and Debug ....................................... 7 Pinouts .............................................................................. 8 CY8C22345, CY8C21345 28-pin SOIC ...................... 8 CY8C22545 44-pin TQFP ........................................... 9 Registers ......................................................................... 10 Register Conventions ................................................ 10 Register Mapping Tables .......................................... 10 Document Number: 001-43084 Rev. *Q Electrical Specifications ................................................ 13 Absolute Maximum Ratings ....................................... 14 Operating Temperature ............................................. 14 DC Electrical Characteristics ..................................... 15 AC Electrical Characteristics ..................................... 21 Packaging Information ................................................... 27 Thermal Impedances ................................................. 28 Solder Reflow Specifications ..................................... 28 Ordering Information ...................................................... 28 Ordering Code Definitions ......................................... 28 Acronyms ........................................................................ 29 Reference Documents .................................................... 29 Document Conventions ................................................. 30 Units of Measure ....................................................... 30 Numeric Conventions .................................................... 30 Glossary .......................................................................... 30 Appendix: Silicon Errata for the PSoC® CY8C21x45, CY8C22x45 Product Family ........................................... 35 Part Numbers Affected .............................................. 35 CY8C21x45, CY8C22x45 Qualification Status .......... 35 Errata Summary ........................................................ 35 Document History Page ................................................. 37 Sales, Solutions, and Legal Information ...................... 39 Worldwide Sales and Design Support ....................... 39 Products .................................................................... 39 PSoC Solutions ......................................................... 39 Page 2 of 39 CY8C21345 CY8C22345 CY8C22545 PSoC Functional Overview The PSoC family consists of many On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. Digital System The Digital System is composed of eight digital PSoC blocks. Each block is an 8-bit resource that may be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Figure 1. Digital System Block Diagram Port 3 Port 2 To System Bus Digital Clocks From Core The PSoC architecture, shown in Figure 1, consists of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows the combining of all the device resources into a complete custom system. The PSoC family can have up to five I/O ports connecting to the global digital and analog interconnects, providing access to eight digital blocks and six analog blocks. Port 0 To Analog System DIGITAL SYSTEM Row 0 DBC00 DBC01 DCC02 4 DCC03 4 Row Output Configuration Row Input Configuration Digital PSoC Block Array 8 8 PSoC Core 8 Row Input Configuration 8 The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 21 vectors, to simplify the programming of real time embedded events. Row 1 DBC00 GIE[7:0] GIO[7:0] Program execution is timed and protected using the included Sleep and watchdog timers (WDT). DBC01 DCC02 DCC03 Global Digital Interconnect Row Output Configuration The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable general-purpose I/O (GPIO). Memory encompasses 16 KB of Flash for program storage, 1 K bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. Port 1 Port 4 GOE[7:0] GOO[7:0] Digital peripheral configurations are: ■ PWMs (8- and 16-Bit) ■ PWMs with Dead band (8- and 16-Bit) The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator). The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz internal low-speed oscillator (ILO) is provided for the Sleep timer and WDT. If crystal accuracy is required, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC), and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. ■ Counters (8 to 32-Bit) ■ Timers (8 to 32-Bit) ■ UART 8 Bit with Selectable Parity (Up to Two) ■ SPI Master and Slave (Up to Two) ■ Shift Register (1 to 32-Bit) ■ I2C Slave and Master (One Available as a System Resource) ■ Cyclical Redundancy Checker/Generator (8 to 32-Bit) PSoC GPIOs provide connection to the CPU, digital, and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin can also generate a system interrupt on high level, low level, and change from last read. ■ IrDA (Up to Two) ■ Pseudo Random Sequence Generators (8 to 32-Bit) The digital blocks may be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This provides a choice of system resources for your application. Family resources are shown in Table 1 on page 5. Document Number: 001-43084 Rev. *Q Page 3 of 39 CY8C21345 CY8C22345 CY8C22545 Analog System Additional System Resources The Analog System consists of a 10-bit SAR ADC and six configurable blocks. System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a MAC, low voltage detection, and power on reset. The merits of each system resource are: The programmable 10-bit SAR ADC is an optimized ADC that can be run up to 200 ksps with ± 1.5 LSB DNL and ± 2.5 LSB INL (true for VDD 3.0 V and Vref 3.0 V). External filters are required on ADC input channels for antialiasing. This ensures that any out-of-band content is not folded into the input signal band. Reconfigurable analog resources allow creating complex analog signal flows. Analog peripherals are very flexible and may be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are: ■ Analog-to-Digital converters (Single or Dual, with 8-bit resolution) ■ Pin-to-pin Comparator ■ Single ended comparators with absolute (1.3 V) reference or 5-bit DAC reference ■ 1.3 V reference (as a System Resource) Analog blocks are provided in columns of four, which include CT-E (Continuous Time) and SC-E (Switched Capacitor) blocks. These devices provide limited functionality Type “E” analog blocks. ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks may be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. ■ Additional Digital resources and clocks optimized for CSD. ■ Support “RTC” block into digital peripheral logic. ■ A multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math and digital filters. ■ The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. ■ Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. ■ An internal 1.3 V reference provides an absolute reference for the analog system, including ADCs and DACs. Figure 2. Analog System Block Diagram Array Input Configuration ACI0[1:0] ACI1[1:0] ACI1[1:0] ACI1[1:0] ACE00 ACE01 ACE10 ACE11 ASE10 ASE11 Block Array AmuxL AmuxR P0[0:7] ACI2[3:0] 10 bit SAR ADC Analog Reference Interface to Digital System AGND Reference Generators Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-43084 Rev. *Q Page 4 of 39 CY8C21345 CY8C22345 CY8C22545 PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. The following table lists the resources available for specific PSoC device groups. Table 1. PSoC Device Characteristics PSoC Part Number Digital I/O Digital Rows Digital Blocks Analog Inputs Analog Outputs Analog Columns Analog Blocks SRAM Size Flash Size CY8C29x66[1] up to 64 4 16 up to 12 4 4 12 2K 32 K CY8C28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 12 + 4[2] 1K 16 K CY8C27x43 up to 44 2 8 up to 12 4 4 12 256 16 K CY8C24x94[1] up to 56 1 4 up to 48 2 2 6 1K 16 K CY8C24x23A [1] up to 24 1 4 up to 12 2 2 6 256 4K CY8C23x33 up to 26 1 4 up to 12 2 2 4 256 8K CY8C22x45[1] up to 38 2 8 up to 38 0 4 6[2] 1K 16 K [1] up to 24 1 4 up to 24 0 4 6[2] 512 8K CY8C21x34[1] up to 28 1 4 up to 28 0 2 4[2] 512 8K [2] 256 4K CY8C21x45 CY8C21x23 up to 16 1 4 up to 8 0 2 CY8C20x34[1] up to 28 0 0 up to 28 0 0 3[2,3] 4 512 8K CY8C20xx6 up to 36 0 0 up to 36 0 0 3[2,3] up to 2 K up to 32 K Getting Started For in-depth information, along with detailed programming details, see the PSoC® Technical Reference Manual. covers a wide variety of topics and skill levels to assist you in your designs. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web. CYPros Consultants Application Notes Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, Solutions Library Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Notes 1. Automotive qualified devices available in this group. 2. Limited analog functionality. 3. Two analog blocks and one CapSense® block. Document Number: 001-43084 Rev. *Q Page 5 of 39 CY8C21345 CY8C22345 CY8C22545 Development Tools PSoC Designer™ is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: ■ Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration ■ Extensive user module catalog ■ Integrated source-code editor (C and assembly) ■ Free C compiler with no size restrictions or time limits ■ Built-in debugger ■ In-circuit emulation ■ Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are ADCs, DACs, amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run Document Number: 001-43084 Rev. *Q time. In essence, this allows you to use more than 100 percent of PSoC's resources for an application. Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and are linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an online support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality in-circuit emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24 MHz) operation. Page 6 of 39 CY8C21345 CY8C22345 CY8C22545 Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is summarized in four steps: specifications. Each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources. 1. Select User Modules. Generate, Verify, and Debug 2. Configure User Modules. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. 3. Organize and Connect. 4. Generate, Verify, and Debug. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance Document Number: 001-43084 Rev. *Q A complete code development environment allows you to develop and customize your applications in either C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events. These include monitoring address and data bus values, memory locations, and external signals. Page 7 of 39 CY8C21345 CY8C22345 CY8C22545 Pinouts This PSoC device family is available in a variety of packages that are listed in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O. CY8C22345, CY8C21345 28-pin SOIC Table 2. Pin Definitions Pin No. Type Digital Analog Pin Name Description 1 I/O I, MR P0[7] Integration Capacitor for MR 2 I/O I, ML P0[5] Integration Capacitor for ML 3 I/O I, ML P0[3] 4 I/O I, ML P0[1] 5 I/O I, ML P2[7] To Compare Column 0 6 I/O ML P2[5] Optional ADC External Vref 7 I/O ML P2[3] 8 I/O ML P2[1] 9 Power Vss Ground Connection 10 I/O ML P1[7] I2C serial clock (SCL) I2C serial data (SDA) 11 I/O ML P1[5] 12 I/O ML P1[3] 13 I/O ML P1[1] 14 Power Vss 15 I/O MR P1[0] 16 I/O MR P1[2] 17 I/O MR P1[4] 18 I/O 19 MR Input I/O MR 21 I/O MR P2[2] 22 I/O MR P2[4] 23 I/O I, MR P2[6] 24 I/O I, MR P0[0] 25 I/O I, MR P0[2] 26 I/O I, MR P0[4] 27 I/O I, MR P0[6] Power AI, MR, P0[7] AI, ML, P0[5] AI, ML, P0[3] AI, ML, P0[1] AI, ML, P2[7] ADC_Ext_Vref, ML, P2[5] ML, P2[3] ML, P2[1] Vss I2C SCL, ML, P1[7] I2C SDA, ML, P1[5] ML, P1[3] I2C SCL, ML, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], MR, AI P0[4], MR, AI P0[2], MR, AI P0[0], MR, AI P2[6], MR, AI P2[4], MR P2[2], MR P2[0], MR XRES P1[6], MR P1[4], MR, EXTCLK P1[2], MR P1[0], MR, I2C SDATA I2C serial clock (SCL), ISSP-SCLK[4] Ground Connection I2C serial Clock (SCL), ISSP-SDATA[4] Optional external clock input (EXT-CLK) P1[6] XRES 20 28 Figure 3. Pin Diagram Active High Pin Reset with Internal Pull Down P2[0] Vdd To Compare Column 1 Supply Voltage LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input. Note 4. ISSP pin which is not HI-Z at POR. Document Number: 001-43084 Rev. *Q Page 8 of 39 CY8C21345 CY8C22345 CY8C22545 CY8C22545 44-pin TQFP Table 3. Pin Definitions I/O ML P2[1] 4 Power Vdd 5 I/O ML P4[5] 6 I/O ML P4[3] 7 I/O ML P4[1] 8 Power Vss Supply Voltage Ground Connection 9 I/O ML P3[7] 10 I/O ML P3[5] 11 I/O ML P3[3] 12 I/O ML P3[1] 13 I/O ML P1[7] I2C serial clock (SCL) 14 I/O ML P1[5] I2C serial data (SDA) 15 I/O ML P1[3] 16 I/O ML P1[1] 17 Power Vss 18 I/O MR P1[0] 19 I/O MR P1[2] 20 I/O MR P1[4] 21 I/O MR P1[6] 22 I/O MR P3[0] 23 I/O MR P3[2] 24 I/O MR P3[4] 25 I/O MR 26 Input I/O MR P4[0] 28 I/O MR P4[2] 29 I/O MR P4[4] Power Vss 31 I/O MR P2[0] 32 I/O MR P2[2] 33 I/O MR P2[4] 34 I/O I, MR P2[6] 35 I/O I, MR P0[0] 36 I/O I, MR P0[2] 37 I/O I, MR P0[4] 38 I/O I, MR P0[6] 39 Power Crystal (XTALin), I2C SCL, TC SCLK[4] Ground Connection Crystal (XTALout), I2C SDA, TC ] SDATA[4 1 2 3 4 5 TQFP 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 P2[4], MR P2[2], MR P2[0], MR Vss P4[4], MR P4[2], MR P4[0], MR XRES P3[6], MR P3[4], MR P3[2], MR Optional external clock input (EXTCLK) P3[6] XRES 27 30 ADC_Ext_Vref, ML, P2[5] ML, P2[3] ML, P2[1] Vdd ML, P4[5] ML, P4[3] ML, P4[1] Vss ML, P3[7] ML, P3[5] ML, P3[3] MR, P1[6] MR, P3[0] 3 Optional ADC External Vref P0[5], ML, AI P0[7], MR, AI Vdd P0[6], MR, AI P0[4], MR, AI P0[2], MR, AI P0[0], MR, AI P2[6], MR, AI P2[3] 41 40 P2[5] ML 39 38 37 36 35 34 ML I/O P2[7], ML, AI P0[1], ML, AI P0[3], ML, AI I/O 2 Figure 4. Pin Diagram 44 43 42 1 Description 12 13 14 15 16 17 18 19 20 21 22 Pin Name Analog ML, P3[1] Type Digital I2C SCL, ML, P1[7] I2C SDA, ML, P1[5] ML, P1[3] I2C SCL, XTALin, ML, P1[1] Vss I2C SDA, XTALout, MR, P1[0] MR, P1[2] EXTCLK, MR, P1[4] Pin No. Active High Pin Reset with Internal Pull Down Ground Connection To Compare Column 1 Vdd Supply Voltage 40 I/O I, MR P0[7] Integration Capacitor for MR 41 I/O I, ML P0[5] Integration Capacitor for ML 42 I/O I, ML P0[3] 43 I/O I, ML P0[1] 44 I/O I, ML P2[7] To Compare Column 0 LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input. Document Number: 001-43084 Rev. *Q Page 9 of 39 CY8C21345 CY8C22345 CY8C22545 Registers This section lists the registers of this PSoC device family by mapping tables. For detailed register information, refer the PSoC Programmable System-on Chip Technical Reference Manual. Register Conventions Register Mapping Tables Table 4. Abbreviations The PSoC device has a total register address space of 512 bytes. The register space is also referred to as I/O space and is broken into two parts. The XIO bit in the Flag register determines which bank the user is currently in. When the XIO bit is set, the user is said to be in the “extended” address space or the “configuration” registers. Convention Description RW Read and write register or bit(s) R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific Document Number: 001-43084 Rev. *Q Note In the following register mapping tables, blank fields are Reserved and must not be accessed. Page 10 of 39 CY8C21345 CY8C22345 CY8C22545 Table 5. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 Addr (0,Hex) Access Name 00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 RW CSD0_DR0_L 11 RW CSD0_DR1_L 12 RW CSD0_CNT_L 13 RW CSD0_CR0 14 RW CSD0_DR0_H 15 RW CSD0_DR1_H 16 RW CSD0_CNT_H 17 RW CSD0_CR1 18 RW CSD1_DR0_L 19 RW CSD1_DR1_L 1A RW CSD1_CNT_L 1B RW CSD1_CR0 1C RW CSD1_DR0_H 1D RW CSD1_DR1_H 1E RW CSD1_CNT_H 1F RW CSD_CR1 DBC00DR0 20 # AMX_IN DBC00DR1 21 W AMUX_CFG DBC00DR2 22 RW PWM_CR DBC00CR0 23 # ARF_CR DBC01DR0 24 # CMP_CR0 DBC01DR1 25 W ASY_CR DBC01DR2 26 RW CMP_CR1 DBC01CR0 27 # DCC02DR0 28 # ADC0_CR DCC02DR1 29 W ADC1_CR DCC02DR2 2A RW SADC_DH DCC02CR0 2B # SADC_DL DCC03DR0 2C # TMP_DR0 DCC03DR1 2D W TMP_DR1 DCC03DR2 2E RW TMP_DR2 DCC03CR0 2F # TMP_DR3 DBC10DR0 30 # DBC10DR1 31 W DBC10DR2 32 RW ACB00CR1* DBC10CR0 33 # ACB00CR2* DBC11DR0 34 # DBC11DR1 35 W DBC11DR2 36 RW ACB01CR1* DBC11CR0 37 # ACB01CR2* DCC12DR0 38 # DCC12DR1 39 W DCC12DR2 3A RW DCC12CR0 3B # DCC13DR0 3C # DCC13DR1 3D W DCC13DR2 3E RW DCC13CR0 3F # Shaded fields are Reserved and must not be accessed. Document Number: 001-43084 Rev. *Q Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72* 73* 74 75 76* 77* 78 79 7A 7B 7C 7D 7E 7F Access # W RW # # W RW # # W RW # # W RW # R W R # R W R RW R W R # R W R RW RW RW RW RW # # RW RW # # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name ASC10CR0* Addr (0,Hex) Access Name 80* RW 81 RW 82 RW 83 RW ASD11CR0* 84* RW 85 RW 86 RW 87 RW 88 RW PWMVREF0 89 RW PWMVREF1 8A RW IDAC_MODE 8B RW PWM_SRC 8C RW TS_CR0 8D RW TS_CMPH 8E RW TS_CMPL 8F RW TS_CR1 90 RW CUR PP 91 RW STK_PP 92 RW PRV PP 93 RW IDX_PP 94 RW MVR_PP 95 RW MVW_PP 96 RW I2C0_CFG 97 RW I2C0_SCR 98 RW I2C0_DR 99 RW I2C0_MSCR 9A RW INT_CLR0 9B RW INT_CLR1 9C RW INT_CLR2 9D RW INT_CLR3 9E RW INT_MSK3 9F RW INT_MSK2 A0 INT_MSK0 A1 INT_MSK1 A2 INT_VC A3 RES_WDT A4 DEC_DH A5 DEC_DL A6 DEC _CR0* A7 DEC_CR1* A8 W MUL0_X A9 W MUL0_Y AA R MUL0_DH AB R MUL0_DL AC RW ACC0_DR1 AD RW ACC0_DR0 AE RW ACC0_DR3 AF RW ACC0_DR2 RDI0RI B0 RW CPU A RDI0SYN B1 RW CPU_T1 RDI0IS B2 RW CPU_T2 RDI0LT0 B3 RW CPU_X RDI0LT1 B4 RW CPU PCL RDI0RO0 B5 RW CPU_PCH RDI0RO1 B6 RW CPU_SP RDI0DSM B7 RW CPU_F RDI1RI B8 RW CPU_TST0 RDI1SYN B9 RW CPU_TST1 RDI1IS BA RW CPU_TST2 RDI1LT0 BB RW CPU TST3 RDI1LT1 BC RW DAC1_D RDI1RO0 BD RW DAC0_D RDI1RO1 BE RW CPU_SCR1 RDI1DSM BF RW CPU_SCR0 # Access is bit specific. * has a different meaning. Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW RW RW RW RW RW # # RW # RW RW RW RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RW RW RW RW W W R R RW RW RW RW # # # # # # # I RW RW RW # RW RW # # Page 11 of 39 CY8C21345 CY8C22345 CY8C22545 Table 6. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 Addr (1,Hex) Access Name 0 RW 1 RW 2 RW 3 RW 4 RW 5 RW 6 RW 7 RW 8 RW 9 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 RW CMP0CR1 11 RW CMP0CR2 12 RW 13 RW VDAC50CR0 14 RW CMP1CR1 15 RW CMP1CR2 16 RW 17 RW VDAC51CR0 18 RW CSCMPCR0 19 RW CSCMPGOEN 1A RW CSLUTCR0 1B RW CMPCOLMUX 1C RW CMPPWMCR 1D RW CMPFLTCR 1E RW CMPCLK1 1F RW CMPCLK0 DBC00FN 20 RW CLK_CR0 DBC00IN 21 RW CLK_CR1 DBC00OU 22 RW ABF_CR0 DBC00CR1 23 RW AMD_CR0 DBC01FN 24 RW CMP_GO_EN DBC01IN 25 RW CMP_GO_EN1 DBC01OU 26 RW AMD_CR1 DBC01CR1 27 RW ALT_CR0 DCC02FN 28 RW ALT_CR1 DCC02IN 29 RW CLK_CR2 DCC02OU 2A RW DBC02CR1 2B RW CLK_CR3 DCC03FN 2C RW TMP_DR0 DCC03IN 2D RW TMP_DR1 DCC03OU 2E RW TMP_DR2 DBC03CR1 2F RW TMP_DR3 DBC10FN 30 RW DBC10IN 31 RW DBC10OU 32 RW ACB00CR1* DBC10CR1 33 RW ACB00CR2* DBC11FN 34 RW DBC11IN 35 RW DBC11OU 36 RW ACB01CR1* DBC11CR1 37 RW ACB01CR2* DCC12FN 38 RW DCC12IN 39 RW DCC12OU 3A RW DBC12CR1 3B RW DCC13FN 3C RW DCC13IN 3D RW DCC13OU 3E RW DBC13CR1 3F RW Shaded fields are Reserved and must not be accessed. Document Number: 001-43084 Rev. *Q Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76* 77* 78 79 7A 7B 7C 7D 7E 7F Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name ASC10CR0* Addr (1,Hex) Access Name 80* RW 81 RW 82 RW 83 RW ASD11CR0* 84* RW 85 RW 86 RW 87 RW 88 RW 89 RW 8A RW 8B RW 8C RW 8D RW 8E RW 8F RW 90 RW GDI_O_IN 91 RW GDI_E_IN 92 RW GDI_O_OU 93 RW GDI_E_OU 94 RW 95 RW 96 RW 97 RW 98 RW MUX_CR0 99 RW MUX_CR1 9A RW MUX_CR2 9B RW MUX_CR3 9C RW DAC_CR1# 9D RW OSC_GO_EN 9E RW OSC_CR4 9F RW OSC_CR3 GDI_O_IN_CR A0 RW OSC_CR0 GDI_E_IN_CR A1 RW OSC_CR1 GDI_O_OU_CR A2 RW OSC_CR2 GDI_E_OU_CR A3 RW VLT_CR RTC_H A4 RW VLT_CMP RTC_M A5 RW ADC0_TR* RTC_S A6 RW ADC1_TR* RTC_CR A7 RW V2BG_TR SADC_CR0 A8 RW IMO_TR SADC_CR1 A9 RW ILO_TR SADC_CR2 AA RW BDG_TR SADC_CR3TRIM AB RW ECO_TR SADC_CR4 AC RW MUX_CR4 I2C0_AD AD RW MUX_CR5 AE RW MUX_CR6 AF RW MUX_CR7 RDI0RI B0 RW CPU A RDI0SYN B1 RW CPU_T1 RDI0IS B2 RW CPU_T2 RDI0LT0 B3 RW CPU_X RDI0LT1 B4 RW CPU_PCL RDI0RO0 B5 RW CPU_PCH RDI0RO1 B6 RW CPU_SP RDI0DSM B7 RW CPU_F RDI1RI B8 RW FLS_PR0 RDI1SYN B9 RW FLS TR RDI1IS BA RW FLS_PR1 RDI1LT0 BB RW RDI1LT1 BC RW FAC_CR0 RDI1RO0 BD RW DAC_CR0# RDI1RO1 BE RW CPU_SCR1 RDI1DSM BF RW CPU_SCR0 # Access is bit specific. * has a different meaning. Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW RW RW RW RW RW # RW RW RW # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW W W RW W RW RW RW RW # # # # # # # I RW W RW SW RW # # Page 12 of 39 CY8C21345 CY8C22345 CY8C22545 Electrical Specifications This section presents the DC and AC electrical specifications of this PSoC device family. For the latest electrical specifications, check the most recent data sheet by visiting http://www.cypress.com. Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications for devices running at greater than 12 MHz are valid for –40 °C TA 70 °C and TJ 82 °C. Figure 5. Voltage versus Operating Frequency 5.25 Vdd Voltage lid n g Va rati n e io Op Reg 4.75 3.00 93 kHz 12 MHz 24 MHz CPU Frequency Document Number: 001-43084 Rev. *Q Page 13 of 39 CY8C21345 CY8C22345 CY8C22545 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 7. Absolute Maximum Ratings Symbol Description Min Typ Max Units –55 – +100 °C – 125 See Package label °C See package label – 72 Hours –40 – +85 °C –0.5 – +6.0 V Vss - 0.5 – Vdd + 0.5 V Vss - 0.5 – Vdd + 0.5 V Maximum current into any port pin –25 – +50 mA ESD Electr static discharge voltage 2000 – – V LU Latch up current – – 200 mA TSTG Storage temperature TBAKETEMP Bake temperature TBAKETIME Bake time TA Ambient temperature with power applied Vdd Supply voltage on Vdd relative to Vss VIO DC input voltage VIOz DC voltage applied to tristate IMIO Notes Higher storage temperatures reduce data retention time Human Body Model ESD Operating Temperature Table 8. Operating Temperature Min Typ Max Units TA Symbol Ambient temperature Description –40 – +85 °C TJ Junction temperature –40 – +100 °C Document Number: 001-43084 Rev. *Q Notes The temperature rise from ambient to junction is package specific. See Table 29 on page 28. The user must limit the power consumption to comply with this requirement. Page 14 of 39 CY8C21345 CY8C22345 CY8C22545 DC Electrical Characteristics DC Chip Level Specifications Table 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C, and are for design guidance only, unless specified otherwise. Table 9. DC Chip Level Specifications Symbol Description Min Typ Max Units Notes Vdd Supply voltage 3.0 – 5.25 V See Table 16 on page 19 IDD Supply current – 7 12 mA Conditions are Vdd = 5.0 V, 25°C, CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz VC2 = 93.75 kHz VC3 = 93.75 kHz IDD3 Supply current – 4 7 mA Conditions are Vdd = 3.3 V TA = 25 °C, CPU = 3 MHz 48 MHz = Disabled VC1 = 1.5 MHz, VC2 = 93.75 kHz VC3 = 93.75 kHz ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT[5] – 3 6.5 A Conditions are with internal slow speed oscillator, Vdd = 3.3 V –40°C <= TA <= 55°C ISBH Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature[5] – 4 25 A Conditions are with internal slow speed oscillator, Vdd = 3.3 V 55 °C < TA <= 85 °C ISBXTL Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal[5] – 4 7.5 A Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3 V, –40 °C <= TA <= 55 °C ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature [5] – 5 26 A Conditions are with properly loaded, 1W max, 32.768 kHz crystal. Vdd = 3.3 V, 55 °C < TA <= 85 °C VREF Reference Voltage (Bandgap) 1.275 1.3 1.325 V Trimmed for appropriate Vdd Note 5. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar functions enabled. Document Number: 001-43084 Rev. *Q Page 15 of 39 CY8C21345 CY8C22345 CY8C22545 DC GPIO Specifications Table 10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only, unless otherwise specified. Table 10. DC GPIO Specifications Min Typ Max Units RPU Symbol Pull-up resistor Description 4 5.6 8 k RPD Pull-down resistor 4 5.6 8 k VOH High output level Vdd – 1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget VOL Low output level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. IOH High level source current 10 – – mA VOH = Vdd – 1.0 V, see the limitations of the total current in the note for VOH. IOL Low level sink current 25 – – mA VOL = 0.75 V, see the limitations of the total current in the note for VOL. VIL Input Low level – – 0.8 V Vdd = 3.0 to 5.25 VIH Input High level 2.1 – V Vdd = 3.0 to 5.25 VH Input hysterisis – 60 – mV IIL Input leakage (absolute value) – 1 – nA Gross tested to 1 A CIN Capacitive load on pins as input – 3.5 10 pF Package and pin dependent. Temp = 25 °C COUT Capacitive load on pins as output – 3.5 10 pF Package and pin dependent. Temp = 25 °C Document Number: 001-43084 Rev. *Q Notes Page 16 of 39 CY8C21345 CY8C22345 CY8C22545 DC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and are for design guidance only. Table 11. 5 V DC Operational Amplifier Specifications Symbol VOSOA Description Min Typ Max Units – 2.5 15 mV – 10 – V/°C Input offset voltage (absolute value) TCVOSOA Average input offset voltage drift Notes IEBOA[6] Input leakage current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 A CINOA Input capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25 °C VCMOA Common mode Voltage Range 0.0 – Vdd - 1 V Table 12. 3.3 V DC Operational Amplifier Specifications Min Typ Max Units VOSOA Symbol Input offset voltage (absolute value) Description – 2.5 15 mV Notes TCVOSOA Average input offset voltage drift – 10 – V/°C IEBOA[6] Input leakage current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 A CINOA Input capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25 °C VCMOA Common mode voltage range 0 – Vdd – 1 V Note 6. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25 °C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA. Document Number: 001-43084 Rev. *Q Page 17 of 39 CY8C21345 CY8C22345 CY8C22545 DC Low Power Comparator Specifications Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C respectively. Typical parameters apply to 5 V at 25 °C and are for design guidance only. Table 13. DC Low Power Comparator Specifications Symbol Description VREFLPC Low power comparator (LPC) reference voltage range VOSLPC LPC voltage offset Min Typ Max Units 0.2 – Vdd – 1 V – 2.5 30 mV Notes SAR10 ADC DC Specifications Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and are for design guidance only. Table 14. SAR10 ADC DC Specifications Description Min Typ Max Units Notes Vadcvref Symbol Reference voltage at pin P2[5] when configured as ADC reference voltage 3.0 – 5.25 V When VREF is buffered inside ADC, the voltage level at P2[5] (when configured as ADC reference voltage) must be always maintained to be at least 300 mV less than the chip supply voltage level on Vdd pin. (Vadcvref < Vdd) Iadcvref Current when P2[5] is configured as ADC VREF – – 0.5 mA Disables the internal voltage reference buffer INL at 10 bits Integral Nonlinearity –2.5 – 2.5 LSB For VDD 3.0 V and Vref 3.0 V –5.0 – 5.0 LSB For VDD < 3.0 V or Vref < 3.0 V –1.5 – 1.5 LSB For VDD 3.0 V and Vref 3.0 V –4.0 – 4.0 LSB For VDD < 3.0 V or Vref < 3.0 V – – 150 ksps Resolution 10 bits DNL at 10 bits Differential Nonlinearity SPS Sample per second Document Number: 001-43084 Rev. *Q Page 18 of 39 CY8C21345 CY8C22345 CY8C22545 DC Analog Mux Bus Specifications Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and are for design guidance only. Table 15. DC Analog Mux Bus Specifications Min Typ Max Units RSW Symbol Switch Resistance to Common Analog Bus Description – – 400 Rgnd Resistance of Initialization Switch to gnd – – 800 Notes Vdd 3.00 DC POR and LVD Specifications Table 16 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and are for design guidance only. Table 16. DC POR and LVD Specifications Symbol Description VPPOR1 VPPOR2 Vdd Value for PPOR Trip PORLEV[1:0] = 01b PORLEV[1:0] = 10b VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Vdd Value for LVD Trip VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Document Number: 001-43084 Rev. *Q Min Typ Max Units – 2.82 4.55 2.95 4.70 V V 2.95 3.06 4.37 4.50 4.62 4.71 3.02 3.13 4.48 4.64 4.73 4.81 3.09 3.20 4.55 4.75 4.83 4.95 V V V V V V Notes Vdd must be greater than or equal to 3.0 V during startup, reset from the XRES pin, or reset from Watchdog. Page 19 of 39 CY8C21345 CY8C22345 CY8C22545 DC Programming Specifications Table 17 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and are for design guidance only. Table 17. DC Programming Specifications Min Typ Max Units Notes VDDP Symbol VDD for programming and erase Description 4.5 5.0 5.5 V This specification applies to the functional requirements of external programmer tools VDDLV Low VDD for verify 3.0 3.1 3.2 V This specification applies to the functional requirements of external programmer tools VDDHV High VDD for verify 5.1 5.2 5.3 V This specification applies to the functional requirements of external programmer tools 3.0 – 5.25 V This specification applies to this device when it is executing internal flash writes VDDIWRITE Supply voltage for flash write operation IDDP Supply Current during Programming or Verify – 5 25 mA VILP Input Low Voltage during Programming or Verify – – 0.8 V VIHP Input High Voltage during Programming or Verify 2.2 – – V IILP Input Current when Applying VILP to P1[0] or P1[1] during Programming or Verify – – 0.2 mA Driving internal pull down resistor IIHP Input Current when Applying VIHP to P1[0] or P1[1] during Programming or Verify – – 1.5 mA Driving internal pull down resistor VOLV Output Low Voltage during Programming or Verify – – Vss + 0.75 V VOHV Output High Voltage during Programming or Verify Vdd - 1.0 – Vdd V 50,000 – – – Erase/write cycles per block 1,800,000 – – – Erase/write cycles 10 – – Years FlashENPB Flash Endurance (per block)[8] (total)[7] FlashENT Flash Endurance FlashDR Flash Data Retention DC I2C Specifications Table 18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and are for design guidance only. Table 18. DC I2C Specifications Min Typ Max Units VILI2C[9] Parameter Input low level Description – – 0.3 × VDD V Notes – – 0.25 × VDD V 4.75 V VDD 5.25 V VIHI2C[9] Input high level 0.7 × VDD – – V 3.0 V VDD 5.25 V 3.0 V VDD 3.6 V Note 7. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. 8. The 50,000 cycle Flash endurance per block is guaranteed only if the Flash operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25 V 9. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO specifications sections.The I2C GPIO pins also meet the above specs. Document Number: 001-43084 Rev. *Q Page 20 of 39 CY8C21345 CY8C22345 CY8C22545 AC Electrical Characteristics AC Chip Level Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and are for design guidance only. Table 19. 5 V and 3.3 V AC Chip-Level Specifications Symbol FIMO24 Description Internal Main Oscillator Frequency for 24 MHz Min 22.8 FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.5 8 6 6.5[10,11,12] FCPU1 CPU Frequency (5 V Nominal) 0.089 – 24 24.6[10,11] FCPU2 CPU Frequency (3.3 V Nominal) 0.089 – 12 12.3[11,12] FBLK5 Digital PSoC Block Frequency0(5 V Nominal) Digital PSoC Block Frequency (3.3 V Nominal) Internal Low Speed Oscillator Frequency Untrimmed Internal Low Speed Oscillator Frequency 0 – 48 49.2[10,11,13] – MHz Refer to Table 23 on page 23. 0 – 24 24.6[11,13] – MHz 15 – 32 85 – kHz 5 – – 100 – kHz The ILO is not adjusted with the factory trim values until after the CPU starts running. See the “System Resets” section in the Technical Reference Manual. µs FBLK33 F32K1 F32KU Min(%) Typ – 24 Max 25.2[10,11,12] Max(%) Units Notes – MHz Trimmed for 5 V or 3.3 V operation using factory trim values. See Figure 5 on page 13. SLIMO mode = 0 < 85 MHz Trimmed for 5 V or 3.3 V 8 operation using factory trim values. See Figure 5 on page 13. SLIMO mode = 0 < 85. – MHz 24 MHz only for SLIMO mode = 0. – MHz SLIMO mode = 0. TXRST External Reset Pulse Width 10 – – – – DC24M DCILO 24 MHz Duty Cycle Internal Low Speed Oscillator Duty Cycle 48 MHz Output Frequency 40 20 – – 50 50 60 80 – – 46.8 – 48.0 49.2 – Maximum frequency of signal on row input or row output SRPOWERUP Power supply slew rate – – – 12.3 – – – – 250 – TPOWERUP Time from end of POR to CPU executing code tjit_IMO[14] 24 MHz IMO cycle-to-cycle jitter (RMS) 24 MHz IMO long term N cycle-to-cycle jitter (RMS) 24 MHz IMO period jitter (RMS) – – – 100 – – – – – 200 300 700 900 – – ps ps – – 100 400 – ps tjit_PLL [14] – – – – 200 300 800 1200 – – ps ps – – 100 700 – ps FOUT48M FMAX 24 MHz IMO cycle-to-cycle jitter (RMS) 24 MHz IMO long term N cycle-to-cycle jitter (RMS) 24 MHz IMO period jitter (RMS) % % MHz Trimmed. Utilizing factory trim values. MHz V/ms Vdd slew rate during power up. ms N = 32 N = 32 Notes 10. Valid only for 4.75 V < Vdd < 5.25 V. 11. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 12. 3.0 V < Vdd < 3.6 V. 13. Refer to the individual user module data sheets for information on maximum frequencies for user modules. 14. Refer to Cypress Jitter Specifications, Understanding Datasheet Jitter Specifications for Cypress Timing Products for more information. Document Number: 001-43084 Rev. *Q Page 21 of 39 CY8C21345 CY8C22345 CY8C22545 AC GPIO Specifications Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and are for design guidance only. Table 20. 5 V and 3.3 V AC GPIO Specifications Symbol Description Min Typ Max Units Notes FGPIO GPIO operating frequency 0 – 12 MHz TRiseF Rise time, normal strong mode, Cload = 50 pF 3 – 18 ns Normal Strong Mode Vdd = 4.5 to 5.25 V, 10% to 90% TFallF Fall time, normal strong mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25 V, 10% to 90% TRiseS Rise time, slow strong mode, Cload = 50 pF 7 27 – ns Vdd = 3 to 5.25 V, 10% to 90% TFallS Fall time, slow strong mode, Cload = 50 pF 7 22 – ns Vdd = 3 to 5.25 V, 10% to 90% Figure 6. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS AC Operational Amplifier Specifications Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and are for design guidance only. Table 21. AC Operational Amplifier Specifications Symbol TCOMP Description Min Typ Comparator Mode Response Time, 50 mV Max Units 100 ns Notes Vdd 3.0 V AC Low Power Comparator Specifications Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for design guidance only. Table 22. AC Low Power Comparator Specifications Symbol TRLPC Description LPC response time Document Number: 001-43084 Rev. *Q Min Typ Max Units – – 50 s Notes 50 mV overdrive comparator reference set within VREFLPC Page 22 of 39 CY8C21345 CY8C22345 CY8C22545 AC Digital Block Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V, at 25 °C and are for design guidance only. Table 23. AC Digital Block Specifications Function All functions Timer Counter Dead Band CRCPRS (PRS Mode) Description Block Input Clock Frequency Vdd 4.75 V Vdd < 4.75 V Input Clock Frequency No Capture, Vdd 4.75 V No Capture, Vdd < 4.75 V With Capture Capture Pulse Width Input Clock Frequency No Enable Input, Vdd 4.75 V No Enable Input, Vdd < 4.75 V With Enable Input Enable Input Pulse Width Kill Pulse Width Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Input Clock Frequency Vdd 4.75 V Vdd < 4.75 V Input Clock Frequency Vdd 4.75 V Vdd < 4.75 V Input Clock Frequency CRCPRS (CRC Mode) SPIM Input Clock Frequency SPIS Transmitter Receiver Input Clock (SCLK) Frequency Width of SS_Negated Between Transmissions Input Clock Frequency Vdd 4.75 V, 2 Stop Bits Vdd 4.75 V, 1 Stop Bit Vdd < 4.75 V Input Clock Frequency Vdd 4.75 V, 2 Stop Bits Vdd 4.75 V, 1 Stop Bit Vdd < 4.75 V Min Typ Max Units Notes – – – – 50.4[15] 25.2[15] MHz MHz – – – – – – 50.4[15] 25.2[15] 25.2[15] MHz MHz MHz 50[16] – – ns – – – 50[16] – – – – 50.4[15] 25.2[15] 25.2[15] – MHz MHz MHz ns 20 50[16] 50[16] – – – – – – ns ns ns – – – – 50.4[15] 25.2[15] MHz MHz – – – – – – 50.4[15] 25.2[15] 25.2[15] MHz MHz MHz – – 8.4[15] MHz The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. – – 4.2[15] 50[16] – – – – – – – – 50.4[15] 25.2[15] 25.2[15] – – – – – – 50.4[15] 25.2[15] 25.2[15] MHz The input clock is the SPI SCLK in SPIS mode. ns The baud rate is equal to the input MHz clock frequency divided by 8. MHz MHz The baud rate is equal to the input MHz clock frequency divided by 8. MHz MHz Notes 15. Accuracy derived from IMO with appropriate trim for VDD range. 16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-43084 Rev. *Q Page 23 of 39 CY8C21345 CY8C22345 CY8C22545 AC External Clock Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and are for design guidance only. Table 24. 5 V AC External Clock Specifications Symbol Description Min Typ Max Units FOSCEXT Frequency 0.093 – 24.6 MHz – High Period 20.6 – 5300 ns – Low Period 20.6 – – ns – Power Up IMO to Switch 150 – – s Notes Table 25. 3.3 V AC External Clock Specifications Min Typ Max Units FOSCEXT Symbol Frequency with CPU Clock divide by 1 Description 0.093 – 12.3 MHz Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. Notes FOSCEXT Frequency with CPU Clock divide by 2 or greater 0.186 – 24.6 MHz If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. – High Period with CPU Clock divide by 1 41.7 – 5300 ns – Low Period with CPU Clock divide by 1 41.7 – – ns – Power Up IMO to Switch 150 – – s SAR10 ADC AC Specifications Table 26 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 26. SAR10 ADC AC Specifications Symbol Description Min Typ Max Units Freq3 Input clock frequency 3 V – – 2.7 MHz Freq5 Input clock frequency 5 V – – 2.7 MHz Document Number: 001-43084 Rev. *Q Notes Page 24 of 39 CY8C21345 CY8C22345 CY8C22545 AC Programming Specifications Table 27 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V, or 3.3 V at 25 °C and are for design guidance only. Table 27. AC Programming Specifications Symbol Description Min Typ Max Units Notes TRSCLK Rise Time of SCLK 1 – 20 ns TFSCLK Fall Time of SCLK 1 – 20 ns TSSCLK Data Set up Time to Falling Edge of SCLK 40 – – ns THSCLK Data Hold Time from Falling Edge of SCLK 40 – – ns FSCLK Frequency of SCLK 0 – 8 MHz FSCLK3 Frequency of SCLK3 0 – 6 MHz VDD < 3.6 V TERASEB Flash Erase Time (Block) – 10 – ms TWRITE Flash Block Write Time – 40 – ms TDSCLK Data Out Delay from Falling Edge of SCLK – – 55 ns 3.6 < Vdd; at 30 pF Load TDSCLK3 Data Out Delay from Falling Edge of SCLK – – 65 ns 3.0 Vdd 3.6; at 30 pF Load TERASEALL Flash Erase Time (Bulk) – 40 – ns TPROGRAM_HOT Flash Block Erase + Flash Block Write Time – – 100 ms TPROGRAM_COLD Flash Block Erase + Flash Block Write Time – – 200 ms Document Number: 001-43084 Rev. *Q Page 25 of 39 CY8C21345 CY8C22345 CY8C22545 AC I2C Specifications Table 28 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, and 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 28. AC Characteristics of the I2C SDA and SCL Pins for Vdd 3.0 V Symbol Standard Mode Description Fast Mode Units Min Max Min Max 0 100 0 400 kHz FSCLI2C SCL Clock Frequency THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. 4.0 – 0.6 – s TLOWI2C LOW Period of the SCL Clock 4.7 – 1.3 – s THIGHI2C HIGH Period of the SCL Clock 4.0 – 0.6 – s TSUSTAI2C Setup Time for a Repeated START Condition 4.7 – 0.6 – s THDDATI2C Data Hold Time 0 – 0 – s TSUDATI2C Data Setup Time 250 – 100[17] – ns TSUSTOI2C Setup Time for STOP Condition 4.0 – 0.6 – s TBUFI2C Bus Free Time Between a STOP and START Condition 4.7 – 1.3 – s TSPI2C Pulse Width of spikes are suppressed by the Input Filter – – 0 50 ns Notes Figure 7. Definition for Timing for Fast/Standard Mode on the I2C Bus I2C_SDA TSUDATI2C THDSTAI2C TSPI2C THDDATI2CTSUSTAI2C TBUFI2C I2C_SCL THIGHI2C TLOWI2C S START Condition TSUSTOI2C Sr Repeated START Condition P S STOP Condition Note 17. A Fast-Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement TSUDATI2C 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + TSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-43084 Rev. *Q Page 26 of 39 CY8C21345 CY8C22345 CY8C22545 Packaging Information Figure 8. 28-pin SOIC 51-85026 *F Figure 9. 44-pin TQFP 51-85064 *E Document Number: 001-43084 Rev. *Q Page 27 of 39 CY8C21345 CY8C22345 CY8C22545 Thermal Impedances Table 29. Thermal Impedances per Package Package Typical JA [19] 28-pin SOIC 68 °C/W 44-pin TQFP 61 °C/W Solder Reflow Specifications Table 30 shows the solder reflow temperature limits that must not be exceeded. Table 30. Solder Reflow Specifications Package Maximum Peak Temperature (TC) Maximum Time above TC – 5 °C 28-pin SOIC 260 °C 30 seconds 44-pin TQFP 260 °C 30 seconds Ordering Information The following table lists the key package features and ordering codes of this PSoC device family. 4 28-pin SOIC (Tape and Reel) CY8C21345-24SXIT 8 512B 28-pin SOIC CY8C22345-24SXI 16 1K XRES Pin –40 °C to +85 °C Analog Outputs 512B Analog Inputs 8 Digital I/O Pins Digital Blocks (Rows of 4) CY8C21345-24SXI Analog Blocks (Columns of 3) Temperature Range 28-pin SOIC Ordering Code RAM (Bytes) Package Flash (Kbytes) Table 31. PSoC Device Family Key Features and Ordering Information 6 24 24[18] 0 Y –40 °C to +85 °C 4 6 24 24[18] 0 Y –40 °C to +85 °C 8 6 24 24[18] 0 Y 28-pin SOIC (Tape and Reel) CY8C22345-24SXIT 16 1K –40 °C to +85 °C 8 6 24 24[18] 0 Y 44-pin TQFP CY8C22545-24AXI 16 1K –40 °C to +85 C 8 6 38 38[18] 0 Y 38 [18] 0 Y 44-pin TQFP (Tape and Reel) CY8C22545-24AXIT 16 1K –40 °C to +85 C 8 6 38 Ordering Code Definitions CY 8 C 2x xxx-SPxx Package Type: PX = PDIP Pb-free SX = SOIC Pb-free PVX = SSOP Pb-free LFX/LTX = QFN Pb-free AX = TQFP Pb-free Thermal Rating: C = Commercial I = Industrial E = Extended CPU Speed: 24 MHz Part Number Family Code (21, 22) Technology Code: C = CMOS Marketing Code: 8 = PSoC Company ID: CY = Cypress Note 18. Ten direct inputs. 19. TJ = TA + POWER x JA Document Number: 001-43084 Rev. *Q Page 28 of 39 CY8C21345 CY8C22345 CY8C22545 Acronyms Table 32 lists the acronyms that are used in this document. Table 32. Acronyms Used in this Datasheet Acronym AC Description Acronym Description alternating current MAC multiply-accumulate ADC analog-to-digital converter MCU microcontroller unit API application programming interface MIPS million instructions per second CMOS complementary metal oxide semiconductor PCB printed circuit board CPU central processing unit PGA programmable gain amplifier CRC cyclic redundancy check PLL phase-locked loop CSD CapSense sigma delta POR power on reset CT continuous time PPOR precision power on reset DAC digital-to-analog converter PRS pseudo-random sequence DC direct current PSoC® Programmable System-on-Chip DNL differential nonlinearity PWM pulse width modulator ECO external crystal oscillator QFN quad flat no leads EEPROM electrically erasable programmable read-only memory RTC real time clock FSK frequency-shift keying SAR successive approximation GPIO general-purpose I/O SC switched capacitor I/O input/output SLIMO slow IMO ICE in-circuit emulator SOIC small-outline integrated circuit IDE integrated development environment SPI™ serial peripheral interface IDAC current DAC SRAM static random access memory ILO internal low speed oscillator SROM supervisory read only memory IMO internal main oscillator SSOP shrink small-outline package INL integral nonlinearity TQFP thin quad flat pack IrDA infrared data association UART universal asynchronous receiver / transmitter ISSP in-system serial programming USB universal serial bus LPC low power comparator WDT watchdog timer LSB least-significant bit XRES external reset LVD low voltage detect Reference Documents CY8C22x45 and CY8C21345 PSoC® Programmable System-on-Chip™ Technical Reference Manual (TRM) (001-48461) Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459) Understanding Datasheet Jitter Specifications for Cypress Timing Products Document Number: 001-43084 Rev. *Q Page 29 of 39 CY8C21345 CY8C22345 CY8C22545 Document Conventions Units of Measure Table 33 lists the units of measures. Table 33. Units of Measure Symbol Unit of Measure Symbol Unit of Measure kB 1024 bytes mV millivolts C degree Celsius nA nanoampere kilohertz ns nanosecond kHz k LSB MHz kilohm W ohm least significant bit % percent megahertz pF picofarad microampere ps picosecond µs microsecond sps samples per second µV microvolt pA pikoampere V volts µA mA milliampere mm millimeter µW microwatts ms millisecond W watt Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals. Glossary active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. analog-to-digital (ADC) A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. API (Application Programming Interface) A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. bandwidth 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. Document Number: 001-43084 Rev. *Q Page 30 of 39 CY8C21345 CY8C22345 CY8C22545 Glossary (continued) bias 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler A program that translates a high level language, such as C, into machine language. configuration space In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. debugger A hardware and software system that allows the user to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition. digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. digital-to-analog (DAC) A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC) converter performs the reverse operation. Document Number: 001-43084 Rev. *Q Page 31 of 39 CY8C21345 CY8C22345 CY8C22545 Glossary (continued) duty cycle The relationship of a clock period high time to its low time, expressed as a percent. emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (XRES) An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. flash An electrically programmable and erasable, non-volatile technology that provides users with the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is off. Flash block The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. frequency The number of cycles or events per unit of time, for a periodic function. gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ICE The in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (ISR) A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. low-voltage detect (LVD) A circuit that senses Vdd and provides an interrupt to the system when Vdd falls below a selected threshold. M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. Document Number: 001-43084 Rev. *Q Page 32 of 39 CY8C21345 CY8C22345 CY8C22545 Glossary (continued) microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal The reference to a circuit containing both analog and digital techniques and components. modulator A device that imposes a signal on a carrier. noise 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. oscillator A circuit that may be crystal controlled and is used to generate a clock frequency. parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (PLL) An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. port A group of pins, usually eight. power on reset (POR) A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware reset. PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark of Cypress. PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. register A storage device with a specific capacity, such as a bit or byte. reset A means of bringing a system back to a know state. See hardware reset and software reset. ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. serial 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. Document Number: 001-43084 Rev. *Q Page 33 of 39 CY8C21345 CY8C22345 CY8C22545 Glossary (continued) shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. SRAM An acronym for static random access memory. A memory device allowing users to store and retrieve data at a high rate of speed. The term static is used because, after a value has been loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. stop bit A signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. VDD A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V. VSS A name for a power net meaning "voltage source." The most negative power supply signal. watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. Document Number: 001-43084 Rev. *Q Page 34 of 39 CY8C21345 CY8C22345 CY8C22545 Appendix: Silicon Errata for the PSoC® CY8C21x45, CY8C22x45 Product Family This section describes the errata for the CY8C21x45, CY8C22x45 family of PSoC devices. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number Device Characteristics CY8C21345 All Variants CY8C21645 All Variants CY8C22045 All Variants CY8C22345 All Variants CY8C22545 All Variants CY8C22645 All Variants CY8C21x45, CY8C22x45 Qualification Status Product Status: In Production Errata Summary The following table defines the errata applicable for this PSoC family device. Items Part Number Silicon Revision Fix Status 1. Free Running Nonstop Reading All CY8C21x45, CY8C22x45 cause 7 LSB Pseudo Code Variation devices affected in SAR10ADC All Silicon fix not planned. Use workaround. 2. Internal Main Oscillator (IMO) All CY8C21x45, CY8C22x45 Tolerance Deviation at Temperature devices affected Extremes All Silicon fix not planned. Use workaround. 1. Free Running Nonstop Reading cause 7 LSB Pseudo Code Variation in SAR10ADC ■ Problem Definition In free running mode, there can be a variation of up to 7 LSB in the digital output of SAR10 ADC. ■ Parameters Affected Code Variation. This is not a specified parameter. It is defined as the number of unique output codes generated by the ADC for a given constant input voltage, in addition to the correct code. For example, for an input voltage of 2.000 V, the expected code is 190hex and the ADC generates three codes: 191hex, 190hex, and 192hex. The code variation is 2 LSB. ■ Trigger Condition(S) SAR10 ADC is configured in the free running mode. ■ Scope of Impact Inaccurate output is possible. ■ Workaround This issue can be averted by using one or both of the following workarounds. Consult a Cypress representative for additional assistance. ❐ Use the averaging technique. That is, take multiple samples of the input, and use a digital averaging filter. ❐ Disable the free running mode before reading data out, and enable the free running mode after completing the read operation. ■ Fix Status No silicon fix is planned. Document Number: 001-43084 Rev. *Q Page 35 of 39 CY8C21345 CY8C22345 CY8C22545 2. Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extremes ■ Problem Definition Asynchronous Digital Communications Interfaces may fail framing beyond 0 to 70 °C. This problem does not affect end-product usage between 0 and 70 °C. ■ Parameters Affected The IMO frequency tolerance. The worst case deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%. ■ Trigger Condiiton(S) The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the datasheet limit of ±2.5% when operated beyond the temperature range of 0 to +70 °C. ■ Scope of Impact This problem may affect UART, IrDA, and FSK implementations. ■ Workaround Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface. ■ Fix Status The cause of this problem and its solution has been identified. No silicon fix is planned to correct the deficiency in silicon. Document Number: 001-43084 Rev. *Q Page 36 of 39 CY8C21345 CY8C22345 CY8C22545 Document History Page Document Title: CY8C21345, CY8C22345, CY8C22545, PSoC® Programmable System-on-Chip Document Number: 001-43084 Revision ECN Orig. of Change Submission Date ** 2251907 PMP / AESA See ECN New data sheet. *A 2506377 EIJ / AESA See ECN Changed data sheet status to “Preliminary”. Changed part numbers to CY8C22x45. Updated data sheet template. Added 56-Pin OCD information. Added: “You must put filters on intended ADC input channels for anti-aliasing. This ensures that any out-of-band content is not folded into the Input Signal Band." To Section Analog System on page 4. Corrected Minimum Electro Static Discharge Voltage in Table 7 on page 14. *B 2558750 PMP / AESA 08/28/2008 Updated Features on page 1, PSoC Core on page 3, Analog System on page 4. Changed DBB to DBC, and DCB to DCC in Register Tables Table 5 on page 11 and Table 6 on page 12. Removed INL at 8 bit reference in Table 14 on page 18. Changed IDD3 value Table 16 on page 19 Typ:3.3 mA, Max 6 mA Added “3.0 V < Vdd < 3.6 V and -40C < TA < 85C, IMO can guarantee 5% accuracy only” to Table 19 on page 21. Updated data sheet template. *C 2606793 NUQ / AESA 11/19/2008 Updated data sheet status to “Final”. Updated block diagram on page 1. Removed CY8C22045 56-Pin OCD information. Added part numbers CY8C21345, CY8C22345, and CY8C22545. For more details, see CDT 31271. *D 2615697 PMP / AESA 12/03/2008 Confirmed CY8C22345 and CY8C21345 have same pinout on page 8. Confirmed that IMO has 5% accuracy in Table 19 on page 21. *E 2631733 PMP / PYRS 01/07/2009 Updated Table 16. SAR10 ADC DC Specifications and Table 29 AC Programming Specifications. Title changed to “CY8C21345, CY8C22345, CY8C22545 PSoC® Programmable System-on-Chip™” *F 2648800 JHU / AESA 01/28/2009 Updated INL, DNL information in Table 14 on page 18, Development Tools on page 6, and TDSCLK parameter in Table 27 on page 25. *G 2658078 HMI / AESA 02/11/2009 Updated section Features on page 1. *H 2667311 JHU / AESA 03/16/2009 Added parameter “F32KU” and added Min% and Max % to parameter “FIMO6” in Table 19 on page 21, according to updated SLIMO spec. *I 2748976 JZHU / PYRS 08/06/2009 Updated F32K1 max rating in Table 19 on page 21. *J 2786560 JZHU 10/23/2009 Added DCILO, TERASEALL, TPROGRAM_HOT, TPROGRAM_COLD, SRPOWERUP, IOH, and IOL parameters. Added Tape and Reel parts in Ordering Information table *K 2901653 NJF 03/30/2010 Updated PSoC Designer Software Subsystems. Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings Modified Note 6 on page 17. Added FOUT48M parameter in 5 V and 3.3 V AC Chip-Level Specifications. Removed AC Analog Mux Bus Specifications. Updated Ordering Code Definitions. Updated links in Sales, Solutions, and Legal Information. *L 3114978 NJF 12/19/10 Document Number: 001-43084 Rev. *Q Description of Change Added DC I2C Specifications. Added Tjit_IMO specification, removed existing jitter specifications. Updated DC Programming Specifications. Updated AC Digital Block Specifications. Updated I2C Timing Diagram. Added Solder Reflow Peak Temperature table. Updated Units of Measure, Acronyms, Glossary, and References sections. Page 37 of 39 CY8C21345 CY8C22345 CY8C22545 Document History Page (continued) Document Title: CY8C21345, CY8C22345, CY8C22545, PSoC® Programmable System-on-Chip Document Number: 001-43084 Revision ECN Orig. of Change Submission Date Description of Change *M 3231771 BOBH / ECU 04/18/11 Updated analog inputs column in Table 31 on page 28 and included reference to Note 18. Updated the following sections: Getting Started, Development Tools, and Designing with PSoC Designer as all the System level designs have been de-emphasized. Updated Table 30, “Solder Reflow Specifications,” on page 28. Updated package diagrams: 51-85026 to *F 51-85064 to *E *N 3578757 PMAD 04/11/2012 Removed reference to AN2012 as the document is in obsolete status. Updated template. No technical updates. Completing sunset review. *O 3598230 LURE / XZNG 04/24/2012 Changed the PWM description string from “8- to 32-bit” to “8- and 16-bit”. *P 3915358 SAMP 02/27/2013 Updated Electrical Specifications (Updated DC Electrical Characteristics (Updated DC GPIO Specifications (Updated Table 10 (Updated Notes for VOH and VOL parameters)))). *Q 3959550 SAMP 04/09/2013 Added Appendix: Silicon Errata for the PSoC® CY8C21x45, CY8C22x45 Product Family. Document Number: 001-43084 Rev. *Q Page 38 of 39 CY8C21345 CY8C22345 CY8C22545 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2013. The information contained herein is subject to change without notice. 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Document Number: 001-43084 Rev. *Q Revised April 9, 2013 Page 39 of 39 PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.