FEATURES Single power supply 750 ps propagation delay input to output 100 ps propagation delay dispersion Differential PECL compatible outputs Differential latch control Internal latch pull-up resistors Power supply rejection greater than 70 dB 750 ps minimum pulse width Equivalent input rise time bandwidth > 750 MHz Typical output rise/fall of 500 ps Programmable Hysteresis APPLICATIONS Automatic test equipment High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero crossing detectors Line receivers and signal restoration Clock drivers FUNCTIONAL BLOCK DIAGRAM NONINVERTING INPUT INVERTING INPUT Q OUTPUT ADCMP551/ ADCMP552/ ADCMP553 Q OUTPUT LATCH ENABLE INPUT LATCH ENABLE INPUT 04722-0-001 Preliminary Technical Data Single Supply High Speed PECL Comparators ADCMP551/ADCMP552/ADCMP553 Figure 1. GENERAL DESCRIPTION The ADCMP551/ADCMP552/ADCMP553 are single supply, high speed comparators fabricated on Analog Devices’ proprietary XFCB process. The devices feature a 750 ps propagation delay with less than 150 ps overdrive dispersion. Dispersion, a measure of the difference in propagation delay under differing overdrive conditions, is a particularly important characteristic of high speed comparators. A separate programmable hysteresis pin is available on the ADCMP552. A differential input stage permits consistent propagation delay with a common-mode range from –0.2 V to VCCI – 2.0 V. Outputs are complementary digital signals are fully compatible with PECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 Ω to VCCO − 2 V. A latch input is included and permits tracking, track-and-hold, or sample-and-hold modes of operation. The latch input pins contain internal pullups that set the latch in tracking mode when left open. The ADCMP551/ADCMP552/ADCMP553 are specified over the –40°C to +85°C industrial temperature range. The ADCMP551 is available in a 16-lead QSOP package; the ADCMP552 is available in a 20-lead QSOP package; and the ADCMP553 is available in an 8-lead MSOP package. Rev. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADCMP551/ADCMP552/ADCMP553 Preliminary Technical Data TABLE OF CONTENTS Specifications..................................................................................... 3 Clock Timing Recovery............................................................. 11 Absolute Maximum Ratings............................................................ 5 Optimizing High Speed Performance ..................................... 11 Thermal Considerations.............................................................. 5 Comparator Propagation Delay Dispersion ........................... 11 ESD Caution.................................................................................. 5 Comparator Hysteresis .............................................................. 12 Pin Configuration and Function Descriptions............................. 6 Minimum Input Slew Rate Requirement ................................ 12 Typical Performance Characteristics ............................................. 8 Typical Application Circuits ......................................................... 13 Timing Information ....................................................................... 10 Outline Dimensions ....................................................................... 14 Application Information................................................................ 11 Ordering Guide .......................................................................... 14 REVISION HISTORY Revision PrA: Preliminary Version Rev. PrB | Page 2 of 14 Preliminary Technical Data ADCMP551/ADCMP552/ADCMP553 SPECIFICATIONS VCCI = 3.3 V, VCCO = 3.3 V, TA = 25°C, unless otherwise noted. Table 1. ADCMP551/ADCMP552/ADCMP553 Electrical Characteristics Parameter DC INPUT CHARACTERISTICS Input Voltage Range Input Differential Voltage Range Input Offset Voltage Input Offset Voltage Channel Matching Offset Voltage Tempco Input Bias Current Input Bias Current Tempco Input Offset Current Input Capacitance Input Resistance, Differential Mode Input Resistance, Common Mode Active Gain Common-Mode Rejection Ratio Hysteresis LATCH ENABLE CHARACTERISTICS Latch Enable Voltage Range Latch Enable Differential Voltage Range Latch Enable Input High Current Latch Enable Input Low Current LE Voltage, Open LE Voltage, Open Latch Setup Time Latch Hold Time Latch to Output Delay Latch Minimum Pulse Width DC OUTPUT CHARACTERISTICS Output Voltage—High Level Output Voltage—Low Level Rise Time Fall Time AC PERFORMANCE Propagation Delay Propagation Delay Tempco Prop Delay Skew—Rising Transition to Falling Transition Within Device Propagation Delay Skew—Channel-to-Channel Overdrive Dispersion Overdrive Dispersion Slew Rate Dispersion Pulse Width Dispersion Duty Cycle Dispersion Common-Mode Voltage Dispersion Symbol Conditions Min VOS −IN = 0 V, +IN = 0 V −0.2 −3 −10.0 ∆VOS/dT IIN −IN = −0.2 V, +IN = +1.3 V −10.0 −3.0 CIN AV CMRR VCM = −0.2 V to +1.3 V RHYS = ∞ Typ ±3.0 ±3.0 10.0 ±7 0.5 ±1.0 1.0 100 600 60 70 ±0.5 VCCI – 1.8 0.4 −150 −150 VCCI – 0.15 VCCI/2 – 0.075 Max Unit VCCI – 2.0 +3 +10.0 V V mV mV µV/°C µA nA/°C µA pF kΩ kΩ dB dB mV +10.0 +3.0 VCCI – 0.8 1.0 +150 +150 VCCI VCCI/2 + 0.075 V V µA µA V V ps ps ps ps VCCO − 0.81 VCCO − 1.54 500 500 V V ps ps tS tH tPLOH, tPLOL tPL @ VCCI – 0.8 V @ VCCI – 1.8 V Latch inputs not connected Latch inputs not connected VOD = 250 mV VOD = 250 mV VOD = 250 mV VOD = 250 mV VOH VOL tR tF PECL 50 Ω to VDD − 2.0 V PECL 50 Ω to VDD − 2.0 V 10% to 90% 10% to 90% tPD VOD = 1 V VOD = 20 mV VOD = 1 V VOD = 1 V 750 850 0.5 100 ps ps ps/°C ps VOD = 1 V 100 ps 50 mV ≤ VOD ≤ 100 mV 100 mV ≤ VOD ≤ 1.5 V 0.4 V/ns ≤ SR ≤ 1.33 V/ns 750 ps ≤ PW ≤ 10 ns 33 MHz, 1 V/ns, VCM = 0.5 V 1 V swing, 0.3 V ≤ VCM ≤ 0.8 V 100 100 100 50 50 100 ps ps ps ps ps ps ∆tPD/dT Rev. PrB | Page 3 of 14 500 500 750 750 VCCO − 1.05 VCCO − 1.95 ADCMP551/ADCMP552/ADCMP553 Parameter AC PERFORMANCE (continued) Equivalent Input Rise Time Bandwidth1 Maximum Toggle Rate Minimum Pulse Width Unit-to-Unit Propagation Delay Skew POWER SUPPLY (ADCMP551/ADCMP552) Input Supply Current Output Supply Current Output Supply Current Input Supply Voltage Output Supply Voltage Positive Supply Differential Power Dissipation Power Dissipation DC Power Supply Rejection Ratio—VCCI DC Power Supply Rejection Ratio—VCCO POWER SUPPLY (ADCMP553) Positive Supply Current Positive Supply Current Positive Supply Voltage Power Dissipation Power Dissipation DC Power Supply Rejection Ratio — VCC HYSTERESIS (ADCMP552 Only) Programmable Hysteresis 1 Preliminary Technical Data Symbol Conditions BWEQ 0 V to 1 V swing, 2 V/ns >50% output swing ∆tPD < 50 ps 750 650 750 100 @ 3.3 V @ 3.3 V without load @ 3.3 V with load Dual Dual 12.5 6 62 3.3 3.3 PWMIN IVCCI IVCCO VCCI VCCO VCCO − VCCI PD Min 3.135 3.135 –0.2 Dual, without load Dual, with load 55 115 70 70 @ 3.3 V without load @ 3.3 V with load Dual Dual, without load Dual, with load 9 35 3.3 30 60 70 PSRRVCCI PSRRVCCO IVCC VCC PD Typ 3.135 PSRRVCC 0 Max Unit MHz MHz ps ps 16 9 70 5.25 5.25 +2.3 70 140 mA mA mA V V V mW mW dB dB 11 42 5.25 40 75 mA mA V mW mW dB 40 mV Equivalent input rise time bandwidth assumes a first order input response and is calculated by the following formula: BWEQ = .22/√(trCOMP2-trIN2), where trIN is the 20/80 input transition time applied to the comparator and trCOMP is the effective transition time as digitized by the comparator input. Rev. PrB | Page 4 of 14 Preliminary Technical Data ADCMP551/ADCMP552/ADCMP553 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltages Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Ground Voltage Differential Input Voltages Input Common-Mode Voltage Differential Input Voltage Input Voltage, Latch Controls Output Output Current Temperature Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Rating −0.5 V to +6.0 V −0.5 V to +6.0 V −0.5 V to +0.5 V −0.5 V to +3.5 V −4.0 V to +4.0 V −0.5 V to +5.5 V 30 mA −40°C to +85°C 125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CONSIDERATIONS The ADCMP551 16-lead QSOP package has a θJA (junction-toambient thermal resistance) of TBD°C/W in still air. The ADCMP552 20-lead QSOP package has a θJA (junction-toambient thermal resistance) of TBD°C/W in still air. The ADCMP553 8-lead MSOP package has a θJA (junction-toambient thermal resistance) of TBD°C/W in still air. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrB | Page 5 of 14 ADCMP551/ADCMP552/ADCMP553 Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 20 VCCO VCCO 1 VCCO 3 LEA 4 LEA 5 ADCMP551 TOP VIEW (Not to Scale) QB 14 VCCO 13 LEB 12 LEB VCCI 6 11 AGND –INA 7 10 –INB +INA 8 9 +INB 19 QB QA 3 Figure 2. ADCMP551 16-Lead QSOP Pin Configuration 18 QB VCCO 4 ADCMP552 LEA 5 TOP VIEW (Not to Scale) LEA 1 17 VCCO 16 LEB LEA 6 15 LEB VCCI 7 14 AGND –INA 8 13 –INB +INA 9 12 +INB HYSA 10 11 HYSB LEA 2 ADCMP553 +INA 3 TOP VIEW (Not to Scale) –INA 4 8 AGND 7 VCC 6 QA 5 QA 04722-0-004 15 QA 2 QB 04722-0-003 16 04722-0-002 QA 1 QA 2 Figure 3. ADCMP552 20-Lead QSOP Pin Configuration Figure 4. ADCMP553 8-Lead MSOP Pin Configuration Table 3. ADCMP551/ADCMP552/ADCMP553 Pin Function Descriptions ADCMP551 3, 14 1 Pin No. ADCMP552 1, 4, 17, 20 2 2 6 Mnemonic VCCO QA 3 5 QA 4 5 2 LEA 5 6 1 LEA 6 7 7 8 4 VCCI −INA 8 9 3 +INA 9 10 11 12 HYSA HYSB +INB 10 13 −INB 11 14 ADCMP553 8 AGND Function Logic Supply Terminal. One of Two Complementary Outputs for Channel A. QA is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEA for more information. One of Two Complementary Outputs for Channel A. QA is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEA for more information. One of Two Complementary Outputs for Channel A Latch Enable. In the compare mode (logic high), the output tracks changes at the input of the comparator. In the latch mode (logic low), the output reflects the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. One of Two Complementary Outputs for Channel A Latch Enable. In the compare mode (logic high), the output tracks changes at the input of the comparator. In the latch mode (logic low), the output reflects the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. Input Supply Terminal. Inverting Analog Input of the Differential Input Stage for Channel A. The inverting A input must be driven in conjunction with the noninverting A input. Noninverting Analog Input of the Differential Input Stage for Channel A. The noninverting A input must be driven in conjunction with the inverting A input. Programmable Hysteresis. Programmable Hysteresis. Noninverting Analog Input of the Differential Input Stage for Channel B. The noninverting B input must be driven in conjunction with the inverting B input. Inverting Analog Input of the Differential Input Stage for Channel B. The inverting B input must be driven in conjunction with the noninverting B input. Analog Ground. Rev. PrB | Page 6 of 14 Preliminary Technical Data ADCMP551/ADCMP552/ADCMP553 ADCMP551 12 Pin No. ADCMP552 15 13 16 LEB 15 18 QB 16 19 QB ADCMP553 7 Mnemonic LEB VCC Function One of Two Complementary Inputs for Channel B Latch Enable. In the compare mode (logic low), the output tracks changes at the input of the comparator. In the latch mode (logic high), the output reflects the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven in conjunction with LEB. One of Two Complementary Inputs for Channel B Latch Enable. In the compare mode (logic low), the output tracks changes at the input of the comparator. In the latch mode (logic high), the output reflects the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven in conjunction with LEB. One of Two Complementary Outputs for Channel B. QB is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEB for more information. One of Two Complementary Outputs for Channel B. QB is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEB for more information. Positive Supply Terminal. Rev. PrB | Page 7 of 14 ADCMP551/ADCMP552/ADCMP553 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS –000 –000 –000 –000 –000 ALL CAPS (Initial caps) ALL CAPS (Initial caps) VCCI = 3.3 V, VCCO = 3.3 V, TA = 25°C, unless otherwise noted. TBD –000 –000 –000 –000 –000 –000 –000 –000 ALL CAPS (Initial caps) –000 –000 –000 –000 –000 –000 –000 TBD –000 –000 –000 –000 ALL CAPS (Initial caps) –000 –000 –000 –000 –000 –000 ALL CAPS (Initial caps) ALL CAPS (Initial caps) –000 TBD TBD –000 –000 –000 ALL CAPS (Initial caps) –000 –000 TBD –000 –000 –000 –000 –000 Figure 9. Hysteresis vs. ∆Latch Figure 6. Input Offset Voltage vs. Temperature –000 –000 –000 ALL CAPS (Initial caps) –000 –000 –000 –000 –000 Figure 8. Input Bias Current vs. Temperature ALL CAPS (Initial caps) ALL CAPS (Initial caps) Figure 5. Input Bias Current vs. Input Voltage –000 TBD –000 –000 –000 ALL CAPS (Initial caps) –000 –000 –000 –000 –000 –000 ALL CAPS (Initial caps) Figure 10. Fall Time vs. Temperature Figure 7. Rise Time vs. Temperature Rev. PrB | Page 8 of 14 –000 ADCMP551/ADCMP552/ADCMP553 –000 –000 –000 –000 ALL CAPS (Initial caps) ALL CAPS (Initial caps) Preliminary Technical Data TBD –000 –000 –000 –000 –000 –000 –000 –000 ALL CAPS (Initial caps) –000 –000 –000 –000 –000 –000 –000 TBD –000 –000 –000 –000 ALL CAPS (Initial caps) –000 Figure 14. Propagation Delay vs. Common-Mode Voltage ALL CAPS (Initial caps) ALL CAPS (Initial caps) Figure 11. Propagation Delay vs. Temperature –000 TBD –000 –000 –000 –000 –000 –000 –000 ALL CAPS (Initial caps) –000 Figure 12. Propagation Delay vs. Overdrive Voltage –000 –000 TBD –000 –000 –000 –000 –000 –000 ALL CAPS (Initial caps) –000 –000 –000 –000 –000 ALL CAPS (Initial caps) Figure 15. Propagation Delay Error vs. Pulse Width –000 ALL CAPS (Initial caps) TBD –000 –000 Figure 13. Rise and Fall of Outputs vs. Time Rev. PrB | Page 9 of 14 –000 ADCMP551/ADCMP552/ADCMP553 Preliminary Technical Data TIMING INFORMATION LATCH ENABLE 50% LATCH ENABLE tS tPL tH DIFFERENTIAL INPUT VOLTAGE VIN VREF ± VOS VOD tPDL tPLOH Q OUTPUT 50% tF tPDH tPLOL tR 04687-0-004 50% Q OUTPUT Figure 16. System Timing Diagram Figure 16 shows the compare and latch features of the ADCMP55x family. Table 4 describes the terms in the diagram. Table 4. Timing Descriptions Symbol tPDH Timing Input to Output High Delay tPDL Input to Output Low Delay tPLOH Latch Enable to Output High Delay tPLOL Latch Enable to Output Low Delay tH Minimum Hold Time tPL tS Minimum Latch Enable Pulse Width Minimum Setup Time tR Output Rise Time tF Output Fall Time VOD Voltage Overdrive Description Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs Minimum time the latch enable signal must be high to acquire an input signal change Minimum time before the negative transition of the latch enable signal that an input signal change must be present to be acquired and held at the outputs Amount of time required to transition from a low to a high output as measured at the 20% and 80% points Amount of time required to transition from a high to a low output as measured at the 20% and 80% points Difference between the differential input and reference input voltages Rev. PrB | Page 10 of 14 Preliminary Technical Data ADCMP551/ADCMP552/ADCMP553 APPLICATION INFORMATION The ADCMP55x series of comparators are very high speed devices. Consequently, high speed design techniques must be employed to achieve the best performance. The most critical aspect of any ADCMP55x design is the use of a low impedance ground plane. A ground plane, as part of a multilayer board, is recommended for proper high speed performance. Using a continuous conductive plane over the surface of the circuit board can create this, allowing breaks in the plane only for necessary signal paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused by ground bounce. A proper ground plane also minimizes the effects of stray capacitance on the circuit board. It is also important to provide bypass capacitors for the power supply in a high speed application. A 1 µF electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors reduce any potential voltage ripples from the power supply. In addition, a 10 nF ceramic capacitor should be placed as close to the power supply pins as possible on the ADCMP55x to ground. These capacitors act as a charge reservoir for the device during high frequency switching. The LATCH ENABLE input is active low (latched). If the latching function is not used, the LATCH ENABLE input pins may be left open. The internal pull-ups on the latch pins set the latch to transparent mode. If the latch is to be used, valid PECL voltages are required on the inputs for proper operation. The PECL voltages should be referenced to VCCI. Occasionally, one of the two comparator stages within the ADCMP551/ADCMP552 is not used. The inputs of the unused comparator should not be allowed to float. The high internal gain may cause the output to oscillate (possibly affecting the comparator that is being used) unless the output is forced into a fixed state. This is easily accomplished by ensuring that the two inputs are at least one diode drop apart, while also appropriately connecting the LATCH ENABLE and LATCH ENABLE inputs as described previously. The best performance is achieved with the use of proper PECL terminations. The open-emitter outputs of the ADCMP55x are designed to be terminated through 50 Ω resistors to VCCO − 2.0 V or any other equivalent PECL termination. If high speed PECL signals must be routed more than a centimeter, microstrip or stripline techniques may be required to ensure proper transition times and prevent output ringing. CLOCK TIMING RECOVERY Comparators are often used in digital systems to recover clock timing signals. High speed square waves transmitted over a distance, even tens of centimeters, can become distorted due to stray capacitance and inductance. Poor layout or improper termination can also cause reflections on the transmission line, further distorting the signal waveform. A high speed comparator can be used to recover the distorted waveform while maintaining a minimum of delay. OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator amplifier, proper design and layout techniques should be used to ensure optimal performance from the ADCMP55x. The performance limits of high speed circuitry can easily be a result of stray capacitance, improper ground impedance, or other layout issues. Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the ADCMP55x. Source resistance in combination with equivalent input capacitance can cause a lagged response at the input, thus delaying the output. The input capacitance of the ADCMP55x, in combination with stray capacitance from an input pin to ground, could result in several picofarads of equivalent capacitance. A combination of 3 kΩ source resistance and 5 pF input capacitance yields a time constant of 15 ns, which is significantly slower than the 750 ps capability of the ADCMP55x. Source impedances should be significantly less than 100 Ω for best performance. Sockets should be avoided due to stray capacitance and inductance. If proper high speed techniques are used, the ADCMP55x should be free from oscillation when the comparator input signal passes through the switching threshold. COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP55x has been specifically designed to reduce propagation delay dispersion over an input overdrive range of 100 mV to 1 V. Propagation delay overdrive dispersion is the change in propagation delay that results from a change in the degree of overdrive (how far the switching point is exceeded by the input). The overall result is a higher degree of timing accuracy since the ADCMP55x is far less sensitive to input variations than most comparator designs. Rev. PrB | Page 11 of 14 ADCMP551/ADCMP552/ADCMP553 Preliminary Technical Data Propagation delay dispersion is an important specification in critical timing applications such as ATE, bench instruments, and nuclear instrumentation. Overdrive dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (Figure 17). For the ADCMP55x, overdrive dispersion is typically 100 ps as the overdrive is changed from 100 mV to 1 V. This specification applies for both positive and negative overdrive since the ADCMP55x has equal delays for positive- and negative-going inputs. introducing a differential voltage between the LATCH ENABLE and LATCH ENABLE. inputs (Figure 23). +VH 2 –VH 2 0V INPUT 1 1.5V OVERDRIVE INPUT VOLTAGE 0 VREF ± VOS OUTPUT Q OUTPUT Figure 18. Comparator Hysteresis Transfer Function 04687-0-005 DISPERSION 04687-0-006 20mV OVERDRIVE –000 COMPARATOR HYSTERESIS The addition of hysteresis to a comparator is often useful in a noisy environment, or where it is not desirable for the comparator to toggle between states when the input signal is at the switching threshold. The transfer function for a comparator with hysteresis is shown in Figure 18. If the input voltage approaches the threshold from the negative direction, the comparator switches from a 0 to a 1 when the input crosses +VH/2. The new switching threshold becomes −VH/2. The comparator remains in a 1 state until the −VH/2 threshold is crossed coming from the positive direction. In this manner, noise centered on 0 V input does not cause the comparator to switch states unless it exceeds the region bounded by ±VH/2. Positive feedback from the output to the input is often used to produce hysteresis in a comparator (Figure 22). The major problem with this approach is that the amount of hysteresis varies with the output logic levels, resulting in a hysteresis that is not symmetrical around zero. In the ADCMP552, hysteresis is generated through the programmable hysteresis pin. A resistor from the HYS pin to VCCI creates a current into the part that is used to generate hysteresis. Hysteresis generated in this manner is independent of output swing and is symmetrical around the trip point. The hysteresis versus resistance curve is shown in Figure 19. ALL CAPS (Initial caps) Figure 17. Propagation Delay Dispersion –000 TBD –000 –000 –000 –000 –000 –000 –000 ALL CAPS (Initial caps) –000 Figure 19. Comparator Hysteresis Transfer Function MINIMUM INPUT SLEW RATE REQUIREMENT As for all high speed comparators, a minimum slew rate must be met to ensure that the device does not oscillate when the input crosses the threshold. This oscillation is due in part to the high input bandwidth of the comparator and the parasitics of the package. Analog Devices recommends a slew rate of 1 V/µs or faster to ensure a clean output transition. If slew rates less than 1 V/µs are used, hysteresis should be added to reduce the oscillation. Another method to implement hysteresis is generated by Rev. PrB | Page 12 of 14 Preliminary Technical Data ADCMP551/ADCMP552/ADCMP553 TYPICAL APPLICATION CIRCUITS ALL RESISTORS 50Ω VIN + ADCMP551/ ADCMP552/ ADCMP553 – –VREF + ADCMP551/ ADCMP552/ ADCMP553 – R2 VCCO – 2V ALL RESISTORS 50Ω Figure 20. High Speed Sampling Circuits Figure 22. Hysteresis Using Positive Feedback + ADCMP551/ ADCMP552/ ADCMP553 – VIN OUTPUTS HYSTERESIS VOLTAGE OUTPUTS VCCO – 2V 450Ω ALL RESISTORS 50Ω UNLESS OTHERWISE NOTED Figure 23. Hysteresis Using Latch Enable Input LATCH ENABLE INPUTS VCCO – 2V ALL RESISTORS 50Ω 04722-0-010 +VREF R1 04722-0-009 VCCO – 2V OUTPUTS 04722-0-011 VREF LATCH ENABLE INPUTS + ADCMP551/ ADCMP552/ ADCMP553 – VIN OUTPUTS 04722-0-012 VREF + ADCMP551/ ADCMP552/ ADCMP553 – VIN Figure 21. High Speed Window Comparator + ADCMP551/ ADCMP552/ ADCMP553 – 100Ω 50Ω 50Ω 50Ω 50Ω 100Ω (VCCO – 2V) × 2 Figure 24. How to Interface a PECL Output to an Instrument with a 50 Ω to Ground Input Rev. PrB | Page 13 of 14 04722-0-013 VIN ADCMP551/ADCMP552/ADCMP553 Preliminary Technical Data OUTLINE DIMENSIONS 0.341 BSC 20 11 0.154 BSC 1 0.236 BSC 10 PIN 1 0.065 0.049 0.010 0.004 0.069 0.053 0.025 BSC 0.012 0.008 COPLANARITY 0.004 SEATING PLANE 8° 0° 0.010 0.006 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137AD Figure 25. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20) Dimensions shown in inches 0.193 BSC 3.00 BSC 8 9 16 0.154 BSC 1 4.90 BSC 4 0.236 BSC 8 5 3.00 BSC PIN 1 0.65 BSC PIN 1 0.069 0.053 0.065 0.049 0.010 0.025 0.004 BSC COPLANARITY 0.004 0.012 0.008 SEATING PLANE 1.10 MAX 0.15 0.00 0.010 0.006 8° 0° 0.38 0.22 COPLANARITY 0.10 0.050 0.016 0.23 0.08 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA COMPLIANT TO JEDEC STANDARDS MO-137AB Figure 27. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Figure 26. 16-Lead Shrink Small Outline Package[QSOP] (RQ-16) Dimensions shown in inches ORDERING GUIDE Model ADCMP551BRQ ADCMP552BRQ ADCMP553BRM Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead QSOP 20-Lead QSOP 8-Lead MSOP © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04687–0–7/04(PrB) Rev. PrB | Page 14 of 14 Package Option RQ-16 RQ-20 RM-8 0.80 0.60 0.40