Cypress CY26112ZC One-pll general purpose clock generator Datasheet

THIS SPEC IS OBSOLETE
Spec No: 38-07096
Spec Title: CY26112 One-PLL General Purpose Clock Generator
Sunset Owner: IJA
Replaced by: N/A
CY26112
One-PLL General Purpose
Clock Generator
Features
Benefits
• Integrated phase-locked loop
Internal PLL with up to 333 MHz internal operation
• Low skew, low jitter, high accuracy outputs
Meets critical timing requirements in complex system designs
• Frequency Select Pin
Dynamic frequency selection
• 3.3V Operation with 2.5 V Output Option
Enables application compatibility
• 16-TSSOP
Industry standard package saves on board space
Part Number
CY26112
Outputs
Input Frequency
Output Frequency Range
4
14.7456 MHz
2 x 3.6864 MHz, 2 x 33/66 MHz (selectable)
Logic Block Diagram
XIN
Q
OSC.
Pin Configurations
Φ
3.6864
VCO
XOUT
CY26112
16-pin TSSOP
3.6864
P
PLL
OUTPUT
MULTIPLEXER
AND
DIVIDERS
FS
XIN
VDD
1
16
XOUT
2
15
AVDD
3
14
OE
4
13
CLK4
CLK3
VSS
AVSS
5
12
N/C
VSSL
NC
6
11
VDDL
7
10
8
9
FS
LCLK2
LCLK1
33/66
33/66
OE
VDDL
VSSL
VDD
AVDD
AVSS
VSS
Output
Pin
Default Frequency
Unit
LCLK1
8
3.6864
MHz
LCLK2
9
3.6864
MHz
CLK3
14
33/66 (selectable)
MHz
CLK4
15
33/66 (selectable)
MHz
Cypress Semiconductor Corporation
Document #: 38-07096 Rev. OBS
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 02, 2004
CY26112
Summary
Name
Pin Number
Description
XIN
1
Reference Input
VDD
2
Voltage Supply
AVDD
3
Analog Voltage Supply
OE
4
Output Enable, OE = 0 three-state; OE = 1 active
AVSS
5
Analog Ground
VSSL
6
LCLK Ground
NC
7
No Connect - Reserved
LCLK1
8
3.6864 MHz Clock output 1 at VDDL level
LCLK2
9
3.6864 MHz Clock output 2 at VDDL level
FS
10
Frequency Select Pin Ð FS = 0: 33 MHz, FS = 1: 66 MHz
VDDL
11
LCLK Voltage Supply (2.5V or 3.3V)
NC
12
No Connect - Reserved
VSS
13
Ground
CLK3
14
Clock output 3-33 MHz/66 MHz
CLK4
15
Clock output 4-33 MHz/66 MHz
XOUT[1]
16
Reference Output
Absolute Maximum Conditions
Parameter
Description
Min.
Max.
Unit
Ð0.5
7.0
V
7.0
V
125
¡C
AVDD + 0.3
V
VDD
Supply Voltage
VDDL
I/O Supply Voltage
TJ
Junction Temperature
Digital Inputs
AVSS Ð 0.3
Digital Outputs referred to VDD
VSS Ð 0.3
VDD + 0.3
V
Digital Outputs referred to VDDL
VSS Ð 0.3
VDDL +0.3
V
Electro-Static Discharge
2
kV
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
3.0
3.3
3.6
V
VDDL
Operating Voltage
2.375
2.5
2.625
V
TA
Ambient Temperature
0
70
¡C
CLOAD
Max. Load Capacitance
fREF
Driven Reference Frequency
15
14.7456
pF
MHz
Note:
1. Float XOUT if XIN is externally driven.
Document #: 38-07096 Rev. OBS
Page 2 of 5
CY26112
DC Electrical Characteristics
Parameter[1]
Name
Description
Min.
Typ.
Max.
Unit
IOH
Output High Current
VOH = VDD Ð 0.5, VDD/VDDL = 3.3V
12
24
mA
IOL
Output Low Current
VOL = 0.5, VDD/VDDL = 3.3V
12
24
mA
IOH
Output High Current
VOH = VDDL Ð 0.5, VDDL = 2.5V
8
16
mA
IOL
Output Low Current
VOL = 0.5, VDDL = 2.5V
8
16
mA
VIH
Input High Voltage
CMOS levels, 70% of VDD
VIL
Input Low Voltage
CMOS levels, 30% of VDD
CIN
Input Capacitance
OE and FS Pins
IIZ
Input Leakage Current
OE and FS Pins
0.7
VDD
0.3
7
VDD
pF
µA
5
IVDD
Supply Current
AVDD/VDDCurrent
25
mA
IVDDL
Supply Current
VDDL Current (VDDL = 3.6V)
7
mA
IVDDL
Supply Current
VDDL Current (VDDL = 2.625V)
5
mA
AC Electrical Characteristics
Parameter[1]
Name
DC
Description
Min.
Typ.
Max.
Unit
Duty Cycle is defined in Figure 2; t1/t2 @ 50%
of VDD
45
50
55
%
t3
Rising Edge Slew Rate Output Clock Rise Time, 20% Ð 80% of
VDD/VDDL=3.3V
0.8
1.4
V/ns
t3
Rising Edge Slew Rate Output Clock Rise Time, 20% Ð 80% of
VDDL = 2.5V
0.6
1.2
V/ns
t4
Falling Edge Slew
Rate
Output Clock Fall Time, 80% Ð 20% of
VDD/VDDL=3.3V
0.8
1.4
V/ns
t4
Falling Edge Slew
Rate
Output Clock Fall Time, 80% Ð 20% of
VDDL = 2.5V
0.6
1.2
V/ns
t5
Skew
Delay between related outputs at rising edge
250
t9
Clock Jitter
Peak to Peak period jitter
350
ps
t10
PLL Lock Time
3
ms
ps
t1
t2
CLK
50%
50%
Figure 1. Duty Cycle Definition; DC = t2/t2\.
t3
t4
80%
CLK
20%
Figure 2. Rise and Fall Time Definitions.
Note:
2. Not 100% tested.
Document #: 38-07096 Rev. OBS
Page 3 of 5
CY26112
Test Circuit
VDD
CLK out
0.1 µF
CLOAD
OUTPUTS
AVDD
0.1 µF
GND
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY26112ZC
Z16
16-Pin TSSOP
Commercial
3.3V
Document #: 38-07096 Rev. OBS
Page 4 of 5
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY26112
Document Title: CY26112 One-PLL General Purpose Clock Generator
Document Number: 38-07096
REV.
ECN NO.
Issue Date
Orig. of Change
**
107331
08/28/01
CKN
New Data Sheet
OBS
294816
See ECN
RGL
To Obsolete the DS
Document #: 38-07096 Rev. OBS
Description of Change
Page 5 of 5
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