ON FAN8831 Sinusoidal piezoelectric actuator driver step-up dc-dc converter Datasheet

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FAN8831
Sinusoidal Piezoelectric Actuator Driver with Step-Up
DC-DC Converter
Features
Description
Step-Up DC-DC Converter
 Integrated Step-up Power Switch up to 36 V
The FAN8831 is a single-chip piezoelectric actuator
driver consisting of step-up DC-DC converter with
integrated 36 V boost switch and a full-bridge output
stage. The device is capable of driving a Piezo bidirectionally at 120 V peak-to-peak from a single 3 V
lithium cell. The step-up DC-DC converter operates in
Critical Conduction Mode (CRM) and is optimized to
work in a coupled inductor configuration to provide
output voltages in excess of 60 V. Over-voltage
protection, over-current protection and thermal
shutdown are all provided. An internal ready is used to
enable the full-bridge gate driver when step-up DC-DC
converter output voltage reaches the proper level with
hysteresis.






Wide Operating Voltage Range of 2.7 to 5.5 V
Adjustable Step-up Output Voltage
Adjustable Step-up Current Limit
Zero Current Detector (ZCD)
Internal Soft-Start
Built-in Protection Circuit
-
Over Voltage Protection (OVP)
Thermal Shutdown (TSD)
Piezo Actuator Driver
 Integrated Full-Bridge Switches (VDS=75 V)

Digitally Implemented Sine Modulator
Package Information
 Small 4.0 mm × 4.0 mm MLP
The boost voltage is set using external resistors, and
step-up current limit is programmable via the external
resistor at OCP pin.
The output H-bridge features four integrated 75 V P and
N-channel for sine wave drive of the Piezo actuator.
Applications

Piezo Actuator
Ordering Information
Part Number
Operating
Temperature Range
Package
Packing Method
FAN8831MPX
-40°C to +125°C
24-Lead, MLP
Tape & Reel
© 2014 Fairchild Semiconductor Corporation
FAN8831 • Rev. 1.0
www.fairchildsemi.com
FAN8831 — Sinusoidal Piezoelectric Actuator Drive with Step-Up DC-DC Converter
December 2014
VDRV
N1
N2
2.7 V ~5.5 V
PGND1
PGND1
VDD
SGND
ZCD
FB
COMP
LX
LX
OCP
NC
FO
FO
FAN8831
EN
EN
OUT1
M
INPUT
INPUT
OUT2
VDRV
VIN
AGND
OVP
RT
Figure 1.
NC
PGND2
ADJ
Typical Application Circuit for Piezo Actuator Driver
Internal Block Diagram
VDRV
INPUT
SINA
IAJD
ADJ
VDRV
UP/DN DAC CLOCK
AGND
SINA
PWM_A
SINB
PWM_B
CONTROL
LOGIC
OUT1
VREF
OUT2
SINB
SINE GENERATOR
OSCILLATOR
RT
PGND2
VREF
VDD
ENABLE
VOLTAGE
MONITOR
AND LOGIC
EN
SGND
FO
OVP_FB
VREADY
FAULT
[tFO=20us]
OVP
TSD
READY
VOLTAGE
REGULATOR
5V LDO
VREF
ZCD
CLAMP
TIMER
LX
COMP
S
Q
VZCD
DRIVER
FB
ZCD
VIN
PWM
OVP_FB
R
VOVP_FB
OVP
OVP
RAMP
GENERATOR
TSD
CURRENT
LIMIT
PGND1
VOVP_OVP
TSD
Figure 2.
© 2014 Fairchild Semiconductor Corporation
FAN8831 • Rev. 1.0
RLIMIT
OCP
Functional Block Diagram
www.fairchildsemi.com
2
FAN8831 — Piezoelectric Actuator Driver with Step-Up DC-DC Converter
Application Diagram
FAN8831 — Piezoelectric Actuator Driver with Step-Up DC-DC Converter
Pin Configuration
PGND1
PGND1
VDD
SGND
ZCD
FB
COMP
LX
OCP
LX
FO
NC
FAN8831
EN
OUT1
INPUT
OUT2
VDRV
VIN
AGND
OVP
RT
Figure 3.
PGND2
ADJ
NC
Pin Assignments
Pin Definitions
Pin #
Name
1,2
PGND1
3
VDD
4
SGND
5
ZCD
6
FB
7
COMP
8
OCP
9
FO
Fault Output.
10
EN
Enable pin to turn on and off the overall system. (Active Low Shutdown Mode).
11
INPUT
12
13
Description
Power Ground 1. It is connected to the source of the step-up switch.
Power supply of step-up DC-DC converter.
Signal Ground. The signal ground for step-up DC-DC converter circuitry.
The input of the zero current detection.
Step-up DC-DC converter output voltage feedback input.
Output of the transconductance error amplifier.
Sets Step-up DC-DC converter current limit.
Logic input for sinusoidal waveform.
ADJ
Output voltage adjust control pin. Connect to internal current source to change output
voltage using an external resistor. Connect a small capacitor (1 nF).
RT
Oscillator frequency control pin.
14
OVP
15
AGND
16
VIN
Voltage sense input of Step-up DC-DC converter for Over-Voltage Protection.
Analog Ground. The signal ground for full-bridge driver circuitry.
Power supply of 5 V LDO.
17
VDRV
18
PGND2
Power supply of full-bridge driver.
19
NC
20
OUT2
Output 2 for full-bridge driver.
21
OUT1
Output 1 for full-bridge driver.
22
NC
Not Connected
23, 24
LX
Switch Node. This pin is connected to the inductor.
Power Ground 2. The power ground for full-bridge driver .
Not Connected
© 2014 Fairchild Semiconductor Corporation
FAN8831 • Rev. 1.0
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
VDRV
DC Link Input Voltage Drain-Source Voltage of each MOSFET
VDD
DC Supply Voltage for DC-DC Converter
VIN,DCDC EN, INPUT, FB and COMP to SGND
VIN
DC Supply Voltage for LDO
VLX
LX to PGND
Max.
Unit
75
V
-0.3
5.5
V
-0.3
VDD +0.3
V
-0.3
75
V
36
V
-0.3
(2)
1S0P with thermal vias
(3)
0.98
1S2P with thermal vias
(4)
2.9
1S0P with thermal vias
(3)
127
1S2P with thermal vias
(4)
43
PD
Power Dissipation
θJA
Thermal Resistance Junction-Air
TA
Operating Ambient Temperature Range
-40
125
°C
TJ
Operating Junction Temperature
-55
150
°C
TSTG
Storage Temperature Range
-55
150
°C
ESD
Electrostatic Discharge Human Body Model, JESD22-A114
Capability
Charged Device Model, JESD22-C101
2
KV
500
V
(2)
W
°C/W
Notes:
1. All voltage values, except differential voltages, are given with respect to SGND, AGND and PGND pin.
2. JEDEC standard: JESD51-2, JESD51-3. Mounted on 76.2×114.3×1.6mm PCB (FR-4 glass epoxy material).
3. 1S0P with thermal vias: one signal layer with zero power plane and thermal vias.
4. 1S2P with thermal vias: one signal layer with two power plane and thermal vias.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
VDRV
Supply Voltage for Full-Bridge Driver
30
VLX
Boost Switch Voltage
10
Typ.
3.0
Max.
Unit
60
V
30
V
3.3
V
VDD
Operating Voltage for DC-DC Converter
2.7
VIN
Operating Voltage for Voltage Regulator
10
60
V
Current Limit Control Resistor
7.0
150
kΩ
ROCP
© 2014 Fairchild Semiconductor Corporation
FAN8831 • Rev. 1.0
www.fairchildsemi.com
4
FAN8831 — Piezoelectric Actuator Driver with Step-Up DC-DC Converter
Absolute Maximum Ratings
VDD=3.0 V, VIN=15.0 V, VDRV=60 V, RT=70 K and TA=-40°C to +125°C. Typical values TA=25°C, unless otherwise
specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Unit
Power Supply Section
(5)
IQ,DD
Quiescent Current for VDD
I Q,IN
Quiescent Current for VIN
I Q,DRV
Quiescent Current for VDRV
ISD,DD
Shutdown Current for VDD
ISD,IN
ISD,DRV
VEN=VCOMP=VDD,
VFB=1.0 V
Device not switching
700
1200
µA
300
500
µA
200
300
µA
1
µA
VEN=0 V,
VDD=VIN=VDRV =3 V
Shutdown Current for VIN
Shutdown Current for VDRV
1
µA
5
10
µA
VDDSTART
Start Threshold Voltage
2.6
2.7
2.8
V
VDDUVHYS
VDD UVLO Hysteresis Voltage
0.1
0.2
0.3
V
0.99
1.0
1.01
V
1
µA
1.5
%/V
Error Amplifier Section
VFB
Feedback Reference Voltage
IFB
FB pin Bias Current
VFB1
Gm
TA=25°C
VFB=0 V ~ 2 V
Feedback Voltage Line Regulation
(6)
Transconductance
2.7 V < VDD < 5 V
0.5
TA=25°C
800
µmho
Zero Current Detect Section
VZCD
Input Voltage Threshold
(7)
1.65
VCLAMPH
Input High Clamp Voltage
IDET=2.3 mA
VCLAMPL
Input Low Clamp Voltage
IDET= -2.3 mA
IZCD,SR
Source Current Capability
IZCD,SK
Sink Current Capability
tZCD,D
Delay From ZCD to Output Turn-On
1.83
2.00
V
3.0
3.5
4.0
V
-0.30
0.12
0.50
V
-2.3
mA
2.3
mA
50
200
ns
25
35
µs
(7)
Maximum On-Time Section
tON,MAX
Maximum On-Time
15
Restart / Maximum Switching Frequency Limit Section
tRST
Restart Timer
fMAX
Maximum Switching Frequency
15
25
35
µs
900
1000
KHz
16
28
40
ms
ROCP=3.3 KΩ, VDD=3.3 V
1.85
2.00
2.15
A
ROCP=22 KΩ,VDD=3.3 V
0.9
1.0
1.1
A
80
130
180
ns
(7)
Soft-Start Timer Section
tSS
Internal Soft-Start
Current Limit Comparator Section
IOCP
tCS_BLANK
OCP Trip Current
Comparator Leading-Edge Blanking Time
(7)
Notes:
5. This is the VDD current consumed when active but not switching. Does not include gate-drive current
6.
7.
VOUT
1

VIN VOUT
The line regulation is calculated based on
This parameter, although guaranteed by design, is not tested in production.
© 2014 Fairchild Semiconductor Corporation
FAN8831 • Rev. 1.0
www.fairchildsemi.com
5
FAN8831 — Piezoelectric Actuator Driver with Step-Up DC-DC Converter
Electrical Characteristics
VDD=3.0 V, VIN=15.0 V, VDRV=60 V, RT=70 K and TA=-40°C to +125°C. Typical values TA=25°C, unless otherwise
specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
0.2
0.5
Ω
1.0
µA
Step-Up Switch Section
RDSON
N-Channel On Resistance
VDD=3.3 V, TA=25°C
ILK_LX
LX Leakage Current
VLX=36 V
Oscillator Section
fOSC
Operating Frequency
RT=58 KΩ
40
50
60
KHz
RT=121 KΩ
20
25
30
KHz
Logic (EN and INPUT) Section
VINPUT+
INPUT Logic High Threshold Voltage
VINPUT-
INPUT Logic Low Threshold Voltage
1.34
IINPUT-
Input Low Current for INPUT and EN
VEN=0 V
IINPUT+
Input High Current for INPUT and EN
VEN=VDD
RINPUT
Input Logic Pull-Down Resistance
VEN= VINPUT=3 V
fINPUT
(8)
Input Logic Operating Frequency
8
V
0.5
V
1
µA
12
16
µA
250
375
KΩ
1000
Hz
20
Full-Bridge Switch Section
RDS,ONP
Output Upper-Side On Resistance
TA=25°C
3.0
5.0
Ω
RDS,ONN
Output Low-Side On Resistance
TA=25°C
3.0
5.0
Ω
VDRV=100% of Target
1.0
V
0.1
V
Output Control Section
VADJ,MAX
Analog Output Control Maximum Voltage
VADJ,MIN
Analog Output Control Minimum Voltage
IADJ+
Internal Current Source for ADJ Pin
(8)
(8)
TA=25°C
9
10
11
µA
0.75
0.80
0.85
V
Protection (Ready, OVP and TSD)
VREADY
Output Ready Threshold Voltage
HYREADY
Output Ready Hysteresis
0.2
VOVP_FB
OVP Threshold Voltage at FB Pin
HYOVP_FB
OVP Hysteresis Voltage at FB Pin
VOVP_OVP
OVP Threshold Voltage at OVP Pin
1.05
1.10
1.10
1.15
V
1.15
0.1
HYOVP_OVP OVP Hysteresis Voltage at OVP Pin
(8)
V
V
1.20
V
0.15
V
TSD
Thermal Shutdown Temperature
150
°C
THYS
Hysteresis Temperature of TSD
50
°C
TFO
Fault Output Duration
20
30
µs
VFOL
Fault Output Low Level Voltage
0.1
0.4
V
(8)
RPU=50 KΩ, VPU=3 V
Note:
8. This parameter, although guaranteed by design, is not tested in production.
© 2014 Fairchild Semiconductor Corporation
FAN8831 • Rev. 1.0
www.fairchildsemi.com
6
FAN8831 — Piezoelectric Actuator Driver with Step-Up DC-DC Converter
Electrical Characteristics
1.06
5
1.04
4
1.02
3
ISD [mA]
VFB [V]
1.00
0.98
2
ISDVIN
0.96
ISDVDRV
1
0.94
0.92
0
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
Temperature[oC]
Figure 4.
0
25
50
75
85
100
125
Temperature [oC]
Reference Voltage vs. Temperature
Figure 5.
3.0
Shutdown Current for VDRV & VIN
vs. Temperature
12
11
10
9
IADJ [mA]
VVDD,UVLO [V]
2.8
2.6
VDD_START
2.4
8
7
6
VDD_STOP
2.2
5
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
Figure 6.
0
25
50
75
85
100
125
Temperature[oC]
Temperature [oC]
VDD UVLO vs. Temperature
Figure 7.
ADJ Current vs. Temperature
2.2
1000
IQIN
IQDRV
IQDD
800
2.0
IOCP [A]
IQCURRENT [mA]
1.8
600
400
1.6
ROCP=3.3k
1.4
ROCP=25.5k
FAN8831 — Piezoelectric Actuator Driver with Step-Up DC-DC Converter
Typical Performance Characteristics
1.2
200
1.0
0
0.8
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
Temperature [oC]
Figure 8.
0
25
50
75
85
100
125
Temperature [oC]
Quiescent Current for VDD, VDRV, & VIN
vs. Temperature
Figure 9.
OCP Current vs. Temperature
4.0
1800
1600
1400
1000
VCLAMPH
VZCD [V]
IOPR [mA]
3.0
IDD
IIN
IDRV
1200
800
600
2.0
VCLAMPL
1.0
400
200
0
0.0
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
Temperature [oC]
Figure 10.
0
25
50
75
85
100
125
Temperature [oC]
Operating Current for VDD, VDRV, & VIN
vs. Temperature
© 2014 Fairchild Semiconductor Corporation
FAN8831 • Rev. 1.0
-15
Figure 11.
ZDC Clamp Voltage vs. Temperature
www.fairchildsemi.com
7
1.2
35
33
31
29
1.1
VOVP_FB [V]
T ONMAX [ms]
27
25
23
21
19
VOVPH_FB
VOVPL_FB
1.0
17
15
0.9
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
Temperature[oC]
Figure 12.
25
50
75
85
100
125
Temperature [oC]
Maximum On-Time vs. Temperature
Figure 13.
Fist OVP (FB) vs. Temperature
1.4
35
33
1.3
31
1.2
27
VOVP_OVP [V]
T RESRART [ms]
29
25
23
21
19
1.1
1.0
VOVPH_OVP
0.9
17
VOVPL_OVP
15
0.8
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
Temperature[oC]
Restart-Time vs. Temperature
Figure 15.
40
1.0
35
0.8
30
0.6
25
20
15
75
85
100
125
Second (OVP) vs. Temperature
VREADYH
0.4
VREADYL
0.2
0.0
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
Temperature[oC]
Figure 16.
25
50
75
85
100
125
Temperature [oC]
Soft-Start Time vs. Temperature
Figure 17.
1.4
1.4
1.2
1.2
1.0
1.0
VIN [V]
VEN [V]
50
Temperature [oC]
VOVP_OVP [V]
T SOFT [ms]
Figure 14.
25
FAN8831 — Piezoelectric Actuator Driver with Step-Up DC-DC Converter
Typical Performance Characteristics
0.8
VEN+
0.6
Ready Voltage vs. Temperature
VIN+
VIN-
0.8
0.6
VEN0.4
0.4
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
Temperature [oC]
Figure 18.
25
50
75
85
100
125
Temperature [oC]
Enable (EN) Threshold Voltage
vs. Temperature
© 2014 Fairchild Semiconductor Corporation
FAN8831 • Rev. 1.0
0
Figure 19.
INPUT Threshold Voltage
vs. Temperature
www.fairchildsemi.com
8
0.5
% of Target Voltage [% ]
100
0.4
RDSON []
0.3
0.2
0.1
80
60
40
20
0
0.0
-40
-30
-15
0
25
50
75
85
100
10
125
20
30
40
Figure 20.
50
60
70
80
90 100 110 120 130 140 150
RADJ [K]
Temperature [oC]
Boost Switch RDSON vs. Temperature
Figure 21.
5.5
% of Sine Amplitude vs. RADJ
300
5.0
250
4.5
VDD=2.7 V
200
3.5
fOSC [kHz]
RDSON []
4.0
3.0
2.5
2.0
RDSONN
1.5
RDSONP
VDD=3 V
VDD=5 V
150
100
50
0
1.0
-40
-30
-15
0
25
50
75
85
100
5
125
15 25 35 45 55 65 75 85 95 105 115 125 135 145 155
RT [k]
Temperature [oC]
Full-Bridge Switch RDSON
vs. Temperature
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Figure 23.
VDD=2.7 V
VDD=3 V
VDD=5 V
fOSC vs. RT
3
5
7.5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
IOCP [A]
Figure 22.
FAN8831 — Piezoelectric Actuator Driver with Step-Up DC-DC Converter
Typical Performance Characteristics
ROCP [k]
Figure 24.
© 2014 Fairchild Semiconductor Corporation
FAN8831 • Rev. 1.0
IOCP vs. ROCP
www.fairchildsemi.com
9
4.00
2.80
18
0.05 C
4.00
13
A
B
2X
19
12
4.00
2.80
4.00
24
7
0.80
PIN 1
QUADRANT
0.05 C
2X
TOP VIEW
1
6
0.30 24X
RECOMMENDED LAND PATTERN
0.10 C
0.08 C
SIDE VIEW
C
SEATING
PLANE
BOTTOM VIEW PIN ONE OPTIONS
PIN #1 IDENT
(0.635) 4X
1
6
NOTES:
24
7
A. CONFORMS TO JEDEC REGISTRATION
MO-220, VARIATION WGGD-6.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
19
(0.650) 4X
12
(0.495) 4X
18
0.50
E. DRAWING FILENAME: MKT-MLP24Erev5.
13
0.10
0.05
BOTTOM VIEW
D. LAND PATTERN IPC REFERENCE :
QFN50P400X400X80-25W6N.
24X
C A B
C
0.20
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