AD AD53522 High speed dual pin electronic Datasheet

a
FEATURES
1000 MHz Toggle Rate
Driver/Comparator/Active Load and Dynamic Clamp
Included
Inhibit Mode Function
100-Lead LQFP Package with Built-In Heat Sink
Driver
48 Output Resistance
800 ps Tr/Tf for a 3 V Step
Comparator
1.1 ns Propagation Delay at 3 V
Load
40 mA Voltage Programmable Current Range
50 ns Settling Time to 15 mV
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Instrumentation and Characterization Equipment
High Speed
Dual Pin Electronic
AD53522
FUNCTIONAL BLOCK DIAGRAM (One-Half)
VCC
VCC
VCC
VEE
VH
VEE
VEE
AD53522
VTERM
VCH
DATA
VHDCPL
DATAB
IOD
OUT
DRIVER
IODB
RLD
VLDCPL
RLDB
VCL
VL
PWRD
HCOMP
VCCO
QH
QHB
COMPARATOR
QL
QLB
PRODUCT DESCRIPTION
The AD53522 is a complete, high speed, single-chip solution
that performs the pin electronics functions of driver, comparator,
and active load (DCL) for ATE applications. In addition, the
driver contains a dynamic clamp function and the active load
contains an integrated Schottky diode bridge.
The driver is a proprietary design that features three active states:
Data High mode, Data Low mode, and Term mode, as well as
an Inhibit State. In conjunction with the integrated dynamic
clamp, this facilitates the implementation of a high speed active
termination. The output voltage range is –0.5 V to +6.5 V to
accommodate a wide variety of test devices.
The dual comparator, with an input range equal to the driver
output range, features PECL compatible outputs. Signal tracking
capability is in the range of 3 V/ns.
The active load can be set for up to 40 mA load current. IOH, IOL,
and the buffered VCOM are independently adjustable. On-board
Schottky diodes provide high speed switching and low capacitance.
Also included is an on-board temperature sensor that gives an
indication of the silicon surface temperature of the DCL. This
information can be used to measure ␪JC and ␪JA or flag an alarm
if proper cooling is lost. Output from the sensor is a current sink
LCOMP
VCOM
IOLC
VCOM_S
+1
V/I
IOXRTN
ACTIVE LOAD
PROT_LO
INHL
PROT_HI
INHLB
IOHC
THERM*
V/I
1.0A/K
DR_GND GND_ROT
PWRGND
9
HQGND THERMSTART
*ONLY 1 (ONE) THERM PER DEVICE
that is proportional to absolute temperature. The gain is trimmed
to a nominal value of 1.0 µA/K. As an example, the output current
can be sensed by using a 10 kΩ resistor connected from 10 V to
the THERM (IOUT) pin. A voltage drop across the resistor will
be developed that equals 10 kΩ ⫻ 1 µA/°K = 10 mV/°K = 2.98 V
at room temperature.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD53522–SPECIFICATIONS
DRIVER1 (T = 85C 5C, +V = +10.5 V 1%, –V
J
S
Spec
No. Parameter
S
= –4.5 V 1%, VCCO = 3.3 V, unless otherwise noted.)
Max
Unit
Spec3
Perf
+3.3
V
N
± 1000
mV
P
–250
+250
µA
P
Max Value Measured during
Linearity Tests
–50
+50
µA
P
Data = H, VH = –0.4 V to +6.5 V,
Vl = –0.5 V (VT = 0 V, VH Meets
Test 20, 21, and 22 Specs)
Data = L, VL = –0.5 V to +6.4 V,
VH = 6.5 V (VT = 0 V, VL Meets
Test 30, 31, and 32 Specs)
VL = –0.05 V, VH = +0.05 V,
VT = 0 V and VL = –0.5 V,
VH = +6.5 V, VT = 0 V
–0.4
+6.5
V
P
–0.5
+6.4
V
P
+0.1
+7.0
V
P
–50
+50
mV
P
–0.3
+0.3
% of VH P
–5
+5
mV
P
–50
+50
mV
P
–0.3
+0.3
% of VL
P
–5
+5
mV
P
mV/°C
N
Conditions
Min
3
DIFFERENTIAL INPUT CHARACTERISTICS
(DATA to DATAB, IOD to IODB, RLD to RLDB)
Voltage Range
Note: Inputs are from Same Logic
Type Family
Differential Voltage with
Note: AC Tests Performed
LVPECL Levels
Bias Current
VIN = 1.5 V, 2.5 V
4
REFERENCE INPUTS
Bias Currents
10
OUTPUT CHARACTERISTICS
Logic High Range
1
2
11
Logic Low Range
12
Amplitude [VH–VL]
20
ABSOLUTE ACCURACY
VH Offset
21
VH Gain Error
22
Linearity Error
30
VL Offset
31
VL Gain Error
32
Linearity Error
33
40
Offset Temperature Coefficient
OUTPUT RESISTANCE
VH = –0.3 V
41
VH = +6.5 V
42
VL = –0.5 V
43
VL = +6.4 V
44
VH = +2.5 V
50
Dynamic Current Limit
51
Static Current Limit
52
Static Current Limit
Data = H, VH = 0 V, VL = –0.5 V,
VT = +3 V
Data = H, VH = –0.4 V to +6.5 V,
VL = –0.5 V, VT = +3 V
Data = H, VH = –0.4 V to +6.5 V,
VL = –0.5 V, VT = +3 V
Data = L, VL = 0 V, VH = +6.5 V,
VT = +3 V
Data = L, VL = –0.5 V to +6.4 V,
VH = +6.5 V, VT = +3 V
Data = L, VL = –0.5 V to +6.4 V,
VH = +6.5 V, VT = +3 V
VL = 0 V, VH = +5 V, VT = 0 V
VL = –0.5 V, VT = 0 V, IOUT = +1,
+30 mA
VL = –0.5 V, VT = 0 V, IOUT = –1,
–30 mA
VH = +6.5 V, VT = 0 V, IOUT = +1,
+30 mA
VH = +6.5 V, VT = 0 V, IOUT = –1,
–30 mA
VL = 0 V, VT = 0 V, IOUT = –30 mA
(Trim Point)
Cbyp = 39 nF, VH = +6.5 V,
VL = –0.5 V, VT = 0 V
Output to –0.5 V, VH = +6.5 V,
VL = –0.5 V, VT = 0 V, DATA = H
Output to +6.5 V, VH = +6.5 V,
VL = –0.5 V, VT = 0 V, DATA = L
–2–
Typ2
0
± 400
± 600
+0.5
+46
+50
Ω
N
+46
+50
Ω
P
+46
+50
Ω
P
+46
+50
Ω
N
Ω
P
mA
N
+47.5
+100
–120
–60
mA
P
+60
+120
mA
P
REV. A
AD53522
DRIVER1 (continued)
Spec
No. Parameter
60
VTERM
Voltage Range
61
VTERM Offset
62
VTERM Gain Error
63
VTERM Linearity Error4
64
70
Offset Temperature Coefficient
Output Resistance DC
72
73
74
80
81
82
90
PSRR, Drive, or Term Mode
Static Current Limit
Static Current Limit
91
1 V Swing
92
3 V Swing
93
3 V Swing
93A
3 V Swing
94
5 V Swing
100
101
102
110
120
121
130
to 4 mV
Delay Change vs. Pulse Width
131
Delay Change vs. Duty Cycle
REV. A
Spec3
Perf
–0.3
+6.3
V
P
–50
+50
mV
P
–0.3
+0.3
% of VSET P
–5
+5
mV
P
mV/°C
Ω
N
+50
Term Mode, VTERM = –0.3 V
to +6.3 V, VL = 0 V, VH = +3 V
(VTERM Meets Test 61, 62, and 63 specs)
Term Mode, VTERM = 0 V,
VL = 0 V, VH = +3 V
Term Mode, VTERM = –0.3 V
to +6.3 V, VL = 0 V, VH = +3 V
Term Mode, VTERM = –0.3 V
to +6.3 V, VL = 0 V, VH = +3 V
VTERM = 0 V, VL = 0 V, VH = +3 V
IOUT = +30 mA, –1 mA,
VTERM = –0.3 V, VH = +3 V, VL = 0 V
IOUT = –30 mA, +1 mA,
VTERM =+6.3 V, VH = +3 V, VL = 0 V
IOUT = ± 30 mA, ± 1 mA,
VTERM = +2.5 V, VH = +3 V, VL = 0 V
+VS , –VS ± 1%
Output to –0.3 V, VTERM = +6.3 V
Output to +6.3 V, VTERM = –0.3 V
Measured 20%–80%, VL = –0.1 V,
VH = +0.1 V, into 50 Ω
Measured 20%–80%, VL = 0 V,
VH = 1 V, into 50 Ω
Measured 10%–90%, VL = 0 V,
VH = 3 V, into 50 Ω
Measured 10%–90%, VL = 0 V,
VH = 3 V, into 500 Ω
Measured 20%–80%, VL = 0 V,
VH = 3 V, into 500 Ω
Measured 10%–90%, VL = 0 V,
VH = 5 V, into 500 Ω
RISE AND FALL TIME TEMPERATURE COEFFICIENT
1 V Swing
(Per Test 91)
3 V Swing
(Per Test 92)
5 V Swing
(Per Test 94)
Overshoot and Preshoot
VL, VH = –0.1 V, +0.1 V,
Driver Terminated into 50 Ω
VL, VH = 0.0 V, 3 V,
Driver Terminated into 50 Ω
SETTLING TIME
to 15 mV
Unit
Min
DYNAMIC PERFORMANCE, DRIVE (VH and VL)
Propagation Delay Time
Measured at 50%, VL = 0 V,
VH = 3 V, into 500 Ω
Propagation Delay T.C.
Measured at 50%, VL = 0 V,
VH = 3 V, into 500 Ω
Delay Matching, Edge-to-Edge
Measured at 50%, VL = 0 V,
VH = 3 V, into 500 Ω
RISE AND FALL TIMES
200 mV Swing
Max
Conditions
VL = 0 V, VH = 0.5 V,
Driver Terminated into 50 Ω
VL = 0 V, VH = 0.5 V
VL/VH = 0/3, PW = 2.5 ns/7.5 ns,
30 ns/90 ns, DC = 25%
VL = 0 V, VH = 3 V, Duty Cycle
(DC) 5% to 95%, T = 40 ns
–3–
Typ2
+0.5
+46
N
N
–60
+120
mV/V
mA
mA
P
N
P
P
1.55
ns
P
ps/°C
N
ps
P
0.25
ns
N
0.3
ns
N
0.8
ns
N
0.8
ns
N
+17.8
–120
+60
1.25
1.4
2
200
0.450
0.560
0.670
ns
P
1.2
1.5
ns
N
±2
±2
±4
ps/°C
ps/°C
ps/°C
0 + 50
% of Step
+ mV
+6.0 + 50 % of Step
+ mV
0 – 50
–6.0 – 50
50
10
25
25
75
N
N
N
N
N
ns
N
µs
ps
N
N
ps
N
AD53522
SPECIFICATIONS (continued)
DRIVER1 (continued)
Spec
No. Parameter
140
MINIMUM WIDTH PULSE
1 V Swing
141
3 V Swing
142
Toggle Rate
150
151
152
153
160
170
171
180
181
182
183
190
191A
191B
192A
192B
Conditions
Min
Measured at 50% point width
VOUT AC Swing = 0.9 VOUT DC
Swing Terminated, 50 Ω Load on
Transmission Line
VH = 1 V, VL = 0 V, Terminated
to 50 Ω,VOUT > 300 mV p-p
DYNAMIC PERFORMANCE, INHIBIT
Delay Time, Active to Inhibit
Measured at 50%, VH = 4 V,
VL = 0 V, VTT = 2
Delay Time, Inhibit to Active
Measured at 50%, VH = 4 V,
VL = 0 V, VTT = 2
Delay Time Matching,
Measured at 50%, VH = 4 V,
Inhibit to Active
VL = 0 V, VTT = 2
Delay Time Matching,
Measured at 50%, VH = 4 V,
Active to Inhibit
VL = 0 V, VTT = 2
I/O Spike
VH = 0 V, VL = 0 V
Rise, Fall Time, Active to Inhibit
VL = 0 V, VTT = 2
(20%–80% of 1 V Output)
Rise, Fall Time, Inhibit to Active
VH = 4 V, VL = 0 V, VTT = 2
(20%–80% of 1 V Output)
DYNAMIC PERFORMANCE, VTERM
Delay Time, VH to VTERM
Measured at 50%, VL = VH = 2 V,
VTERM = 0 V, VTT = 0 V
Delay Time, VL to VTERM
Measured at 50%, VL = VH = 0 V,
VTERM = 2 V, VTT = 0 V
Delay Time, VTERM to VH
Measured at 50%, VL = VH = 2 V,
VTERM = 0 V, VTT = 0 V
Delay Time, VTERM to VL
Measured at 50%, VL = VH = 0 V,
VTERM = 2 V, VTT = 0 V
Overshoot and Preshoot
VH/VL, VTERM = (0 V, 2 V),
(0 V, 6 V)
VTERM Rise Time, VL to VT,
VL, VH = 0 V, VTERM = 2 V,
Normal Mode
20%–80%
VTERM Rise Time, VT to VH,
VL, VH = 2 V, VTERM = 0 V,
Normal Mode
20%–80%
VTERM Fall Time, VT to VL,
VL, VH = 0 V, VTERM = 2 V,
Normal Mode
20%–80%
VTERM Fall Time, VH to VT,
VL, VH = 2V, VTERM = 0 V,
Normal Mode
20%–80%
–4–
–6.0 + 50
Unit
Spec3
Perf
0.6
ns
N
1.5
ns
N
1000
MHz
N
2
Typ
Max
1.7
2.0
ns
P
1.7
2.2
ns
P
150
250
ps
P
150
250
ps
P
200
1.2
mV p-p
ns
N
N
0.6
ns
N
1.5
1.9
ns
P
1.6
1.9
ns
P
1.6
2.0
ns
P
1.6
2.0
ns
P
+6.0 + 50 % of Step N
+ mV
1.0
ns
N
0.6
ns
N
0.6
ns
N
1.0
ns
N
REV. A
AD53522
COMPARATOR1
Spec
No. Parameter
200
201
202
203
DC INPUT CHARACTERISTICS
VCCO Range
Offset Voltage (VOS)
Offset Voltage Drift
HCOMP, LCOMP
206
207
208
209
210
BIAS CURRENTS
Voltage Range (VCM)
Differential Voltage (VDIFF)
Gain Error
Linearity Error
Extended Range Operation
220
DIGITAL OUTPUTS
Logic 1 Voltage Q
221
Logic 0 Voltage QB
222
Logic Differential, Q–QB
225
Slew Rate
240
241
250
260
270
280
281
282
290
300
301
302
Conditions
Min
Common-Mode Voltage = 0 V
Common-Mode Voltage = 0 V
Over Linearity Range
+2.0
–25
Q or QB, 150 Ω to GND,
150 Ω from Q to QB
Q or QB, 150 Ω to GND,
150 Ω from Q to QB
Q or Qb, 150 Ω to GND,
150 Ω from Q to QB
Q or QB (20% – 80% of output,
150 Ω from Q to QB)
INPUT CHARACTERISTICS (INHL, INHLB)
See Driver Spec No. 1
Input Voltage
VIOH = 1 V, VIOL = 1 V,
VCOM = 2 V, VDUT = 0 V
INHL, INHLB Bias Current
INHL, INHLB = 0 V, 3.3 V,
AC Tests 0.2 V and 0.8 V
VIOH Current Program Range,
VDUT = 0.8 V, 6.5 V
IOH = 0 mA to –40 mA
–5–
Max
Unit
Spec3
Perf
+4.5
+25
V
mV
µV/°C
µA
N
P
N
P
+50
–50
+50
–0.5
+6.5
+7
0.0
+2
V
V
%FSR
mV
V
P
P
N
N
P
VCCO – 1.05
VCCO – 0.85
V
P
VCCO – 2.2
VCCO – 1.5
V
P
1.15
V
P
ps
N
1.0
ns
ps/°C
P
N
120
100
275
ps
ps
ps
N
N
N
ps
N
ns
N
125
mV
ps
N
P
0
+3.3
V
P
–250
+250
µA
P
0
+4.0
V
P
VIN = –0.5 V to +6.5 V
–0.25
VIN = –0.5 V to +6.5 V
–2
HCOMP, LCOMP = –1, Output –1.0
Toggle VOUT from –0.9 V to –1.1 V
CHANNEL COMPARATOR SWITCHING PERFORMANCE
PROPAGATION DELAY5, 6, 7
Input to Output
VIN = 3 V p-p, 2 V/ns
Propagation Delay Tempco
VIN = 3 V p-p, 2 V/ns
Prop Delay Change with respect to:
Slew Rate: 1, 2, 3 V/ns
VIN = 0 V to 3 V
Amplitude: 500 mV, 1.0 V, 3.0 V VIN = 1.0 V/ns
Equivalent Input Rise Time
VIN = 0 V to 2 V, < 80 ps,
20%–80% Rise Time
Driver in VTERM = 0 V
Pulse Width Linearity
VIN = 0 V to 3 V, 2 V/ns, PW =
3, 4, 5, 10 ns, Driver Hi-Z mode
Settling Time
Settling to ± 8 mV, VIN = 0 V to
3 V, Driver Hi-Z mode
Hysteresis
Comparator Propagation Delay
VIN = 0 V to 3 V, 2 V/ns
Matching, HCOMP to LCOMP
REV. A
Typ2
0.65
0.9
380
0.7
1.1
50
25
6
AD53522
SPECIFICATIONS (continued)
ACTIVE LOAD1
Spec
No. Parameter
303
304
305
310
311
312
320
VIOL Current Program Range,
IOL = 0 mA to 40 mA
VIOH, VIOL Input Bias Current
IOXRTN Range
VDUT = –0.5 V, +6.5 V
VDUT Range
VDUT Range,
IOH = 0 mA to –40 mA
VDUT Range,
IOL = 0 mA to +40 mA
OUTPUT CHARACTERISTICS
Accuracy
Gain Error, Load Current,
Normal Range Calculated at
1 mA and 40 mA points2
321
Load Offset
322
323
Load Nonlinearity
Output Current Tempco
324
IOH Extended Range
330
331
332
VCOM BUFFER
VCOM Buffer Offset Error
VCOM Buffer Bias Current
VCOM Buffer Gain Error
333
340
VCOM Buffer Linearity Error
DYNAMIC PERFORMANCE
Propagation Delay
± IMAX to INHIBIT
341
INHIBIT to ± IMAX
342
Propagation Delay Matching
350
I/O Spike
360
Settling Time to 15 mV
361
Settling Time to 4 mV
Max
Unit
Spec3
Perf
4.0
+300
V
µA
P
P
V
N
+6.5
V
P
+0.8
+6.5
V
P
–0.5
+5.2
V
P
+0.35
%ISET
P
+300
µA
P
+80
µA
µA/°C
P
N
%
P
Conditions
Min
VDUT = –0.5 V, +5.2 V
VIOL = 0 V, 4 V and
VIOH = 0 V, 4 V
IOL = +40 mA, IOH = –40 mA,
0
–300
IOL = +40 mA, IOH = –40 mA,
|VDUT – VCOM|> 1.3 V
VDUT – VCOM > 1.3 V
–0.5
VCOM – VDUT > 1.3 V
Typ
2
–0.5, +6.5
IOL, IOH = 25 µA – 40 mA,
–0.35
VCOM = 0 V, VDUT = ± 2 V, and
IOL = 25 µA to 40 mA, VCOM = +6.5 V,
VDUT = +5.2 V and IOH = 25 µA to
40 mA, VCOM = –0.5 V, VDUT = +0.8 V
Calculated from Intercept of 1 mA
–300
and 40 mA Points
IOL, IOH from 25 µA to 40 mA
–80
Measured at IOH, IOL = 200 µA
< ±3
Driver Inhibited, IOH = 1 mA,
Change in IOH from VTT = 0 V to
VTT = –1.0 V
2
IOL, IOH = 40 mA, VCOM = 0 V
VCOM = 0 V
IOL, IOH = 40 mA,
VCOM = –0.5 V to +6.5 V
IOL, IOH = 40 mA,
VCOMI = –0.5 V to +6.5 V
–50
–20
–4
+50
+20
+4
mV
µA
%
P
P
P
–10
+10
mV
P
VTT = +2 V, VCOM = +4 V/0 V,
IOL = +20 mA, IOH = –20 mA
VTT= +2 V, VCOM = +4 V/0 V,
IOL = +20 mA, IOH = –20 mA
Matching = (Test 340 Value) –
(Test 341 Value)
VCOM = 0 V, IOL = +20 mA,
IOH = –20 mA
IOL = +20 mA, IOH = –20 mA,
50 Ω Load, to ± 15 mV
IOL = +20 mA, IOH = –20 mA,
50 Ω Load, to ± 4 mV
1.0
1.3
2.0
ns
P
1.2
1.8
2.4
ns
P
+1.0
ns
P
250
mV
N
50
ns
N
10
µs
N
–6–
–1.0
REV. A
AD53522
DYNAMIC CLAMP1
Spec
No. Parameter
400
401
402
410
411
420
430
440
441
Input Voltage VCH
Input Voltage VCL
Input Bias Current VCH/VCL
VCH, VCL Offset Error
VCH, VCL Gain Error
Static Current Capability
Incremental Resistance
VCHP, VCLP Protection
Diodes Vf @ 500 µA
Protection Diodes Max Current
Conditions
Max
Unit
Spec3
Perf
7.5
+4
+250
+250
1.01
75
52
0.64
V
V
µA
mV
V/V
mA
Ω
V
P
P
P
P
P
N
P
P
2
mA
N
Max
Unit
Spec3
Perf
0
–250
35
–20
5
+250
60
+20
V
µA
%
nA
P
P
P
P
–500
+500
nA
P
–1
–500
–5
+1
+500
+5
µA
nA
µA
pF
pF
P
P
P
N
N
Unit
Spec3
Perf
15
+10.5
–4.5
465
570
V
V
V
mA
N
N
N
P
475
600
mA
P
45
mA
P
7.2
7.9
W
P
5.2
1
5.9
W
µA/°K
P
N
Min
Overrange Spec 401, 402
ITEST = 1 mA
ITEST = 1 mA
11 mA to 21 mA
2
–1.5
–250
–250
0.96
50
45
0.52
Typ2
48
For Information Only
TOTAL FUNCTION
Spec
No. Parameter
500
501
503
504
505
600
601
602
605
606
PWRD Input Voltage
PWRD Bias Current
Power-Down Supply Reduction
Power-Down Output
Leakage Current
Power-Down Output
Leakage Current
Output Leakage Current
Output Leakage Current
Output Leakage Current
Output Capacitance
Output Capacitance Term
Conditions
Min
PWRD Trip Point 1.4 V ± 0.15 V
VIOH = 0 V, VIOL = 0 V
VIOH = 0 V, VIOL = 0 V,
VOUT = –0.5 V to +5.5 V
VIOH = 0 V, VIOL = 0 V,
VOUT = 5.5 V to 6.5 V
VOUT = –0.5 V to +6.5 V
VOUT = 0 V to 5 V
VOUT = –1 V
Driver and Load Inhibited
Driver VTERM = 0 V, Load Inhibited
Typ2
9.2
2.5
POWER SUPPLIES
Spec
No. Parameter
610
620
630
640
Total Supply Range
Positive Supply, VCC
Negative Supply, VEE
Positive Supply Current, VCC
650
Negative Supply Current, VEE
651
Comparator Supply Current
Overhead, VCCO
660
Total Power Dissipation
661
700
Total Power Dissipation
Temperature Sensor Gain Factor
Conditions
Min
Driver = Inhibit, ILOAD Program = 40 mA,
Load = Active
Driver = Inhibit, ILOAD Program = 40 mA,
Load = Active
Driver = Inhibit, ILOAD Program = 40 mA,
Load = Active (IVCCO – (comparator
logic output currents))
Driver = Inhibit, ILOAD Program = 40 mA,
Load = Active
Driver = Inhibit, ILOAD Program = 40 mA, 0 mA
RLOAD = 10 kΩ, VSOURCE = 10.5 V
2
Typ
Max
NOTES
1
All temperature coefficients are measured at TJ = 75°C to 95°C. In test figures, voltmeter loading is 1 MΩ or greater, scope probe loading is 100 kΩ in parallel with 0.6 pF.
2
Typical values are not tested or guaranteed. Nominal values are generated from design or simulation analyses and/or limited bench evaluations and are not tested or guaranteed.
3
Spec Perf: N = Nominal, O = Operating Condition, T = Typical, P = Production, Max/Min.
4
VTERM linearity over the following condition: VL – 6 V < VTERM < VH + 6 V.
5
All ac input values are referred to the source end of transmission line input.
6
All ac tests are performed with driver in VTERM mode except where noted.
7
Rise time is calculated SQRT((comp out Tr) 2 – (comp in Tr) 2).
Specifications are subject to change without notice.
REV. A
–7–
AD53522
DATA to DATAB, IOD to IODB, RLD to RLDB . . . ± 3 V
INHL to INHLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 6 V
VH, VL, VTERM to GND (RSERIES < 500 Ω) . +7.5 V, –1.1 V
VH to VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 V, –3.5 V
(VH – VTERM) and (VTERM – VL) . . . . . . . . . . . . . ± 8 V
Reflection Clamp High/Low . . . . . . . . . . . . . . . +8.5 V, –2 V
Protection Clamp Breakdown Voltage . . . . . . . . . . . . . . 12 V
Protection Clamp Current . . . . . . . . . . . . . . . . . . . . . ± 5 mA
VOUT to HCOMP or LCOMP . . . . . . . . . . . . . . . . . . ± 7.8 V
ENVIRONMENTAL
Operating Temperature (Junction) . . . . . . . . . . . . . . . 175°C
Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec)3 . . . . . . . . . . . 260°C
ABSOLUTE MAXIMUM RATINGS 1
POWER SUPPLY VOLTAGE
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 V
VEE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
VCCO to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
PWRGND, DRGND, GND_ROT, or HQGND . . . . ± 0.4 V
OUTPUTS
VOUT Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite2
VOUT, Inhibit Mode . . . . . . . . . . . . . . . . . . . . . +8.5 V, –2 V
VOUT, Inhibit Mode . . . . . VL – 5.5 V < VOUT < VH + 5.5 V
VHDCPL . . . . . . . . Do Not Connect Except for Cap to VCC
VLDCPL . . . . . . . . Do Not Connect Except for Cap to VEE
QH, QHB, QL, QLB Maximum IOUT:
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Surge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 V, 0 V
Driver Output Capacitance, Maximum . . . . . . . . . . . . 10 pF
INPUTS
DATA, DATAB, IOD, IODB, RLD, RLDB
. . . . . . . . . . . . . . . . . . . . . . . . (VCCO + 1.5 V, VCCO – 4.5 V)
INHL, INHLB, CMPD . . . . . . . . . . . . . . . –0.4 V to +5.5 V
PWRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.4 V to +4.5 V
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2
Output short circuit protection is guaranteed as long as proper heat sinking is
employed to ensure compliance with the operating temperature limits.
3
To ensure lead coplanarity (± 0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in environments at 24 °C
± 5°C (75°F ± 10°F) with relative humidity not to exceed 65%.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD53522JSQ
0°C to 70°C
100-Lead LQFP-EDQUAD
with Integral Heat Slug
SQ-100
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD53522 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Table I. Driver Truth Table
Table II. Comparator Truth Table
DATA DATAB IOD IODB
RLD
RLDB
0
1
X
1
0
X
1
1
0
0
0
1
X
X
0
X
X
1
X
X
0
1
1
0
Output
State
VOUT
VL
VH
INH and
CLAMP
VTERM
> HCOMP
> HCOMP
< HCOMP
< HCOMP
> LCOMP
< LCOMP
> LCOMP
< LCOMP
QH
Output States
QHB
QL
QLB
1
1
0
0
0
0
1
1
0
1
0
1
1
0
1
0
Table III. Active Load Truth Table
VDUT
INHL INHLB IOH
<VCOM 0
>VCOM 0
X
1
1
1
0
Output States (Including Diode Bridge)
IOL
I(VOUT)
V(IOHC) ⫻ +10 mA V(IOLC) ⫻ –10 mA IOL
V(IOHC) ⫻ +10 mA V(IOLC) ⫻ –10 mA IOH
0
0
0
–8–
REV. A
AD53522
PROT_HI1 1
VCC
RLD1
IOD1
IODB1
DATA1
DATAB1
PWRGND
PWRGND
VCOM1
VH1
VTERM1
VL1
HCOMP1
91 90
PWRGND
VEE
93 92
INHLB1
HQGND
94
INHL1
IOHC1
100 99 98 97 96 95
THERM
IOLC1
VCOM_S1
PWRGND
PWRGND
PROT_LO1
PIN CONFIGURATION
89
88
87
86
85
84
83
82
81 80
79
78
77
76
PIN 1
IDENTIFIER
LCOMP1
75
IOXRTN1 2
74
VCC
VCH1 3
73
VCC
VCL1 4
72
VEE
VHDCPL1 5
71
VEE
HEAT SLUG
OUT1 6
70
QH1
VLDCPL1 7
69
QHB1
PWRGND 8
68
VCCO1
PWRGND 9
67
QLB1
DR_GND 10
66
QL1
PWRGND 11
65
RLDB1
64
PWRD1
63
GND_ROT
62
PWRD2
PWRGND 15
61
RLDB2
DR_GND2 16
60
QL2
PWRGND 17
59
QLB2
PWRGND 18
58
VCCO2
VLDCPL2 19
57
QHB2
OUT2 20
56
QH2
VHDCPL2 21
55
VEE
VCL2 22
54
VEE
VCC
AD53522
PWRGND 12
GND_ROT 13
TOP VIEW
(Not to Scale)
PWRGND 14
41 42 43
44
45
46
47 48
49
50
RLD2
IOD2
IODB2
PWRGND
PWRGND
VCOM2
VH2
VL2
HCOMP2
VTERM2
40
DATAB2
39
DATA2
38
PWRGND
INHL2
37
THERMSTART
36
VCOM_S2
35
PWRGND
33 34
PWRGND
32
PROT_LO2
26 27 28 29 30 31
VCC
LCOMP2
VEE
51
INHLB2
VCC
PROT_HI2 25
HQGND
52
IOHC2
53
IOLC2
VCH2 23
IOXRTN2 24
NOTE
DIE IS MOUNTED TO THE BACK OF THE HEAT SLUG.
THE PACKAGE IS MOUNTED TO THE BOARD, HEAT SLUG UP.
PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Description
1
PROT_HI1
Channel 1, Output Voltage Sensing Diode.
2
IOXRTN1
Current Return Path for the Active Load for Channel 1. Typically connected to a power ground.
3
VCH1
Analog Input Voltage that Sets the Reflection Clamp High Level of Channel 1.
4
VCL1
Analog Input Voltage that Sets the Reflection Clamp Low Level of Channel 1.
5
VHDCPL1
Internal Supply Decoupling for the Driver Output Stage of Channel 1. This pin needs to be connected to
VCC through a 39 nF (minimum) capacitor.
6
OUT1
Input/Output For The Driver, Window Comparator, Reflection Clamp, and Active Load of Channel 1.
7
VLDCPL1
Internal Supply Decoupling for the Driver Output Stage of Channel 1. This pin needs to be connected to
VEE through a 39 nF (minimum) capacitor.
8, 9, 11, 12, 14, PWRGND
15, 17, 18, 27,
28, 38, 44, 45,
81, 82, 88, 98, 99
Power Ground.
10
Analog Ground.
REV. A
DR_GND
–9–
AD53522
Pin Number
Mnemonic
Description
13
GND_ROT
Analog Ground.
16
DR_GND2
Analog Ground.
19
VLDCPL2
Internal Supply Decoupling for the Driver Output Stage of Channel 2. This pin needs to be connected to
VEE through a 39 nF (minimum) capacitor.
20
OUT2
Input/Output for the Driver, Window Comparator, Reflection Clamp, and Active Load of Channel 2
21
VHDCPL2
Internal Supply Decoupling for the Driver Output Stage of Channel 2. This pin needs to be connected to
VCC through a 39 nF (minimum) capacitor.
22
VCL2
Analog Input Voltage that Sets the Reflection Clamp Low Level of Channel 2
23
VCH2
Analog Input Voltage that Sets the Reflection Clamp High Level of Channel 2
24
IOXRTN2
Current Return Path for the Active Load for Channel 2. Typically connected to a power ground.
25
PROT_HI2
Channel 2, Output Voltage Sensing Diode.
26
PROT_LO2
Channel 2, Output Voltage Sensing Diode.
29
VCOM_S2
Analog Output Voltage that Represents a Buffered VCOM1 Input
30
THERMSTART Temperature Sensor Startup Pin. Normally not connected.
31
IOLC2
Analog Input Voltage that Programs the Channel 2 Active Load Source Current.
32
IOHC2
Analog Input Voltage that Programs the Channel 2 Active Load Sink Current.
33
HQGND
Clean Analog Ground for the Active Load for Channel 2.
34
INHL2
One of Two Complementary Inputs that Control the Inhibit Mode for the Active Load Bridge of Channel 2.
35
INHLB2
One of Two Complementary Inputs that Control the Inhibit Mode for the Active Load Bridge of Channel 2.
36, 54, 55,
71, 72, 90
VEE
Negative Supply Terminal.
37, 52, 53,
73, 74, 89
VCC
Positive Supply Terminal.
39
RLD2
One of Two Complementary Inputs that Control, in Conjunction with IOD2 and IODB2, the Operating
Mode of the Channel 2 Driver. Refer to Table I for specific conditions.
40
IOD2
One of Two Complementary Inputs that Control, in Conjunction with RLD2 and RLDB2, the Operating
Mode of the Channel 2 Driver. Refer to Table I for specific conditions.
41
IODB2
One of Two Complementary Inputs that Control, in Conjunction with RLD2 and RLDB2, the Operating
Mode of the Channel 2 Driver. Refer to Table I for specific conditions.
42
DATA2
One of Two Complementary Inputs that Determine the High and Low State of the Channel 2 Driver.
Driver output is high for DATA2 > DATAB2. Refer to Table I for specific conditions.
43
DATAB2
One of Two Complementary Inputs that Determine the High and Low State of the Channel 2 Driver.
Driver output is high for DATA2 > DATAB2. Refer to Table I for specific conditions.
46
VCOM2
Analog Input Voltage that Establishes the Commutation Voltage for the Active Load Diode Bridge for Channel 2.
47
VH2
Analog Input Voltage that Sets the Logic 1 Level of the Driver Output Limit for Channel 2. Determines
the driver output for DATA2 > DATAB2.
48
VTERM2
Analog Input Voltage that Set the Termination Voltage Level of the Channel 2 Driver when in VTERM Mode.
49
VL2
Analog Input Voltage that Set the Logic 0 Level of the Driver Output Limit for Channel 2. Determines
the driver output for DATAB2 > DATA2.
50
HCOMP2
Analog Input Voltage that Sets the Logic 1 Compare Reference for the Window Comparator of Channel 2.
51
LCOMP2
Analog Input Voltage that Sets the Logic 0 Compare Reference for the Window Comparator of Channel 2.
56
QH2
One of Two Complementary Outputs for the Logic 1 Window Comparator of Channel 1.
57
QHB2
One of Two Complementary Outputs for the Logic 1 Window Comparator of Channel 1.
58
VCCO2
Input Supply Voltage for QH2, QHB2, QL2, and QLB2 Signals and Reference Voltage for DATA2, DATAB2,
IOD2, IODB2, RLD2, and RLDB2.
59
QLB2
One of Two Complementary Outputs for the Logic 0 Window Comparator of Channel 2.
–10–
REV. A
AD53522
Pin Number
Mnemonic
Description
60
QL2
One of Two Complementary Outputs for the Logic 0 Window Comparator of Channel 2.
61
RLDB2
One of Two Complementary Inputs that Control, in Conjunction with IOD2 and IODB2, the Operating
Mode of the Channel 2 Driver. Refer to Table I for specific conditions.
62
PWRD2
Power-Down Control for Channel 2.
63
GND_ROT
Analog Ground.
64
PWRD1
Power-Down Control for Channel 1.
65
RLDB1
One of Two Complementary Inputs that Control, in Conjunction with IOD1 and IODB1, the Operating
Mode of the Channel 1 Driver.
66
QL1
One of Two Complementary Outputs for the Logic 0 Window Comparator of Channel 1.
67
QLB1
One of Two Complementary Outputs for the Logic 0 Window Comparator of Channel 1.
68
VCCO1
Input Supply Voltage for QH1, QHB1, QL1, and QLB1 Signals and Reference Voltage for DATA1,
DATAB1, IOD1, IODB1, RLD1, and RLDB1.
69
QHB1
One of Two Complementary Outputs for the Logic 1 Window Comparator of Channel 1.
70
QH1
One of Two Complementary Outputs for the Logic 1 Window Comparator of Channel 1.
75
LCOMP1
Analog Input Voltage that Sets the Logic 0 Compare Reference for the Window Comparator of Channel 1.
76
HCOMP1
Analog Input Voltage that Sets the Logic 1 Compare Reference for the Window Comparator of Channel 1.
77
VL1
Analog Input Voltage that Sets the Logic 0 Level of the Driver Output Limit for Channel 1. Determines
the driver output for DATAB1 > DATA1.
78
VTERM1
Analog Input Voltage that Sets the Termination Voltage Level of the Channel 1 Driver when in VTERM Mode.
79
VH1
Analog Input Voltage that Sets the Logic 1 Level of the Driver Output Limit for Channel 1. Determines
the driver output for DATA1 > DATAB1.
80
VCOM1
Analog Input Voltage that Establishes the Commutation Voltage for the Active Load Diode Bridge for Channel 1.
83
DATAB1
One of Two Complementary Inputs that Determine the High and Low State of the Channel 1 Driver.
Driver output is high for DATA1 > DATAB1. Refer to the Driver Truth Table for specific conditions.
84
DATA1
One of Two Complementary Inputs that Determine the High and Low State of the Channel 1 Driver.
Driver output is high for DATA1 > DATAB1. Refer to the Driver Truth Table for specific conditions.
85
IODB1
One of Two Complementary Inputs that Control, in Conjunction with RLD1 and RLDB1, the Operating
Mode of the Channel 1 Driver. Refer to Table I for specific conditions.
86
IOD1
One of Two Complementary Inputs that Control, in Conjunction with RLD1 and RLDB1, the Operating
Mode of the Channel 1 Driver. Refer to Table I for specific conditions.
87
RLD1
One of Two Complementary Inputs that Control, in Conjunction with IOD1 and IODB1, the Operating
Mode of the Channel 1 Driver. Refer to Table I for specific conditions.
91
INHLB1
One of Two Complementary Inputs that Control the Inhibit Mode for the Active Load Bridge of Channel 1.
92
INHL1
One of Two Complementary Inputs that Control the Inhibit Mode for the Active Load Bridge of Channel 1.
93
HQGND
Clean Analog Ground for the Active Load for Channel 1.
94
IOHC1
Analog Input Voltage that Programs the Channel 1 Active Load Sink Current.
95
IOLC1
Analog Input Voltage that Programs the Channel 1 Active Load Source Current.
96
THERM
Temperature Sensor Output Pin. A resistor (10 kΩ) should be connected between THERM and V CC.
The approximate die temperature can be determined by measuring the current through the resistor. The
typical scale factor is 1 µA/°K.
97
VCOM_S1
Analog Output Voltage that Represents a Buffered VCOM1 Input.
100
PROT_LO1
Channel 1 Output Voltage Sensing Diode.
REV. A
–11–
AD53522
OUTLINE DIMENSIONS
100-Lead Low Profile Quad Flat Package, Integrated Heat Sink [LQFP-ED]
(SQ-100)
C02786–0–10/03(A)
Dimensions shown in millimeters
16.00 BSC SQ
1.60 MAX
0.75
0.60
0.45
SEATING
PLANE
14.00 BSC SQ
100
1
76
75
PIN 1
9.78
9.65
9.40
BOTTOM VIEW
(PINS DOWN)
1.45
1.40
1.35
12.00
REF
0.20
0.09
0.15
0.05
0.08
MAX LEAD
COPLANARITY
7ⴗ
3.5ⴗ
0ⴗ
VIEW A
50
25
26
0.50 BSC
VIEW A
ROTATED 90ⴗ CCW
49
0.27
0.22
0.17
COMPLIANT TO JEDEC STANDARDS MS-026BED-HU
Revision History
Location
Page
10/03—Data Sheet changed from REV. 0 to REV. A.
Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–12–
REV. A