Altera EPXA1 Excalibur device overview Datasheet

Excalibur Device Overview
May 2002, ver. 2.0
Features...
Data Sheet
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Altera Corporation
DS-EXCARM-2.0
Combination of a world-class RISC processor system with industryleading programmable logic on a single device
Industry-standard ARM922T™ 32-bit RISC processor core operating
at up to 200 MHz
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ARMv4T instruction set with Thumb® extensions
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Memory management unit (MMU) included for real-time
operating system (RTOS) support
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Harvard cache architecture with 64-way set associative separate
8-Kbyte instruction and 8-Kbyte data caches
APEX™ 20KE-like programmable logic architecture ranging from
100,000 to 1,000,000 gates (see Table 1 on page 3)
Advanced bus architecture based on advanced microcontroller bus
architecture (AMBA™) high-performance bus (AHB)
Embedded programmable on-chip peripherals
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ETM9 embedded trace module to assist software debugging
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Flexible interrupt controller
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Universal asynchronous receiver/transmitter (UART)
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General-purpose timer
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Watchdog timer
Advanced memory support
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Internal single-port SRAM up to 256 Kbytes
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Internal dual-port SRAM up to 128 Kbytes
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Internal SDRAM controller
Single data-rate (SDR) and double data-rate (DDR) support
Up to 512 Mbytes
Data rates to 133 (266) MHz
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Expansion bus interface (EBI)
Compatible with industry-standard flash memory, SRAMs,
and peripheral devices
Four devices, each up to 32 Mbytes
PLD configuration/reconfiguration possible via the embedded
processor software
Fully configurable memory map
Extensive embedded system debug facilities
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SignalTap™ embedded logic analyzer
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ARM® JTAG processor debug support
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Real-time data/instruction processor trace
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Background debug monitoring via the IEEE Std. 1149.1 (JTAG)
interface
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Excalibur Device Overview
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Multiple and separate clock domains controlled by softwareprogrammable phased-lock loops (PLLs) for embedded
processor, SDRAM, and PLD
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ClockBoost™ circuitry provides clock multiplication for the
embedded stripe and the PLD
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ClockLock™ circuitry reduces clock delay and skew in the
PLD
Advanced packaging options (see Tables 2 and 3 on page 3)
1.8-V supply voltage, but many I/O standards supported:
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SSTL-3
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LVTTL
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GTL+
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LVDS
SOPC Builder system development tool
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Intuitive graphical user interface (GUI) simplifies system
definition and customization
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Wizard interface facilitates function customization for each
component
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Automatically-generated logic integrates processors,
memories, peripherals, IP cores, on-chip buses and bus
arbiters
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VHDL or Verilog HDL code created for system connection
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Software develoment environment generated to match the
target hardware
Extended Quartus™ II development environment for Excalibur™
support
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Integrated hardware and software development
environment
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MegaWizard® Plug-In interface configures the embedded
processor, PLD, bus connections, and peripherals
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C/C++ compiler, source-level debugger, and RTOS support
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This document provides updated information about
Excalibur devices and should be used together with the
APEX 20K Programmable Logic Device Family Data Sheet.
Altera Corporation
Excalibur Device Overview
Table 1. Excalibur Device Overview
Feature
Processor
EPXA1
EPXA4
EPXA10
ARM922T
ARM922T
ARM922T
Maximum operating frequency
200 MHz
200 MHz
200 MHz
Single-port SRAM
32 Kbytes
128 Kbytes
256 Kbytes
Dual-port SRAM
16 Kbytes
64 Kbytes
128 Kbytes
100,000
400,000
1,000,000
4,160
16,640
38,400
Typical gates
Logic elements (LEs)
Embedded system blocks (ESBs)
Maximum system gates
26
104
160
263,000
1,052,000
1,772,000
Maximum user I/Os (1)
246
488
711
UART, timer, watchdog timer
Yes
Yes
Yes
JTAG debug module
Yes
Yes
Yes
Embedded trace module
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Yes
Yes
General purpose I/O Port
4 bits
8 bits
-
Yes
-
-
Low-power PLL
Note:
(1)
Maximum available user I/Os = shared stripe I/O + PLD I/O
Table 2. Excalibur Device FineLine™ BGA Package Sizes
Feature
FineLine BGA
484 Pin
672 Pin
Pitch (mm)
1.00
1.00
1.00
2
529
729
1,089
23 × 23
27 × 27
33 × 33
Area (mm )
Length × Width (mm × mm)
1,020 Pin
Table 3. Excalibur Device FineLine BGA Package Options & User I/O
Counts Note (1)
Device
FineLine BGA
484 Pin
EPXA1
EPXA4
186
672 Pin
1,020 Pin
246
426
EPXA10
488
711
Note to Tables 2 and 3:
(1)
Altera Corporation
I/O counts include dedicated input and clock pins.
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Excalibur Device Overview
General
Description
Devices belonging to the Excalibur family combine an unparalleled
degree of integration and programmability. They offer an
outstanding embedded system development platform, providing a
cost-efficient access to leading-edge embedded processors and PLD
performance.
The Excalibur family offers a variety of PLD densities and memory
sizes to fit a wide range of applications and requirements. The highperformance embedded architecture is ideal for compute-intensive
as well as high data-bandwidth applications.
Figure 1 shows the structure of the Excalibur devices. The embedded
stripe contains the processor core, peripherals, and memory
subsystem. The amounts of single- and dual-port memory vary as
listed in Table 1 on page 3.
Figure 2 on page 5 shows the system architecture of the embedded
stripe and the interfaces to the PLD portion of the devices. This
architecture promotes maximum integration with minimal system
cost and allows the embedded stripe and PLD to be independently
optimized for maximum performance.
Figure 1. Excalibur Architecture
JTAG
PLL
UART
External
Memory
Interfaces
Trace
Module
Interrupt
Controller
ARM922T
SRAM
SRAM
SRAM
Embedded
Processor
Stripe
Timer
Watchdog
Timer
DPRAM
DPRAM
DPRAM
XA1
32 Kbytes SRAM
16 Kbytes DPRAM
PLD
XA4
128 Kbytes SRAM
64 Kbytes DPRAM
XA10
256 Kbytes SRAM
128 Kbytes DPRAM
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Altera Corporation
Excalibur Device Overview
Figure 2. Excalibur System Architecture
External
Interface
Ports
SDRAM
Flash
ROM
SRAM
Embedded Processor Stripe
ARM922T
+ Cache
+ MMU
Interrupt
Controller
Watchdog
Timer
SDRAM
Controller
EBI
UART
AHB1
AHB1-2
Bridge
Configuration
Logic
Master
Slave
Master
AHB2
Master
Slave
PLDToStripe
Bridge
AHB
Slave
Port
DualPort
SRAM 0
Port A
SinglePort
SRAM 0
PLL
Reset
Module
Timer
StripeToPLD
Bridge
Slave
Master
AHB
Master
Port
Stripe Interface
Port B
Used for dual-port SRAM with dedicated
PLD access (no access to AHB1 and
AHB2)
PLD
Master(s)
User Modules Requiring
Direct Access to Large
Dual-Port or Single-Port RAMs
User's Slave Modules in the PLD
PLD
PLD Clock Domain(s)
Altera Corporation
AHB2 Clock Domain
Processor Clock Domain (AHB1)
SDRAM Clock Domain
Bus Control
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Excalibur Device Overview
Two AMBA-compliant AHBs ensure that the embedded processor
activity is unaffected by peripheral and memory operation. Three
bidirectional AHB-to-AHB bridges enable embedded peripherals
and PLD-implemented peripherals to exchange data with the
embedded processor or with other peripherals.
The Excalibur family is supported by the following development
tools:
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Functional
Description
SOPC Builder from Altera®
Quartus II from Altera
ADS, GNUPro and other third-party tools
The Excalibur system architecture (embedded processor bus
structure, on-chip memory, and peripherals) combines the
performance advantages of ASIC integration with the flexibility and
time-to-market advantages of PLDs.
The Embedded Processor
The ARM922T is a member of the ARM9 family of processor cores.
Its Harvard architecture, implemented using a five-stage pipeline,
allows single clock-cycle instruction operation through
simultaneous fetch, decode, execute, memory, and write stages.
Figure 3 on page 7 shows the Excalibur embedded processor, the
ARM922T.
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Altera Corporation
Excalibur Device Overview
Figure 3. ARM922T Embedded Processor Internal Organization
IPA(31..0)
Instruction
MMU
Instruction
Cache
(8 Kbyte)
Embedded
Trace
Module
C13
IMVA(31..0)
IVA(31..0)
JTAG
ARM9TDMI
Processor Core
(+ Embedded ICE
Interface)
ID(31..0)
AMBA
Bus
Interface
DD(31..0)
AHB
Write
Data
Buffer
DVA(31..0)
DMVA(31..0)
C13
Data MMU
Data Cache
(8 Kbyte)
Write-Back
Page
Address
TAG RAM
WBPA(31..0)
DPA(31..0)
C13
Context Identification Register
Independent of PLD configuration, the embedded processor can
undertake the following activities:
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Boot from external memory
Execute embedded software
Communicate with the external world
Run a real-time operating system
Run interactive embedded software debugging sessions
Configure/reconfigure the PLD
Detect errors and restart/reboot/reconfigure the entire system
as necessary
The PLD can be configured to implement various extensions:
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Altera Corporation
Additional soft-core peripherals such as a UART, Ethernet
MAC, CAN controllers, PCI, or any other IP core
Peripherals that are bus masters, sharing the embedded stripe
on-chip and off-chip memories as well as other PLD peripheral
Peripherals that are slaves, controlled by the embedded
processor
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Excalibur Device Overview
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Peripherals that exchange data using the on-chip dual-port
RAM
High speed data paths under embedded processor control
Multi-processor systems, using multiple Nios embedded
processor solutions
Additional embedded processor interrupt sources and controls
PLD designers can take full advantage of the extensive range of
Altera intellectual property (IP) Megacore® functions to implement
complex system-on-a-programmable-chip (SOPC) designs in
minimal time but with maximum customization.
The bidirectional bridges and dual-port memory interfaces between
the embedded stripe and the PLD are synchronous to the clock
domain that drives them; however, the embedded processor domain
and the PLD domains are asynchronous. The clock domain for each
side of the interfaces can be optimized for performance. The
bidirectional bridges handle the resynchronization across the
domains and are capable of supporting 32-bit data accesses to the
entire 4-Gbyte address range (32-bit address bus).
The SDRAM memory controller PLL allows users to tune the
frequency of the system clock to the speed of the external memory
implemented in their systems.
Internal Memory
The embedded stripe contains both single-port and dual-port SRAM.
There are two blocks of single-port SRAM; both are accessible to the
AHB masters via an arbitrated interface within memory. Each block
is independently arbitrated, allowing one block to be accessed by one
bus master while the other block is accessed by the other bus master.
Up to 256 Kbytes of single-port SRAM are available, as two blocks of
2 × 128 Kbytes. Each single-port SRAM block is byte-addressable.
The size of the SRAM blocks depends on the device, as shown in
Table 1. Byte, half-word and word accesses are allowed and are
enabled by the slave interface. The behavior of byte and half-word
reads is controlled by the system endianness.
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Altera Corporation
Excalibur Device Overview
In addition, there are either one or two blocks of dual-port SRAM in
the embedded stripe, depending on the device type. The outputs of
the dual-port memories can be registered. One of the ports gives
dedicated access to the PLD; the other port can be configured for
access by AHB masters or by the PLD. The width of the data port to
the PLD is configurable as ×8, ×16, or ×32 bits. For the larger devices,
the dual-port SRAM blocks can be combined to form a ×64-bit datawidth interface. This allows the designer to build deeper and wider
memories and multiplex the data outputs within the stripe.
External Memory Controllers
The Excalibur family provides two embedded memory controllers
that can be accessed by any of the bus masters: one for external
SDRAM, and a second for external flash memory or SRAM.
The SDRAM memory controller supports the following commonlyavailable memory standards, without the addition of any logic:
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Single-data rate (SDR) 133-MHz data rates
Double-data rate (DDR) 266-MHz data rates
An embedded stripe PLL supplies the appropriate timing to the
SDRAM memory controller subsystem. Users can program the
frequency to match the chosen memory components.
The EBI supports the interface to system ROM, allowing external
flash memory access and reprogramming. In addition, static RAM
and simple peripherals can be connected to this interface externally.
Embedded Peripherals
A single 16-Kbyte memory region in the embedded stripe contains
configuration and control registers, plus status and control registers
for the embedded peripherals. The region contains the following
modules:
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Altera Corporation
Configuration Registers
Embedded Stripe PLLs
UART
Timer
Watchdog timer
General Purpose I/O Port
Interrupt controller
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Excalibur Device Overview
Software
Development
Tools
In a co-development environment where both the hardware and
software components constitute an integral part of the embedded
processor PLD design process, Altera provides seamless support
with SOPC Builder and Quartus II; ADS, GNUPro and third-party
development tools are also available.
See the Altera web site, http://www.altera.com, for details of the
software development tools.
Excalibur devices are compatible with any available tools
for the ARM922T from ARM or third parties.
SOPC Builder
SOPC Builder allows embedded system designers to create systemon-a-programmable-chip (SOPC) designs in a fraction of the time
traditionally required for embedded system-on-chip (SOC) design.
It provides an intuitive GUI that simplifies the definition and
customization of a user’s system. Designers select and parameterize
IP blocks from a drop-down list of communication, digital signal
processing (DSP), microprocessor, and bus interface cores. Then
SOPC Builder automatically generates all of the logic necessary to
integrate them and also uses the specified system information to
create appropriate VHDL or Verilog HDL code to connect the system
components together, resulting in an HDL description of the entire
system.
SOPC Builder automatically generates a software development
environment that matches the target hardware, saving days or weeks
of software design time, and jump-starts software development with
components such as the following:
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Header files that define memory maps, interrupt priorities and
data structures corresponding to each hardware peripheral
Routines to access hardware peripherals in the system
OS/RTOS kernels with appropriate hardware drivers
SOPC Builder automatically generates a simulation model of the
system, a test bench for the system, and a full environment for
immediate system simulation.
Figure 4 on page 11 shows an example of an SOPC Builder screen.
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Altera Corporation
Excalibur Device Overview
Figure 4. Sample SOPC Builder Screen
Quartus II
The Quartus II development system can be used for both PLD logic
design and the integration of embedded software. The Quartus II
software provides an integrated package for complete hardware
logic design, including HDL and schematic design entry,
compilation and logic synthesis, full simulation and timing analysis,
and programming file generation, as well as hardware logic debug
using SignalTap logic analyzer.
Altera Corporation
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Excalibur Device Overview
With the Quartus II SoftMode™ co-design capability, embedded
software development, debugger support, and unified
programming file generation can be easily combined from a single
integrated design environment (IDE). The Quartus II tools are preconfigured to support embedded software development tools such
as the ARM Developer Suite or Red Hat GNUPro Tools for
ARM922T processors. The Quartus II software operates on
Windows-based PCs, Sun SPARCstations, and HP 9000 Series
700/800 workstations. The Quartus II software provides
NativeLink® integration to third-party, industry-standard PC and
UNIX workstation-based electronic design automation (EDA) tools.
Figure 5 shows the Quartus II development tool flow.
Figure 5. Quartus II Development Tool Flow
SOPC
Builder
Hardware
Design Entry
Excalibur
MegaWizard
Software
Design Entry
Assemble,
Compile and Link
Synthesis
Software
Executable
Image
Place and Route
PLD
Configuration
Image
Image
Conversion
Configuration
Device
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Flash
Image
Serial
Bitstream
Altera Corporation
Excalibur Device Overview
Altera supplies a variety of embedded software functions to support
flash memory programming and PLD configuration.
Configuration
Excalibur devices are configured at system power-up with data
stored in a configuration device or flash memory. The same memory
can store application software for the embedded processor. The user
can reconfigure the device in-circuit by using the on-chip processor,
using configuration data stored anywhere in its memory system. The
user can make real-time changes during system operation, which
enables innovative reconfigurable computing applications.
Simulation Model
Initial simulation models of the ARM922T are compatible with the
following simulators:
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Quartus II simulator
Cadence NC-Verilog and NC-VHDL simulators
ModelSim simulator
Synopsys VCS simulator
Trace
A trace port provided on the ETM9 is compatible with the external
trace analysis tools. This feature allows real-time visibility of
embedded processor execution, and is tightly integrated with the
source-level debugging tools.
Excalibur Development Kit
Altera offers separately an Excalibur development kit, which
includes a development board compatible with the EPXA10 device.
Figure 6 on page 14 illustrates the Altera Excalibur development
board, showing the provision for board expansion.
Altera Corporation
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Excalibur Device Overview
Figure 6. Excalibur Development Board
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2
3
4
5
6
6
7
6
6
9
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8
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11
12
15
14
12
8
8
13
+
+
+
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Key
1 RS232 Connector for
embedded UART
2 Second (soft) UART
3 RJ45 Connector
4 Transformer
5 Clk_ref
6 4-Mbyte Flash Memory x 4
7 PHY Transceiver
8 Daughter Card Connector
9 PCI Connectors
10 Mictor Connector (EBI)
11 Mictor Connector (JTAG)
12 Mictor Connector (SDRAM) x 2
13 Mictor Connector (ETM9)
14 SDRAM DIMM Module
15 Mictor Connector (UART + EBI)
16 Power Supply x 2
17 ATX Connector PSU
18 MasterBlaster Connector
19 Multi-ICE Connector
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18
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Excalibur Device Overview
The EPXA10 development kit provides a powerful platform for
designing embedded processor PLD solutions. The kit features the
EPXA10 device, a member of the Excalibur family with an
ARM922T-based processor subsystem tightly coupled to the PLD
fabric. The EPXA10 development kit delivers flexible debug and
trace facilities to support the system under development, connection
cables and a full complement of software solutions including SOPC
Builder to generate the system, utilities and resource material,
third-party demo and evaluation software and documentation. The
development kit is the ideal development platform for complete
SOPC designs based on Excalibur devices for both ASIC prototyping
and low-to-moderate volume production runs.
Typical
Application
Figure 7 on page 15 shows how the Excalibur device and other
elements can be integrated in an application. In this example, the
Excalibur device is configured for a voice-over packet gateway
application. The elements of the embedded processor stripe, PLD
modules, and off-chip peripherals are clearly identified.
Figure 7. Excalibur Device in a Voice-Over Packet Gateway Application
ARM-Based Embedded Processor Device
Time Division
Multiplexing
Private
Branch
Exchange
Interface
Multiplexer/
Demultiplexer
Echo
Cancellation
PHY
PHY
10/100
Ethernet
MAC
10/100
Ethernet
MAC
Customer Implementation
ARM-Based Embedded Processor Stripe
Altera IP Implementation
ARM922T
Embedded
Processor
Packet/Voice
Conversion
HDLC
xDSL
HDLC
T1
CAM
ATM
SAR
SDRAM
Controller
Expansion
Bus
Interface
SDRAM
Boot
Flash
UTOPIA
Bus
Interface
ATM
Uplink
Non-PLD Solution
Altera Corporation
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Excalibur Device Overview
Revision History
This document provides updated information as described below.
Version 2.0
This version provides updated information, including:
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Device features and package sizes
Functional description
Software development tools
Excalibur development boards
Version 1.2
This version provides updated information, including:
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Operating speed and other device features
Updated system architecture (Figure 2)
Minor textual changes
Version 1.1
This version provides updated information, including:
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Literature Services:
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16
Revised maximum amount of external SDRAM supported
Minor formatting and textual changes
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