Intel A80960KB20 Embedded 32-bit microprocessor with integrated floating-point unit Datasheet

80960KB
80960KB
EMBEDDED 32-BIT MICROPROCESSOR
WITH INTEGRATED FLOATING-POINT UNIT
■ High-Performance Embedded
■ Built-in Interrupt Controller
Architecture
— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Execution at
25 MHz
■ 512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached
Instructions
■ Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored
On-Chip
— Register Scoreboarding
■ 4 Gigabyte, Linear Address Space
— 31 Priority Levels, 256 Vectors
— 3.4 µs Latency @ 25 MHz
■ Easy to Use, High Bandwidth 32-Bit Bus
— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
■ 132-Lead Packages:
— Pin Grid Array (PGA)
— Plastic Quad Flat-Pack (PQFP)
■ On-Chip Floating Point Unit
— Supports IEEE 754 Floating Point
Standard
— Four 80-Bit Registers
— 13.6 Million Whetstones/s (Single
Precision) at 25 MHz
■ Pin Compatible with 80960KA
FOUR
80-BIT FP
REGISTERS
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
80-BIT
FPU
32-BIT
BUS CONTROL
LOGIC
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICROINSTRUCTION
SEQUENCER
MICROINSTRUCTION
ROM
32-BIT
BURST
BUS
Figure 1. The 80960KB Processor’s Highly Parallel Architecture
© INTEL CORPORATION, 2004
August, 2004
Order Number: 270565-008
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Copyright © Intel Corporation 1997, 2004
Contents
80960KB
EMBEDDED 32-BIT MICROPROCESSOR
1.0 THE i960® PROCESSOR .......................................................................................................................... 1
1.1 Key Performance Features ................................................................................................................. 2
1.1.1 Memory Space And Addressing Modes ................................................................................... 4
1.1.2 Data Types ............................................................................................................................... 4
1.1.3 Large Register Set ................................................................................................................... 4
1.1.4 Multiple Register Sets .............................................................................................................. 5
1.1.5 Instruction Cache ..................................................................................................................... 5
1.1.6 Register Scoreboarding ........................................................................................................... 5
1.1.7 High Bandwidth Local Bus ....................................................................................................... 6
1.1.8 Interrupt Handling .................................................................................................................... 6
1.1.9 Debug Features ....................................................................................................................... 6
1.1.10 Fault Detection ....................................................................................................................... 7
1.1.11 Built-in Testability ................................................................................................................... 7
2.0 ELECTRICAL SPECIFICATIONS ............................................................................................................ 10
2.1 Power and Grounding ....................................................................................................................... 10
2.2 Power Decoupling Recommendations ............................................................................................. 10
2.3 Connection Recommendations ........................................................................................................ 11
2.4 Characteristic Curves ....................................................................................................................... 11
2.5 Test Load Circuit ............................................................................................................................... 14
2.7 DC Characteristics ............................................................................................................................ 15
2.6 Absolute Maximum Ratings .............................................................................................................. 15
2.8 AC Specifications ............................................................................................................................. 16
2.8.1 AC Specification Tables ......................................................................................................... 17
3.0 MECHANICAL DATA ................................................................................................................................ 21
3.1 Packaging ......................................................................................................................................... 21
3.1.1 Pin Assignment ...................................................................................................................... 21
3.2 Pinout ............................................................................................................................................... 25
3.3 Package Thermal Specification ........................................................................................................ 29
4.0 WAVEFORMS .......................................................................................................................................... 33
5.0 REVISION HISTORY ............................................................................................................................... 38
iii
Contents
FIGURES
Figure 1.
80960KA Programming Environment ........................................................................................ 1
Figure 2.
Instruction Formats .................................................................................................................... 4
Figure 3.
Multiple Register Sets Are Stored On-Chip ............................................................................... 6
Figure 4.
Connection Recommendations for Low Current Drive Network .............................................. 11
Figure 5.
Connection Recommendations for High Current Drive Network .............................................. 11
Figure 6.
Typical Supply Current vs. Case Temperature ......................................................................... 12
Figure 7.
Typical Current vs. Frequency (Room Temp) .......................................................................... 12
Figure 8.
Typical Current vs. Frequency (Hot Temp) .............................................................................. 13
Figure 9.
Worst-Case Voltage vs. Output Current on Open-Drain Pins .................................................. 13
Figure 10.
Capacitive Derating Curve ....................................................................................................... 13
Figure 11.
Test Load Circuit for Three-State Output Pins ......................................................................... 14
Figure 12.
Test Load Circuit for Open-Drain Output Pins .......................................................................... 14
Figure 13.
Drive Levels and Timing Relationships for 80960KA Signals .................................................. 16
Figure 14.
Processor Clock Pulse (CLK2) ........................................................................................ ........ 20
Figure 15.
RESET Signal Timing ................................................................................................. ............. 20
Figure 16.
132-Lead Pin-Grid Array (PGA) Package ............................................................................... . 21
Figure 17.
80960KA PGA Pinout—View from Bottom (Pins Facing Up) ................................................... 22
Figure 18.
80960KA PGA Pinout—View from Top (Pins Facing Down) .................................................... 23
Figure 19.
80960KA 132-Lead Plastic Quad Flat-Pack (PQFP) Package ................................................ 23
Figure 20.
PQFP Pinout - View From Top ................................................................................................. 24
Figure 21.
HOLD Timing ........................................................................................................................... 30
Figure 22.
16 MHz Maximum Allowable Ambient Temperature ................................................................ 31
Figure 23.
20 MHz Maximum Allowable Ambient Temperature ................................................................ 31
Figure 24.
25 MHz Maximum Allowable Ambient Temperature ................................................................ 32
Figure 25.
Maximum Allowable Ambient Temperature
for the Extended Temperature 80960KA at 20 MHz in PGA Package ...................................... 32
Figure 27.
Burst Read and Write Transaction Without Wait States ........................................................... 34
Figure 28.
Burst Write Transaction with 2, 1, 1, 1 Wait States .................................................................. 35
Figure 29.
Accesses Generated by Quad Word Read Bus Request,
Misaligned Two Bytes from Quad Word Boundary (1, 0, 0, 0 Wait States) .............................. 36
Figure 30.
Interrupt Acknowledge Transaction ......................................................................................... 37
iv
Contents
TABLES
Table 1.
80960KA Instruction Set ............................................................................................................ 3
Table 2.
Memory Addressing Modes ....................................................................................................... 4
Table 3.
80960KA Pin Description: L-Bus Signals ................................................................................... 8
Table 4.
80960KA Pin Description: Support Signals ............................................................................... 9
Table 5.
DC Characteristics ................................................................................................................... 15
Table 6.
80960KA AC Characteristics (16 MHz) ................................................................................... 17
Table 7.
80960KA AC Characteristics (20 MHz) ................................................................................... 18
Table 9.
80960KA PGA Pinout — In Pin Order ..................................................................................... 25
Table 10.
80960KA PGA Pinout — In Signal Order ................................................................................ 26
Table 11.
80960KA PQFP Pinout — In Pin Order ................................................................................... 27
Table 12.
80960KA PQFP Pinout — In Signal Order .............................................................................. 28
Table 13.
80960KA PGA Package Thermal Characteristics ................................................................... 29
Table 14.
80960KA PQFP Package Thermal Characteristics ................................................................. 30
v
80960KB
1.0
THE i960® PROCESSOR
The 80960KB is a member of Intel’s i960® 32-bit
processor family, which is designed especially for
embedded applications. It includes a 512-byte
instruction cache, an integrated floating-point unit
and a built-in interrupt controller. The 80960KB has
a large register set, multiple parallel execution units
and a high-bandwidth burst bus. Using advanced
RISC technology, this high performance processor is
capable of execution rates in excess of 9.4 million
instructions per second*. The 80960KB is well-suited
for a wide range of applications including non-impact
printers, I/O control and specialty instrumentation.
The embedded market includes applications as
diverse as industrial automation, avionics, image
processing, graphics and networking. These types of
* Relative to Digital Equipment Corporation’s VAX-11/780
at 1 MIPS (VAX-11™ is a trademark of Digital Equipment
Corporation)
applications require high integration, low power
consumption, quick interrupt response times and
high performance. Since time to market is critical,
embedded microprocessors need to be easy to use
in both hardware and software designs.
All members of the i960 processor family share a
common core architecture which utilizes RISC
technology so that, except for special functions, the
family members are object-code compatible. Each
new processor in the family adds its own special set
of functions to the core to satisfy the needs of a
specific application or range of applications in the
embedded market.
Software written for the 80960KB will run without
modification on any other member of the 80960
Family. It is also pin-compatible with the 80960KA
and the 80960MC which is a military-grade version
that supports multitasking, memory management,
multiprocessing and fault tolerance.
0000 0000H
FFFF FFFFH
ADDRESS SPACE
ARCHITECTURALLY
DEFINED
DATA STRUCTURES
FETCH
LOAD
STORE
INSTRUCTION CACHE
INSTRUCTION
STREAM
INSTRUCTION
EXECUTION
PROCESSOR STATE
REGISTERS
INSTRUCTION
POINTER
g0
g15
SIXTEEN 32-BIT GLOBAL REGISTERS
REGISTER CACHE
SIXTEEN 32-BIT LOCAL REGISTERS
r0
r15
ARITHMETIC
CONTROLS
PROCESS
CONTROLS
TRACE
CONTROLS
FOUR 80-BIT FLOATING POINT REGISTERS
CONTROL REGISTERS
Figure 2. 80960KB Programming Environment
1
80960KB
1.1
Key Performance Features
The 80960 architecture is based on the most recent
advances in microprocessor technology and is
grounded in Intel’s long experience in the design and
manufacture of embedded microprocessors. Many
features contribute to the 80960KB’s exceptional
performance:
1. Large Register Set. Having a large number of
registers reduces the number of times that a
processor needs to access memory. Modern
compilers can take advantage of this feature to
optimize execution speed. For maximum flexibility, the 80960KB provides thirty-two 32-bit
registers and four 80-bit floating point registers.
(See Figure 2.)
2. Fast Instruction Execution. Simple functions
make up the bulk of instructions in most
programs so that execution speed can be
improved by ensuring that these core instructions are executed as quickly as possible. The
most frequently executed instructions such as
register-register moves, add/subtract, logical
operations and shifts execute in one to two
cycles. (Table 1 contains a list of instructions.)
3. Load/Store Architecture. One way to improve
execution speed is to reduce the number of
times that the processor must access memory
to perform an operation. As with other
processors based on RISC technology, the
80960KB has a Load/Store architecture. As
such, only the LOAD and STORE instructions
reference memory; all other instructions
operate on registers. This type of architecture
simplifies instruction decoding and is used in
combination with other techniques to increase
parallelism.
4. Simple Instruction Formats. All instructions
in the 80960KB are 32 bits long and must be
aligned on word boundaries. This alignment
makes it possible to eliminate the instruction
alignment stage in the pipeline. To simplify the
instruction decoder, there are only five
instruction formats; each instruction uses only
one format. (See Figure 3.)
5. Overlapped Instruction Execution. Load
operations allow execution of subsequent
instructions to continue before the data has
been returned from memory, so that these
instructions can overlap the load. The
80960KB manages this process transparently
2
to software through the use of a register scoreboard. Conditional instructions also make use
of a scoreboard so that subsequent unrelated
instructions may be executed while the conditional instruction is pending.
6. Integer Execution Optimization. When the
result of an arithmetic execution is used as an
operand in a subsequent calculation, the value
is sent immediately to its destination register.
Yet at the same time, the value is put on a
bypass path to the ALU, thereby saving the
time that otherwise would be required to
retrieve the value for the next operation.
7. Bandwidth Optimizations. The 80960KB gets
optimal use of its memory bus bandwidth
because the bus is tuned for use with the
on-chip instruction cache: instruction cache
line size matches the maximum burst size for
instruction fetches. The 80960KB automatically
fetches four words in a burst and stores them
directly in the cache. Due to the size of the
cache and the fact that it is continually filled in
anticipation of needed instructions in the
program flow, the 80960KB is relatively insensitive to memory wait states. The benefit is that
the 80960KB delivers outstanding performance
even with a low cost memory system.
8. Cache Bypass. If a cache miss occurs, the
processor fetches the needed instruction then
sends it on to the instruction decoder at the
same time it updates the cache. Thus, no extra
time is spent to load and read the cache.
80960KB
Table 1. 80960KB Instruction Set
Data Movement
Load
Store
Move
Load Address
Comparison
Arithmetic
Add
Subtract
Multiply
Divide
Remainder
Modulo
Shift
Branch
Compare
Unconditional Branch
Conditional Compare
Conditional Branch
Compare and Increment Compare and Branch
Compare and Decrement
Debug
Modify Trace Controls
Mark
Force Mark
Synchronous
Synchronous Load
Synchronous Move
Miscellaneous
Atomic Add
Atomic Modify
Flush Local Registers
Modify Arithmetic
Controls
Scan Byte for Equal
Test Condition Code
Modify Process Controls
Logical
And
Not And
And Not
Or
Exclusive Or
Not Or
Or Not
Exclusive Nor
Not
Nand
Rotate
Call/Return
Call
Call Extended
Call System
Return
Branch and Link
Decimal
Decimal Move
Decimal Add with Carry
Decimal Subtract with
Carry
Bit and Bit Field
Set Bit
Clear Bit
Not Bit
Check Bit
Alter Bit
Scan For Bit
Scan Over Bit
Extract
Modify
Fault
Conditional Fault
Synchronize Faults
Floating Point
Move Real
Add
Subtract
Multiply
Divide
Remainder
Scale
Round
Square Root
Sine
Cosine
Tangent
Arctangent
Log
Log Binary
Log Natural
Exponent
Classify
Copy Real Extended
Compare
Conversion
Convert Real to Integer
Convert Integer to Real
3
80960KB
OpcodeDisplacement
Control
Compare and
Branch
Register to
Register
Memory
Access—Short
Memory
Access—Long
OpcodeReg/LitRegMDisplacement
OpcodeRegReg/LitModesExt’d OpReg/Lit
OpcodeRegBaseMXOffset
OpcodeRegBaseModeScalexxOffset
Displacement
Figure 3. Instruction Formats
1.1.1
Memory Space And Addressing Modes
1.1.2
Data Types
The 80960KB offers a linear programming
environment so that all programs running on the
processor are contained in a single address space.
Maximum address space size is 4 Gigabytes (232
bytes).
The 80960KB recognizes the following data types:
For ease of use the 80960KB has a small number of
addressing modes, but includes all those necessary
to ensure efficient execution of high-level languages
such as C. Table 2 lists the modes.
• 32-, 64- and 80-bit real numbers
Table 2. Memory Addressing Modes
• 12-Bit Offset
• 32-Bit Offset
• Register-Indirect
• Register + 12-Bit Offset
• Register + 32-Bit Offset
• Register + (Index-Register x Scale-Factor)
• Register x Scale Factor + 32-Bit Displacement
• Register + (Index-Register x Scale-Factor) +
32-Bit Displacement
• Scale-Factor is 1, 2, 4, 8 or 16
4
Numeric:
• 8-, 16-, 32- and 64-bit ordinals
• 8-, 16-, 32- and 64-bit integers
Non-Numeric:
• Bit
• Bit Field
• Triple Word (96 bits)
• Quad-Word (128 bits)
1.1.3
Large Register Set
The 80960KB programming environment includes a
large number of registers. In fact, 32 registers are
available at any time. The availability of this many
registers greatly reduces the number of memory
accesses required to perform algorithms, which
leads to greater instruction processing speed.
There are two types of general-purpose registers:
local and global. The 20 global registers consist of
sixteen 32-bit registers (G0 though G15) and four
80-bit registers (FP0 through FP3). These registers
80960KB
perform the same function as the general-purpose
registers provided in other popular microprocessors.
The term global refers to the fact that these registers
retain their contents across procedure calls.
The local registers, on the other hand, are procedure
specific. For each procedure call, the 80960KB
allocates 16 local registers (R0 through R15). Each
local register is 32 bits wide. Any register can also be
used for single or double-precision floating-point
operations; the 80-bit floating-point registers are
provided for extended precision.
1.1.4
Multiple Register Sets
To further increase the efficiency of the register set,
multiple sets of local registers are stored on-chip
(See Figure 4). This cache holds up to four local
register frames, which means that up to three
procedure calls can be made without having to
access the procedure stack resident in memory.
Although programs may have procedure calls nested
many calls deep, a program typically oscillates back
and forth between only two to three levels. As a
result, with four stack frames in the cache, the
probability of having a free frame available on the
cache when a call is made is very high. In fact, runs
of representative C-language programs show that
80% of the calls are handled without needing to
access memory.
If four or more procedures are active and a new
procedure is called, the 80960KB moves the oldest
local register set in the stack-frame cache to a
procedure stack in memory to make room for a new
set of registers. Global register G15 is the frame
pointer (FP) to the procedure stack.
Global and floating point registers are not
exchanged on a procedure call, but retain their
contents, making them available to all procedures for
fast parameter passing.
1.1.5
Instruction Cache
To further reduce memory accesses, the 80960KB
includes a 512-byte on-chip instruction cache. The
instruction cache is based on the concept of locality
of reference; most programs are not usually
executed in a steady stream but consist of many
branches, loops and procedure calls that lead to
jumping back and forth in the same small section of
code. Thus, by maintaining a block of instructions in
cache, the number of memory references required to
read instructions into the processor is greatly
reduced.
To load the instruction cache, instructions are
fetched in 16-byte blocks; up to four instructions can
be fetched at one time. An efficient prefetch
algorithm increases the probability that an instruction
will already be in the cache when it is needed.
Code for small loops often fits entirely within the
cache, leading to a great increase in processing
speed since further memory references might not be
necessary until the program exits the loop. Similarly,
when calling short procedures, the code for the
calling procedure is likely to remain in the cache so it
will be there on the procedure’s return.
1.1.6
Register Scoreboarding
The instruction decoder is optimized in several ways.
One optimization method is the ability to overlap
instructions by using register scoreboarding.
Register scoreboarding occurs when a LOAD moves
a variable from memory into a register. When the
instruction initiates, a scoreboard bit on the target
register is set. Once the register is loaded, the bit is
reset. In between, any reference to the register
contents is accompanied by a test of the scoreboard
bit to ensure that the load has completed before
processing continues. Since the processor does not
need to wait for the LOAD to complete, it can
execute additional instructions placed between the
LOAD and the instruction that uses the register
contents, as shown in the following example:
ld data_2, r4
ld data_2, r5
Unrelated instruction
Unrelated instruction
add R4, R5, R6
In essence, the two unrelated instructions between
LOAD and ADD are executed “for free” (i.e., take no
apparent time to execute) because they are
executed while the register is being loaded. Up to
three load instructions can be pending at one time
with three corresponding scoreboard bits set. By
exploiting this feature, system programmers and
compiler writers have a useful tool for optimizing
execution speed.
5
80960KB
ONE OF FOUR
LOCAL
REGISTER SETS
REGISTER
CACHE
LOCAL REGISTER SET
R0
0
31
R15
Figure 4. Multiple Register Sets Are Stored On-Chip
1.1.7
Floating-Point Arithmetic
In the 80960KB, floating-point arithmetic has been
made an integral part of the architecture. Having the
floating-point unit integrated on-chip provides two
advantages. First, it improves the performance of the
chip for floating-point applications, since no
additional bus overhead is associated with
floating-point calculations, thereby leaving more time
for other bus operations such as I/O. Second, the
cost of using floating-point operations is reduced
because a separate coprocessor chip is not
required.
The 80960KB floating-point (real-number) data types
include single-precision (32-bit), double-precision
(64-bit) and extended precision (80-bit) floating-point
numbers. Any registers may be used to execute
floating-point operations.
The processor provides hardware support for both
mandatory and recommended portions of IEEE
Standard 754 for floating-point arithmetic, including
all arithmetic, exponential, logarithmic and other
transcendental functions. Table 3 shows execution
times for some representative instructions.
Table 3. Sample Floating-Point Execution Times
(µs) at 25 MHz
Function
Add
Subtract
Multiply
Divide
32-Bit
0.4
0.4
0.7
1.3
64-Bit
0.5
0.5
1.3
2.9
Square Root
Arctangent
Exponent
Sine
Cosine
3.7
10.1
11.3
15.2
15.2
3.9
13.1
12.5
16.6
16.6
1.1.8
High Bandwidth Local Bus
The 80960KB CPU resides on a high-bandwidth
address/data bus known as the local bus (L-Bus).
The L-Bus provides a direct communication path
between the processor and the memory and I/O
subsystem interfaces. The processor uses the L-Bus
to fetch instructions, manipulate memory and
respond to interrupts. L-Bus features include:
• 32-bit multiplexed address/data path
• Four-word burst capability which allows transfers
from 1 to 16 bytes at a time
• High bandwidth reads and writes with
66.7 MBytes/s burst (at 25 MHz)
Table 4 defines L-bus signal names and functions;
Table 5 defines other component-support signals
such as interrupt lines.
6
80960KB
1.1.9
Interrupt Handling
The 80960KB can be interrupted in two ways: by the
activation of one of four interrupt pins or by sending
a message on the processor’s data bus.
The 80960KB is unusual in that it automatically
handles interrupts on a priority basis and can keep
track of pending interrupts through its on-chip
interrupt controller. Two of the interrupt pins can be
configured to provide 8259A-style handshaking for
expansion beyond four interrupt lines.
1.1.10 Debug Features
The 80960KB has built-in debug capabilities. There
are two types of breakpoints and six trace modes.
Debug features are controlled by two internal 32-bit
registers: the Process-Controls Word and the
Trace-Controls Word. By setting bits in these control
words, a software debug monitor can closely control
how the processor responds during program
execution.
The 80960KB provides two hardware breakpoint
registers on-chip which, by using a special
command, can be set to any value. When the
instruction pointer matches either breakpoint register
value, the breakpoint handling routine is automatically called.
The 80960KB also provides software breakpoints
through the use of two instructions: MARK and
FMARK. These can be placed at any point in a
program and cause the processor to halt execution
at that point and call the breakpoint handling routine.
The breakpoint mechanism is easy to use and
provides a powerful debugging tool.
Tracing is available for instructions (single step
execution), calls and returns and branching. Each
trace type may be enabled separately by a special
debug instruction. In each case, the 80960KB
executes the instruction first and then calls a trace
handling routine (usually part of a software debug
monitor). Further program execution is halted until
the routine completes, at which time execution
resumes at the next instruction. The 80960KB’s
tracing mechanisms, implemented completely in
hardware, greatly simplify the task of software test
and debug.
1.1.11 Fault Detection
The 80960KB has an automatic mechanism to
handle faults. Fault types include floating point, trace
and arithmetic faults. When the processor detects a
fault, it automatically calls the appropriate fault
handling routine and saves the current instruction
pointer and necessary state information to make
efficient recovery possible. Like interrupt handling
routines, fault handling routines are usually written to
meet the needs of specific applications and are often
included as part of the operating system or kernel.
For each of the fault types, there are numerous
subtypes that provide specific information about a
fault. For example, a floating point fault may have
the subtype set to an Overflow or Zero-Divide fault.
The fault handler can use this specific information to
respond correctly to the fault.
1.1.12 Built-in Testability
Upon reset, the 80960KB automatically conducts an
exhaustive internal test of its major blocks of logic.
Then, before executing its first instruction, it does a
zero check sum on the first eight words in memory to
ensure that the memory image was programmed
correctly. If a problem is discovered at any point
during the self-test, the 80960KB asserts its
FAILURE pin and will not begin program execution.
Self test takes approximately 47,000 cycles to
complete.
System manufacturers can use the 80960KB’s
self-test feature during incoming parts inspection. No
special diagnostic programs need to be written. The
test is both thorough and fast. The self-test capability
helps ensure that defective parts are discovered
before systems are shipped and, once in the field,
the self-test makes it easier to distinguish between
problems caused by processor failure and problems
resulting from other causes.
1.1.13 CHMOS
The 80960KB is fabricated using Intel’s CHMOS IV
(Complementary High Speed Metal Oxide Semiconductor) process. The 80960KB is currently available
in 16, 20 and 25 MHz versions.
7
80960KB
Table 4. 80960KB Pin Description: L-Bus Signals (Sheet 1 of 2)
NAME
CLK2
LAD31:0
TYPE
DESCRIPTION
I
SYSTEM CLOCK provides the fundamental timing for 80960KB systems. It is
divided by two inside the 80960KB and four 80-bit registers (FP0 through FP3) to
generate the internal processor clock.
I/O
LOCAL ADDRESS / DATA BUS carries 32-bit physical addresses and data to
and from memory. During an address (Ta) cycle, bits 2-31 contain a physical word
address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, bits 0-31
contain read or write data. These pins float to a high impedance state when not
active.
T.S.
Bits 0-1 comprise SIZE during a Ta cycle. SIZE specifies burst transfer size in
words.
ALE
O
T.S.
ADS
O
O.D.
W/R
O
O.D.
DT/R
O
O.D.
DEN
O
O.D.
READY
LOCK
I
I/O
O.D.
LAD1
LAD0
0
0
1
1
0
1
0
1
1 Word
2 Words
3 Words
4 Words
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
asserted during a Ta cycle and deasserted before the beginning of the Td state. It
is active LOW and floats to a high impedance state during a hold cycle (Th).
ADDRESS/DATA STATUS indicates an address state. ADS is asserted every Ta
state and deasserted during the following Td state. For a burst transaction, ADS is
asserted again every Td state where READY was asserted in the previous cycle.
WRITE/READ specifies, during a Ta cycle, whether the operation is a write or
read. It is latched on-chip and remains valid during Td cycles.
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from
the L-Bus. It is low during Ta and Td cycles for a read or interrupt acknowledgment; it is high during Ta and Td cycles for a write. DT/R never changes state
when DEN is asserted.
DATA ENABLE (active low) enables data transceivers. The processor asserts
DEN# during all Td and Tw states. The DEN# line is an open drain-output of the
80960KB-processor.
READY indicates that data on LAD lines can be sampled or removed. If READY
is not asserted during a Td cycle, the Td cycle is extended to the next cycle by
inserting a wait state (Tw) and ADS is not asserted in the next cycle.
BUS LOCK prevents bus masters from gaining control of the L-Bus during
Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert
LOCK.
At the start of a RMW operation, the processor examines the LOCK pin. If the pin
is already asserted, the processor waits until it is not asserted. If the pin is not
asserted, the processor asserts LOCK during the Ta cycle of the read transaction.
The processor deasserts LOCK in the Ta cycle of the write transaction. During the
time LOCK is asserted, a bus agent can perform a normal read or write but not a
RMW operation.
The processor also asserts LOCK during interrupt-acknowledge transactions.
Do not leave LOCK unconnected. It must be pulled high for the processor to
function properly.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
8
ERRATA - 6/13/97
DEN pin description omitted.
80960KB
Table 4. 80960KB Pin Description: L-Bus Signals (Sheet 2 of 2)
NAME
BE3:0
TYPE
DESCRIPTION
O
BYTE ENABLE LINES specify the data bytes (up to four) on the bus which are
used in the current bus cycle. BE3 corresponds to LAD31:24; BE0 corresponds to
LAD7:0.
O.D.
The byte enables are provided in advance of data:
Byte enables asserted during Ta specify the bytes of the first data word.
Byte enables asserted during Td specify the bytes of the next data word, if any
(the word to be transmitted following the next assertion of READY).
Byte enables that occur during Td cycles that precede the last assertion of
READY are undefined. Byte enables are latched on-chip and remain constant
from one Td cycle to the next when READY is not asserted.
For reads, byte enables specify the byte(s) that the processor will actually use.
L-Bus agents are required to assert only adjacent byte enables (e.g., asserting
just BE0 and BE2 is not permitted) and are required to assert at least one byte
enable. Address bits A0 and A1 can be decoded externally from the byte enables.
HOLD
HLDA
I
HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it floats its
three-state bus lines and open-drain control lines, asserts HLDA and enters the
Th state. When HOLD deasserts, the processor deasserts HLDA and enters the
Ti or Ta state.
O
HOLD ACKNOWLEDGE: Notifies an external bus master that the processor has
relinquished control of the bus.
T.S.
CACHE
O
T.S.
CACHE indicates when an access is cacheable during a Ta cycle. It is not
asserted during any synchronous access, such as a synchronous load or move
instruction used for sending an IAC message. The CACHE signal floats to a high
impedance state when the processor is idle.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
Table 5. 80960KB Pin Description: Support Signals (Sheet 1 of 2)
NAME
BADAC
TYPE
DESCRIPTION
I
BAD ACCESS, if asserted in the cycle following the one in which the last READY
of a transaction is asserted, indicates that an unrecoverable error has occurred
on the current bus transaction or that a synchronous load/store instruction has not
been acknowledged.
During system reset the BADAC signal is interpreted differently. If the signal is
high, it indicates that this processor will perform system initialization. If it is low,
another processor in the system will perform system initialization instead.
RESET
I
RESET clears the processor’s internal logic and causes it to reinitialize.
During RESET assertion, the input pins are ignored (except for BADAC and
IAC/INT0), the three-state output pins are placed in a high impedance state and
other output pins are placed in their non-asserted states.
RESET must be asserted for at least 41 CLK2 cycles for a predictable RESET.
The HIGH to LOW transition of RESET should occur after the rising edge of both
CLK2 and the external bus clock and before the next rising edge of CLK2.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
9
80960KB
Table 5. 80960KB Pin Description: Support Signals (Sheet 2 of 2)
NAME
FAILURE
TYPE
DESCRIPTION
O
INITIALIZATION FAILURE indicates that the processor did not initialize correctly.
After RESET deasserts and before the first bus transaction begins, FAILURE
asserts while the processor performs a self-test. If the self-test completes
successfully, then FAILURE deasserts. The processor then performs a zero
checksum on the first eight words of memory. If it fails, FAILURE asserts for a
second time and remains asserted. If it passes, system initialization continues
and FAILURE remains deasserted.
O.D.
IAC/INT0
I
INTERAGENT COMMUNICATION REQUEST/INTERRUPT 0 indicates an IAC
message or an interrupt is pending. The bus interrupt control register determines
how the signal is interpreted. To signal an interrupt or IAC request in a
synchronous system, this pin — as well as the other interrupt pins — must be
enabled by being deasserted for at least one bus cycle and then asserted for at
least one additional bus cycle. In an asynchronous system the pin must remain
deasserted for at least two bus cycles and then asserted for at least two more bus
cycles.
During system reset, this signal must be in the logic high condition to enable
normal processor operation. The logic low condition is reserved.
INT1
I
INTERRUPT 1, like INT0, provides direct interrupt signaling.
INT2/INTR
I
INTERRUPT2/INTERRUPT REQUEST: The interrupt control register determines
how this pin is interpreted. If INT2, it has the same interpretation as the INT0 and
INT1 pins. If INTR, it is used to receive an interrupt request from an external
interrupt controller.
I/O
INTERRUPT3/INTERRUPT ACKNOWLEDGE: The bus interrupt control register
determines how this pin is interpreted. If INT3, it has the same interpretation as
the INT0, INT1 and INT2 pins. If INTA, it is used as an output to control
interrupt-acknowledge transactions. The INTA output is latched on-chip and
remains valid during Td cycles; as an output, it is open-drain.
INT3/INTA
O.D.
N.C.
N/A
NOT CONNECTED indicates pins should not be connected. Never connect any
pin marked N.C. as these pins may be reserved for factory use.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
2.0
ELECTRICAL SPECIFICATIONS
2.1
Power and Grounding
The 80960KB is implemented in CHMOS IV
technology and therefore has modest power requirements. Its high clock frequency and numerous
output buffers (address/data, control, error and
arbitration signals) can cause power surges as
multiple output buffers simultaneously drive new
signal levels. For clean on-chip power distribution,
V CC and VSS pins separately feed the device’s
functional units. Power and ground connections
10
must be made to all 80960KB power and ground
pins. On the circuit board, all Vcc pins must be
strapped closely together, preferably on a power
plane; all Vss pins should be strapped together,
preferably on a ground plane.
2.2
Power Decoupling
Recommendations
Place a liberal amount of decoupling capacitance
near the 80960KB. When driving the L-bus the
processor can cause transient power surges, particularly when connected to a large capacitive load.
80960KB
Low inductance capacitors and interconnects are
recommended for best high frequency electrical
performance. Inductance is reduced by shortening
board traces between the processor and decoupling
capacitors as much as possible.
2.3
VCC
OPEN-DRAIN OUTPUT
180 Ω
Connection Recommendations
For reliable operation, always connect unused inputs
to an appropriate signal level. In particular, if one or
more interrupt lines are not used, they should be
pulled up. No inputs should ever be left floating.
All open-drain outputs require a pullup device. While
in most cases a simple pullup resistor is adequate, a
network of pullup and pulldown resistors biased to a
valid VIH ( >3.0 V) and terminated in the characteristic
impedance of the circuit board is recommended to
limit noise and AC power consumption. Figure 5 and
Figure 6 show recommended values for the resistor
network for low and high current drive, assuming a
characteristic impedance of 100 Ω. Terminating
output signals in this fashion limits signal swing and
reduces AC power consumption.
NOTE: Do not connect external logic to pins marked
N.C.
VCC
OPEN-DRAIN OUTPUT
220 Ω
Low Drive Network:
VOH = 3.0 V
IOL = 20.7 mA
High Drive Network:
VOH = 3.4 V
IOL = 25.3 mA
390 Ω
Figure 6. Connection Recommendations
for High Current Drive Network
2.4
Characteristic Curves
Figure 7 shows typical supply current requirements
over the operating temperature range of the
processor at supply voltage (VCC) of 5 V. Figure 8
and Figure 9 show the typical power supply current
(ICC) that the 80960KB requires at various operating
frequencies when measured at three input voltage
(VCC) levels and two temperatures.
For a given output current (IOL) the curve in Figure
10 shows the worst case output low voltage (VOL).
Figure 11 shows the typical capacitive derating
curve for the 80960KB measured from 1.5V on the
system clock (CLK) to 1.5V on the falling edge and
1.5V on the rising edge of the L-Bus address/data
(LAD) signals.
330 Ω
Figure 5. Connection Recommendations
for Low Current Drive Network
11
80960KB
380
VCC = 5.0 V
360
25 MHz
20 MHz
16 MHz
POWER SUPPLY CURRENT (mA)
340
320
300
280
260
240
220
200
-60-40-20020406080100120140
CASE TEMPERATURE (°C)
Figure 7. Typical Supply Current vs. Case Temperature
400
TEMP = +22°C
380
@5.5V
@4.5V
TYPICAL SUPPLY CURRENT (mA)
360
@5.0V
340
320
300
280
260
240
220
200
180
16
20
25
OPERATING FREQUENCY (MHz)
Figure 8. Typical Current vs. Frequency (Room Temp)
12
80960KB
380
TEMP = +22°C
360
@5.5V
TYPICAL SUPPLY CURRENT (mA)
340
@5.0V
@4.5V
320
300
280
260
240
220
200
180
160
16
20
25
OPERATING FREQUENCY (MHz)
Figure 9. Typical Current vs. Frequency (Hot Temp)
(TEMP = +85°C, VCC = 4.5V)
30
FALLING
THREE-STATE OUTPUT
VALID DELAY(ns)
OUTPUT LOW VOLTAGE (V)
(TEMP = +85°C, VCC = 4.5V)
0.8
0.6
0.4
0.2
0.0
0
10
20
30
40
50
OUTPUT LOW CURRENT(mA)
Figure 10. Worst-Case Voltage vs. Output
Current on Open-Drain Pins
2.5
Test Load Circuit
Figure 12 illustrates the load circuit used to test the
25
20
15
10
RISING
5
0
0 20 40 60 80 100
CAPACITIVE LOAD(pF)
Figure 11. Capacitive Derating Curve
80960KB’s three-state pins; Figure 13 shows the
load circuit used to test the open drain outputs. The
open drain test uses an active load circuit in the form
13
80960KB
of a matched diode bridge. Since the open-drain
outputs sink current, only the IOL legs of the bridge
are necessary and the IOH legs are not used. When
the 80960KB driver under test is turned off, the
output pin is pulled up to VREF (i.e., VOH). Diode D1
is turned off and the IOL current source flows through
diode D2.
When the 80960KB open-drain driver under test is
on, diode D1 is also on and the voltage on the pin
being tested drops to VOL. Diode D2 turns off and IOL
flows through diode D1.
THREE-STATE OUTPUT
CL
CL = 50 pF for all signals
Figure 12. Test Load Circuit for Three-State
Output Pins
IOL
OPEN-DRAIN OUTPUT
D1
CL
D2
I OL Tested at 25 mA
VREF = VCC
D1 and D2 are matched
CL = 50 pF for all signals
Figure 13. Test Load Circuit for Open-Drain
Output Pins
14
80960KB
2.6
Absolute Maximum Ratings
NOTICE:This is a production data sheet. The specifications are subject to change without notice.
*WARNING: Stressing the device beyond the
“Absolute Maximum Ratings” may cause
permanent damage. These are stress ratings
only. Operation beyond the “Operating Conditions” is not recommended and extended
exposure beyond the “Operating Conditions” may
affect device reliability.
Operating Temperature(PGA)................... 0°C to +85°C Case
(PQFP) ............. 0°C to +100°C Case
Storage Temperature .................................... –65°C to +150°C
Voltage on Any Pin .................................. –0.5V to VCC +0.5V
Power Dissipation ............................................ 2.5W (25 MHz)
2.7
DC Characteristics
PGA:
PQFP:
80960KB (16 MHz) TCASE = 0°C to +85° C, VCC = 5V ± 10%
80960KB (20 and 25 MHz) TCASE = 0°C to +85° C, VCC = 5V ± 5%
80960KB (16 MHz) TCASE = 0°C to +100°C, VCC = 5V ± 10%
80960KB (20 and 25 MHz) TCASE = 0°C to +100°C, VCC = 5V ± 5%
Table 6. DC Characteristics
Symbol
Min
Max
Units
VIL
Input Low Voltage
Parameter
–0.3
+0.8
V
VIH
Input High Voltage
2.0
VCC + 0.3
V
Notes
VCL
CLK2 Input Low Voltage
–0.3
+0.8
V
VCH
CLK2 Input High Voltage
0.55 VCC
VCC + 0.3
V
VOL
Output Low Voltage
0.45
V
(1,2)
VOH
Output High Voltage
V
(3,4)
ICC
Power Supply Current:
16 MHz
20 MHz
25 MHz
315
360
420
mA
mA
mA
(5)
(5)
(5)
2.4
ILI
Input Leakage Current
±15
µA
0 ≤ VIN ≤ VCC
ILO
Output Leakage Current
±15
µA
0.45 ≤ VO ≤ VCC
CIN
Input Capacitance
10
pF
fC = 1 MHz (6)
CO
Output Capacitance
12
pF
fC = 1 MHz (6)
CCLK
Clock Capacitance
10
pF
fC = 1 MHz (6)
NOTES:
1. For three-state outputs, this parameter is measured at:
Address/Data ........................................ 4.0 mA
Controls.................................................. 5.0 mA
2. For open-drain outputs ........................... 25 mA
3. This parameter is measured at:
Address/Data ...................................... -1.0 mA
Controls................................................ -0.9 mA
ALE ..................................................... -5.0 mA
4. Not measured on open-drain outputs.
5. Measured at worst case frequency, VCC and temperature, with device operating and outputs loaded to the test conditions
in Figures 12 and 13. Figure 7, Figure 8 and Figure 9 indicate typical values.
6. Input, output and clock capacitance are not tested.
15
80960KB
2.8
For input timings the specifications refer to the time
at which the signal reaches (for input setup) or
leaves (for hold time) the TTL levels of LOW (0.8 V)
or HIGH (2.0 V). All AC testing should be done with
input voltages of 0.4 V and 2.4 V, except for the
clock (CLK2), which should be tested with input
voltages of 0.45 V and 0.55 VCC.
AC Specifications
This section describes the AC specifications for the
80960KB pins. All input and output timings are
specified relative to the 1.5 V level of the rising edge
of CLK2. For output timings the specifications refer
to the time it takes the signal to reach 1.5 V.
A
EDGE
CLK2
B
1.5V
D
C
1.5V
A
B
1.5V
C
1.5V
0.8V
T6
OUTPUTS:
LAD 31:0
ADS
W/R, DEN
BE3:0
HLDA
CACHE
LOCK, INTA
T9
1.5V
T8
T13
T8
T14
1.5V
1.5V
ALE
1.5V
VALID OUTPUT
T7
T6
T9
1.5V
DT/R
T10
INPUTS:
LAD31:0
BADAC
IAC/INT0, INT1
INT2/INTR, INT3
HOLD
LOCK
READY
VALID OUTPUT
T11
2.0V
2.0V
0.8V
0.8V
T12
1.5V
T11
2.0V
2.0V
0.8V
0.8V
VALID INPUT
Figure 14. Drive Levels and Timing Relationships for 80960KB Signals
16
80960KB
2.8.1
AC Specification Tables
Table 7. 80960KB AC Characteristics (16 MHz)
Symbol
Parameter
Min
Max
Units
Notes
Input Clock
T1
Processor Clock Period (CLK2)
T2
Processor Clock Low Time (CLK2)
T3
Processor Clock High Time (CLK2)
T4
Processor Clock Fall Time (CLK2)
T5
Processor Clock Rise Time (CLK2)
T6
Output Valid Delay
2
25
ns
HLDA Output Valid Delay
4
28
ns
T7
ALE Width
15
T8
ALE Output Valid Delay
2
T9
Output Float Delay
HLDA Output Float Delay
31.25
125
ns
VIN = 1.5V
8
ns
VIL = 10% Point = 1.2V
8
ns
VIH = 90% Point = 0.1V + 0.5 VCC
10
ns
VIN = 90% Point to 10% Point (1)
10
ns
VIN = 10% Point to 90% Point (1)
Synchronous Outputs
T6H
T9H
ns
18
ns
2
20
ns
(2)
4
20
ns
(2)
Synchronous Inputs
T10
Input Setup 1
3
ns
(3)
T11
Input Hold
5
ns
(3)
T11H
HOLD Input Hold
4
ns
(3)
T12
Input Setup 2
8
ns
(3)
T13
Setup to ALE Inactive
10
ns
T14
Hold after ALE Inactive
8
ns
T15
Reset Hold
3
ns
(3)
T16
Reset Setup
5
ns
(3)
T17
Reset Width
1281
ns
41 CLK2 Periods Minimum
NOTES:
1. Clock rise and fall times are not tested.
2. A float condition occurs when the maximum output current becomes less than ILO. Float delay is not tested; however, it
should not be longer than the valid delay.
3. LAD31:0, BADAC, HOLD, LOCK and READY are synchronous inputs. IAC/INT0, INT1, INT2/INTR and INT3 may be synchronous or asynchronous.
17
80960KB
Table 8. 80960KB AC Characteristics (20 MHz)
Symbol
Parameter
Min
Max
Units
Notes
Input Clock
T1
Processor Clock Period (CLK2)
25
T2
Processor Clock Low Time (CLK2)
T3
Processor Clock High Time (CLK2)
T4
Processor Clock Fall Time (CLK2)
T5
Processor Clock Rise Time (CLK2)
T6
Output Valid Delay
2
20
ns
HLDA Output Valid Delay
4
23
ns
T7
ALE Width
12
T8
ALE Output Valid Delay
2
18
ns
T9
Output Float Delay
2
20
ns
(2)
HLDA Output Float Delay
4
20
ns
(2)
125
ns
VIN = 1.5V
6
ns
VIL = 10% Point = 1.2V
6
ns
VIH = 90% Point = 0.1V + 0.5 VCC
10
ns
VIN = 90% Point to 10% Point (1)
10
ns
VIN = 10% Point to 90% Point (1)
Synchronous Outputs
T6H
T9H
ns
Synchronous Inputs
T10
Input Setup 1
3
ns
(3)
T11
Input Hold
5
ns
(3)
T11H
HOLD Input Hold
4
ns
(3)
T12
Input Setup 2
7
ns
(3)
T13
Setup to ALE Inactive
10
ns
T14
Hold after ALE Inactive
8
ns
T15
Reset Hold
3
ns
T16
Reset Setup
5
ns
T17
Reset Width
1025
ns
41 CLK2 Periods Minimum
NOTES:
1. Clock rise and fall times are not tested.
2. A float condition occurs when the maximum output current becomes less than ILO. Float delay is not tested; however, it
should not be longer than the valid delay.
3. LAD31:0, BADAC, HOLD, LOCK and READY are synchronous inputs. IAC/INT0, INT1, INT2/INTR and INT3 may be synchronous or asynchronous.
18
80960KB
Table 9. 80960KB AC Characteristics (25 MHz)
Symbol
Parameter
Min
Max
Units
Notes
Input Clock
T1
Processor Clock Period (CLK2)
20
T2
Processor Clock Low Time (CLK2)
T3
Processor Clock High Time (CLK2)
T4
Processor Clock Fall Time (CLK2)
T5
Processor Clock Rise Time (CLK2)
T6
Output Valid Delay
2
18
ns
HLDA Output Valid Delay
4
23
ns
T7
ALE Width
12
T8
ALE Output Valid Delay
2
T9
Output Float Delay
HLDA Output Float Delay
125
ns
VIN = 1.5V
5
ns
VIL = 10% Point = 1.2V
5
ns
VIH = 90% Point = 0.1V + 0.5 VCC
10
ns
VIN = 90% Point to 10% Point (1)
10
ns
VIN = 10% Point to 90% Point (1)
Synchronous Outputs
T6H
T9H
ns
18
ns
2
18
ns
(2)
4
20
ns
(2)
Synchronous Inputs
T10
Input Setup 1
3
ns
(3)
T11
Input Hold
5
ns
(3)
T11H
HOLD Input Hold
4
ns
T12
Input Setup 2
7
ns
T13
Setup to ALE Inactive
8
ns
T14
Hold after ALE Inactive
8
ns
T15
Reset Hold
3
ns
T16
Reset Setup
5
ns
T17
Reset Width
820
ns
41 CLK2 Periods Minimum
NOTES:
1. Clock rise and fall times are not tested.
2. A float condition occurs when the maximum output current becomes less than ILO. Float delay is not tested; however, it
should not be longer than the valid delay.
3. LAD31:0, BADAC, HOLD, LOCK and READY are synchronous inputs. IAC/INT0, INT1, INT2/INTR and INT3 may be synchronous or asynchronous.
19
80960KB
T1
T3
HIGH LEVEL (MIN) 0.55VCC
90%
1.5 V
10%
LOW LEVEL (MAX) 0.8V
T5
T2
T4
Figure 15. Processor Clock Pulse (CLK2)
CLK2
CLK
RESET
...
...
...
FIRST
A B C
D
A
T15 T16
T17
OUTPUTS
...
INIT PARAMETERS (BADAC,
INT0/IAC) MUST BE SET UP 8 CLOCKS
PRIOR TO THIS CLK2 EDGE
INIT PARAMETERS MUST BE HELD
BEYOND THIS CLK2 EDGE
Figure 16. RESET Signal Timing
20
T15 = RESET HOLD
T16 = RESET SETUP
T17 = RESET WIDTH
80960KB
3.0
MECHANICAL DATA
3.1
Packaging
3.1.1
Pin Assignment
The PGA and PQFP have different pin assignments.
Figure 18 shows the view from the PGA bottom (pins
facing up) and Figure 19 shows a view from the PGA
top (pins facing down). Figure 20 shows the PQFP
package; Figure 21 shows the PQFP pinout with
signal names. Notice that the pins are numbered in
order from 1 to 132 around the package perimeter.
Table 10 and Table 11 list the function of each PGA
pin; Table 12 and Table 13 list the function of each
PQFP pin.
The 80960KB is available in two package types:
• 132-lead ceramic pin-grid array (PGA). Pins are
arranged 0.100 inch (2.54 mm) center-to-center, in
a 14 by 14 matrix, three rows around (see Figure
17).
• 132-lead plastic quad flat pack (PQFP). This
package uses fine-pitch gull wing leads arranged
in a single row along the package perimeter with
0.025 inch (0.64 mm) spacing (see Figure 20).
Dimensions for both package types are given in the
Intel Packaging handbook (Order #240800).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A B C D
E
F G H
J
K
L M N
P
Figure 17. 132-Lead Pin-Grid Array (PGA) Package
21
80960KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
P
VCC
N.C. N.C.
N.C. N.C.
N.C.
N.C.
N.C. N.C.
N.C.
N.C.
N.C. VSS
VCC
VSS
N.C. N.C.
N.C. N.C.
N.C.
N.C.
N.C. N.C.
N.C.
N.C.
N.C. N.C.
N.C.
N.C.
VCC
VSS
VSS VCC
N.C.
N.C.
N.C. N.C.
VSS
VCC
N.C. N.C.
N.C.
DEN
N.C.
VCC
VSS N.C.
N.C.
BE3
FAIL
VSS
VCC N.C.
N.C.
DT/R
BE2
VSS
N.C. N.C.
N.C.
W/R
BE0 LOCK
N.C. N.C.
N.C.
LAD30 READY BE1
N.C. N.C.
N.C.
LAD29 LAD31 CACHE
N.C. N.C.
N.C.
LAD28 LAD26 LAD27
N.C. VSS
N.C.
VCC N.C.
N.C.
INT3 INT1
INT0
N
N
M
M
L
L
K
K
J
J
H
H
G
G
F
F
E
E
D
D
ALE
ADS HLDA
C
C
HOLD LAD25 BADAC VCC VSS LAD20 LAD13 LAD8 LAD3 VCC
VSS
B
B
LAD23 LAD24 LAD22 LAD21 LAD18 LAD15 LAD12 LAD10 LAD6 LAD2 CLK2 LAD0 RESET VSS
A
A
VCC
1
VSS LAD19 LAD17 LAD 16 LAD14 LAD11 LAD9 LAD7 LAD5 LAD4 LAD1 INT2
2
3
4
5
6
7
8
9
10
11
12
13
VCC
14
Figure 18. 80960KB PGA Pinout—View from Bottom (Pins Facing Up)
ERRATA
6-17-97:
Pin M2 was N.C.; should be VCC .
Pin M13 was VCC; should be N.C.
This page now shows it correctly.
22
80960KB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VCC
VSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VCC
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
N.C.
N.C.
N.C.
VCC
VSS
N.C.
N.C.
N.C.
N.C.
VCC
VSS
VSS
VCC
N.C.
N.C.
N.C.
VSS
VCC
N.C.
DEN
N.C.
N.C.
VCC
VSS
FAIL
BE3
N.C.
N.C.
N.C.
VSS
BE2
DT/R
N.C.
N.C.
N.C.
LOCK
BE0
W/R
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
P
L
K
G
F
E
D
M
K
J
H
J
H
G
BE1 READY LAD30
F
CACHE LAD31 LAD29
E
N.C. VSS
N.C.
LAD27 LAD26 LAD28
N.C.
N.C.
VCC
HLDA ADS
INT0
INT1 INT3
D
ALE
C
B
N
L
X XXXXX XX
X XXXXX
XXXXXX
M
x80960KB-25
N
P
C
VSS
VCC LAD3 LAD8 LAD13 LAD20 VSS
VCC BADAC LAD25 HOLD
VSS RESET LAD0 CLK2 LAD2 LAD6 LAD10 LAD12 LAD15 LAD18 LAD21 LAD 22 LAD24 LAD23
A
B
A
VCC
14
INT2 LAD1 LAD4 LAD5 LAD7 LAD9 LAD11 LAD14 LAD16 LAD17 LAD 19 VSS
13
12
11
10
9
8
7
6
5
4
3
2
VCC
1
Figure 19. 80960KB PGA Pinout—View from Top (Pins Facing Down)
Figure 20. 80960KB 132-Lead Plastic Quad Flat-Pack (PQFP) Package
NOTE: To address the fact that many of the package prefix variables have changed,
all package prefix variables in this document are now indicated with an "x".
23
x80960KB-25
2
3
4
5
6
7
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VCC
VCC
NC
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VCC
NC
NC
NC
NC
VCC
VCC
NC
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
NC
VSS
VSS
1
HLDA
A LE
LAD26
LAD27
LAD28
LAD29
LAD30
LAD31
VSS
CACHE
W /R
READY
DT/R
BE0
BE1
BE2
BE3
FAILURE
VSS
LOCK
DEN
VSS
VSS
NC
NC
VSS
VSS
NC
VCC
VCC
LAD3
LAD4
LAD5
LAD6
LAD7
LAD8
LAD9
LAD10
LAD11
LAD12
VSS
LAD13
LAD14
LAD15
LAD16
LAD17
LAD18
LAD19
LAD20
LAD21
LAD22
VSS
LAD23
LAD24
LAD25
BADAC
HOLD
NC
ADS
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
XXXXXXXX
XXXXXX
XXXXXX
LAD0
LAD1
LAD2
VSS
NC
VSS
VSS
VSS
NC
NC
NC
NC
NC
RESET
VCC
CLK2
VSS
NC
INT3/INTA
INT2/INTR
INT1
IAC/INT0
VSS
VCC
VCC
NC
VSS
VSS
NC
NC
NC
NC
VCC
VSS
NC
VCC
VCC
80960KB
Figure 21. PQFP Pinout - View From Top
NOTE: To address the fact that many of the package prefix variables have changed,
all package prefix variables in this document are now indicated with an "x".
24
80960KB
3.2
Pinout
Table 10. 80960KB PGA Pinout — In Pin Order
Pin
Signal
Pin
Signal
Pin
Signal
Pin
A1
VCC
C6
LAD20
H1
W/R
M10
Signal
VSS
A2
VSS
C7
LAD13
H2
BE0
M11
VCC
A3
LAD19
C8
LAD 8
H3
LOCK
M12
N.C.
A4
LAD17
C9
LAD 3
H12
N.C.
M13
N.C.
A5
LAD16
C10
VCC
H13
N.C.
M14
N.C.
A6
LAD14
C11
VSS
H14
N.C.
N1
VSS
A7
LAD11
C12
INT3/INTA
J1
DT/R
N2
N.C.
A8
LAD9
C13
INT1
J2
BE2
N3
N.C.
A9
LAD7
C14
IAC/INT0
J3
V SS
N4
N.C.
A10
LAD5
D1
ALE
J12
N.C.
N5
N.C.
A11
LAD4
D2
ADS
J13
N.C.
N6
N.C.
A12
LAD1
D3
HLDA
J14
N.C.
N7
N.C.
A13
INT2/INTR
D12
VCC
K1
BE3
N8
N.C.
A14
VCC
D13
N.C.
K2
FAILURE
N9
N.C.
B1
LAD23
D14
N.C.
K3
V SS
N10
N.C.
B2
LAD24
E1
LAD28
K12
VCC
N11
N.C.
B3
LAD22
E2
LAD26
K13
N.C.
N12
N.C.
B4
LAD21
E3
LAD27
K14
N.C.
N13
N.C.
B5
LAD18
E12
N.C.
L1
DEN
N14
N.C.
B6
LAD15
E13
VSS
L2
N.C.
P1
VCC
B7
LAD12
E14
N.C.
L3
VCC
P2
N.C.
B8
LAD10
F1
LAD29
L12
VSS
P3
N.C.
B9
LAD6
F2
LAD31
L13
N.C.
P4
N.C.
B10
LAD2
F3
CACHE
L14
N.C.
P5
N.C.
B11
CLK2
F12
N.C.
M1
N.C.
P6
N.C.
B12
LAD0
F13
N.C.
M2
VCC
P7
N.C.
B13
RESET
F14
N.C.
M3
V SS
P8
N.C.
B14
VSS
G1
LAD30
M4
V SS
P9
N.C.
C1
HOLD
G2
READY
M5
VCC
P10
N.C.
C2
LAD25
G3
BE1
M6
N.C.
P11
N.C.
N.C.
C3
BADAC
G12
N.C.
M7
N.C.
P12
C4
V CC
G13
N.C.
M8
N.C.
P13
VSS
C5
VSS
G14
N.C.
M9
N.C.
P14
VCC
NOTE:
Do not connect any external logic to any pins marked N.C.
25
80960KB
Table 11. 80960KB PGA Pinout — In Signal Order
Signal
Pin
Signal
Pin
Signal
Pin
Signal
ADS
D2
LAD15
B6
N.C.
J14
N.C.
P9
ALE
D1
LAD16
A5
N.C.
K13
N.C.
P10
BADAC
C3
LAD17
A4
N.C.
K14
N.C.
P11
P12
BE0
H2
LAD18
B5
N.C.
L13
N.C.
BE1
G3
LAD19
A3
N.C.
L14
N.C.
L2
BE2
J2
LAD20
C6
N.C.
M1
READY
G2
BE3
K1
LAD21
B4
N.C.
M6
RESET
B13
CACHE
F3
LAD22
B3
N.C.
M7
V CC
A1
CLK2
B11
LAD23
B1
N.C.
M8
V CC
A14
DEN
L1
LAD24
B2
N.C.
M9
V CC
C4
DT/R
J1
LAD25
C2
N.C.
M12
V CC
C10
FAILURE
K2
LAD26
E2
N.C.
M13
V CC
D12
HLDA
D3
LAD27
E3
N.C.
M14
V CC
K12
HOLD
C1
LAD28
E1
N.C.
N2
V CC
L3
IAC/INT0
C14
LAD29
F1
N.C.
N3
V CC
M2
INT1
C13
LAD30
G1
N.C.
N4
V CC
M5
INT2/INTR
A13
LAD31
F2
N.C.
N5
V CC
M11
INT3/INTA
C12
LOCK
H3
N.C.
N6
VCC
P1
LAD0
B12
N.C.
D13
N.C.
N7
V CC
P14
LAD1
A12
N.C.
D14
N.C.
N8
VSS
A2
LAD2
B10
N.C.
E12
N.C.
N9
VSS
B14
LAD3
C9
N.C.
E14
N.C.
N10
VSS
C5
LAD4
A11
N.C.
F12
N.C.
N11
VSS
C11
LAD5
A10
N.C.
F13
N.C.
N12
VSS
E11
LAD6
B9
N.C.
F14
N.C.
N13
VSS
J3
LAD7
A9
N.C.
G12
N.C.
N14
VSS
K3
LAD8
C8
N.C.
G13
N.C.
P2
VSS
L12
LAD9
A8
N.C.
G14
N.C.
P3
VSS
M3
LAD10
B8
N.C.
H12
N.C.
P4
VSS
M4
LAD11
A7
N.C.
H13
N.C.
P5
VSS
M10
LAD12
B7
N.C.
H14
N.C.
P6
VSS
N1
LAD13
C7
N.C.
J12
N.C.
P7
VSS
P13
LAD14
A6
N.C.
J13
N.C.
P8
W/R
H1
NOTE:
26
Pin
Do not connect any external logic to any pins marked N.C.
80960KB
Table 12. 80960KB PQFP Pinout — In Pin Order
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
1
HLDA
34
N.C.
67
VSS
100
LAD0
2
ALE
35
VCC
68
VSS
101
LAD1
3
LAD26
36
VCC
69
N.C.
102
LAD2
4
LAD27
37
N.C.
70
VCC
103
VSS
5
LAD28
38
N.C.
71
VCC
104
LAD3
6
LAD29
39
N.C.
72
N.C.
105
LAD4
7
LAD30
40
N.C.
73
VSS
106
LAD5
8
LAD31
41
VCC
74
VCC
107
LAD6
9
VSS
42
VSS
75
N.C.
108
LAD7
10
CACHE
43
N.C.
76
N.C.
109
LAD8
Pin
Pin
11
W/R
44
N.C.
77
N.C.
110
LAD9
12
READY
45
N.C.
78
N.C.
111
LAD10
13
DT/R
46
N.C.
79
VSS
112
LAD11
14
BE0
47
N.C.
80
VSS
113
LAD12
15
BE1
48
N.C.
81
N.C.
114
VSS
16
BE2
49
N.C.
82
VCC
115
LAD13
17
BE3
50
N.C.
83
VCC
116
LAD14
18
FAILURE
51
N.C.
84
VSS
117
LAD15
19
VSS
52
VSS
85
IAC/INT0
118
LAD16
20
LOCK
53
VSS
86
INT1
119
LAD17
21
DEN
54
N.C.
87
NT2/INTR
120
LAD18
22
VSS
55
VCC
88
NT3/INTA
121
LAD19
23
VSS
56
VCC
89
N.C.
122
LAD20
24
N.C.
57
VSS
90
VSS
123
LAD21
25
N.C.
58
N.C.
91
CLK2
124
LAD22
26
VSS
59
N.C.
92
VCC
125
VSS
27
VSS
60
N.C.
93
RESET
126
LAD23
28
N.C.
61
N.C.
94
N.C.
127
LAD24
29
VCC
62
N.C.
95
N.C.
128
LAD25
30
VCC
63
N.C.
96
N.C.
129
BADAC
31
N.C.
64
N.C.
97
N.C.
130
HOLD
32
VSS
65
N.C.
98
N.C.
131
N.C.
33
VSS
66
N.C.
99
VSS
132
ADS
NOTE:
Do not connect any external logic to any pins marked N.C.
27
80960KB
Table 13. 80960KB PQFP Pinout — In Signal Order
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
ADS
132
LAD15
117
N.C.
49
VCC
41
ALE
2
LAD16
118
N.C.
50
VCC
55
BADAC
129
LAD17
119
N.C.
51
VCC
56
BE0
14
LAD18
120
N.C.
54
VCC
70
BE1
15
LAD19
121
N.C.
58
VCC
71
BE2
16
LAD20
122
N.C.
59
VCC
74
BE3
17
LAD21
123
N.C.
60
VCC
82
CACHE
10
LAD22
124
N.C.
61
VCC
83
CLK2
91
LAD23
126
N.C.
62
VCC
92
DEN
21
LAD24
127
N.C.
63
VSS
9
DT/R
13
LAD25
128
N.C.
64
VSS
19
FAILURE
18
LAD26
3
N.C.
65
V SS
22
HLDA
1
LAD27
4
N.C.
66
V SS
23
HOLD
130
LAD28
5
N.C.
69
V SS
26
IAC/INT0
85
LAD29
6
N.C.
72
V SS
27
INT1
86
LAD30
7
N.C.
75
V SS
32
INT2/INTR
87
LAD31
8
N.C.
76
V SS
33
INT3/INTA
88
LOCK
20
N.C.
77
VSS
42
LAD0
100
N.C.
24
N.C.
78
VSS
52
LAD1
101
N.C.
25
N.C.
81
VSS
53
LAD2
102
N.C.
28
N.C.
89
VSS
57
LAD3
104
N.C.
31
N.C.
94
VSS
67
LAD4
105
N.C.
34
N.C.
95
VSS
68
LAD5
106
N.C.
37
N.C.
96
VSS
73
LAD6
107
N.C.
38
N.C.
97
VSS
79
LAD7
108
N.C.
39
N.C.
98
VSS
80
LAD8
109
N.C.
40
N.C.
131
VSS
84
LAD9
110
N.C.
43
READY
12
V SS
90
LAD10
111
N.C.
44
RESET
93
VSS
99
LAD11
112
N.C.
45
VCC
29
V SS
103
LAD12
113
N.C.
46
VCC
30
V SS
114
LAD13
115
N.C.
47
VCC
35
V SS
125
LAD14
116
N.C.
48
VCC
36
W/R
11
NOTE:
28
Do not connect any external logic to any pins marked N.C.
80960KB
3.3
Package Thermal Specification
If the 80960KB is to be used in a harsh environment
where the ambient temperature may exceed the
limits for the normal commercial part, consider using
an
extended
temperature
device.
These
components are available at 16, 20 and 25 MHz in
the ceramic PGA package. Extended operating
temperature range is –40° C to +125°C (case).
The 80960KB is specified for operation when case
temperature is within the range 0°C to 85°C (PGA)
or 0°C to 100°C (PQFP). Measure case temperature
at the top center of the package. Ambient temperature can be calculated from:
•
TJ = TC + P*θjc
•
TA = TJ + P*θja
•
TC = TA + P*[θja−θjc]
Figure 26 shows the maximum allowable ambient
temperature for the 20 MHz extended temperature
TA80960KB at various airflows. The curve assumes
an ICC of 420 mA, VCC of 5.0 V and a TCASE of
+125°C.
Values for θja and θjc for various airflows are given in
Table 12 for the PGA package and in Table 12 for
the PQFP package. The PGA’s θja can be reduced
by adding a heatsink. For the PQFP, however, a
heatsink is not generally used since the device is
intended to be surface mounted.
Maximum allowable ambient temperature (TA)
permitted without exceeding TC is shown by the
graphs in Figures 23, 24, 25 and 26. The curves
assume the maximum permitted supply current (ICC)
at each speed, VCC of +5.0 V and a TCASE of +85°C
(PGA) or +100°C (PQFP).
Table 14. 80960KB PGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
50
100
200
400
600
800
(0)
(0.25)
(0.50)
(1.01)
(2.03)
(3.04)
(4.06)
θ Junction-to-Case
2
2
2
2
2
2
2
θ Case-to-Ambient
(No Heatsink)
19
18
17
15
12
10
9
θ Case-to-Ambient
(Omnidirectional
Heatsink)
16
15
14
12
9
7
6
θ Case-to-Ambient
(Unidirectional Heatsink)
15
θJA
θJ-PIN
θJC
θJ-CAP
14
13
11
8
6
5
NOTES:
1. This table applies to 80960KB PGA plugged into socket or soldered directly to board.
2. θJA = θJC + θCA
3. θJ-CAP = 4°C/W (approx.)
θJ-PIN = 4°C/W (inner pins) (approx.)
θJ-PIN = 8°C/W (outer pins) (approx.)
29
80960KB
Table 15. 80960KB PQFP Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
50
100
200
400
600
800
(0)
(0.25)
(0.50)
(1.01)
(2.03)
(3.04)
(4.06)
θ Junction-to-Case
9
9
9
9
9
9
9
θ Case-to-Ambient (No Heatsink)
22
19
18
16
11
9
8
NOTES:
1. This table applies to 80960KB PQFP soldered directly to board.
2. θJA = θJC + θCA
3. θJL = 18°C/W (approx.)
θJB = 18°C/W (approx.)
θJC
θJL
θJB
Th
Th
Th
CLK2
CLK
T12
T11
HOLD
T6H
T9H
HLDA
Figure 22. HOLD Timing
30
80960KB
90
TEMPERATURE (oC)
85
80
75
70
65
60
55
0
200
400
600
800
AIRFLOW (ft/min)
PQFP
PGA with no
heatsink
PGA with omnidirectional heatsink
PGA with unidirectional heatsink
Figure 23. 16 MHz Maximum Allowable Ambient Temperature
90
85
TEMPERATURE (oC)
80
75
70
65
60
55
50
0
200
400
600
800
AIRFLOW (ft/min)
PQFP
PGA with no
heatsink
PGA with omnidirectional heatsink
PGA with unidirectional heatsink
Figure 24. 20 MHz Maximum Allowable Ambient Temperature
31
80960KB
85
80
TEMPERATURE (oC)
75
70
65
60
55
50
45
40
0
100
200
300
400
500
600
700
800
AIRFLOW (ft/min)
PQFP
PGA with no
heatsink
PGA with omnidirectional heatsink
PGA with unidirectional heatsink
Figure 25. 25 MHz Maximum Allowable Ambient Temperature
TEMPERATURE (o C)
120
115
110
105
100
95
90
0
100
200
300
400
500
600
700
800
AIRFLOW (ft/min)
PGA with no
heatsink
PGA with omnidirectional heatsink
PGA with unidirectional heatsink
Figure 26. Maximum Allowable Ambient Temperature for the Extended Temperature TA-80960KB at 20
MHz in PGA Package
32
80960KB
4.0
WAVEFORMS
Figures 27, 28, 29 and 30 show the waveforms for various transactions on the 80960KB’s local bus.
Ta
Td
Tr
Ta
Td
Tr
CLK2
CLK
LAD31:0
ALE
ADS
BE3:0
W/R
DT/R
DEN
READY
Figure 27. Non-Burst Read and Write Transactions Without Wait States
33
80960KB
Ta
Td
Td
Tr
Ta
Td
Td
Td
CLK2
CLK
LAD31:0
ALE
ADS
BE3:0
W/R
DT/R
DEN
READY
Figure 28. Burst Read and Write Transaction Without Wait States
34
Td
Tr
80960KB
Ta
Tw
Tw
Td
Tw
Td
Tw
Td
Tw
Td
Tr
CLK2
CLK
LAD31:0
ALE
ADS
BE3:0
W/R
DT/R
DEN
READY
Figure 29. Burst Write Transaction with 2, 1, 1, 1 Wait States
35
80960KB
Ta
Tw
Td
Td
Td
Td
Tr
Ta
Tw
Td
Tr
CLK2
CLK
LAD31:0
ALE
ADS
BE3:2
BE1:0
W/R
DT/R
DEN
READY
Figure 30. Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad
Word Boundary (1, 0, 0, 0 Wait States)
36
80960KB
PREVIOUS
CYCLE
INTERRUPT
ACKNOWLEDGEMENT
INTERRUPT
ACKNOWLEDGEMENT
IDLE
(5 BUS STATES)
CYCLE 1
TX
TX
Ta
Td
CYCLE 2
Tr
TI
TI
TI
TI
TI
Ta
Tw
Td
Tr
CLK2
CLK
INTR
LAD31:0
ADDR
ADDR
VECTOR
ALE
ADS
INTA
DT/R
DEN
LOCK
READY
NOTE:
INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1.
For a second interrupt to be acknowledged, INTR must be low for at least three cycles before it can be reasserted.
Figure 31. Interrupt Acknowledge Transaction
37
80960KB
5.0
REVISION HISTORY
Revision -008
To address the fact that many of the package prefix variables have changed, all package
prefix variables in this document are now indicated with an "x".
No revision history was maintained in earlier revisions of this data sheet. All errata that has been
identified to date is incorporated into this revision. The sections significantly changed since the
previous revision are:
Section
Last
Rev.
Description
Table 4. 80960KB Pin
Description: L-Bus Signals (pg. 8)
-005
LOCK pin description rewritten for clarity.
2.3. Connection Recommendations (pg. 11)
-005
Changed suggested open-drain termination networks to reflect
more realistic operating conditions with reduction in DC power
consumption.
Figure 9. Typical Current vs.
Frequency (Hot Temp) (pg. 13)
-005
Added figure for typical power supply current at hot
temperature to aid thermal analysis.
Figure 12. Test Load Circuit for
Three-State Output Pins (pg. 14)
-005
All outputs now specified with standard 50 pF test loads to
agree with actual test methodology.
Figure 13. Test Load Circuit for
Open-Drain Output Pins (pg. 14)
2.7. DC Characteristics (pg. 15)
-005
ICC max specification reduced:
WAS:
375 mA
420 mA
480 mA
IS:
315 mA
360 mA
420 mA
AT:
16 MHz
20 MHz
25 MHz
Figures 7, 8, 9, 23, 24, 25 and 26 have also been changed
accordingly.
2.8. AC Specifications (pg. 16)
-005
25 MHz operation extended to product in PQFP package. T8
min. improved at all frequencies from 0 ns to 2 ns and T8 max.
improved from 20 ns to 18 ns.
T8H max improvement:
WAS:
31ns
26ns
24ns
IS:
28ns
23ns
23ns
AT:
16 MHz
20 MHz
25 MHz
Functional Waveforms
-005
Redrawn for clarity. CLK signal drawn with more likely phase
relationship to CLK2. Open-drain output signals drawn to show
correct inactive states.
Various
-005
Deleted all references to 10 MHz. Intel no longer offers a
10 MHz 80960KB device.
Table 4. 80960KB Pin
Description: L-Bus Signals (pg. 8)
-006
DEN pin description omitted from revision -005.
Figure 18, 80960KB PGA
Pinout—View from Bottom (Pins
Facing Up) (pg. 22)
-006
38
Pin M2 was N.C., now shows as VCC
Pin M13 was VCC , now shows as N.C.