Am29SL400C Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number Am29SL400C Revision A Amendment +5 Issue Date March 3, 2005 This Page Left Intentionally Blank. ADVANCE INFORMATION Am29SL400C 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory Distinctive Characteristics ■ Single power supply operation — 1.65 to 2.2 V for read, program, and erase operations — Ideal for battery-powered applications ■ Manufactured on 0.32 µm process technology ■ High performance — Access times as fast as 100 ns ■ Ultra low power consumption (typical values at 5 MHz) — — — — 1 µA Automatic Sleep Mode current 1 µA standby mode current 5 mA read current 20 mA program/erase current ■ Flexible sector architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences ■ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses ■ Minimum 1,000,000 erase cycle guarantee per sector ■ 20-year data retention at 125°C ■ Package option — 48-ball FBGA — 48-pin TSOP ■ Compatibility with JEDEC standards — Pinout and software compatible with single-power supply Flash — Superior inadvertent write protection ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion ■ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data ■ Top or bottom boot block configurations available This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# Am29SL400C Rev: A Amendment+5 Refer to AMD’s Website (www.amd.com) for the latest information. A d v a n c e I n f o r m a t i o n General Description The Am29SL400C is an 4Mbit, 1.8 V volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-pin TSOP and 48-ball FBGA packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed and erased in-system with a single 1.8 volt VCC supply. No VPP is required for write or erase operations. The device can also be programmed in standard EPROM programmers. The standard device offers access times of 100, 110, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. 2 The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. March 3, 2005 A d v a n c e I n f o r m a t i o n Table of Contents Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Special Handling Instructions for FBGA Packages ............6 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9 Table 1. Am29SL400C Device Bus Operations ......................... 9 Word/Byte Configuration ........................................................9 Requirements for Reading Array Data .................................9 Writing Commands/Command Sequences ....................... 10 Program and Erase Operation Status ................................. 10 Standby Mode ............................................................................ 10 Automatic Sleep Mode ............................................................ 10 RESET#: Hardware Reset Pin ............................................... 10 Output Disable Mode ................................................................11 Table 2. Am29SL400CT Top Boot Block Sector Address Table ...................................................................................... 11 Table 3. Am29SL400CB Bottom Boot Block Sector Address Table ........................................................................ 11 Autoselect Mode .........................................................................11 Table 4. Am29SL400C Autoselect Codes (High Voltage Method) ................................................................................. 12 Sector Protection/Unprotection ...........................................12 Temporary Sector Unprotect ................................................12 Figure 1. In-System Sector Protect/Unprotect Algorithms.... 13 Figure 2. Temporary Sector Unprotect Operation................. 14 Hardware Data Protection .................................................... 14 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 14 Reading Array Data .................................................................. 14 Reset Command ........................................................................ 14 Autoselect Command Sequence ...........................................15 Word/Byte Program Command Sequence ........................15 Figure 3. Program Operation.......................................................... 16 Chip Erase Command Sequence ...........................................16 Sector Erase Command Sequence .......................................16 Figure 4. Erase Operation ............................................................... 17 Command Definitions ............................................................. 18 Table 5. Am29SL400C Command Definitions .......................... 18 Write Operation Status .......................................................... 18 DQ7: Data# Polling .................................................................. 19 Figure 5. Data# Polling Algorithm................................................. 19 RY/BY#: Ready/Busy# ............................................................. 19 DQ6: Toggle Bit I ..................................................................... 20 DQ2: Toggle Bit II .................................................................... 20 Reading Toggle Bits DQ6/DQ2 ........................................... 20 Figure 6. Toggle Bit Algorithm ....................................................... 21 DQ5: Exceeded Timing Limits ...............................................21 March 3, 2005 DQ3: Sector Erase Timer ....................................................... 21 Table 6. Write Operation Status ................................................. 22 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 22 Figure 7. Maximum Negative Overshoot Waveform............. 22 Figure 8. Maximum Positive Overshoot Waveform .............. 22 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ............................................................ 25 Figure 10. Typical ICC1 vs. Frequency........................................... 25 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11. Test Setup ......................................................................... 26 Table 7. Test Specifications ............................................................ 26 Key to Switching Waveforms ............................................... 26 Figure 12. Input Waveforms and Measurement Levels .......... 26 Read Operations .......................................................................27 Figure 13. Read Operations Timings ............................................ 27 Hardware Reset (RESET#) ................................................... 28 Figure 14. RESET# Timings ............................................................. 28 Figure 15. BYTE# Timings for Read Operations ...................... 29 Figure 16. BYTE# Timings for Write Operations.................... 29 Erase/Program Operations ................................................... 30 Figure 17. Program Operation Timings........................................ 31 Figure 18. Chip/Sector Erase Operation Timings .................... 32 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 19. Data# Polling Timings (During Embedded Algorithms) ......................................................................................... 33 Figure 20. Toggle Bit Timings (During Embedded Algorithms) ......................................................................................... 33 Figure 21. DQ2 vs. DQ6 .................................................................. 34 Temporary Sector Unprotect ...............................................34 Figure 22. Temporary Sector Unprotect Timing Diagram................................................................................................ 34 Figure 23. Sector Protect/Unprotect Timing Diagram .......... 35 Alternate CE# Controlled Erase/Program Operations ..................................................................................36 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 24. Alternate CE# Controlled Write Operation Timings ................................................................................................. 37 Erase and Programming Performance . . . . . . . . 38 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 38 TSOP Pin and BGA Package Capacitance . . . . . 38 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 39 TS048—48-Pin Standard TSOP ............................................39 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . .40 FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 8 mm Package .................................................... 40 Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . 41 3 A d v a n c e I n f o r m a t i o n Product Selector Guide Family Part Number Speed Options Am29SL400C Regulated Voltage Range VCC = 1.7–2.2 V -100R Standard Voltage Range VCC = 1.65–2.2 V -110 -120 -150 Max access time, ns (tACC) 100 110 120 150 Max CE# access time, ns (tCE) 100 110 120 150 Max OE# access time, ns (tOE) 35 45 50 65 Note: See “AC Characteristics” for full specifications. Block Diagram DQ0–DQ15 (A-1) RY/BY# VCC Sector Switches VSS Erase Voltage Generator RESET# WE# BYTE# Input/Output Buffers State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# VCC Detector A0–A17 4 Timer Address Latch STB STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix March 3, 2005 A d v a n c e I n f o r m a t i o n Connection Diagrams A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1 March 3, 2005 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Standard TSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 5 A d v a n c e I n f o r m a t i o n Connection Diagram 48-Ball FBGA (Top View, Balls Facing Down) A6 B6 C6 D6 E6 A13 A12 A14 A15 A16 A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A4 B4 C4 D4 E4 F4 G4 H4 WE# RESET# NC NC DQ5 DQ12 VCC DQ4 A3 B3 C3 D3 E3 F3 G3 H3 RY/BY# NC NC NC DQ2 DQ10 DQ11 DQ3 A2 B2 C2 D2 E2 F2 G2 H2 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A1 B1 C1 D1 E1 F1 G1 H1 A3 A4 A2 A1 A0 CE# OE# VSS Special Handling Instructions for FBGA Packages Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PLCC, PDIP, 6 F6 G6 BYTE# DQ15/A-1 H6 VSS SSOP). The package and/or data integrity may be compromised if the package body is exposed to temperatures about 150°C for prolonged periods of time. March 3, 2005 A d v a n c e I n f o r m a t i o n Pin Configuration NC A0–A17 Logic Symbol = 18 addresses DQ0–DQ14= 15 data inputs/outputs DQ15/A-1 = = Pin not connected internally 18 DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) A0–A17 DQ0–DQ15 (A-1) BYTE# = Selects 8-bit or 16-bit mode CE# CE# = Chip enable OE# OE# = Output enable WE# WE# = Write enable RESET# RESET# = Hardware reset pin, active low BYTE# RY/BY# = Ready/Busy# output VCC = 1.65–2.2 V single power supply VSS = Device ground March 3, 2005 16 or 8 RY/BY# 7 A d v a n c e I n f o r m a t i o n Ordering Information Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am29SL400C T 100R E C TEMPERATURE RANGE C = Commercial (0°C to +70°C) D = Commercial (0°C to +70°C) with Pb-free Package F = Industrial (-40°C to +85°C) with Pb-free Package I = Industrial (–40°C to +85°C) PACKAGE TYPE WA = 48-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 8 mm package (FBA048) E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top Sector B = Bottom Sector DEVICE NUMBER/DESCRIPTION Am29SL400C 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory 1.8 Volt-only Read, Program, and Erase Valid Combinations for TSOP Packages Order Number Order Number AM29SL400CT100R, AM29SL400CB100R AM29SL400CT110, AM29SL400CB110 AM29SL400CT120, AM29SL400CB120 AM29SL400CT150, AM29SL400CB150 Valid Combinations for FBGA Packages Package Marking AM29SL400CT100R, AM29SL400CB100R EC, EI, ED, EF A400CT10R, A400CB10R AM29SL400CT110, AM29SL400CB110 WAC AM29SL400CT120, AM29SL400CB120 WAD, AM29SL400CT150, AM29SL400CB150 WAI WAF A400CT11V, A400CB11V A400CT12V, A400CB12V C, I, D, F A400CT15V, A400CB15V Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 8 March 3, 2005 A d v a n c e I n f o r m a t i o n Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the ad- Table 1. dress and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am29SL400C Device Bus Operations DQ8–DQ15 CE# OE# WE # RESET# Addresses (Note 1) DQ0– DQ7 BYTE# = VIH BYTE# = VIL Read L L H H AIN DOUT DOUT Write L H L H AIN DIN DIN DQ8–DQ14 = High-Z, DQ15 = A-1 VCC ± 0.2 V X X VCC ± 0.2 V X High-Z High-Z High-Z Output Disable L H H H X High-Z High-Z High-Z Reset X X X L X High-Z High-Z High-Z Sector Protect (Note 2) L H L VID Sector Address, A6 = L, A1 = H, A0 = L DIN X X Sector Unprotect (Note 2) L H L VID Sector Address, A6 = H, A1 = H, A0 = L DIN X X Temporary Sector Unprotect X X X VID AIN DIN DIN High-Z Operation Standby Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 10 ± 1.0 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A17:A0 in word mode (BYTE# = VIH), A17:A-1 in byte mode (BYTE# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection/Unprotection” section. Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. March 3, 2005 WE# should remain at VIH . The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See Reading Array Data‚ on page 14 for more information. Refer to the AC Read Operations table for timing specifications and to Figure 14‚ on page 28 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. 9 A d v a n c e I n f o r m a t i o n Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to Word/Byte Configuration‚ on page 9 for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The Word/Byte Program Command Sequence‚ on page 15 has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 on page 11 and Table 3 on page 11 indicate the address space that each sector occupies. A sector address consists of the address bits required to uniquely select a sector. Command Definitions‚ on page 18 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode‚ on page 11 and Autoselect Command Sequence‚ on page 15 for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics‚ on page 28 contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status‚ on page 18 for more information, and to AC Characteristics‚ on page 28 for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.2 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within V CC ± 0.2 V, the device will be in the 10 standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, RESET#: Hardware Reset Pin. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in DC Characteristics‚ on page 24 represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 50 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.2 V, the device draws CMOS standby current (I CC4 ). If RESET# is held at V IL but not within VSS ±0.2 V, the standby current is greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is completed within a time of t READY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. March 3, 2005 A d v a n c e I n f o r m a t i o n Refer to the AC Characteristics tables for RESET# parameters and to Figure 15‚ on page 29 for the timing diagram. Table 2. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Am29SL400CT Top Boot Block Sector Address Table Address Range (in hexadecimal) Sector A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) SA0 0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh SA1 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh SA2 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh SA3 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh SA4 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh SA5 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh SA6 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh SA7 1 1 1 0 X X 32/16 70000h–77FFFh 38000h–3BFFFh SA8 1 1 1 1 0 0 8/4 78000h–79FFFh 3C000h–3CFFFh SA9 1 1 1 1 0 1 8/4 7A000h–7BFFFh 3D000h–3DFFFh SA10 1 1 1 1 1 X 16/8 7C000h–7FFFFh 3E000h–3FFFFh Table 3. (x8) Address Range (x16) Address Range Am29SL400CB Bottom Boot Block Sector Address Table Address Range (in hexadecimal) Sector A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) SA0 0 0 0 0 0 X 16/8 00000h–03FFFh 00000h–01FFFh SA1 0 0 0 0 1 0 8/4 04000h–05FFFh 02000h–02FFFh SA2 0 0 0 0 1 1 8/4 06000h–07FFFh 03000h–03FFFh SA3 0 0 0 1 X X 32/16 08000h–0FFFFh 04000h–07FFFh SA4 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh SA5 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh SA6 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh SA7 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh SA8 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh SA9 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh SA10 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh (x8) Address Range (x16) Address Range Note for Tables 2 and 3: Address range is A17:A-1 in byte mode and A17:A0 in word mode. See “Word/Byte Configuration” section for more information. Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming March 3, 2005 algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4 on page 12. In addition, when verifying sector protection, the sector address must appear on the appro- 11 A d v a n c e I n f o r m a t i o n priate highest order address bits (see Table 2 on page 11 and Table 3 on page 11). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. Table 4. Description Am29SL400C Autoselect Codes (High Voltage Method) A17 A11 to to WE# A12 A10 CE# OE# Manufacturer ID: AMD L L H Device ID: Am29SL400C (Top Boot Block) Word L L H Byte L L H Device ID: Am29SL400C (Bottom Boot Block) Word L L H Byte L L H Sector Protection Verification Mode To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5 on page 18. This method does not require VID. See Command Definitions‚ on page 18 for details on using the autoselect mode. L L H A9 A8 to A7 A6 A5 to A2 A1 A0 DQ8 to DQ15 DQ7 to DQ0 X 01h 22h 70h X 70h 22h F1h X F1h X 01h (protected) X 00h (unprotected ) X X VID X L X L L X X VID X L X L H X SA X X VID VID X X L L X X L H H L L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods. Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2‚ on page 14 shows the algorithms and Figure 24‚ on page 37 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The device is shipped with all sectors unprotected. AMD offers the option of programming and protect- 12 ing sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode‚ on page 11 for details. Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 3‚ on page 16 shows the algorithm, and Figure 22 shows the timing diagrams, for this feature. March 3, 2005 A d v a n c e I n f o r m a t i o n START START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT = 1 RESET# = VID Wait 1 µs Temporary Sector Unprotect Mode No PLSCNT = 1 RESET# = VID Wait 1 µs No First Write Cycle = 60h? First Write Cycle = 60h? Yes Yes Set up sector address No All sectors protected? Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Wait 150 µs Increment PLSCNT Temporary Sector Unprotect Mode Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Reset PLSCNT = 1 Read from sector address with A6 = 0, A1 = 1, A0 = 0 Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 Increment PLSCNT No No PLSCNT = 25? Yes Yes No Yes Device failed Protect another sector? No PLSCNT = 1000? Yes Remove VID from RESET# Device failed Write reset command Sector Protect Algorithm Read from sector address with A6 = 1, A1 = 1, A0 = 0 Data = 01h? Sector Protect complete Set up next sector address No Data = 00h? Yes Last sector verified? No Yes Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Figure 1. In-System Sector Protect/Unprotect Algorithms March 3, 2005 13 A d v a n c e I n f o r m a t i o n START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) tection against inadvertent writes (refer to Table 5 on page 18 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Figure 2. Temporary Sector Unprotect Operation Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data pro- Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 5 on page 18 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the AC Characteristics section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address 14 Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the Reset Command‚ on page 14 section, next. See also Requirements for Reading Array Data‚ on page 9 for more information. The Read Operations table provides the read parameters, and Figure 14‚ on page 28 shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the de- March 3, 2005 A d v a n c e I n f o r m a t i o n vice ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 5 on page 18 shows the address and data requirements. This method is an alternative to that shown in Table 4 on page 12, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address 01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table 2 on page 11 and Table 3 on page 11 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device auto- March 3, 2005 matically generates the program pulses and verifies the programmed cell margin. Table 5 on page 18 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status‚ on page 18 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1. Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 5 on page 18 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t cares. The device then returns to reading array data. Figure 3‚ on page 16 illustrates the algorithm for the program operation. See Erase/Program Operations‚ on page 30 for parameters, and Figure 17‚ on page 31 for timing diagrams. 15 A d v a n c e I n f o r m a t i o n of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status‚ on page 18 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. START Figure 4‚ on page 17 illustrates the algorithm for the erase operation. See Erase/Program Operations‚ on page 30 for parameters, and to Figure 18 for timing diagrams. Write Program Command Sequence Sector Erase Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Yes Increment Address No Last Address? Yes Programming Completed Note: See Table 5 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 5 on page 18 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity The system can determine the status 16 Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 5 on page 18 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. March 3, 2005 A d v a n c e I n f o r m a t i o n When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to Write Operation Status‚ on page 18 for information on these status bits.) Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations‚ on page 30 for parameters, and to Figure 18‚ on page 32 for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are don’t-cares when writing the Erase Suspend command. program operation. See Write Operation Status‚ on page 18 for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence‚ on page 15 for more information. The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. START Write Erase Command Sequence When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Normal read and write timings and command definit i o n s a p p l y. R e a d i n g a t a n y a d d r e s s w i t h i n erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status‚ on page 18 for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard March 3, 2005 Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Notes: 1. See Table 5 on page 18 for erase command sequence. 2. See DQ3: Sector Erase Timer‚ on page 21 for more information. Figure 4. Erase Operation 17 A d v a n c e I n f o r m a t i o n Command Definitions Cycles Table 5. Command Sequence (Note 1) Am29SL400C Command Definitions Bus Cycles (Notes 2-5) First Second Addr Dat a Read (Note 6) 1 RA RD Reset (Note 7) 1 XXX F0 Autoselect (Note 8) Manufacturer ID Word Byte Device ID, Top Boot Block Word Device ID, Bottom Boot Block Word Sector Protect Verify (Note 9) Program Unlock Bypass Byte Byte 4 4 4 Word 555 AAA 555 AAA 555 AAA AA AA AA 555 4 Addr 2AA 555 2AA 555 2AA 555 Third Dat a 555 55 AAA 555 55 AAA 555 55 AAA 2AA AA 55 AAA 555 AAA Word 555 2AA 555 Word Byte 4 3 AAA 555 AAA AA AA 555 2AA 555 55 AAA 555 55 AAA 2 XXX A0 PA PD Unlock Bypass Reset (Note 11) 2 XXX 90 XXX 00 Sector Erase Word Byte Word Byte 6 6 555 AAA 555 AAA AA AA Erase Suspend (Note 12) 1 XXX B0 Erase Resume (Note 13) 1 XXX 30 2AA 555 2AA 555 Data 90 X00 01 X01 70h X02 70h X01 FIh 90 90 90 Byte Byte Addr 555 Unlock Bypass Program (Note 10) Chip Erase Addr Fourth Dat a 55 55 555 AAA 555 AAA A0 X02 FIh (SA) X02 XX00 (SA) X04 00 PA PD Fifth Addr Dat a Sixth Addr Dat a XX01 01 20 80 80 555 AAA 555 AAA AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17–A12 uniquely select any sector. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles. 5. Address bits A17–A11 are don’t cares for unlock and command cycles, unless SA or PA required. 6. No unlock or command cycles required when reading array data, unless SA or PA required. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle. 9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command 18 Sequence” for more information. 10. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. 12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 13. The Erase Resume command is valid only during the Erase Suspend mode. Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 6 on page 22 and the following March 3, 2005 A d v a n c e I n f o r m a t i o n subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. START DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. Read DQ7–DQ0 Addr = VA During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading array data. DQ7 = Data? No No DQ5 = 1? Yes During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7–DQ0 on the following read cycles. This is beca us e DQ 7 m ay c h a n ge a s ynch r onou sly with DQ0–DQ6 while Output Enable (OE#) is asserted low. Figure 19‚ on page 33 Data# Polling Timings (During Embedded Algorithms), illustrates this. Table 6 on page 22 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. Yes Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes program- March 3, 2005 19 A d v a n c e I n f o r m a t i o n ming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 6 on page 22 shows the outputs for RY/BY#. Figure 14‚ on page 28, Figure 17‚ on page 31, and Figure 18‚ on page 32 shows RY/BY# for reset, program, and erase operations, respectively. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle (The system may use either OE# or CE# to control the read cycles). When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling‚ on page 19). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 6 on page 22 shows the outputs for Toggle Bit I on DQ6. Figure 6‚ on page 21 shows the toggle bit algorithm. Figure 20‚ on page 33 shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II‚ on page 20. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing 20 (tha t is , the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. The device toggles DQ2 with each OE# or CE# read cycle. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 on page 22 to compare outputs for DQ2 and DQ6. Figure 6‚ on page 21 shows the toggle bit algorithm in flowchart form, and the section DQ2: Toggle Bit II‚ on page 20 explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 20‚ on page 33 shows the toggle bit timing diagram. Figure 21‚ on page 34 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6‚ on page 21 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6‚ on page 21). March 3, 2005 A d v a n c e I n f o r m a t i o n Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed. START Read DQ7–DQ0 (Note 1) Under both these conditions, the system must issue the reset command to return the device to reading array data. Read DQ7–DQ0 Toggle Bit = Toggle? No Yes No DQ5 = 1? Yes Read DQ7–DQ0 Twice Toggle Bit = Toggle? (Notes 1, 2) No Yes Program/Erase Operation Not Complete, Write Reset Command The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to “0.” Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a 1. Program/Erase Operation Complete DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also Sector Erase Command Sequence‚ on page 16. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 1, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 6 on page 22 shows the outputs for DQ3. Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text. Figure 6. Toggle Bit Algorithm DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. March 3, 2005 21 A d v a n c e Table 6. Erase Suspend Mode Write Operation Status DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) RY/BY# DQ7# Toggle 0 N/A No toggle 0 0 Toggle 0 1 Toggle 0 1 No toggle 0 N/A Toggle 1 Reading within Non-Erase Suspended Sector Data Data Data Data Data 1 Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0 Operation Standard Mode I n f o r m a t i o n Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Notes: 1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5: Exceeded Timing Limits‚ on page 21 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. Absolute Maximum Ratings Storage Temperature Plastic Packages . . . . . . . . . . . . . .–65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . .–65°C to +125°C Voltage with Respect to Ground . . . . . . . . . . . . . . . . VCC (Note 1)–0.5 V to +2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A9, OE#, and RESET# (Note 2) . . . . . . . . . –0.5 V to +11.0 V . . . . . . All other pins (Note 1)–0.5 V to VCC+0.5 V Output Short Circuit Current (Note 3) . . . . . 100 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See. Maximum DC input voltage on pin A9 is +11.0 V which may overshoot to 12.5 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 20 ns 20 ns 20 ns 0.0 V VCC +2.0 V –0.5 V VCC +0.5 V –2.0 V 2.0 V 20 ns Figure 7. Maximum Negative Overshoot Waveform 22 20 ns 20 ns Figure 8. Maximum Positive Overshoot Waveform March 3, 2005 A d v a n c e I n f o r m a t i o n Operating Ranges Commercial (C) Devices VCC for regulated voltage range . +1.70 V to +2.2 V Operating ranges define those limits between which the functionality of the device is guaranteed. Ambient Temperature (TA). . . . . . . . . 0°C to +70°C Industrial (I) Devices Ambient Temperature (TA). . . . . . . –40°C to +85°C VCC Supply Voltages VCC for full voltage range . . . . . +1.65 V to +2.2 V March 3, 2005 23 A d v a n c e I n f o r m a t i o n DC Characteristics CMOS Compatible Parameter Description Test Conditions Min ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ILIT A9 Input Load Current VCC = VCC max; A9 = 11.0 V ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ICC1 VCC Active Read Current (Notes 1, 2) Typ Max Unit ±1.0 µA 35 µA ±1.0 µA CE# = VIL, OE# = VIH, Byte Mode 5 MHz 5 10 1 MHz 1 3 CE# = VIL, OE# = VIH, Word Mode 5 MHz 5 10 1 MHz 1 3 20 25 mA mA ICC2 VCC Active Write Current (Notes 2, 3, 5) CE# = VIL, OE# = VIH ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.2 V 1 5 µA ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.2 V 1 5 µA ICC5 Automatic Sleep Mode (Notes 2, 3) VIH = VCC ± 0.2 V; VIL = VSS ± 0.2 V 1 5 µA VIL Input Low Voltage –0.5 0.2 x VCC V VIH Input High Voltage 0.8 x VCC VCC + 0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect 9.0 11.0 V IOL = 2.0 mA, VCC = VCC min 0.25 V IOL = 100 µA, VCC = VCC min 0.1 V VOL1 VOL2 VOH1 VOH2 VLKO Output Low Voltage Output High Voltage VCC = 2.0 V IOH = –2.0 mA, VCC = VCC min 0.7 x VCC V IOH = –100 µA, VCC = VCC min VCC–0.1 V Low VCC Lock-Out Voltage (Note 4) 1.2 1.5 V Notes: 1. The ICC current listed is typically less than 1 mA/MHz, with OE# at VIH. Typical VCC is 2.0 V. 2. The maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 50 ns. 5. Not 100% tested. 24 March 3, 2005 A d v a n c e I n f o r m a t i o n DC Characteristics (Continued) Zero Power Flash Supply Current in mA 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 Time in ns Note: Addresses are switching at 1 MHz Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 10 Supply Current in mA 8 6 2.2 V 4 1.8 V 2 0 1 2 3 4 5 Frequency in MHz Note: T = 25 °C Figure 10. Typical ICC1 vs. Frequency March 3, 2005 25 A d v a n c e I n f o r m a t i o n Test Conditions Table 7. Test Specifications Test Condition All Speed Options Unit Output Load Capacitance, CL (including jig capacitance) 30 pF 5 ns 0.0–2.0 V Input timing measurement reference levels 1.0 V Output timing measurement reference levels 1.0 V Input Rise and Fall Times Device Under Test Input Pulse Levels CL Figure 11. Test Setup Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H 2.0 V Input Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 1.0 V Measurement Level 1.0 V Output 0.0 V Figure 12. Input Waveforms and Measurement Levels 26 March 3, 2005 A d v a n c e I n f o r m a t i o n AC Characteristics Read Operations Parameter Speed Options JEDEC Std Description tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay tGLQV tOE tEHQZ tGHQZ Test Setup -100R -110 -120 -150 Unit Min 100 110 120 150 ns CE# = VIL OE# = VIL Max 100 110 120 150 ns OE# = VIL Max 100 110 120 150 ns Output Enable to Output Delay Max 35 45 50 65 ns tDF Chip Enable to Output High Z (Note 1) Max 16 ns tDF Output Enable to Output High Z (Note 1) Max 16 ns Read Min 0 ns Toggle and Data# Polling Min 30 ns Min 0 ns tOEH Output Enable Hold Time (Note 1) tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) tAXQX Notes: 1. Not 100% tested. 2. See Figure 11‚ on page 26 and Table 7 on page 26 for test specifications. tRC Addresses Stable Addresses tACC CE# tDF tOE OE# tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs RESET# RY/BY# 0V Figure 13. Read Operations Timings March 3, 2005 27 A d v a n c e I n f o r m a t i o n AC Characteristics Hardware Reset (RESET#) Parameter JEDEC Std Description Test Setup All Speed Options Unit tREADY RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) Max 20 µs tREADY RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH RESET# High Time Before Read (See Note) Min 200 ns tRPD RESET# Low to Standby Mode Min 20 µs tRB RY/BY# Recovery Time Min 0 ns Note: Not 100% tested. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Figure 14. RESET# Timings 28 March 3, 2005 A d v a n c e I n f o r m a t i o n AC Characteristics Word/Byte Configuration (BYTE#) Parameter JEDEC Speed Options Description Std -100R -110 -120 -150 10 Unit tELFL/tELFH CE# to BYTE# Switching Low or High Max ns tFLQZ BYTE# Switching Low to Output HIGH Z Max 50 55 60 60 ns tFHQV BYTE# Switching High to Output Active Min 100 110 120 150 ns CE# OE# BYTE# BYTE# Switching from word to byte mode DQ0–DQ14 tELFL Data Output (DQ0–DQ14) Address Input DQ15 Output DQ15/A-1 Data Output (DQ0–DQ7) tFLQZ tELFH BYTE# BYTE# Switching from byte to word mode Data Output (DQ0–DQ7) DQ0–DQ14 Address Input DQ15/A-1 Data Output (DQ0–DQ14) DQ15 Output tFHQV Figure 15. BYTE# Timings for Read Operations CE# The falling edge of the last WE# signal WE# BYTE# tSET (tAS) tHOLD (tAH) Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 16. BYTE# Timings for Write Operations March 3, 2005 29 A d v a n c e I n f o r m a t i o n AC Characteristics Erase/Program Operations Parameter Speed Options JEDEC Std Description -100R -110 -120 -150 Unit tAVAV tWC Write Cycle Time (Note 1) Min 100 110 120 150 ns tAVWL tAS Address Setup Time Min tWLAX tAH Address Hold Time Min 50 55 60 70 ns tDVWH tDS Data Setup Time Min 50 55 60 70 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns 0 ns tGHWL tGHWL tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min tWHWL tWPH Write Pulse Width High Min 30 tWHWH1 tWHWH1 Programming Operation (Notes 1, 2) Byte Typ 10 Word Typ 12 tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 2 sec tVCS VCC Setup Time Min 50 µs tRB Recovery Time from RY/BY# Min 0 ns Program/Erase Valid to RY/BY# Delay Min 200 ns tBUSY 50 55 60 70 ns ns µs Notes: 1. Not 100% tested. 2. See the Erase and Programming Performance‚ on page 38 section for more information. 30 March 3, 2005 A d v a n c e I n f o r m a t i o n AC Characteristics Program Command Sequence (last two cycles) tAS tWC Addresses Read Status Data (last two cycles) 555h PA PA PA tAH CE# tCH OE# tWHWH1 tWP WE# tWPH tCS tDS tDH A0h Data PD Status tBUSY DOUT tRB RY/BY# VCC tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Figure 17. Program Operation Timings March 3, 2005 31 A d v a n c e I n f o r m a t i o n AC Characteristics Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SA VA 555h for chip erase tAH CE# tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h In Progress 30h Complete 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status‚ on page 18 2. Illustration shows device in word mode. Figure 18. Chip/Sector Erase Operation Timings 32 March 3, 2005 A d v a n c e I n f o r m a t i o n AC Characteristics tRC Addresses VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement Status Data Status Data Valid Data True High Z DQ0–DQ6 Valid Data True tBUSY RY/BY# Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 19. Data# Polling Timings (During Embedded Algorithms) tRC Addresses VA VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ6/DQ2 tBUSY Valid Status Valid Status (first read) (second read) Valid Status Valid Data (stops toggling) RY/BY# Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 20. Toggle Bit Timings (During Embedded Algorithms) March 3, 2005 33 A d v a n c e I n f o r m a t i o n AC Characteristics Enter Embedded Erasing Erase Suspend Erase WE# Enter Erase Suspend Program Erase Suspend Read Erase Resume Erase Suspend Program Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 21. DQ2 vs. DQ6 Temporary Sector Unprotect Parameter JEDEC Std tVIDR tRSP Description VID Rise and Fall Time RESET# Setup Time for Temporary Sector Unprotect All Speed Options Unit Min 500 ns Min 4 µs 10 V RESET# 0 or 1.8 V 0 or 1.8 V tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRSP RY/BY# Figure 22. Temporary Sector Unprotect Timing Diagram 34 March 3, 2005 A d v a n c e I n f o r m a t i o n AC Characteristics VID VIH RESET# SA, A6, A1, A0 Valid* Valid* Sector Protect/Unprotect Data 60h 1 µs Valid* Verify 60h 40h Status Sector Protect: 150 µs Sector Unprotect: 15 ms CE# WE# OE# * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 23. Sector Protect/Unprotect Timing Diagram March 3, 2005 35 A d v a n c e I n f o r m a t i o n AC Characteristics Alternate CE# Controlled Erase/Program Operations Speed Options Parameter JEDEC Std Description tAVAV tWC Write Cycle Time (Note 1) Min tAVEL tAS Address Setup Time Min tELAX tAH Address Hold Time Min 50 55 60 70 ns tDVEH tDS Data Setup Time Min 50 55 60 70 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min tEHEL tCPH CE# Pulse Width High Min 30 tWHWH1 tWHWH1 Programming Operation (Notes 1, 2) Byte Typ 10 Word Typ 12 tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 2 -100R -110 -120 -150 Unit 100 110 120 150 ns 0 50 55 ns 60 70 ns ns µs sec Notes: 1. Not 100% tested. 2. See the Erase and Programming Performance‚ on page 38 section for more information. 36 March 3, 2005 A d v a n c e I n f o r m a t i o n AC Characteristics 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tCP CE# tWS tWHWH1 or 2 tCPH tBUSY tDS tDH DQ7# Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# Notes: 1. PA = program address, PD = program data, DQ7# = complement of the data written, DOUT = data written 2. Figure indicates the last two bus cycles of command sequence. 3. Word mode address used as an example. Figure 24. Alternate CE# Controlled Write Operation Timings March 3, 2005 37 A d v a n c e I n f o r m a t i o n Erase and Programming Performance Parameter Typ (Note 1) Max (Note 2) Unit 2 15 s Sector Erase Time Chip Erase Time 38 s Byte Programming Time 10 300 µs Word Programming Time 12 360 µs Chip Programming Time Byte Mode 5 40 s (Note 3) Word Mode 3.5 30 s Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 2.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 1.8 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5 on page 18 for further information on command definitions. 6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles. Latchup Characteristics Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 11.0 V Input voltage with respect to VSS on all I/O pins –0.5 V VCC + 0.5 V –100 mA +100 mA VCC Current Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time. TSOP Pin and BGA Package Capacitance Parameter Symbol Parameter Description Test Setup CIN Input Capacitance VIN = 0 COUT Output Capacitance VOUT = 0 CIN2 Control Pin Capacitance VIN = 0 Typ Max Unit TSOP 6 7.5 pF Fine-pitch BGA 4.2 5.0 pF TSOP 8.5 12 pF Fine-pitch BGA 5.4 6.5 pF TSOP 7.5 9 pF Fine-pitch BGA 3.9 4.7 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. Data Retention Parameter Minimum Pattern Data Retention Time 38 Test Conditions Min Unit 150°C 10 Years 125°C 20 Years March 3, 2005 A d v a n c e I n f o r m a t i o n Physical Dimensions TS048—48-Pin Standard TSOP Dwg rev AA; 10/99 March 3, 2005 39 A d v a n c e I n f o r m a t i o n Physical Dimensions FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 8 mm Package Dwg rev AF; 10/99 40 March 3, 2005 A d v a n c e I n f o r m a t i o n Revision Summary Revision A + 3 (February 26, 2003) Revision A (August 14, 2002) Global Initial Release. Added 110 ns speed option. Revision A+1 (August 28, 2002) Distinctive Characteristics Sector Protection/Unprotection Updated Automatic Sleep Mode and standby mode current values. Changed beginning of second paragraph from, “The primary method....” to read, “Sector protection/unprotection.” Pin Configuration Updated VCC low-end value. Deleted third paragraph. Ordering Information FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 8 mm package Changed WB package type to WA. Changed number in row D in table from 9.00 mm to 8.0 mm. Revision A + 2 (February 5, 2003) Global Changed fastest speed option from 103 ns to 100 ns, regulated voltage, added 110 ns speed option standard voltage. General Description Changed first sentenced to indicate 48-pin TSOP package option. Command Definitions, Table 5 Removed TBD markers from device ID, Top Boot Block to 70h. DC Characteristics, CMOS Compatible Updated VCC Standby and Reset currents Typ values, and Automatic Sleep Mode Typ value. Revision A+ 4 (March 18, 2003) Ordering Information, Valid Combinations Removed dashes from Order Numbers. Revision A + 5 (March 3, 2005) Ordering Information Added Commercial and Industrial Pb-free Package temperatures. Valid Combinations for TSOP package Added two package codes Removed TBD markers from device ID, Bottom Boot Block to FIh. Valid Combination for FBGA package Changed address bits A18–A11 to A17–A11. Global Physical Dimensions, 48-pin TSOP Added Colophon. Changed from Reverse to Standard TSOP package. Updated Trademark information. March 3, 2005 Added two package codes 41 A d v a n c e I n f o r m a t i o n Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks Copyright ©2003-2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 42 March 3, 2005