Agere BPNGA16P Quad differential driver Datasheet

Data Sheet
January 1999
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Features
■
Pin-equivalent to the general-trade 26LS31 device,
with improved speed, reduced power consumption,
and significantly lower levels of EMI
■
Four line drivers per package
■
Meets ESDI standards
■
2.0 ns maximum propagation delay
■
Single 5.0 V ± 10% supply
■
Operating temperature range: −40 °C to +125 °C
(wider than the 41 Series)
■
400 Mbits/s maximum data rate
■
Logic to convert TTL input logic levels to differential, pseudo-ECL output logic levels
■
No line loading when VCC = 0 (BDG1A, BDP1A
only)
■
High output driver for 50 Ω loads
■
<0.2 ns output skew (typical)
■
On-chip 220 Ω loads available
■
Third-state outputs available
■
Surge-protection to ±60 V for 10 ms available
(BPNGA, BPNPA, BPPGA)
■
Available in four package types
■
ESD performance better than the 41 Series
■
Lower power requirement than the 41 Series
Description
These quad differential drivers are TTL input-topseudo-ECL-differential-output used for digital data
transmission over balanced transmission lines. All
devices in this family have four drivers with a single
enable control in a common package. These drivers
are compatible with many receivers, including the
Agere Systems Inc. 41 Series receivers and transceivers. They are pin equivalent to the general-trade
26LS31, but offer increased speed, decreased power
consumption, and significantly lower levels of electromagnetic interference (EMI). They replace the Agere
41 Series drivers.
The BDG1A device is the generic driver in this family
and requires the user to supply external resistors on
the circuit board for impedance matching.
The BDGLA is a low-power version of the BDG1A,
reducing the power requirement by more than one
half. The BDGLA features a 3-state output with a typical third-state level of 0.2 V.
The BDP1A is equivalent to the BDG1A but has
220 Ω termination resistors to ground on each driver
output. This eliminates the need for external pulldown resistors when driving a 100 Ω impedance line.
The BPNGA and BPNPA are equivalent to the
BDG1A and BDP1A, respectively, except that a lightning protection circuit has been added to the driver
outputs. This circuit will absorb large transitions on
the transmission lines without destroying the device.
The BPPGA combines the features of the BPNGA
and BPNPA. Two of the gates have their outputs terminated to ground through 220 Ω resistors while the
two remaining gates require external termination
resistors.
When the BDG1A and the BDP1A devices are powered down, the output circuit appears as an open circuit relative to the power supplies; hence, they will
not load the transmission line. For those circuits with
termination resistors, the line will remain impedance
matched when the circuit is powered down. The
BPNGA, BPNPA, BPPGA, and BDGLA will load the
transmission line, because of the protection circuit,
when the circuit is powered down.
The packaging options that are available for these
quad differential line drivers include a 16-pin DIP; a
16-pin, J-lead SOJ; a 16-pin, gull-wing SOIC; and a
16-pin, narrow-body, gull-wing SOIC.
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Data Sheet
January 1999
Pin Information
AI
AO
16 VCC
1
2
AO
3
E1
A
AI
15 DI
D
AO
2
14 DO
AO
3
4
13 DO
E1
BO
5
12 E2
BO
6
11 CO
A
15 DI
D
AO
2
15 DI
D
4
13 DO
E1
4
13 DO
BO
5
12 E2
BO
5
12 E2
BO
6
11 CO
BO
6
BI
10 CO
A
3
B
7
16 VCC
1
AO
11 CO
BI
10 CO
7
10 CO
7
C
8
9
GND
CI
8
BDG1A
BDGLA
BPNGA
14 DO
B
C
GND
AI
14 DO
B
BI
16 VCC
1
C
9
CI
GND
BDP1A
BPNPA
8
9
CI
BPPGA
12-2038b (F)
Figure 1. Quad Differential Driver Logic Diagrams
Table 1. Enable Truth Table
E1
0
1
0
1
E2
0
0
1
1
Condition
Active
Active
Disabled
Active
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter
Power Supply Voltage
Ambient Operating Temperature
Storage Temperature
2
Symbol
VCC
TA
Tstg
Min
—
−40
−55
Max
6.5
125
150
Unit
V
°C
°C
Agere Systems Inc.
Data Sheet
January 1999
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Electrical Characteristics
For electrical characteristics over the entire temperature range, see Figures 7 through 9.
Table 2. Power Supply Current Characteristics
TA = –40 °C to +125 °C, VCC = 5 V ± 0.5 V.
Parameter
Power Supply Current (VCC = 5.5 V):
All Outputs Disabled:
BDG1A*, BPNGA*
BDP1A†, BPNPA†
BDGLA*
BPPGA*†
All Outputs Enabled:
BDG1A*, BPNGA*
BDP1A†, BPNPA†
BDGLA*
BPPGA*†
Symbol
Min
Typ
Max
Unit
ICC
ICC
ICC
ICC




45
120
35
85
65
160
55
115
mA
mA
mA
mA
ICC
ICC
ICC
ICC




25
150
14
90
40
200
20
115
mA
mA
mA
mA
* Measured with no load (BPPGA has no load on drivers C and D).
† The additional power dissipation is the result of integrating the termination resistors into the device. ICC is measured with a 100 Ω resistor
across the driver outputs (BPPGA has terminating resistors on drivers A and B).
Third State
These drivers produce pseudo-ECL levels, and the third-state mode is different than the conventional TTL devices.
When a driver is placed in the third state, the bases of the output transistors are pulled low, bringing the outputs
below the active-low levels. This voltage is typically 2 V for most drivers. In the bidirectional bus application, the
driver of one device, which is in its third state, may be back driven by another driver on the bus whose voltage in
the low state is lower than the third-stated device. This could come about due to differences in the drivers’ independent power supplies. In this case, the device in the third state will control the line, thus clamping the line and reducing the signal swing. If the difference voltage between the independent power supplies and the drivers is small,
then this consideration can be ignored. In the typical case, the difference voltage can be as much as 1 V without
significantly affecting the amplitude of the driving signal.
Agere Systems Inc.
3
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Data Sheet
January 1999
Electrical Characteristics (continued)
Table 3. Voltage and Current Characteristics
For the variation in VOH and VOL over the temperature range, see Figures 7 and 8.
TA = –40 °C to +125 °C.*
Parameter
Output Voltages:
Low*
High*:
BDG1A, BDP1A, BPNGA, BPNPA, BPPGA
BDGLA
Differential Voltage (VOH – VOL)
Output Voltages (TA = 0 °C to 85 °C):
Low*
High*:
BDG1A, BDP1A, BPNGA, BPNPA, BPPGA
BDGLA
Differential Voltage (VOH – VOL)
Third State, IOH = –1.0 mA, VCC = 4.5 V:
BDG1A, BDP1A, BPNGA, BPNPA, BPPGA
BDGLA
Input Voltages:
Low, VCC = 5.5 V:
Data Input
Enable Input
High, VCC = 4.5 V
Clamp, VCC = 4.5 V, II = –5.0 mA
Short-circuit Output Current, VCC = 5.5 V
Input Currents, VCC = 5.5 V:
Low, VI = 0.4 V
High, VI = 2.7 V
Reverse, VI = 5.5 V
Output Resistors:
BDP1A, BPNPA, BPPGA§
*
†
‡
§
4
Symbol
Min
Typ
Max
Unit
VOL
VOH – 1.4
VOH − 1.1
VOH − 0.65
V
VOH
VOH
VDIFF
VCC − 1.8
VCC − 2.5
0.65
VCC − 1
VCC − 2
1.1
VCC − 0.8
VCC − 1.6
1.4
V
V
V
VOL
VOH – 1.4
VOH − 1.1
VOH − 0.8
V
VOH
VOH
VDIFF
VCC − 1.5
VCC − 2.5
0.8
VCC − 1
VCC − 2
1.1
VCC − 0.8
VCC − 1.6
1.4
V
V
V
VOZ
VOZ
—
—
VOL − 0.5
0.2
VOL − 0.2
0.5
V
V
VIL†
VIL†
VIH
VIK
IOS‡
—
—
2.0
—
–100
—
—
—
—
—
0.8
0.7
—
−1.0
—
V
V
V
V
mA
IIL
IIH
IIH
—
—
—
—
—
—
−400
20
100
µA
µA
µA
RO
—
220
—
Ω
Values are with terminations as per Figure 4 or equivalent.
The input levels and difference voltage provide zero noise immunity and should be tested only in a static, noise-free environment.
Test must be performed one lead at a time to prevent damage to the device.
See Figure 1 for BPPGA terminations.
Agere Systems Inc.
Data Sheet
January 1999
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Timing Characteristics
Table 4. Timing Characteristics (See Figures 2 and 3.)
For tP1 and tP2 propagation delays over the temperature range, see Figure 9.
Propagation delay test circuit connected to output (see Figure 6).
TA = –40 °C to +125 °C, VCC = 5 V ± 0.5 V.
Parameter
Propagation Delay:
Input High to Output†
Input Low to Output†
Capacitive Delay
Disable Time (either E1 or E2):
High-to-high Impedance
Low-to-high Impedance
Enable Time (either E1 or E2):
High Impedance to High
High Impedance to Low
Output Skew, |tP1 – tP2|
|tPHH – tPHL|, |tPLH – tPLL|
Difference Between Drivers
Rise Time (20%—80%)
Fall Time (80%—20%)
Symbol
Min
Typ
Max
Unit
tP1*
tP2*
∆tp
0.8
0.8
—
1.2
1.2
0.02
2.0
2.0
0.03
ns
ns
ns/pF
tPHZ
tPLZ
4
4
8
8
12
12
ns
ns
tPZH
tPZL
4
4
—
—
—
—
—
8
8
0.1
0.2
—
0.7
0.7
12
12
0.3
0.5
0.3
2
2
ns
ns
ns
ns
ns
ns
ns
tskew1
tskew2
∆tskew
ttLH
ttHL
* tP1 and tP2 are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure 2).
† CL = 5 pF. Capacitor is connected from each output to ground.
Agere Systems Inc.
5
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Data Sheet
January 1999
Timing Characteristics (continued)
2.4 V
1.5 V
0.4 V
INPUT
TRANSITION
tP1
tP2
VOH
OUTPUTS
VOL
tPHH
tPLL
OUTPUT
VOH
(VOH + VOL)/2
VOL
OUTPUT
VOH
(VOH + VOL)/2
VOL
tPHL
OUTPUT
tPLH
80%
20%
VOH
80%
20%
ttLH
VOL
ttHL
12-2677F
Figure 2. Driver Propagation-Delay Timing
3.0 V
1.3 V
0.0 V
E1*
3.0 V
1.3 V
0.0 V
E2†
tPHZ
tPZH
VOH
VOL + 0.2 V
VOL
VOL – 0.1 V
OUTPUT
VOL
VOL – 0.1 V
OUTPUT
tPLZ
tPZL
12-2268.dC
* E2 = 1 while E1 changes state.
† E1 = 0 while E2 changes state.
Note: In the third state, both outputs (i.e., OUTPUT and OUTPUT) are 0.2 V below the low state.
Figure 3. Driver Enable and Disable Timing for a High Input
6
Agere Systems Inc.
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and
Data Sheet
January 1999
Test Conditions
Output Characteristics
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the
data transmission driver devices are measured with the
following output load circuits.
Figure 6 illustrates typical driver output characteristics.
Included are load lines for two typical termination configurations.
OUTPUT VOLTAGE (V)
VCC – 2 V
VCC – 1 V
VCC
100 Ω
DO(–)
200 Ω
VOH
10
200 Ω
20
Y LOAD
BDG1A, BPNGA, BDGLA, BPPGA (Gates A & B)
VOL
12-2271F
30
π LOAD
100 Ω
DO
OUTPUT CURRENT (mA)
DO(+)
40
DO
12-2269F
BDP1A, BPNPA, BPPGA (Gates C & D)
12-2271.bC
A. Output Current vs. Output Voltage for Loads
Shown in C and D (BDG1A, BDP1A, BPNGA,
BPNPA, and BPPGA)
Figure 4. Driver Test Circuit
OUTPUT VOLTAGE (V)
VCC – 3 V
VCC – 2 V
VCC – 1 V
VCC
10
110 Ω
20
Y LOAD
VOL
DUT
110 Ω
+60 V
SURGE
10 µs
DURATION
+
–
+
–
30
π LOAD
+60 V
SURGE
40
10 µs
DURATION
1 ms
REPETITION
12-2818aC
B. Output Current vs. Output Voltage for Loads
Shown in C and D (BDGLA)
1 ms
REPITITION
12-2640.aF
Note: Surges can be applied simultaneously, but never in opposite
polarities.
OUTPUT CURRENT (mA)
VOH
+5 V
60 Ω
60 Ω
DO
DO
90 Ω
Figure 5. Lightning-Surge Testing Configuration
(BPNGA, BPNPA, and BPPGA)
12-2270F
C. Y Load
100 Ω
DO(+)
DO(–)
200 Ω
200 Ω
12-2271F
D. π Load
Figure 6. Driver Output Current vs. Voltage
Characteristics
Agere Systems Inc.
7
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Data Sheet
January 1999
0
2.3
–0.5
PROPAGATION DELAY (ns)
OUTPUT VOLTAGE RELATIVE TO VCC
Temperature Characteristics
VOH MAX
–1.0
–1.5
VOH MIN
VOL MAX
–2.0
–2.5
–50
VOL MIN
–25
0
25
50
75
100
125 150
TEMPERATURE (°C)
2.1
1.9
1.7
1.5
1.3
RANGE FOR tP1 AND tP2
MAX
MIN
1.1
0.9
0.7
0.5
0.3
–50
–25
0
25
50
75
100
125 150
TEMPERATURE (°C)
12-3467F
Figure 7. VOL and VOH Extremes vs. Temperature
for 100 Ω Load
12-3469aF
Figure 9. Min and Max for tP1 and tP2 Propagation
Delays vs. Temperature
Handling Precautions
DIFFERENTIAL VOLTAGE (V)
1.2
CAUTION: This device is susceptible to damage
as a result of electrostatic discharge.
Take proper precautions during both
handling and testing. Follow guidelines such as JEDEC Publication No.
108-A (Dec. 1988).
VOH – VOL TYP
1.0
0.8
VOH – VOL MIN
0.6
0.4
0
–50
–25
0
25
50
75
100
125 150
TEMPERATURE (°C)
12-3468F
Figure 8. Differential Voltage (VOH – VOL) vs.
Temperature for 100 Ω Load
When handling and mounting line driver products,
proper precautions should be taken to avoid exposure
to electrostatic discharge (ESD). The user should
adhere to the following basic rules for ESD control:
1. Assume that all electronic components are sensitive to ESD damage.
2. Never touch a sensitive component unless properly
grounded.
3. Never transport, store, or handle sensitive components except in a static-safe environment.
8
Agere Systems Inc.
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and
Data Sheet
January 1999
ESD Failure Models
The HBM ESD threshold voltage presented here was
obtained by using these circuit parameters.
Agere employs two models for ESD events that can
cause device damage or failure.
1. A human-body model (HBM) that is used by most
of the industry for ESD-susceptibility testing and
protection-design evaluation. ESD voltage thresholds are dependent on the critical parameters used
to define the model. A standard HBM (resistance =
1500 Ω, capacitance = 100 pF) is widely used and,
therefore, can be used for comparison purposes.
2. A charged-device model (CDM), which many
believe is the better simulator of electronics manufacturing exposure.
Tables 5 and 6 illustrate the role these two models play
in the overall prevention of ESD damage. HBM ESD
testing is intended to simulate an ESD event from a
charged person. The CDM ESD testing simulates
charging and discharging events that occur in production equipment and processes, e.g., an integrated circuit sliding down a shipping tube.
Table 5. Typical ESD Thresholds for Data
Transmission Drivers
Device
HBM
Threshold
CDM
Threshold
BDG1A, BDGLA
>2500
>1000
BDP1A
>2500
>2000
BPPGA, BPNGA,
BPNPA
>3000
>2000
Table 6. ESD Damage Protection
ESD Threat Controls
Control
Model
Personnel
Processes
Wrist straps
ESD shoes
Antistatic flooring
Human-body model
(HBM)
Static-dissipative
materials
Air ionization
Charged-device
model (CDM)
Latch-Up
Latch-up evaluation has been performed on the data transmission drivers. Latch-up testing determines if powersupply current exceeds the specified maximum due to the application of a stress to the device under test. A device
is considered susceptible to latch-up if the power supply current exceeds the maximum level and remains at that
level after the stress is removed.
Agere performs latch-up testing per an internal test method that is consistent with JEDEC Standard No. 17 (previously JC-40.2) “CMOS Latch-Up Standardized Test Procedure.”
Latch-up evaluation involves three separate stresses to evaluate latch-up susceptibility levels:
1. dc current stressing of input and output pins.
2. Power supply slew rate.
3. Power supply overvoltage.
Table 7. Latch-Up Test Criteria and Test Results
Data Transmission
Driver ICs
Minimum Criteria
Test Results
dc Current Stress of
I/O Pins
≥150 mA
≥250 mA
Power Supply
Slew Rate
≤1 µs
≤100 ns
Power Supply
Overvoltage
≥1.75 × Vmax
≥2.25 × Vmax
Based on the results in Table 6, the data transmission drivers pass the Agere latch-up testing requirements and are
considered not susceptible to latch-up.
Agere Systems Inc.
9
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Data Sheet
January 1999
Outline Diagrams
16-Pin DIP
Dimensions are in millimeters.
L
N
B
1
W
PIN #1 IDENTIFIER ZONE
H
SEATING PLANE
0.38 MIN
2.54 TYP
0.58 MAX
5-4410r.2 (C)
Package
Description
PDIP3 (Plastic
Dual-In-Line
Package)
Package Dimensions
Number of
Pins
(N)
Maximum Length
(L)
Maximum Width
Without Leads
(B)
Maximum Width
Including Leads
(W)
Maximum Height
Above Board
(H)
16
20.57
6.48
7.87
5.08
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts,
please contact your Agere Sales Representative.
10
Agere Systems Inc.
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Data Sheet
January 1999
Outline Diagrams (continued)
16-Pin SOIC (SONB/SOG)
Dimensions are in millimeters.
L
N
B
1
PIN #1 IDENTIFIER ZONE
W
H
SEATING PLANE
0.10
0.51 MAX
1.27 TYP
0.61
0.28 MAX
5-4414r.3 (C)
Package
Description
SONB (SmallOutline, Narrow
Body)
SOG (SmallOutline, GullWing)
Package Dimensions
Number of
Pins
(N)
Maximum Length
(L)
Maximum Width
Without Leads
(B)
Maximum Width
Including Leads
(W)
Maximum Height
Above Board
(H)
16
10.11
4.01
6.17
1.73
16
10.49
7.62
10.64
2.67
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts,
please contact your Agere Sales Representative.
Agere Systems Inc.
11
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Data Sheet
January 1999
Outline Diagrams (continued)
16-Pin SOIC (SOJ)
Dimensions are in millimeters.
L
N
B
1
PIN #1 IDENTIFIER ZONE
W
H
SEATING PLANE
0.10
1.27 TYP
0.51 MAX
0.79 MAX
5-4413r.3 (C)
Package
Description
SOJ (SmallOutline, J-Lead)
Package Dimensions
Number of
Pins
(N)
Maximum Length
(L)
Maximum Width
Without Leads
(B)
Maximum Width
Including Leads
(W)
Maximum Height
Above Board
(H)
16
10.41
7.62
8.81
3.18
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts,
please contact your Agere Sales Representative.
12
Agere Systems Inc.
Data Sheet
January 1999
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and
Power Dissipation
System designers incorporating Agere data transmission drivers in their applications should be aware of
package and thermal information associated with these
components.
Proper thermal management is essential to the longterm reliability of any plastic encapsulated integrated
circuit. Thermal management is especially important
for surface-mount devices, given the increasing circuit
pack density and resulting higher thermal density. A
key aspect of thermal management involves the junction temperature (silicon temperature) of the integrated
circuit.
Several factors contribute to the resulting junction temperature of an integrated circuit:
■
Ambient use temperature
■
Device power dissipation
■
Component placement on the board
■
Thermal properties of the board
■
Thermal impedance of the package
Thermal impedance of the package is referred to as
Θja and is measured in °C rise in junction temperature
per watt of power dissipation. Thermal impedance is
also a function of airflow present in system application.
The following equation can be used to estimate the
junction temperature of any device:
The power dissipated in the output is a function of the:
■
Termination scheme on the outputs
■
Termination resistors
■
Duty cycle of the output
Package thermal impedance depends on:
■
Airflow
■
Package type (e.g., DIP, SOIC, SOIC/NB)
The junction temperature can be calculated using the
previous equation, after power dissipation levels and
package thermal impedances are known.
Figure 10 illustrates the thermal impedance estimates
for the various package types as a function of airflow.
This figure shows that package thermal impedance is
higher for the narrow-body SOIC package. Particular
attention should, therefore, be paid to the thermal management issues when using this package type.
In general, system designers should attempt to maintain junction temperature below 125 °C. The following
factors should be used to determine if specific data
transmission drivers in particular package types meet
the system reliability objectives:
■
System ambient temperature
■
Power dissipation
■
Package type
■
Airflow
Tj = TA + PD Θja
140
where:
TA is ambient temperature (°C).
PD is power dissipation (W).
Θja is package thermal impedance (junction to ambient—°C/W).
The power dissipation estimate is derived from two factors:
■
Internal device power
■
Power associated with output terminations
Multiplying ICC times VCC provides an estimate of internal power dissipation.
130
THERMAL RESISTANCE
Θja (°C/W)
Tj is device junction temperature (°C).
120
110
100
SOIC/NB
90
80
70
J-LEAD SOIC/GULL WING
60
50
40
DIP
0
200
400
600
800
1000
1200
AIRFLOW (ft./min.)
12-2753F
Figure 10. Power Dissipation
Agere Systems Inc.
13
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Data Sheet
January 1999
Ordering Information
Part Number
BDG1A16E
BDG1A16E-TR
BDG1A16G
BDG1A16G-TR
BDG1A16NB
BDG1A16NB-TR
BDG1A16P
BDP1A16E
BDP1A16E-TR
BDP1A16G
BDP1A16G-TR
BDP1A16P
BDGLA16E
BDGLA16E-TR
BDGLA16G
BDGLA16G-TR
BDGLA16NB
BDGLA16NB-TR
BDGLA16P
BPNGA16E
BPNGA16E-TR
BPNGA16G
BPNGA16G-TR
BPNGA16NB
BPNGA16NB-TR
BPNGA16P
BPNPA16E
BPNPA16E-TR
BPNPA16G
BPNPA16G-TR
BPNPA16P
BPPGA16E
BPPGA16E-TR
BPPGA16G
BPPGA16G-TR
BPPGA16P
14
Intern.
Term.
None
None
None
None
None
None
None
220 Ω
220 Ω
220 Ω
220 Ω
220 Ω
None
None
None
None
None
None
None
None
None
None
None
None
None
None
220 Ω
220 Ω
220 Ω
220 Ω
220 Ω
220 Ω
220 Ω
220 Ω
220 Ω
220 Ω
Surge
Prot.
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Package Type
16-pin, Plastic SOJ
Tape & Reel SOJ
16-pin, Plastic SOIC
Tape & Reel SOIC
Plastic SOIC/NB
Tape & Reel SOIC/NB
16-pin, Plastic DIP
16-pin, Plastic SOJ
Tape & Reel SOJ
16-pin, Plastic SOIC
Tape & Reel SOIC
16-pin, Plastic DIP
16-pin, Plastic SOJ
Tape & Reel SOJ
16-pin, Plastic SOIC
Tape & Reel SOIC
Plastic SOIC/NB
Tape & Reel SOIC/NB
16-pin, Plastic DIP
16-pin, Plastic SOJ
Tape & Reel SOJ
16-pin, Plastic SOIC
Tape & Reel SOIC
Plastic SOIC/NB
Tape & Reel SOIC/NB
16-pin, Plastic DIP
16-pin, Plastic SOJ
Tape & Reel SOJ
16-pin, Plastic SOIC
Tape & Reel SOIC
16-pin, Plastic DIP
16-pin, Plastic SOJ
Tape & Reel SOJ
16-pin, Plastic SOIC
Tape & Reel SOIC
16-pin, Plastic DIP
Comcode
107914186
107914194
107914160
107914178
107914202
107914210
107914004
107914293
107914301
107914319
107914327
107914335
107914228
107914236
107914244
107914251
107914269
107914277
107914285
107914343
107914350
107914368
107914376
107914384
107914392
107914400
107914418
107914426
107914434
107914442
107949745
107949752
107949760
107949778
107949786
107949794
Former
Pkg. Type
1041
1041
1141
1141
1241
1241
41
1041
1041
1141
1141
41
1041
1041
1141
1141
1241
1241
41
1041
1041
1141
1141
1241
1241
41
1041
1041
1141
1141
41
1041
1041
1141
1141
41
Former
Part #
LG, MG, MGA
LG, MG, MGA
LG, MG, MGA
LG, MG, MGA
LG, MG, MGA
LG, MG, MGA
LG, MG, MGA
LP, MP, MPA
LP, MP, MPA
LP, MP, MPA
LP, MP, MPA
LP, MP, MPA
MGL3
MGL3
MGL3
MGL3
MGL3
MGL3
MGL3
NG
NG
NG
NG
NG
NG
NG
NP
NP
NP
NP
NP
PG
PG
PG
PG
PG
Agere Systems Inc.
Data Sheet
January 1999
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Notes
Agere Systems Inc.
15
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
http://www.agere.com
E-MAIL:
[email protected]
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA:
Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)
JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)
EUROPE:
Tel. (44) 7000 624624, FAX (44) 1344 488 045
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright © 2002 Agere Systems Inc.
All Rights Reserved
January 1999
DS99-144HSI (Replaces DS99-044HSI)
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