AD AD5543BRM Current output/ serial input, 16-/14-bit dac Datasheet

a
FEATURES
16-Bit Resolution AD5543
14-Bit Resolution AD5553
1 LSB DNL
2 LSB INL for AD5543
1 LSB INL for AD5553
Low Noise 12 nV/√Hz
Low Power, IDD = 10 A
0.5 s Settling Time
4Q Multiplying Reference-Input
2 mA Full-Scale Current 20%, with VREF = 10 V
Built-in RFB Facilitates Voltage Conversion
3-Wire Interface
Ultracompact MSOP-8 and SOIC-8 Packages
Current Output/
Serial Input, 16-/14-Bit DAC
AD5543/AD5553
FUNCTIONAL BLOCK DIAGRAM
AD5543/AD5553
RFB
VDD
D/A
CONVERTER
VREF
IOUT
16 OR 14
DAC
REGISTER
CONTROL
LOGIC
CS
16 OR 14
CLK
APPLICATIONS
Automatic Test Equipment
Instrumentation
Digitally Controlled Calibration
Industrial Control PLCs
GND
16-/14-BIT SHIFT
REGISTER
SDI
1.0
0.8
0.6
GENERAL DESCRIPTION
0
–0.2
–0.4
–0.6
65536
61440
57344
53248
49152
45056
40960
36864
32768
28672
24575
20480
16384
8152
–1.0
12288
–0.8
0
A serial-data interface offers high speed, 3-wire microcontroller
compatible inputs using serial data in (SDI), clock (CLK), and
chip select (CS).
0.2
4096
The applied external reference VREF determines the full-scale
output current. An internal feedback resistor (RFB) facilitates the
R-2R and temperature tracking for voltage conversion when
combined with an external op amp.
0.4
INL – LSB
The AD5543/AD5553 are precision 16-/14-bit, low power,
current output, small form factor digital-to-analog converters.
They are designed to operate from a single 5 V supply with a
± 10 V multiplying reference.
CODE
Figure 1. Integral Nonlinearity Error
The AD5543/AD5553 are packaged in ultracompact
(3 mm 4.7 mm) MSOP-8 and SOIC-8 packages.
FFFFH
8000H
4000H
2000H
1000H
0800H
0400H
0200H
0100H
0080H
0040H
0020H
0010H
0008H
0004H
0002H
0001H
REF LEVEL
0.000dB
/DIV
12.000dB
MARKER 4 311 677.200Hz
MAG (A/R) –2.939dB
0000H
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
10
100
START 10.000Hz
1k
10k
100k
1M
10M
STOP 50 000 000.000Hz
Figure 2. Reference Multiplying Bandwidth
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD5543/AD5553–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VDD = 5 V 10%, VSS = 0 V, IOUT = Virtual GND, GND = 0 V, VREF = 10 V,
TA = Full operating temperature range, unless otherwise noted.)
Parameter
Symbol
Condition
5 V 10% Unit
STATIC PERFORMANCE1
Resolution
N
1 LSB = VREF/216 = 153 µV when VREF = 10 V AD5543
1 LSB = VREF/214 = 610 µV when VREF = 10 V AD5553
Grade: AD5553C
Grade: AD5543B
Monotonic
Data = 0000H, TA = 25°C
Data = 0000H, TA = TA max
Data = FFFFH
16
14
±1
±2
±1
10
20
± 1/± 4
1
Bits
Bits
LSB max
LSB max
LSB max
nA max
nA max
mV typ/max
ppm/°C typ
–15/+15
5
5
V min/max
kΩ typ3
pF typ
2
mA typ
200
pF typ
Relative Accuracy
INL
Differential Nonlinearity
Output Leakage Current
DNL
IOUT
Full-Scale Gain Error
Full-Scale Tempco2
GFSE
TCVFS
REFERENCE INPUT
VREF Range
Input Resistance
Input Capacitance2
VREF
RREF
CREF
ANALOG OUTPUT
Output Current
IOUT
Output Capacitance2
COUT
Data = FFFFH for AD5543
Data = 3FFFH for AD5553
Code Dependent
LOGIC INPUTS AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
VIL
VIH
IIL
CIL
0.8
2.4
10
10
V max
V min
µA max
pF max
INTERFACE TIMING 2, 4
Clock Input Frequency
Clock Width High
Clock Width Low
CS to Clock Setup
Clock to CS Hold
Data Setup
Data Hold
fCLK
tCH
tCL
tCSS
tCSH
tDS
tDH
50
10
10
0
10
5
10
MHz
ns min
ns min
ns min
ns min
ns min
ns min
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
VDD RANGE
IDD
Logic Inputs = 0 V
Logic Inputs = 0 V
PDISS
PSS
∆VDD = ± 5%
4.5/5.5
10
0.055
0.006
V min/max
µA max
mW max
%/% max
AC CHARACTERISTICS4
Output Voltage Settling Time
tS
0.5
µs typ
4
7
MHz typ
nV-s typ
–65
7
–85
12
dB
nV-s typ
dB typ
nV/√Hz
Reference Multiplying BW
DAC Glitch Impulse
BW
Q
Feedthrough Error
Digital Feedthrough
Total Harmonic Distortion
Output Spot Noise Voltage
VOUT/VREF
Q
THD
eN
To ± 0.1% of Full Scale,
Data = 0000H to FFFFH to 0000H for AD5543
Data = 0000H to 3FFFH to 0000H for AD5553
VREF = 5 V p-p, Data = FFFFH
VREF = 0 V, Data = 7FFFH to 8000H for AD5543
Data = 1FFFH to 2000H for AD5553
Data = 0000H, VREF = 100 mV rms, same channel
CS = 1, and fCLK = 1 MHz
VREF = 5 V p-p, Data = FFFFH, f = 1 kHz
f = 1 kHz, BW = 1 Hz
NOTES
1
All static performance tests (except I OUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 R FB terminal
is tied to the amplifier output. The op amp +IN is grounded and the DAC I OUT is tied to the op amp –IN. Typical values represent average readings measured at 25 °C.
2
These parameters are guaranteed by design and are not subject to production testing.
3
All ac characteristic tests are performed in a closed-loop system using an AD841 I-to-V converter amplifier.
4
All input control signals are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
–2–
REV. A
AD5543/AD5553
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V, +18 V
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
V(IOUT) to GND . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Input Current to Any Pin except Supplies . . . . . . . . . . ± 50 mA
Package Power Dissipation . . . . . . . . . . . . . (TJ Max – TA )/JA
Thermal Resistance JA
8-Lead Surface Mount (MSOP-8) . . . . . . . . . . . . . 150°C/W
8-Lead Surface Mount (SOIC-8) . . . . . . . . . . . . . . 100°C/W
Maximum Junction Temperature (TJ Max) . . . . . . . . . . 150°C
Operating Temperature Range
Models B, C . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature
RN-8, RM-8 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . 215°C
RN-8, RM-8 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . 220°C
Pin
No. Mnemonic Function
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
1
CLK
2
SDI
3
RFB
4
VREF
5
IOUT
6
7
GND
VDD
8
CS
PIN CONFIGURATION
MSOP and SOIC-8
CLK 1
AD5543/
AD5553
8
Clock Input. Positive-edge triggered, clocks
data into shift register.
Serial Register Input. Data loads directly
into the shift register MSB first. Extra leading
bits are ignored.
Internal Matching Feedback Resistor. Connects to external op amp for voltage output.
DAC Reference Input Pin. Establishes DAC
full-scale voltage. Constant input resistance
versus code.
DAC Current Output. Connects to inverting
terminal of external precision I-to-V op amp
for voltage output.
Analog and Digital Ground
Positive Power Supply Input. Specified range
of operation 5 V ± 10%.
Chip Select. Active low digital input. Transfers
shift-register data to DAC register on rising
edge. See Truth Table for operation.
CS
VDD
TOP VIEW
RFB 3 (Not to Scale) 6 GND
SDI 2
VREF 4
7
5
IOUT
ORDERING GUIDE*
Model
INL
(LSB)
RES
(LSB)
Temperature
Range
Package
Description
AD5543BR
AD5543BRM
AD5553CRM
±2
±2
±1
16
16
14
–40°C to +85°C SOIC-8
–40°C to +85°C MSOP-8
–40°C to +85°C MSOP-8
Package
Option
Marking
RN-8
RM-8
RM-8
AD5543
DXB
DUC
*The AD5543 contains 1040 transistors. The die size measures 55 mil 73 mil, 4,015 sq. mil.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5543/AD5553 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
DNL – LSB
INL – LSB
AD5543/AD5553–Typical Performance Characteristics
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
–1.0
0
8192
16384
0
24576 32768 40960 49152 57344 65536
CODE – Decimal
TPC 1. AD5543 Integral Nonlinearity Error
4096
6144
8192 10240
CODE – Decimal
1.5
VREF = 2.5V
TA = 25C
0.8
1.0
LINEARITY ERROR – LSB
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0.5
INL
0
DNL
–0.5
–1.0
GE
–0.8
–1.5
–1.0
0
8192
16384
24576 32768 40960 49152 57344 65536
CODE – Decimal
2
TPC 2. AD5543 Differential Nonlinearity Error
4
6
SUPPLY VOLTAGE VDD – V
10
8
TPC 5. Linearity Errors vs. VDD
1.0
5
VDD = 5V
TA = 25C
0.8
SUPPLY CURRENT IDD – mA
0.6
0.4
INL – LSB
12288 14336 16384
TPC 4. AD5553 Differential Nonlinearity Error
1.0
DNL – LSB
2048
0.2
0
–0.2
–0.4
–0.6
4
3
2
1
–0.8
–1.0
0
2048
4096
6144
8192 10240
CODE – Decimal
12288 14336
0
16384
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
LOGIC INPUT VOLTAGE VIH – V
TPC 3. AD5553 Integral Nonlinearity Error
TPC 6. Supply Current vs. Logic Input Voltage
–4–
REV. A
AD5543/AD5553
3.0
SUPPLY CURRENT – mA
2.5
2.0
5555H
1.5
8000H
1.0
FFFFH
0000H
0.5
0
10k
100k
1M
10M
CLOCK FREQUENCY – Hz
100M
TPC 7. AD5543 Supply Current vs. Clock Frequency
TPC 10. Settling Time
90
VDD = 5V 10%
VREF = 10V
80
70
CS (5V/DIV)
PSRR – dB
60
VDD = 5V
VREF = 10V
CODES 8000H ↔ 7FFFH
50
40
30
VOUT (50mV/DIV)
20
10
0
10
100
10k
1k
FREQUENCY – Hz
100k
0
1M
/DIV
12.000dB
MARKER 4 311 677.200Hz
MAG (A/R) –2.939dB
FFFFH
8000H
4000H
2000H
1000H
0800H
0400H
0200H
0100H
0080H
0040H
0020H
0010H
0008H
0004H
0002H
0001H
0000H
10
100
START 10.000Hz
1k
10k
100k
1M
10M
STOP 50 000 000.000Hz
TPC 9. Reference Multiplying Bandwidth
REV. A
1.0
1.5
2.0
2.5
3.0
TIME – s
3.5
4.0
4.5
5.0
TPC 11. Midscale Transition and Digital Feedthrough
TPC 8. Power Supply Rejection vs. Frequency
REF LEVEL
0.000dB
0.5
–5–
AD5543/AD5553
SDI
D15
D14
D13
D12
D11
D10
D9
D1
D8
D0
CLK
t
tDS
tCH
DH
tCL
tCSH
tCSS
CS
Figure 3a. AD5543 Timing Diagram
SDI
D13
D12
D11
D10
D9
D8
D7
D1
D6
D0
CLK
t
tDS
tCH
DH
tCL
tCSH
tCSS
CS
Figure 3b. AD5553 Timing Diagram
Table I. Control-Logic Truth Table
CLK
CS
Serial Shift Register Function
DAC Register
X
↑+
X
X
H
L
H
↑+
No Effect
Shift Register Data Advanced One Bit
No Effect
Shift Register Data Transferred to DAC Register
Latched
Latched
Latched
New Data Loaded from Serial Register
↑+ positive logic transition; X Don't Care
Table II. AD5543 Serial Input Register Data Format; Data is Loaded in the MSB-First Format
MSB
LSB
Bit Position
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Data-Word
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table III. AD5553 Serial Input Register Data Format; Data is Loaded in the MSB-First Format
MSB
LSB
Bit Position
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Data-Word*
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
*A full 16-bit data-word can be loaded into the AD5553 serial input register, but only the last 14 bits entered will be transferred to the DAC register when CS returns
to logic high.
–6–
REV. A
AD5543/AD5553
various resistances and capacitances. External amplifier choice
should take into account the variation in impedance generated
by the AD5543 on the amplifier’s inverting input node. The
feedback resistance, in parallel with the DAC ladder resistance,
dominates output voltage noise. To maintain good analog performance, power supply bypassing of 0.01 µF to 0.1 µF ceramic or
chip capacitors in parallel with a 1 µF tantalum capacitor is recommended. Due to degradation of power supply rejection ratio in
frequency, users must avoid using switching power supplies.
CIRCUIT OPERATION
The AD5543/AD5553 contains a 16-/14-bit, current output,
digital-to-analog converter, a serial input register, and a DAC
register. Both converters use a 3-wire serial data interface.
D/A Converter Section
The DAC architecture uses a current steering R-2R ladder
design. Figure 4 shows the typical equivalent DAC structure.
The DAC contains a matching feedback resistor for use with an
external op amp, (see Figure 5). With RFB and IOUT terminals
connected to the op amp output and inverting node respectively, a precision voltage output can be achieved as:
VOUT = – VREF × D / 65, 536 ( AD 5543)
(1)
VOUT = – VREF × D / 16, 384 ( AD 5553)
(2)
SERIAL DATA INTERFACE
The AD5543/AD5553 uses a 3-wire (CS, SDI, CLK) serial
data interface. New serial data is clocked into the serial input
register in a 16-bit data-word format for AD5543. The MSB is
loaded first. Table II defines the 16 data-word bits. Data is
placed on the SDI pin and clocked into the register on the positive
clock edge of CLK, subject to the data setup and hold time
requirements specified in the interface timing specifications.
Only the last 16 bits clocked into the serial register are interrogated when the CS pin is strobed to transfer the serial register
data to the DAC register. Since most microcontrollers output
serial data in 8-bit bytes, two data bytes can be written to the
AD5543/AD5553. After loading the serial register, the rising edge
of CS transfers the serial register data to the DAC register;
during this strobe, the CLK should not be toggled. For the
AD5553, with 16-bit clock cycles, the two LSBs are ignored.
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages.
These DACs are designed to operate with either negative or
positive reference voltages. The VDD power pin is only used by
the internal logic to drive the DAC switches’ ON and OFF states.
VDD
R
R
R
RFB
VREF
2R
2R
2R
R
5k
S2
S1
IOUT
ESD Protection Circuits
GND
All logic-input pins contain back-biased ESD protection Zener
diodes connected to ground (GND) and VDD as shown in Figure 6.
VDD
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY;
SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED
DIGITAL
INPUTS
Figure 4. Equivalent R-2R DAC Circuit
5k
Note that a matching switch is used in series with the internal 5 kΩ
feedback resistor. If users attempt to measure RFB, power must be
applied to VDD to achieve continuity.
DGND
VDD
Figure 6. Equivalent ESD Protection Circuits
U1
VDD
VREF
VREF
PCB Layout and Power Supply Bypassing
RFB
It is a good practice to employ compact, minimum lead length
PCB layout design. The leads to the input should be as short as
possible to minimize IR drop and stray inductance.
U2
IOUT
GND
V+
AD8628
V–
VO
It is also essential to bypass the power supplies with quality
capacitors for optimum stability. Supply leads to the device should
be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic capacitors. Low-ESR 1 µF to 10 µF tantalum or electrolytic capacitors
should also be applied at the supplies to minimize transient
disturbance and filter out low frequency ripple
AD5543/AD5553
–5V
Figure 5. Voltage Output Configuration
These DACs are also designed to accommodate ac reference
input signals. The AD5543 accommodates input reference
voltages in the range of –12 V to +12 V. The reference voltage
inputs exhibit a constant nominal input resistance value of 5 kΩ,
± 30%. The DAC output (IOUT) is code-dependent, producing
REV. A
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error.
–7–
AD5543/AD5553
APPLICATIONS
Stability
Bipolar Output
The AD5543/AD5553 is inherently a 2-quadrant multiplying
D/A converter. That is, it can easily be set up for unipolar output
operation. The full-scale output polarity is the inverse of the
reference input voltage.
VDD
U1
C1
RFB
VDD
IOUT
VREF
VREF
In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing. This
is easily accomplished by using an additional external amplifier
U4 configured as a summing amplifier (see Figure 9). In this
circuit, the second amplifier U4 provides a gain of 2 that increases
the output span magnitude to 5 V. Biasing the external amplifier
with a 2.5 V offset from the reference voltage results in a full
4-quadrant multiplying circuit. The transfer equation of this circuit
shows that both negative and positive output voltages are created
as the input data (D) is incremented from code zero (VOUT =
–2.5 V) to midscale (VOUT = 0 V) to full-scale (VOUT = +2.5 V).
VO
AD8628
GND
U2
AD5543/AD5553
Figure 7. Optional Compensation Capacitor for Gain
Peaking Prevention
In the I-to-V configuration, the IOUT of the DAC and the inverting
node of the op amp must be connected as close as possible, and
proper PCB layout technique must be employed. Since every code
change corresponds to a step function, gain peaking may occur
if the op amp has limited GBP and there is excessive parasitic
capacitance at the inverting node.
VOUT = (D / 32, 768 – 1) × VREF ( AD 5543)
(3)
VOUT = (D / 16, 384 – 1) × VREF ( AD 5553)
(4)
For AD5543, the resistance tolerance becomes the dominant
error of which users should be aware.
An optional compensation capacitor C1 can be added for stability
as shown in Figure 7. C1 should be found empirically but 20 pF
is generally adequate for the compensation.
R1
R2
10k0.01% 10k0.01%
Positive Voltage Output
C2
To achieve the positive voltage output, an applied negative
reference to the input of the DAC is preferred over the output
inversion through an inverting amplifier because of the resistor’s
tolerance errors. To generate a negative reference, the reference
can be level-shifted by an op amp such that the VOUT and GND
pins of the reference become the virtual ground and –2.5 V
respectively, (see Figure 8).
U4
+5V
ADR03
+5V
U1
VDD
VOUT VIN
VREF
GND
GND
+5V
5k0.01%
R3
RFB
C1
IOUT
V+
1/2AD8620
V–
VO
–5V
1/2AD8620
U3
–2.5 < VO < +2.5
+5V
AD5553 ONLY
ADR03
U4
Figure 9. Four-Quadrant Multiplying Application Circuit
VOUT VIN
+5V
GND
V+
1/2AD8620
V–
U3
U2
U1
VDD
VREF
C1
RFB
IOUT
VO
–2.5V
1/2AD8628
GND
–5V
AD5543/AD5553
U2
0 < VO < +2.5
Figure 8. Positive Voltage Output Configuration
–8–
REV. A
AD5543/AD5553
If the resistors are perfectly matched, ZO is infinite, which is
desirable, and behaves as an ideal current source. On the other
hand, if they are not matched, ZO can be either positive or negative. Negative can cause oscillation. As a result, C1 is needed to
prevent the oscillation. For critical applications, C1 could be
found empirically, but typically falls in the range of few pF.
Programmable Current Source
Figure 10 shows a versatile V-I conversion circuit using an
improved Howland Current Pump. In addition to the precision
current conversion it provides, this circuit enables a bidirectional current flow and high voltage compliance. This circuit
can be used in 4 to 20 mA current transmitters with up to 500 Ω
of load. In Figure 10, it can be shown that if the resistor network is
matched, the load current is:
IL =
(R2 + R3) / R1 × V
VDD
U1
REF
×D
(5)
VDD
R3
R3 in theory can be made small to achieve the current needed
within the U3 output current driving capability. This circuit is
versatile such that AD8510 can deliver ± 20 mA in both directions and the voltage compliance approaches 15 V, which is
limited mainly by the supply voltages of U3. However, users
must pay attention to the compensation. Without C1, it can be
shown that the output impedance becomes:
R1' R3( R1 + R2)
ZO =
(6)
R1 R2' + R3' – R1' R2 + R3
(
)
(
VREF
VREF
RFB
IOUT
GND
R1'
R2'
150k 15k
AD8628
C1
10pF
AD5543/AD5553
U2
VDD
U3
V+
AD8510
V–
)
R3'
50
R3
50
VSS
VL
R1
150k
R2
15k
LOAD
IL
Figure 10. Programmable Current Source with Bidirectional Current Control and High Voltage Compliance
Capabilities
REV. A
–9–
AD5543/AD5553
OUTLINE DIMENSIONS
8-Lead microSOIC Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4.90
BSC
3.00
BSC
1
4
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.80
0.40
8
0
0.23
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(RN-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
SEATING
0.10
PLANE
6.20 (0.2440)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.33 (0.0130)
0.50 (0.0196)
45
0.25 (0.0099)
8
0.25 (0.0098) 0 1.27 (0.0500)
0.41 (0.0160)
0.19 (0.0075)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–10–
REV. A
AD5543/AD5553
Revision History
Location
Page
2/03—Data Sheet changed from REV. 0 to REV. A.
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
REV. A
–11–
–12–
PRINTED IN U.S.A.
C02917–0–2/03(A)
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