PRELIMINARY CM3202 DDR VDDQ and Termination Voltage Regulator Features Product Description • The CM3202 is a dual-output low noise linear regulator designed to meet SSTL-2 and SSTL-3 specifications for DDR-SDRAM VDDQ supply and termination voltage VTT supply. With integrated power MOSFET’s, the CM3202 can source up to 2A of VDDQ current, and source or sink up to 2A VTT current. The typical dropout voltage for VDDQ is 500 mV at 2A load current. • • • • • • • • • • • • • • Two linear regulators -Maximum 2A current from VDDQ -Source and sink up to 2A VTT current 1.7V to 2.8V adjustable VDDQ output voltage 500mV typical VDDQ dropout voltage at 2A VTT tracking at 50% of VDDQ Excellent load and line regulation, low noise Fast transient response Meet JEDEC DDR-I and DDR-II memory power spec. Linear regulator design requires no inductors and has low external component count Integrated power MOSFETs Dual purpose ADJ/Shutdown pin Built-in over-current limit with short-circuit foldback and thermal shutdown for VDDQ and VTT Fast transient response 5mA quiescent current TDFN-8 and SOIC-8 packages for high performance thermal dissipation and easy PC board layout Optional RoHS Compliant Lead-free packaging The CM3202 provides fast response to transient load changes. Load regulation is excellent, less than 1%, from no load to full load. It also has built-in over-current limits and thermal shutdown at 170°C. The CM3202 is packaged in an easy-to-use TDFN-8 and SOIC-8. Low thermal resistance (55°C/W) allows it to withstand 1.55W (1) dissipation at 85°C ambient. It can operate over the industrial ambient temperature range of –40°C to 85°C. Applications Note(1) : • • • • • • • • If TDFN-8 is mounted on a double-sided printed circuit board with two square inches of copper area, it can to withstand 2W dissipation at 85°C ambient then. DDR memory and active termination buses Desktop Computers, Servers Residential and Enterprise Gateways DSL Modems Routers and Switchers DVD recorders 3D AGP cards LCD TV and STB Typical Application 3.3V 220u VDDQ 4.7u 220u 1 2 3 220u 4 4.7u VIN VDDQ VIN VDDQ CM3202 VTT ADJSD GND GND 4.7u 8 C hip S et VDDQ DL0 RT0 7 887 DLn 6 5 S/D RTn 845 DDR REF Memory 1.25V , 2.5A VTT 1k 1u VREF © 2006 California Micro Devices Corp. All rights reserved. 05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 1 PRELIMINARY CM3202 Package Pinout PACKAGE / PINOUT DIAGRAM TOP VIEW TOP VIEW 8 7 6 5 VIN 1 8 VDDQ VIN 2 7 VDDQ VIN VTT 3 6 ADJSD GND 4 5 GND Pin 1 Marking 1 NC 2 VTT 3 NC 4 8 GND PAD VDDQ 7 ADJSD 6 GND 5 GND 1 2 3 4 8-Lead SOIC Package CM3202-00DE 8-Lead TDFN Package CM3202-00SM Note: This drawing is not to scale. Ordering Information PART NUMBERING INFORMATION Lead-free Finish Pins Package Ordering Part Number1 Part Marking 8 TDFN CM3202-00DE CM3202 8 SOIC CM3202-00SM CM3202 Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS VIN to GND [GND - 0.3] to +6.0 V Pin Voltages VDDQ ,VTT to GND ADJSD to GND [GND - 0.3] to +6.0 [GND - 0.3] to +6.0 V V Storage Temperature Range -65 to +150 °C Operating Temperature Range -40 to +85 °C 300 °C Lead Temperature (Soldering, 10s) © 2006 California Micro Devices Corp. All rights reserved. 2 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 05/08/06 PRELIMINARY CM3202 Specifications (cont’d) ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) VIN = 3.3V, typical values are at TA = 25°C (unless otherwise specified) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT S 3 3.3 3.6 V VIN VIN Supply Voltage Range VUVLO Under-voltage Lockout UVLO Hysterisis Quiescent Current IQ All outputs are no load VDDQ = 0V, VTT = 0V, ADJSD = 3.3V (shutdown) VDDQ = 2.5V, VTT = 1.25V, (no load) 2.5 200 200 V mV mA 5 mA 2.8 A VDDQ Regulator VOUT = 2.5V Output Current Limit VREF Reference Voltage 1.250 1.265 V IBIAS Input Bias Current (IADJ) VADJSD = VREF 30 200 nA VR LOAD Load Regulation IO = 10mA to 2A 1 VR LINE Line Regulation VIN = 3.15V to 3.5V, IO = 10mA 1 % VDROPOUT Dropout Voltage VIN = 3.15V, IO = 2A 500 mV Output Current Limit (Source) VOUT = 1.25V 2.8 A Output Current Limit (Sink) VOUT = 1.25V 2.8 A Load Regulation IO = 0A to 2A 1 % IO = 0A to -2A 1 % 170 50 °C °C 1.235 % VTT Regulator VR VTTLOAD Over Temperature Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis © 2006 California Micro Devices Corp. All rights reserved. 05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 3 PRELIMINARY CM3202 Typical Operating Characteristics VDDQ vs. Temperature VTT vs. VDDQ 2.51 1.65 1.55 2.505 1.35 VDDQ (V) VTT (V) 1.45 1.25 1.15 1.05 2. 5 2.495 0.95 0.85 2.49 0.75 1.5 1.75 2 2.25 2.5 2.75 3 -40 -20 3.25 0 40 60 80 Temperatur e VDDQ (V) VDDQ vs. Load Current 10 0 12 0 14 0 o C VDDQ Dropout vs. IDDQ Dropout Voltage (mV) VDDQ (V) 20 Ta=25 oC Vin=3.3V Ta=25 oC IDDQ (A) IDDQ (A) Startup into Full Load Vin UVLO VDDQ VTT 1ms/div 1V/div © 2006 California Micro Devices Corp. All rights reserved. 4 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 05/08/06 PRELIMINARY CM3202 Typical Operating Characteristics (cont’d) VDDQ Transient Response VTT Transient Response IOUT IOUT VDDQ VTT VIN = 3.3V IOUT Step: 15mA ~ 1.5A VIN = 3.3V IOUT Step: -750mA ~ +750mA With TDFN-8 Package VDDQ Transient Response VTT Transient Response IOUT IOUT VDDQ VTT VIN = 3.3V IOUT Step: 15mA ~ 700mA VIN = 3.3V IOUT Step: -350mA ~ +350mA With SOIC-8 Package © 2006 California Micro Devices Corp. All rights reserved. 05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 5 PRELIMINARY CM3202 Pin Description Pin Descriptions PIN DESCRIPTIONS PIN(S) TDFN 8 PIN(S) SOIC 8 NAME 1 1, 2 VIN 2, 4 DESCRIPTION Input voltage pin, typically 3.3V from the silver box. NC 3 3 VTT VTT regulator output voltage pin, which is preset to 50% of VDDQ. 5, 6 4, 5 GND Ground pin. The back tab is also ground and serves as the package heatsink. It should be soldered to the circuit board copper to remove excess heat from the IC. This pin is for VDDQ output voltage Adjustment. The VDDQ output voltage is set using an external resistor divider connected to ADJSD. The output voltage is determined by the following formula R1 + R2 V DDQ = 1.25V × --------------------R1 7 6 ADJSD where R1 is the ground-side resistor and R2 is the upper resistor of the divider. Connect these resistors to the VDDQ output at the point of regulation. In addition, functions as a Shutdown pin. Apply a voltage higher than VIN0.6V to this pin to simultaneously shutdown both VDDQ and VTT outputs. The outputs are restored when the voltage is lowered below VIN-0.6V. A low-leakage diode in series with the Shutdown signal is recommended to avoid interference with the voltage adjustment setting. 8 7, 8 VDDQ VDDQ regulator output voltage pin. © 2006 California Micro Devices Corp. All rights reserved. 6 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 05/08/06 PRELIMINARY CM3202 Application Information (cont’d) 9,1 89/2 %DQGJDS 9''4 $'-6' 1.22V &XUUHQW /LPLW 273 6KXWGRZQ &XUUHQW /LPLW 9''4 977 9''4 &XUUHQW /LPLW CM3202 *1' Application Information Powering DDR Memory Double-Data-Rate (DDR) memory has provided a huge step in performance for personal computers, servers and graphic systems. As is apparent in its name, DDR operates at double the data rate of earlier RAM, with two memory accesses per cycle versus one. DDR SDRAM's transmit data at both the rising falling edges of the memory bus clock. DDR’s use of Stub Series Terminated Logic (SSTL) topology improves noise immunity and power-supply rejection, while reducing power dissipation. To achieve this performance improvement, DDR requires more complex power management architecture than previous RAM technology. industry standard, defined in JEDEC document JESD8-9. SSTL_2 maintains high-speed data bus signal integrity by reducing transmission reflections. JEDEC further defines the DDR SDRAM specification in JESD79C. DDR memory requires three tightly regulated voltages: VDDQ, VTT, and VREF (see Figure 1). In a typical SSTL_2 receiver, the higher current VDDQ supply voltage is normally 2.5V with a tolerance of ±200-mV. The active bus termination voltage, VTT, is half of VDDQ. VREF is a reference voltage that tracks half of VDDQ, ± 1%, and is compared with the VTT terminated signal at the receiver. VTT must be within ±40-mV of VREF. Unlike the conventional DRAM technology, DDR SDRAM uses differential inputs and a reference voltage for all interface signals. This increases the data bus bandwidth, and lowers the system power consumption. Power consumption is reduced by lower operating voltage, a lower signal voltage swing associated with Stub Series Terminated Logic (SSTL_2) and by the use of a termination voltage, VTT. SSTL_2 is an © 2006 California Micro Devices Corp. All rights reserved. 05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 7 PRELIMINARY CM3202 Application Info (cont’d) VTT (=VDDQ/2) VDDQ VDDQ Rt = 25 Rs = 25 Line Transmitter Receiver VREF (=VDDQ/2) Figure 1. Typical DDR terminations, Class II The VTT power requirement is proportional to the number of data lines and the resistance of the termination resistor, but does not vary with memory size. In a typical DDR data bus system each data line termination may momentarily consume 16.2-mA to achieve the 405-mV minimum over VTT needed at the receiver: 405mV- = 16.2mA I terminaton = --------------------Rt ( 25Ω ) and the two-quadrant VTT termination regulator has current sink and source capability to ±2A. The VDDQ linear regulator uses a PMOS pass element for a very low dropout voltage, typically 500mV at a 2A output. The output voltage of VDDQ can be set by an external voltage divider. The second output, VTT, is regulated at VDDQ/2 by an internal resistor divider. The VTT regulator can source, as well as sink, up to 2A current. The CM3202 is designed for optimal operation from a nominal 3.3VDC bus, but can work with VIN as high as 5V. When operating at higher VIN voltages, attention must be given to the increased package power dissipation and proportionally increased heat generation. VREF is typically routed to inputs with high impedance, such as a comparator, with little current draw. An adequate VREF can be created with a simple voltage divider of precision, matched resistors from VDDQ to ground. A small ceramic bypass capacitor can also be added for improved noise performance. Input and Output Capacitors A typical 64 Mbyte SSTL-2 memory system, with 128 terminated lines, has a worst-case maximum VTT supply current up to ± 2.07A. However, a DDR memory system is dynamic, and the theoretical peak currents only occur for short durations, if they ever occur at all. These high current peaks can be handled by the VTT external capacitor. In a real memory system, the continuous average VTT current level in normal operation is less than ± 200 mA. The VDDQ power supply, in addition to supplying current to the memory banks, could also supply current to controllers and other circuitry. The current level typically stays within a range of 0.5A to 1A, with peaks up to 2A or more, depending on memory size and the computing operations being performed. The tight tracking requirements and the need for VTT to sink, as well as source, current provide unique challenges for powering DDR SDRAM. CM3202 Regulator The CM3202 dual output linear regulator provides all of the power requirements of DDR memory by combining two linear regulators into a single TDFN-8 or SOIC-8 package. VDDQ regulator can supply up to 2A current, The CM3202 requires that at least a 220μF electrolytic capacitor be located near the VIN pin for stability and to maintain the input bus voltage during load transients. An additional 4.7μF ceramic capacitor between the VIN and the GND, located as close as possible to those pins, is recommended to ensure stability. A minimum of a 220μF electrolytic capacitor is recommended for the VDDQ output. An additional 4.7μF ceramic capacitor between the VDDQ and GND, located very close to those pins, is recommended. A minimum of a 220μF, electrolytic capacitor is recommended for the VTT output. This capacitor should have low ESR to achieve best output transient response. SP or OSCON capacitors provide low ESR at high frequency, and thus are a good choice. In addition, place a 4.7μF ceramic capacitor between the VTT pin and GND, located very close to those pins. The total ESR must be low enough to keep the transient within the VTT window of 40mV during the transition for source to sink. An average current step of ± 0.5A requires: 40mV ESR < --------------- = 40mΩ 1A Both outputs will remain stable and in regulation even during light or no load conditions. © 2006 California Micro Devices Corp. All rights reserved. 8 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 05/08/06 PRELIMINARY CM3202 Application Info (cont’d) Thermal Considerations Adjusting VDDQ Output Voltage The CM3202 internal bandgap reference is set at 1.25V. The VDDQ voltage is adjustable by using a resistor divider, R1 and R2: R1 + R2 V DDQ = V ADJ × --------------------R1 where VADJ = 1.25V (±-1%). For best regulator stability, we recommend that R1 and R2 not exceed 10kΩ each. Shutdown ADJSD also serves as a shutdown pin. When this is pulled high, > (VIN - 0.6V), the VDDQ output is turned off and both source and sink MOSFET’s of the VTT regulator are set to a high impedance state. During shutdown, the quiescent current is reduced to less than 3mA, independent of output load. It is recommended that a 1N914 or equivalent low leakage diode be placed between ADJSD Pin and an external shutdown signal to prevent interference with the ADJ pin’s normal operation. When the diode anode is pulled low, or left open, the CM3202 is again enabled. Typical Thermal Characteristics The overall junction to ambient thermal resistance (θJA) for device power dissipation (PD) primarily consists of two paths in the series. The first path is the junction to the case (θJC) which is defined by the package style and the second path is case to ambient (θCA) thermal resistance which is dependent on board layout. The final operating junction temperature for any condition can be estimated by the following thermal equation: T JUNC = T AMB + P D × ( θ JC ) + P D × ( θ CA ) = T AMB + P D × ( θ CA ) When a CM3202 is mounted on a double-sided printed circuit board with two square inches of copper allocated for “heat spreading,” the θJA is approximately 42.5-°C/Watt for the CM3202-00DE (TDFN-8) and 85-°C/Watt for CM3202-00SM (SOIC-8). Based on the over temperature limit of 170°C with an ambient of 85°C, the available power of the package will be: PD(TDFN8) = 170 °C 85°C = 2W 42.5 °C / W PD(SOIC8) = 170 °C 85°C = 1W 85°C / W Current Limit, Foldback and Over-temperature Protection The CM3202 features internal current limiting with thermal protection. During normal operation, VDDQ limits the output current to approximately 2A and VTT limits the output current to approximately ±2A. When VTT is current limiting into a hard short circuit, the output current folds back to a lower level, about 1A, until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the junction temperature of the device exceeds 170-°C (typical), the thermal protection circuitry triggers and shuts down both outputs. Once the junction temperature has cooled to below about 120-°C, the CM3202 returns to normal operation. PCB Layout Considerations TheCM3202 has a heat spreader attached to the bottom of the TDFN-8 package in order for the heat to be transferred more easily from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself. By positioning the matching pad on the PCB top layer to connect to the spreader during the manufacturing, the heat will be transferred between the two pads. See the Figure 2, the CM3202-00DE (TDFN-8) and CM3202-00SM (SOIC-8) show the recommended PCB layout. Please be noted that there are six vias in the SOIC-8 package (four vias in the TDFN-8 package) on either side to allow the heat to dissipate into the ground and power planes on the inner layers of the PCB. Vias can be placed underneath the chip, but this can be resulted in © 2006 California Micro Devices Corp. All rights reserved. 05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 9 PRELIMINARY CM3202 Application Info (cont’d) blocking of the solder. The ground and power planes need to be at least 2 square inches of copper by the vias. It also helps dissipation if the chip is positioned away from the edge of the PCB, and not near other heat-dissipating devices. A good thermal link from the PCB pad to the rest of the PCB will assure the best heat transfer from the CM3202-00DE (TDFN-8) to ambient, θJA, of approximately 42.5 -°C/W, or θJA of approximately 85 °C/W for the CM3202-00SM (SOIC8). Top View Bottom Layer Ground Plane Top Layer Copper Connects to Heat Spreader Pin Solder Mask Thermal PAD Solder Mask Vias (0.3mm Diameter) (TDFN-8 Package) Top View Bottom Layer Ground Plane Top Layer Copper Connects to Heat Spreader Pin Solder Mask Vias (0.3mm Diameter) (SOIC-8 Package) Note: This drawing is not to scale Figure 2. Thermal Layout © 2006 California Micro Devices Corp. All rights reserved. 05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 10 PRELIMINARY CM3202 Mechanical Details TDFN-08 Mechanical Specifications Mechanical Package Diagrams The CM3202-00DE is supplied in an 8-lead, 0.65mm pitch TDFN package. Dimensions are presented below. D PACKAGE DIMENSIONS TDFN JEDEC No. MO-229 (Var. WEEC-1)= Leads 6 Dim. Millimeters Inches Min Nom Max Min Nom Max A 0.70 0.75 0.80 0.028 0.030 0.031 A1 0.00 0.02 0.05 0.000 0.001 0.002 A2 0.45 0.55 0.65 0.018 0.022 0.026 A3 0.20 b 0.25 D 0.30 0.010 3.00 D2 1.90 E 2.00 1.60 e 1.70 2.10 0.075 0.20 L 0.20 # per tape and reel 1 0.012 3 4 TOP VIEW 0.014 0.079 0.083 0.10 C 1.80 0.063 0.067 0.071 0.08 C 0.026 A1 0.45 0.008 0.012 A SIDE VIEW 0.008 0.30 2 0.118 0.65 K 5 0.118 3.00 E2 6 Pin 1 Marking 0.008 0.35 7 E Package 8 A3 A2 0.018 3000 pieces 5 6 7 8 Controlling dimension: millimeters D2 E2 = This package is compliant with JEDEC standard MO-229, variation VEEC-1 with exception of the "D2", "E2" and "b" dimensions as called out in the table above. GNDC0.25 PAD L 4 K 3 2 1 b e 8X BOTTOM VIEW 0.10 M CAB Package Dimensions for 8-Lead TDFN © 2006 California Micro Devices Corp. All rights reserved. 05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 11 PRELIMINARY CM3202 Mechanical Details (cont’d) SOIC-8 Mechanical Specifications Dimensions for CM3202-00SM devices packaged in 8lead SOIC packages with an intagrated heatslug are presented below. Mechanical Package Diagrams TOP VIEW D PACKAGE DIMENSIONS Package SOIC-8 Leads 8 Dimensions Millimeters 8 6 5 Inches Min Max Min Max A 1.30 1.62 0.051 0.064 A1 0.03 0.10 0.001 0.004 B 0.33 0.51 0.013 0.020 C 0.18 0.25 0.007 0.010 D 4.83 5.00 0.190 0.197 E 3.81 3.99 0.150 0.157 e 7 1.27 BSC H 1 5.79 6.20 0.228 0.244 L 0.41 1.27 0.016 0.050 # per tape and reel 2500 pieces 3 4 A H 100 pieces* 2 E SIDE VIEW 0.050 BSC # per tube Pin 1 Marking A1 SEATING PLANE e B END VIEW C Controlling dimension: inches * This is an approximate number which may vary. L ** Centered on package centerline. Package Dimensions for SOIC-8 © 2006 California Micro Devices Corp. All rights reserved. 05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 12