DS50EV401
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SNLS288E – JANUARY 2008 – REVISED MARCH 2013
DS50EV401 2.5 Gbps / 5.0 Gbps or 8.0 Gbps Quad Cable and Backplane Equalizer
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FEATURES
DESCRIPTION
•
The DS50EV401 is a low power, programmable
equalizer specifically designed to reduce inter-symbol
interference (ISI) induced by a variety of interconnect
media. In all modes, the equalizer can operate, error
free, with an input eye that is completely closed by
interconnect ISI. The MODE control, allows the user
to select between equalization settings for 8.0 Gbps
operation or 2.5 Gbps / 5.0 Gbps operation.
1
2
•
•
•
•
•
•
•
•
•
•
•
Automatic power management on an
individual lane basis
Data rate optimized equalization
Operates over 7 meter of 24 AWG Twin-ax
Cables up to 8 Gbps
Typical residual deterministic jitter:
0.18 UI @ 8 Gbps w/ 30” of FR4
0.18 UI @ 5 Gbps w/ 40” of FR4
0.16 UI @ 2.5 Gbps w/ 40” of FR4
8 kV HBM ESD protection
-40 to 85°C operating temperature range
7 mm x 7 mm 48-pin leadless WQFN package
Single power supply of either 3.3V or 2.5V
Low power (typically 95 mW per channel at
2.5V VDD)
The DS50EV401 uses Current-mode logic (CML) on
both input and output ports, which provide constant
50 ohm single-ended impedance to AC ground.
Differential signaling is implemented through out the
entire signal path to minimize supply induced jitter.
The DS50EV401 is available in a 7mm x 7mm 48-pin
leadless WQFN package, and is powered from a
single power supply of either 3.3 or 2.5V.
Application Diagram
EQ
CHANNEL - LOSS
1/4 DS50EV401
SerDes
ASIC/FPGA
EQ
Switch
Device
CHANNEL - LOSS
1/4 DS50EV401
LINE CARD(S)
BACKPLANE
or CABLE
SWITCH CARD
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
DS50EV401
SNLS288E – JANUARY 2008 – REVISED MARCH 2013
www.ti.com
PIN DESCRIPTIONS
Pin Name
Pin Number
I/O, Type
Description
HIGH SPEED DIFFERENTIAL I/O
IN_0+
IN_0-
1
2
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
terminating resistor connects IN_0+ to VDD and IN_0- to VDD.
IN_1+
IN_1-
4
5
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
terminating resistor connects IN_1+ to VDD and IN_1- to VDD.
IN_2+
IN_2-
8
9
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
terminating resistor connects IN_2+ to VDD and IN_2- to VDD.
IN_3+
IN_3-
11
12
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
terminating resistor connects IN_3+ to VDD and IN_3- to VDD.
OUT_0+
OUT_0-
36
35
O, CML
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_0+ to VDD and OUT_0- to VDD.
OUT_1+
OUT_1-
33
32
O, CML
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_1+ to VDD and OUT_1- to VDD.
OUT_2+
OUT_2-
29
28
O, CML
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_2+ to VDD and OUT_2- to VDD.
OUT_3+
OUT_3-
26
25
O, CML
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_3+ to VDD and OUT_3- to VDD.
14
I, LVCMOS
MODE selects the equalizer frequency for EQ channels. MODE is internally pulled low.
L = 6.0 - 8.0 Gbps setting
H = 2.5 Gbps / 5.0 Gbps setting
EN0
44
I, LVCMOS
Channel 0 Enable Input Pin
H = normal operation (enabled)
L = standby mode
Pin is internally pulled High.
EN1
42
I, LVCMOS
Channel 1 Enable Input Pin
H = normal operation (enabled)
L = standby mode
Pin is internally pulled High.
EN2
40
I, LVCMOS
Channel 2 Enable Input Pin
H = normal operation (enabled)
L = standby mode
Pin is internally pulled High.
EN3
38
I, LVCMOS
Channel 3 Enable Input Pin
H = normal operation (enabled)
L = standby mode
Pin is internally pulled High.
SD0
45
O, LVCMOS
Channel 0 Signal Detect Output Pin
H = signal detected
L = no signal detected
SD1
43
O, LVCMOS
Channel 1 Signal Detect Output Pin
H = signal detected
L = no signal detected
SD2
41
O, LVCMOS
Channel 2 Signal Detect Output Pin
H = signal detected
L = no signal detected.
SD3
39
O, LVCMOS
Channel 3 Signal Detect Output Pin
H = signal detected
L = no signal detected
VDD
3, 6, 7,
10, 13,
15, 46
Power
VDD = 2.5V ± 5% or 3.3V ± 10%. VDD pins should be tied to VDD plane through low
inductance path. A 0.1μF bypass capacitor should be connected between each VDD pin to
GND planes.
GND
22, 24,
27, 30,
31, 34
Ground
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
DAP
Ground
Ground reference. The exposed pad at the center of the package must be connected to
ground plane of the board.
EQUALIZATION CONTROL
MODE
DEVICE CONTROL
POWER
Exposed Pad
2
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SNLS288E – JANUARY 2008 – REVISED MARCH 2013
PIN DESCRIPTIONS (continued)
Pin Name
Pin Number
I/O, Type
Description
OTHER
Reserv
16, 17, 18,
19, 20, 21,
23, 37, 47,
48
Reserved. Do not connect. Leave open.
Reserv
Reserv
VDD
SD0
EN0
SD1
EN1
SD2
EN2
SD3
EN3
Reserv
48
47
46
45
44
43
42
41
40
39
38
37
Connection Diagram
IN_0+
1
36
OUT_0+
IN_0-
2
35
OUT_0-
VDD
3
34
GND
IN_1+
4
33
OUT_1+
IN_1-
5
DS50EV401
32
OUT_1-
VDD
6
TOP VIEW
(not to scale)
31
GND
VDD
7
30
GND
29
OUT_2+
DAP = GND
22
23
24
Reserv
GND
VDD
GND
OUT_3-
21
25
Reserv
12
20
IN_3-
Reserv
OUT_3+
19
26
Reserv
11
18
IN_3+
Reserv
GND
17
27
Reserv
10
16
VDD
Reserv
OUT_2-
15
28
VDD
9
14
IN_2-
MODE
8
13
IN_2+
Figure 1. TOP VIEW — Not to scale
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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DS50EV401
SNLS288E – JANUARY 2008 – REVISED MARCH 2013
Absolute Maximum Ratings
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(1) (2)
Supply Voltage (VDD)
-0.5V to +4.0V
LVCMOS Input Voltage
-0.5V + 4.0V
LVCMOS Output Voltage
-0.5V to 4.0V
CML Input/Output Voltage
-0.5V to 4.0V
Junction Temperature
+150°C
Storage Temperature
-65°C to +150°C
ESD Rating
HBM, 1.5 kΩ, 100 pF
>8 kV
Thermal Resistance
θJA, No Airflow
(1)
30°C/W
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute
Maximum Numbers are specified for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating
Voltages only.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
(2)
Recommended Operating Conditions
Min
Typ
Max
Units
V
Supply Voltage
VDD to GND, or
2.375
2.5
2.625
VDD to GND
3.0
3.3
3.6
V
Ambient Temperature
-40
25
+85
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges with default register settings unless other specified.
Symbol
Parameter
Conditions
Min
(1) (2)
Typ
Max
Units
510
700
mW
100
mW
490
mW
POWER
PD
PD
N
Power Dissipation
3.3V Operation
Signal active, VDD = 3.3V, 3.6V
Power Dissipation
2.5V Operation
Signal active, VDD = 2.5V, 2.625V
380
No signal, VDD = 2.5V, 2.625V
30
mW
Supply Noise Tolerance
Up to 50 MHz
100
mVP-P
(3)
No signal, VDD = 3.3V, 3.6V
LVCMOS / LVTTL DC SPECIFICATIONS
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VOH
High Level Output Voltage
3.3V Operation
2.0
VDD
V
2.5V Operation
1.6
VDD
V
-0.3
0.8
V
IOH = -3mA, 3.3V Operation
2.4
IOH = -3mA, 2.5V Operation
2.0
VOL
Low Level Output Voltage
IOL = 3mA
IIH
Input High Current
VIN = VDD, MODE pin (pull down)
IIL
Input Low Current
(1)
(2)
(3)
4
V
V
0.4
V
+140
μA
VIN = VDD, EN pins (pull up)
-15
+15
μA
VIN = 0V, MODE pin (pull down)
-15
+15
μA
VIN = 0V, EN pins (pull up)
-40
μA
Typical values represent most likely parametric norms at VDD = 3.3V or 2.5V, TA = 25°C., and at the Recommended Operation
Conditions at the time of product characterization and are not ensured.
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Allowed supply noise (mVP-P sine wave) under typical conditions.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified. (1) (2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
400
1000
1600
mVP-P
CML RECEIVER INPUTS (IN_n+, IN_n-)
VTX
Input Voltage Swing (Launch
Amplitude)
Measured at point A, AC or DC
coupled, Figure 2
VIN-S
Input Voltage Sensitivity
AC-Coupled or DC-Coupled
Required Differential Envelope
measured at point B, Figure 2, (4),
See FR4 / BACKPLANE Typical
Performance Eye Diagrams,
170
mVP-P
10
dB
RLI
Differential Input Return Loss
100 MHz – 4.0 GHz, with fixture’s
effect de-embedded
RIN
Input Resistance
Single ended to VDD
40
50
60
Ω
Differential measurement with
OUT_n+ and OUT_n- terminated
by 50Ω to GND AC-Coupled,
Figure 3
800
1000
1200
mVP-P
CML OUTPUTS (OUT_n+, OUT_n-)
VO
Output Voltage Swing
VOCM
Output Common-Mode Voltage
Single-ended measurement DCCoupled with 50Ω termination, (5)
VDD –
0.25
V
tR, tF
Transition Time
20% to 80% of differential output
voltage, measured within 1” from
output pins, Figure 3, (5)
40
ps
RO
Output Resistance
Single-ended to VDD
RLO
Differential Output Return Loss
100 MHz – 4.0 GHz, with fixture’s
effect de-embedded. IN_n+ = static
high
tPLHD
Differential Low to High
Propagation Delay
tPHLD
Differential High to Low
Propagation Delay
tID
Idle to Valid Differential Data
tDI
Valid Differential data to idle
tCCSK
Inter Pair Channel to Channel
Skew
40
50
Ω
60
10
dB
240
ps
240
ps
VIN = 800 mVp-p, 5 Gbps, EIEOS,
40” of 6 mil microstrip FR4,
Figure 5, (7)
8
ns
VIN = 800 mVp-p, 5 Gbps, EIOS,
40” of 6 mil microstrip FR4,
Figure 5, (7)
8
ns
Difference in 50% crossing
between channels
7
ps
UIP-P
Propagation delay measurement at
50% VO between input to output,
100 Mbps, Figure 4, (6)
EQUALIZATION
DJ1
DJ2
DJ3
RJ
(4)
(5)
(6)
(7)
(8)
(9)
Residual Deterministic Jitter at 8
Gbps
30” of 6 mil microstrip FR4,
MODE=0, PRBS-7 (27-1) pattern,
0.18
Residual Deterministic Jitter at 5
Gbps
40” of 6 mil microstrip FR4,
MODE=1, PRBS-7 (27-1) pattern,
0.18
0.21
UIP-P
Residual Deterministic Jitter at 2.5
Gbps
40” of 6 mil microstrip FR4,
MODE=1, PRBS-7 (27-1) pattern,
0.16
0.18
UIP-P
Random Jitter
(6) (9)
(7) (8)
(7) (8)
(7) (8)
0.5
psrms
VIN-S is a measurement of the input differential envelope, see FR4 / BACKPLANE Typical Performance Eye Diagrams. The device does
not require an open eye.
Specification is ensured by characterization at optimal MODE setting and is not tested in production.
Measured with clock-like {11111 00000} pattern.
Specification is ensured by characterization at optimal MODE setting and is not tested in production.
Deterministic jitter is measured at the differential outputs (point C of Figure 2), minus the deterministic jitter before the test channel (point
A of Figure 2). Random jitter is removed through the use of averaging or similar means.
Random jitter contributed by the equalizer is defined as sqrt (JOUT2 – JIN2). JOUT is the random jitter at equalizer outputs in ps-rms, see
point C of Figure 2; JIN is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 2.
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DS50EV401
SNLS288E – JANUARY 2008 – REVISED MARCH 2013
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TIMING DIAGRAMS
A
B
C
6 mil FR4 Test Channel
DS50EV401
Signal Source
INPUT
SMA
Connector
OUTPUT
SMA
Connector
Figure 2. Test Setup Diagram
OUT+
80%
VO = (OUT+) ± (OUT-)
80%
0V
20%
20%
OUTtR
tF
Figure 3. CML Output Transition Times
IN
0V
tPLHD
OUT
tPHLD
0V
Figure 4. Propagation Delay Timing Diagram
IN+
VIN
0V
INtID
tDI
OUT+
VO
0V
OUT-
Figure 5. Idle Timing Diagram
6
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SNLS288E – JANUARY 2008 – REVISED MARCH 2013
A
A'
B
B'
5
0
5
0
VOH = VDD
Single-ended
Wavefroms
@ A and B
Vocm
VOL = VDD - 500mV
Vo = 1000 mVp-p
Differential
Wavefrom
A-B
0V (DIFF)
Figure 6. CML Output Swings at A/B
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DS50EV401
SNLS288E – JANUARY 2008 – REVISED MARCH 2013
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FUNCTIONAL DESCRIPTION
DS50EV401 APPLICATIONS INFORMATION
The DS50EV401 is a programmable quad equalizer optimized for copper backplanes and cables at transmission
rates of 2.5 Gbps up to 8 Gbps. The device consists of an input receive equalizer followed by a limiting amplifier.
The equalizer is designed to open an input eye that is completely closed due to inter-symbol interference (ISI)
induced by the channel interconnect. The equalization is set to keep residual deterministic jitter below 0.2 unit
intervals (UI) regardless of data rate. This equalization scheme allows one equalization setting to satisfy most
serial links between 2.5 and 5.0 Gbps. The DS50EV401 is intended as a unidirectional receiver that should be
placed in close physical proximity to the link end point. Therefore the transmitter does not include de-emphasis
as TX equalization would not be needed over the short distance between the equalizer and the end point.
1/4 DS50EV401
VDD
VDD
VDD
DC Offset Correction
VDD
IN_n+
OUT_n+
CML
Driver
Limiting
Amplifier
Equalizer
IN_n-
OUT_nInput Termination
Output Termination
ENn
MODE
SDn
Signal Detect
Figure 7. General Block Diagram
Data Channels
The DS50EV401 consists of four data channels. Each channel provides input termination, receiver equalization,
signal limiting, offset cancellation, and a CML output driver, as shown in Figure 7. The data channels support two
levels of equalization, controlled by the pin MODE. The equalization levels are set simultaneously on all 4
channels, as described in Table 1.
When an idle condition is sensed on a channel’s input, the transmit driver is automatically placed into electrical
idle mode. The common mode voltage is set, and the differential output is forced to zero. To save power, the
output driver current is powered off when the device is in electrical idle mode. All other circuits maintain their bias
currents allowing a fast recovery from idle to the active state. Electric idle is performed on a per channel basis,
and several channels can be in idle while others are actively passing data.
Table 1. MODE Control Table
6 mil microstrip FR4
trace length (in)
8
24 AWG Twin-AX cable
length (m)
Frequency
Channel Loss
MODE
0–30
0–7
8 Gbps
16 dB
0
0–40
0–10
2.5 Gbps
5.0 Gbps
14 dB
20 dB
1
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APPLICATION INFORMATION
GENERAL RECOMMENDATIONS
The DS50EV401 is a high performance device capable of delivering excellent performance. As with most CML
devices, it is recommended that AC coupling capacitors be used to ensure I/O compatibility with other devices. In
order to extract full performance from the device in a particular application, good high-speed design practices
must be followed. TI’s LVDS Owner's Manual (literature number SNLA187), provides detailed information about
managing signal integrity and power delivery to get the most from your design.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and outputs must have a controlled differential impedance of 100Ω. It is preferable to route CML
lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if
possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of
a given differential pair. Route the CML signals away from other signals and noise sources on the printed circuit
board. See AN-1187 (SNOA401) for additional information on WQFN packages.
PACKAGE FOOTPRINT / SOLDERING
See Application Note number 1187, “Leadless Leadframe Package” for information on PCB footprint and
soldering recommendations.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS50EV401 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of
the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.1μF bypass capacitor should be
connected to each VDD pin such that the capacitor is placed as close as possible to the DS50EV401. Smaller
body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as
well. These capacitors can be either tantalum or an ultra-low ESR ceramic and should be placed as close as
possible to the DS50EV401.
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DS50EV401
SNLS288E – JANUARY 2008 – REVISED MARCH 2013
3V3
www.ti.com
VDD
DS50EV401
VDD
3V3
10 PF
10 PF
VDD
Quad EQUALIZER
VDD
VDD
OUT_1+
IN_1-
OUT_1-
IN_2+
OUT_2+
IN_2-
OUT_2-
IN_3+
OUT_3+
IN_3-
OUT_3EN0
SD0
EN1
SD1
EN2
SD2
EN3
SD3
MODE
AC Couple CAPS 75 nF
OUT_0-
IN_1+
Signal Detect Outputs
Control Interface
CML outPUT PORT - 4 CHANNEL
OUT_0+
IN_0AC Couple CAPS 75 nF
CML INPUT PORT - 4 CHANNEL
IN_0+
DAP
Reserv
GND
MODE: Tie High or
Low or drive.
(Speed Select)
All Bypass CAPS
0.1 PF unless noted.
VDD
GND
Figure 8. Typical Interface Circuit
The CML inputs are AC coupled to the device as shown in Figure 8. Internal to the device are 50Ω terminations
to VDD.
The CML outputs drive 100 Ω transmission lines and are AC coupled and terminated at their load.
The ENABLE inputs and SIGNAL DETECT outputs are optional. Internal to the device the signal detect circuity is
connected to the enable circuit providing the automatic power management feature. When the No-signal
condition is detected, the respective channel is placed in standby mode. The MODE pin is used to select
between low and high data rate equalization settings. Depending upon the application it may be tied High, tied
Low, or driven. There are several reserved pins on the device, these are NC pins and should be left open.
Power is supplied through six VDD pins to the device. A 0.1µF capacitor is recommended per pin as close to the
device as possible. A larger bulk capacitor is also recommended to be placed near by the device. Ground is
supplied to the device via the ground pins and also the DAP.
10
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TYPICAL PERFORMANCE EYE DIAGRAMS
FR4 / BACKPLANE Typical Performance Eye Diagrams
The plots show the unequalized and equalized eye patterns for various interconnects as noted. Unequalized is
shown in the left column and the corresponding equalized eye pattern in shown in the right column.
Figure 9. Unequalized Signal (40 in FR4, 2.5 Gbps, PRBS7)
Figure 10. Equalized Signal (40 in FR4, 2.5 Gbps, PRBS7,
MODE=1)
Figure 11. Unequalized Signal (40 in FR4, 5 Gbps, PRBS7)
Figure 12. Equalized Signal (40 in FR4, 5 Gbps, PRBS7,
MODE=1)
Figure 13. Unequalized Signal (30 in FR4, 8 Gbps, PRBS7)
Figure 14. Equalized Signal (30 in FR4, 8 Gbps, PRBS7,
MODE=0)
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DS50EV401
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TYPICAL PERFORMANCE EYE DIAGRAMS (continued)
Twin-AX CABLES Typical Performance Eye Diagrams
The plots show the unequalized and equalized eye patterns for various interconnects as noted. Unequalized is
shown in the left column and the corresponding equalized eye pattern in shown in the right column.
12
Figure 15. Unequalized Signal (10 m 24 AWG Twin-AX
Cable, 2.5 Gbps, PRBS7)
Figure 16. Equalized Signal (10 m 24 AWG Twin-AX
Cable, 2.5 Gbps, PRBS7, MODE=1)
Figure 17. Unequalized Signal (10 m 24 AWG Twin-AX
Cable, 5 Gbps, PRBS7)
Figure 18. Equalized Signal (10 m 24 AWG Twin-AX
Cable, 5 Gbps, PRBS7, MODE=1)
Figure 19. Unequalized Signal (7 m 24 AWG Twin-AX
Cable, 8 Gbps, PRBS7)
Figure 20. Equalized Signal (7 m 24 AWG Twin-AX
Cable, 8 Gbps, PRBS7, MODE=0)
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REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
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PACKAGE OPTION ADDENDUM
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8-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
DS50EV401SQE/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
WQFN
NJU
48
250
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
DS50EV401
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DS50EV401SQE/NOPB
Package Package Pins
Type Drawing
WQFN
NJU
48
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
178.0
16.4
Pack Materials-Page 1
7.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.3
1.3
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS50EV401SQE/NOPB
WQFN
NJU
48
250
213.0
191.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
NJU0048D
SQA48D (Rev A)
www.ti.com
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