AVAGO ACPL-344JT Miller-current clamping Datasheet

ACPL-344JT
Automotive 2.5A Gate-Drive Optocoupler
with Integrated IGBT Desat Overcurrent Sensing,
Miller-Current Clamping, and Under-Voltage Lockout Feedback
Data Sheet
Description
Features
The Avago Technologies Automotive 2.5A Gate-Drive
Optocoupler features fast propagation delay with
excellent timing-skew performance. Smart features that
are integrated to protect the IGBT include IGBT
desaturation sensing with soft-shutdown protection
and fault feedback, under-voltage lockout and feedback,
and active Miller-current clamping. This full-featured
and easy-to-implement IGBT gate-drive optocoupler
comes in a compact, surface-mountable SO-16 package
for space savings. It is suitable for traction power-train
inverter, power converter, battery charger, air-con, and
oil-pump motor drives in HEV and EV applications and
satisfies automotive AEC-Q100 semiconductor
requirements.
• Qualified to AEC-Q100 Grade 1 Test Guidelines
Avago's R2Coupler isolation products provide reinforced
insulation and reliability that deliver safe-signal isolation
critical in automotive and high-temperature industrial
applications.
Functional Diagram
VE VCC2
13
VCC1
3
/UVLO
5
/FAULT
6
Input
Driver
2
AN
7
CA
8
• High Noise Immunity:
– Miller-Current Clamping
– Direct LED input with low-input impedance and
low-noise sensitivity
– Negative Gate Bias
• Peak output current: 2.5A max.
• Miller Clamp-Sinking Current: 1.9A max.
• Wide Operating Voltage: 15V to 25V
• Propagation delay: 250 ns max.
• Integrated fail-safe IGBT protection
– Desat sensing, 'Soft' IGBT turn-off, and Fault
Feedback
– Under-Voltage Lock-Out protection (UVLO) with
Feedback
• SO-16 package with 8 mm clearance and creepage
LED2+
• Regulatory approvals:
– UL1577, CSA
– IEC/EN/DIN EN 60747-5-5
14
DESAT
Applications
Over
Current
• Automotive isolated IGBT/MOSFET inverter gate drive
1
11
VO
10
SSD/
CLAMP
4
SS Control
Miller Control
9
16
VEE2 VEE2
Figure 1. ACPL-344JT Functional Diagram.
• Common Mode Rejection (CMR): >50 kV/μs at
VCM = 1500V
15
UVLO
Output
Driver
VEE1
NC
NC
12
• Automotive temperature range: –40°C to +125°C
• Automotive DC-DC converter
• AC and brushless-DC motor drives
• Industrial inverters for power supplies and motor
controls
• Uninterruptible power supplies (UPS)
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
Part Number
RoHS Compliant
Package
Surface Mount
ACPL-344JT
-000E
SO-16
X
ACPL-344JT
-500E
X
Tape and Reel
X
IEC/EN/DIN EN
60747-5-5
Quantity
X
45 per tube
X
850 per reel
To order, choose a part number from the Part Number column and combine with the desired option from the RoHS
Compliant column to form an order entry.
Example 1:
ACPL-344JT-500E orders the SO-16 Surface Mount package in Tape and Reel packaging with RoHS-compliant IEC/EN/
DIN EN 60747-5-5 Safety Approval.
Option data sheets are available. Contact your Avago sales representative or authorized distributor for information.
Package Outline Drawings
16-Lead Surface Mount
0.457 typ.
(0.018)
1.270 BSC
(0.050)
Recommended Land Pattern
Part Number
Date Code
RoHS
Compliance
Indicator
A 344JT
• YYWW
EE
+0.254
10.363 –0.127
(0.408 +0.010)
–0.005)
+0.254
+0.010)
(0.295 –0.005)
Extended
Datecode for
lot tracking
4)
9°(×
3.505 ±0.127
(0.138 ±0.005)
Dimensions in millimeters (inches)
11.634
(0.458)
7.493 –0.127
0.203 ±0.102
(0.008 ±0.004)
Standoff
Note:
Lead coplanarity = 0.10 mm (0.004 inches)
Floating lead protrusion = 0.25 mm (0.010 inches) max.
Mold Flash on each side = 0.127 mm (0.005 inches) max.
2.160
(0.085)
0.635
(0.025)
1.270
(0.050)
8.763 ±0.254
(0.345 ±0.010)
9°(×
4)
(0 to 8°)
0.635 min.
(0.025)
10.363 ±0.254
(0.408 ±0.010)
Recommended Lead-free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision).
Non-halide flux should be used.
2
0.254 typ.
(0.010)
Product Overview Description
The ACPL-344JT (shown in Figure 1) is a highly integrated power control device that incorporates all the necessary
components for a complete, isolated IGBT gate-drive circuit. It features IGBT desaturation sensing with soft-shutdown
protection and fault feedback, under-voltage lockout and feedback, and active Miller current clamping in a SO-16
package. Direct LED input allows flexible logic configuration and differential current-mode driving with low-input
impedance—greatly increasing noise immunity.
Package Pin Out
1 VEE1
VEE2 16
2 NC
LED2+ 15
3 VCC1
DESAT 14
4 NC
VE 13
5 /UVLO
VCC2 12
6 /FAULT
VO 11
7 AN
SSD/CLAMP 10
8 CA
VEE2 9
Figure 2. Pin-out of ACPL-344JT
Pin Description
Pin Name
Function
Pin Name
Function
VEE1
Input common
VEE2
Negative power supply
NC
No connection
LED2+
No connection, for testing only
VCC1
Input power supply
DESAT
Desat overcurrent sensing
NC
No connection
VE
IGBT Emitter Reference
/UVLO
VCC2 undervoltage lockout feedback
VCC2
Positive power supply
Driver output to IGBT gate
/FAULT
Overcurrent fault feedback
VO
AN
Input LED anode
SSD/CLAMP Soft Shutdown/Miller Current clamping output.
(For proper functionality, this pin must be connected to
the gate of the IGBT directly or through a current buffer.)
CA
Input LED cathode
VEE2
3
Negative Power Supply
Typical Application/Operation
Introduction to Fault Detection and Protection
The power stage of a typical three-phase inverter is susceptible to several types of failures, most of which are
potentially destructive to the power IGBTs. These failure modes can be grouped into four basic categories: phase and
rail supply short circuits due to user misconnect or bad wiring, control signal failures due to noise or computational
errors, overload conditions induced by the load, and component failures in the gate-drive circuitry. Under any of these
fault conditions, the current through the IGBTs can increase rapidly, causing excessive power dissipation and heating.
The IGBTs become damaged when the current load approaches the saturation current of the device, and the
collector-to-emitter voltage rises above the saturation voltage level. The drastically increased power dissipation
quickly overheats the power device and destroys it. To prevent damage to the drive, fault protection must be
implemented to reduce or turn-off the overcurrent during a fault condition.
A circuit providing fast local-fault detection and shutdown is an ideal solution, but the number of required
components, board space consumed, cost, and complexity have, until now, limited its use to high performance drives.
The features this circuit must have include high speed, low cost, low resolution, low power dissipation, and small size.
The ACPL-344JT satisfies these criteria by combining a high-speed, high-output current driver, high-voltage optical
isolation between the input and output, local IGBT desaturation detection and shut down, and optically isolated fault
and UVLO-status feedback signal into a single 16-pin surface-mount package.
The fault-detection method adopted in the ACPL-344JT monitors the saturation (collector) voltage of the IGBT and
triggers a local-fault shutdown sequence if the collector voltage exceeds a predetermined threshold. A small gatedischarge device slowly reduces the high short-circuit IGBT current to prevent damaging voltage spikes. Before the
dissipated energy can reach destructive levels, the IGBT is shut off. During the off state of the IGBT, the fault detect
circuitry is simply disabled to prevent false ‘fault’ signals.
The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short-circuit
capability of the power device is known, but this method will fail if the gate-drive voltage decreases enough to only
partially turn on the IGBT. By directly measuring the collector voltage, the ACPL-344JT limits the power dissipation
in the IGBT even with insufficient gate-drive voltage. Another more subtle advantage of the desaturation detection
method is that power dissipation in the IGBT is monitored, while the current sense method relies on a preset current
threshold to predict the safe limit of operation. Therefore, an overly- conservative overcurrent threshold is not required
to protect the IGBT.
Recommended Application Circuit
The ACPL-344JT has non-inverting gate-control inputs, and an open-collector fault and UVLO outputs suitable for
wired-OR applications.
The recommended application circuit shown in Figure 3 shows a typical gate-drive implementation using the ACPL344JT.
The two supply bypass capacitors (1.0 μF minimum) provide the large transient currents necessary during a switching transition. The Desat diode and 220 pF blanking capacitor are the necessary external components for the fault
detection circuitry. The gate resistor (10Ω) serves to limit gate-charge current and indirectly control the IGBT collector
voltage rise-and-fall times. The open-collector fault and UVLO outputs have a passive 10 kΩ pull-up resistor and a 330
pF filtering capacitor.
4
DESAT Fault Detection Blanking Time
The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to
allow the collector voltage to fall below the DESAT threshold. This time period, called the total DESAT blanking time, is
controlled by the both internal DESAT blanking time tDESAT(BLANKING) (Figure 6) and external blanking time, determined
by internal charge current, the DESAT voltage threshold, and the external DESAT capacitor.
The total blanking time is calculated in terms of internal blanking time (tDESAT(BLANKING)), external capacitance (CBLANK),
FAULT threshold voltage (VDESAT ), and DESAT charge current (ICHG):
tBLANK = tDESAT(BLANKING) + CBLANK × VDESAT/ICHG
VCC2
VCC1
1 VEE1
+ 5V
10 kΩ
1 µF
VEE2 16
2 NC
LED2+ 15
3 VCC1
DESAT 14
4 NC
10 kΩ
130Ω
330 pF
330 pF
130Ω
220 pF
VE 13
5 /UVLO
µC
1 kΩ
10 µF
VCC2 12
6 /FAULT
1 µF
VO 11
7 AN
SSD/CLAMP 10
8 CA
VEE2 9
ACPL-344JT
10Ω
10 µF
VEE2
Figure 3. Typical gate-drive circuit with Desat current sensing using ACPL-344JT.
Description of Gate Driver and Miller Clamping
The gate driver is directly controlled by the LED current. When LED current is driven HIGH, the output of ACPL-344JT
is capable of delivering 2.5A sourcing current to drive the IGBT’s gate. While LED is switched off, the gate driver can
provide 2.5A sinking current to switch the gate off fast. An additional Miller clamping pull-down transistor is activated
when output voltage reaches about 2V with respect to VEE2 to provide a low impedance path to Miller Current, as
shown in Figure 4.
IF
VO
V GATE
Figure 4. Gate-Drive Signal Behavior.
5
Description of Under-Voltage Lockout
Insufficient gate voltage to IGBT can increase turn-on resistance of IGBT, resulting in large power loss and IGBT damage
due to high heat dissipation. ACPL-344JT monitors the output power supply constantly. When output power supply is
lower than under-voltage lockout (UVLO) threshold, gate-driver output shuts off to protect IGBT from low voltage bias.
During power-up, the UVLO feature forces the gate driver output LOW to prevent unwanted turn-on at lower voltage.
V CC1
V CC2
V UVLO+
V UVLO -
LED I F
t UVLO_ON
t UVLO_OFF
VO
/FAULT
/UVLO
t PHL_UVLO
t PLH_UVLO
Figure 5. Circuit Behaviors at Power up and Power down.
Description of Operation During Overcurrent Condition
1. DESAT terminal monitors IGBT’s VCE voltage.
2. When the voltage on the DESAT terminal exceeds 7V, the output voltage (VOUT ) to IGBT gate goes to Hi-Z state and
the SSD/CLAMP output is slowly lowered.
3. FAULT output goes LOW, notifying the microcontroller of the fault condition.
4. Microcontroller takes appropriate action.
5. When tDESAT(MUTE) expires, LED input must be kept LOW for tDESAT(RESET) before the fault condition is cleared. FAULT
status returns to HIGH and SSD/CLAMP output returns to Hi-Z state.
6. Output (VOUT ) starts to respond to LED input after the fault condition is cleared.
t DESAT (RESET)
IF
Hi-Z
V O state
SSD/Clamp
State
Hi-Z
SSD Clamp
Hi-Z
t DESAT (90%)
VGATE
VDESAT_TH
VDESAT
t DESAT (BLANKING)
V /FAULT
t DESAT (MUTE)
t DESAT (/FAULT)
Figure 6. Circuit Behaviors During Overcurrent Event.
6
Clamp
Hi-Z
Clamp
The ACPL-344JT is approved by the following organizations:
UL
CSA
IEC/EN/DIN EN 60747-5-5
Approved under
UL 1577, component recognition
program up to VISO = 5000VRMS
Approved under
CSA Component Acceptance Notice #5,
File CA 88324.
Approved under
IEC 60747-5-5
EN 60747-5-5
DIN EN 60747-5-5
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics
Description
Symbol
Characteristic Unit
Insulation Classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150VRMS
for rated mains voltage ≤ 300VRMS
for rated mains voltage ≤ 600VRMS
for rated mains voltage ≤ 1000VRMS
I – IV
I – IV
I – IV
I – III
Climatic Classification
40/125/21
Pollution Degree (DIN VDE 0110/1.89)
2
Maximum Working Insulation Voltage
VIORM
1230
VPEAK
Input to Output Test Voltage, Method b
VIORM × 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial discharge < 5 pC
VPR
2306
VPEAK
Input to Output Test Voltage, Method a
VIORM × 1.6 = VPR, Type and Sample Test, tm = 10 sec,
Partial Discharge < 5 pC
VPR
1968
VPEAK
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
VIOTM
8000
VPEAK
Safety-limiting values – maximum values allowed in the event of a failure (also see Figure 7)
Case Temperature
Input Power
Output Power
TS
175
PS,INPUT
400
PS,OUTPUT 1200
Insulation Resistance at TS, VIO = 500 V
RS
>109
°C
mW
mW
Ω
Notes:
1. Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Surface mount classification is class A in accordance with CECCOO802.
2. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulation section IEC/EN/DIN
EN 60747-5-5, for a detailed description of Method a and Method b partial-discharge test profiles.
1400
PS, Output
PS, Input
PS —Power (mW)
1200
1000
800
600
400
200
0
0
25
50
75
100 125 150
TS—Case Temperature (°C)
175
Figure 7. Dependence of safety limiting values on temperature.
7
200
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External Air Gap (Clearance)
L(101)
8.3
mm
Measured from input terminals to output terminals,
shortest distance through air.
Minimum External Tracking
(Creepage)
L(102)
8.3
mm
Measured from input terminals to output terminals,
shortest distance path along body.
0.5
mm
Through insulation distance conductor to conductor,
usually the straight line distance thickness between the
emitter and detector.
>175
V
DIN IEC 112/VDE 0303 Part 1
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance (Comparative
Tracking Index)
CTI
Isolation Group
IIIa
Material Group (DIN VDE 0110)
Absolute Maximum Ratings
Unless otherwise specified, all voltages at input IC reference to VEE1, all voltages at output IC reference to VEE2.
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
–55
+150
°C
Operating Temperature
TA
–40
+125
°C
IC Junction Temperature
TJ
150
°C
Average Input Current
IF(AVG)
20
mA
Peak Transient Input Current
(<1 μs pulse width, 300 pps)
IF(TRAN)
1
A
Reverse Input Voltage
VR
6
V
/Fault Output Current (Sinking)
I/FAULT
10
mA
/Fault Pin Voltage
V/FAULT
+6
V
/UVLO Output Current (Sinking)
I/UVLO
10
mA
/UVLO Pin Voltage
V/UVLO
–0.5
+6
V
Positive Input Supply Voltage
VCC1
–0.5
+26
V
Total Output Supply Voltage
VCC2–VEE2
–0.5
+30
V
Negative Output Supply Voltage
VEE2–VE
–15
+0.5
V
Positive Output Supply Voltage
VCC2–VE
–0.5
+30
V
Gate-Drive Output Voltage
Vo(peak)
–0.5
VCC2 + 0.5
V
–0.5
Note
1
2
Peak Output Current
|IO(peak)|
2.5
A
3
Peak Clamping Sinking Current
ICLAMP
2
A
3
Miller Clamping Pin Voltage
VCLAMP–VEE2
–0.5
VCC2 + 0.5
V
Desat Voltage
VDESAT–VE
VE – 0.5
VCC2 + 0.5
V
4
Output IC Power Dissipation
PO
580
mW
1
Input IC Power Dissipation
PI
150
mW
8
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Notes
Operating Temperature
TA
–40
+125
°C
Input Supply Voltage
VCC1
8
18
V
Total Output Supply Voltage
VCC2–VEE2
15
25
V
5
Negative Output Supply Voltage
VEE2–VE
–10
0
V
3
Positive Output Supply Voltage
VCC2–VE
15
25
V
Input LED Current
IF(ON)
10
16
mA
Input Voltage (OFF)
VF(OFF)
–5.5
+0.8
V
Input Pulse Width
tON(LED)
500
ns
Electrical Specifications
Unless otherwise specified, all Minimum/Maximum specifications are at recommended operating conditions, all voltages at input IC are referenced to VEE1, all voltages at output IC referenced to VEE2. All typical values at TA = 25°C, VCC1 =
12 V, VCC2–VEE2 = 20 V, VE–VEE2 = 0 V.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
IC Supply Current
Input Supply Current
ICC1
3.7
6.0
mA
8
Output Low Supply Current
ICC2L
10.5
13.2
mA
IF = 0 mA
VCC2 = 20V
9
Output High Supply Current
ICC2H
10.6
13.6
mA
IF = 10 mA
VCC2 = 20V
9
1.55
1.85
V
IF = 10 mA
10
V
IF = –10 μA
Logic Input and Output
LED Forward Voltage (VAN – VCA)
VF
1.25
LED Reverse Breakdown
Voltage(VCA – VAN)
VBR
6
LED Input Capacitance
CIN
90
LED Turn-on Current Threshold
Low to High
ITH+
2.7
6.6
mA
VO = 5V
11
LED Turn-on Current Threshold
High to Low
ITH–
2.1
6.4
mA
VO = 5V
11
LED Turn-on Current Hysteresis
ITH_HYS
0.6
FAULT Logic Low Output Current
IFAULT_L
FAULT Logic High Output Current
IFAULT_H
UVLO Logic Low Output Current
IUVLO_L
UVLO Logic High Output Current
IUVLO_H
9
4.0
pF
mA
9.0
20
4.0
9.0
20
mA
V/FAULT = 0.4V
uA
V/FAULT = 5V
mA
V/UVLO = 0.4V
uA
V/UVLO = 5V
Note
Electrical Specifications (continued)
Unless otherwise specified, all Minimum/Maximum specifications are at recommended operating conditions, all voltages at input IC are referenced to VEE1, all voltages at output IC referenced to VEE2. All typical values at TA = 25°C, VCC1 =
12 V, VCC2–VEE2 = 20 V, VE–VEE2 = 0 V.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
–2.0
–0.75
A
VO = VCC2 – 3 V
12
4
13
4
Gate Driver
High Level Output Current
IOH
Low Level Output Current
IOL
1.0
High Level Output Voltage
VOH
VCC2 – 0.5 VCC2 – 0.2
Low Level Output Voltage
VOL
VIN to High Level Output
Propagation Delay Time
tPLH
VIN to Low Level Output
Propagation Delay Time
2.2
A
VO = VEE2 + 2.5V
V
IO = –100 mA
6-8
0.1
0.5
V
IO = 100 mA
50
130
250
ns
Vsource = 5V
Rf = 260Ω
Rg = 10Ω
Cload = 10 nF
f = 10 kHz
Duty Cycle = 50%
tPHL
50
150
250
ns
Pulse Width Distortion
PWD
–100
+20
+100
ns
11,12
Dead Time Distortion (tPLH–tPHL)
DTD
–150
–40
+105
ns
12,13
10% to 90% Rise Time
tR
70
ns
90% to 10% Fall Time
tF
50
ns
Output High Level Common
Mode Transient Immunity
|CMH|
50
>70
kV/μs
TA = 25°C,
IF = 10 mA
VCM = 1500V
21
14
Output Low Level Common Mode |CML|
Transient Immunity
50
>70
kV/μs
TA = 25°C,
IF = 0 mA
VCM = 1500V
21
15
22
35
48
mA
VSSD – VEE2 = 14 V
15
2.0
3.0
0.75
1.9
14,19
9
14,19
10
Active Miller Clamp and Soft Shutdown
Low Level Soft Shutdown Current
During Fault Condition
ISSD
Clamp Threshold Voltage
V TH_CLAMP
Clamp Low Level Sinking Current
ICLAMP
V
A
VCLAMP =
VEE2 + 2.5 V
VCC2 UVLO Protection (UVLO voltage VUVLO reference to VE)
VCC2 UVLO Threshold Low to High
VUVLO+
11.0
12.4
13.7
V
VO > 5 V
8,16
VCC2 UVLO Threshold High to Low
VUVLO-
10.1
11.3
12.8
V
VO < 5 V
8,17
VCC2 UVLO Hysteresis
VUVLO_HYS
1.1
V
8
VCC2 to UVLO High Delay
tPLH_UVLO
10
μs
18
VCC2 to UVLO Low Delay
tPHL_UVLO
10
μs
19
VCC2 UVLO to VOUT High Delay
tUVLO_ON
10
μs
20
VCC2 UVLO to VOUT Low Delay
tUVLO_OFF
10
μs
21
10
Electrical Specifications (continued)
Unless otherwise specified, all minimum/maximum specifications are at recommended operating conditions, all
voltages at input IC are referenced to VEE1, all voltages at output IC referenced to VEE2. All typical values at TA = 25°C,
VCC1 = 12V, VCC2 – VEE2 = 20V, VE – VEE2 = 0V.
Parameter
Symbol
Min.
Typ.
Max.
Units
VDESAT
6.2
7.0
7.8
V
–0.6
Test Conditions
Fig.
Note
16
8
Desaturation Protection (Desat voltage VDESAT reference to VE)
Desat Sensing Threshold
Desat Charging Current
ICHG
–1.2
–0.9
Desat Discharging Current
IDSCHG
20
53
Internal Desat Blanking Time
tDESAT(BLANKING) 0.3
0.6
Desat Sense to 90% SSD Delay
tDESAT(90%)
0.3
μs
23
Desat Sense to 10% SSD Delay
tDESAT(10%)
0.8
μs
24
Desat to Low Level /FAULT Signal Delay
tDESAT(/FAULT)
7.0
μs
25
Output Mute Time due to Desat
tDESAT(MUTE)
2.3
3.2
4.1
ms
26
Time for Input Kept Low Before Fault Reset to
High
tDESAT(RESET)
2.3
3.2
4.1
ms
27
Max.
Units
Test Conditions
VRMS
RH < 50%, t = 1 min. 28, 29, 30
TA = 25°C
1.0
mA
VDESAT = 2 V
17
mA
VDESAT = 8 V
18
μs
CSSD = 1 nF
22
Package Characteristics
Parameter
Symbol Min.
Input-Output Momentary Withstand Voltage
VISO
Typ.
Resistance (Input-Output)
RI-O
1014
Ω
VI-O = 500 VDC
f = 1 MHz
5000
Capacitance (Input-Output)
CI-O
1.3
pF
Thermal coefficient between LED and input IC
AEI
35.4
°C/W
Thermal coefficient between LED and output IC
AEO
33.1
°C/W
Thermal coefficient between input IC and output IC
AIO
25.6
°C/W
Thermal coefficient between LED and Ambient
AEA
176.1
°C/W
Thermal coefficient between input IC and Ambient
AIA
92
°C/W
Thermal coefficient between output IC and Ambient
AOA
76.7
°C/W
11
Notes
30
Notes:
1. Output IC power dissipation is derated linearly above 100°C from 580 mW to 260 mW at 125°C.
2. This supply is optional. Required only when negative gate drive is implemented.
3. Maximum pulse width = 1 μs, maximum duty cycle = 1%.
4. Maximum 500 ns pulse width if peak VDESAT > 10 V.
5. 15V is the recommended minimum operating positive supply voltage (VCC2 – VE) to ensure adequate margin in excess of the maximum VUVLO+
threshold of 13.5V.
6. For High-Level Output Voltage testing, VOH is measured with a DC-load current. When driving capacitive loads, VOH approaches VCC as IOH
approaches zero.
7. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
8. Once VOUT of the ACPL-344JT is allowed to go high (VCC2 – VE > VUVLO), the DESAT detection feature of the ACPL-344JT will be the primary source
of IGBT protection. UVLO is required to ensure DESAT is functional. Once VCC2 exceeds VUVLO+ threshold, DESAT remains functional until VCC2
is below the VUVLO- threshold. Thus, the DESAT detection and UVLO features of the ACPL-344JT work in conjunction to ensure constant IGBT
protection.
9. tPLH is defined as the propagation delay from 50% of LED input IF to 50% of High-level output.
10. tPHL is defined as the propagation delay from 50% of LED input IF to 50% of Low-level output.
11. Pulse Width Distortion (PWD) is defined as (tPHL – tPLH) of any given unit.
12. As measured from IF to VO.
13. Dead Time Distortion (DTD) is defined as (tPLH – tPHL) between any two ACPL-344JT parts under the same test conditions.
14. Common-mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common-mode pulse, VCM, to assure that the
output remains in a high state (meaning VO > 15V).
15. Common-mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common-mode pulse, VCM, to assure that the
output remains in a low state (meaning VO < 1.0V).
16. The “increasing” (meaning turn-on or “positive going” direction) of VCC2 – VE.
17. The “decreasing” (meaning turn-off or “negative going” direction) of VCC2 – VE.
18. The delay time when VCC2 exceeds UVLO+ threshold to UVLO High – 50% of UVLO positive-going edge.
19. The delay time when VCC2 falls below UVLO– threshold to UVLO Low – 50% of UVLO negative-going edge.
20. The delay time when VCC2 exceeds UVLO+ threshold to 50% of High-level output.
21. The delay time when VCC2 falls below UVLO– threshold to 50% of Low-level output.
22. The delay time for ACPL-344JT to respond to a DESAT fault condition without any external DESAT capacitor.
23. The amount of time from when DESAT threshold is exceeded to 90% of VGATE at mentioned test conditions.
24. The amount of time from when DESAT threshold is exceeded to 10% of VGATE at mentioned test conditions.
25. The amount of time from when DESAT threshold is exceeded to FAULT output Low – 50% of VCC1 voltage.
26. The amount of time when DESAT threshold is exceeded, Output is mute to LED input.
27. The amount of time when DESAT Mute time is expired, LED input must be kept LOW for Fault status to return to HIGH.
28. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000VRMS for 1 second.
29. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuousvoltage rating. For the continuous-voltage rating, refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-5 Insulation
Characteristics Table.
30. Device considered a two-terminal device: pins 1 through 8 are shorted together and pins 9 through 16 are shorted together.
12
Thermal Characteristics are based on the ground planes layout of the evaluation PCB, shown as follows:
60 mm
60 mm
VEE1
VEE1
40 mm
40 mm
VEE2
VEE2
PCB Top Side
PCB Bottom Side
Notes on Thermal Calculation
Application and environmental design for ACPL-344JT must ensure that the junction temperature of the internal ICs and
LED within the gate driver optocoupler do not exceed 150°C. The following equations calculate the maximum power
dissipation and its corresponding effect on junction temperatures.
LED Junction Temperature = (AEA × PE) + (AEI × PI) + (AEO × PO) + TA
Input IC Junction Temperature = (AEI × PE) + (AIA × PI) + (AIO × PO) + TA
Output IC Junction Temperature = (AEO × PE) + (AIO × PI) + (AOA × PO) + TA
PE—LED Power Dissipation
PI—Input IC Power Dissipation
PO—Output IC Power Dissipation
Calculation of LED Power Dissipation
LED Power Dissipation, PE = IF(LED) (Recommended Max) × VF(LED) (125°C) × Duty Cycle
Example: PE = 16 mA × 1.25 × 50% duty cycle = 10 mW
Calculation of Input IC Power Dissipation
Input IC Power Dissipation, PI = ICC1 (Max) × VCC1 (Recommended Max.)
Example: PI = 6 mA × 18 V = 108 mW
13
Calculation of Output IC Power Dissipation
Output IC Power Dissipation, PO = VCC2 (Recommended Max.) × ICC2 (Max.) + PHS + PLS
PHS—High Side Switching Power Dissipation
PLS—Low Side Switching Power Dissipation
PHS = (VCC2 × QG × fPWM) × ROH(MAX)/(ROH(MAX) + RGH)/2
PLS = (VCC2 × QG × fPWM) × ROL(MAX)/(ROL(MAX) + RGL)/2
QG—IGBT Gate Charge at Supply Voltage
fPWM—LED Switching Frequency
ROH(MAX)—Maximum High Side Output Impedance—VOH(MIN)/IOH(MIN)
RGH—Gate Charging Resistance
ROL(MAX)—Maximum Low Side Output Impedance—VOL(MIN)/IOL(MIN)
RGL—Gate Discharging Resistance
Example:
ROH(MAX) = (VCC2 – VOH(MIN))/IOH(MIN) = 3V/0.75A = 4Ω
ROL(MAX) = VOL(MIN) / IOL(MIN) = 2.5V/1A = 2.5Ω
PHS = (20V × 1 μC × 10 kHz) × 4Ω/(4Ω + 10Ω)/2 = 28.57 mW
PLS = (20V × 1 μC × 10 kHz) × 2.5Ω/(2.5Ω + 10Ω)/2 = 20 mW
PO = 20 V × 13.6 mA + 28.57 mW + 20 mW = 320.57 mW
Calculation of Junction Temperature
LED Junction Temperature = 176.1 °C/W × 10 mW + 35.4 °C/W × 108 mW + 33.1 × 320.57 mW + TA = 16.2°C + TA
Input IC Junction Temperature = 35.4 °C/W × 10 mW + 92 °C/W × 108 mW + 25.6 × 320.57 mW + TA = 18.5°C + TA
Output IC Junction Temperature = 33.1 °C/W × 10 mW + 25.6 °C/W × 108 mW + 76.7 × 320.57 mW + TA = 27.7°C + TA
14
12
ICC2—Input Supply Current (mA)
ICC1—Input Supply Current (mA)
4.2
4.1
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
–40
ICCL1
ICCH1
–20
0
20
40
60
80
TA—Temperature (°C)
100
120
ITH—LED Current Threshold (mA)
IF—Forward Current (mA)
10.00
0
–20
20
40
60
80
TA—Temperature (°C)
100
120
140
1.00
0.10
1.2
1.3
1.4
1.5
VF—Forward Voltage (V)
ITH+
ITH–
3.5
3
2.5
2
1.5
1
–50
1.6
–25
0
25
50
75
TA—Temperature (°C)
100
125
Figure 11. ITH Across Temperature.
20
8
–40°C
25°C
125°C
19.5
19
7
VOL—Output Low Voltage (V)
VOH —Output High Voltage (V)
9.5
4
Figure 10. IF vs. VF.
18.5
18
17.5
0
Figure 12. VOH vs. IOH.
15
10
Figure 9. ICC2 Across Temperature.
TA = 25°C
17
10.5
9
–40
100.00
0.01
11
140
Figure 8. ICC1 Across Temperature.
ICCL2
ICCH2
11.5
0.5
1
1.5
IOH—Output High Current (A)
2
2.5
–40°C
25°C
125°C
6
5
4
3
2
1
0
0
1
Figure 13. VOL vs. IOL.
2
3
IOL —Output Low Current (A)
4
5
45
200
tPHL
40
tPLH
35
ISSD - Soft Shutdown Current
During Fault Condition (mA)
TP—Propagation Delay (ns)
250
150
100
50
0
–50
–25
0
25
50
75
TA—Temperature (°C)
100
ICHG - Desat Charging Current (mA)
VDESAT —Desat Threshold (V)
IDSCHG—Desat Discharging Current (mA)
–40°C
25°C
125°C
10
5
0
5
10
15
20
VSSD—Soft Shutdown Voltage (V)
25
–0.75
7
6.8
–0.8
–0.85
6.6
6.4
–0.9
–0.95
6.2
–20
0
20
40
60
80
TA—Temperature (°C)
100
120
140
Figure 16. VDESAT Threshold Across Temperature.
60
50
40
30
20
10
–20
0
20
40
60
80
TA —Temperature (°C)
–1
–40
–20
0
20
40
60
80
TA —Temperature (°C)
Figure 17. ICHG Across Temperature.
70
Figure 18. IDCHG Across Temperature.
16
15
–0.7
7.2
0
–40
20
Figure 15. ISSD vs. VSSD.
7.4
6
–40
25
0
125
Figure 14. TP Across Temperature.
30
100
120
140
100
120
140
VEE1
VEE2
LED2+
VCC1
DESAT
NC
VE
/UVLO
Signal Source
5V
Vsource
0V
/FAULT
260Ω
RF
Vo
VCC2
10Ω
VO
AN
SSD/CLAMP
CA
VEE2
RG
CLOAD
10 nF
_
+
NC
20V
ACPL-344JT
VSOURCE
tPLH
VO
50%
tPHL
Figure 19. Propagation Delay Test Circuit.
VEE1
NC
LED2+
VCC1
DESAT
NC
+ 5V
−
130Ω
0.1F
_
20V
+
VO
AN
SSD/CLAMP
CA
VEE2
+
LED2+
VCC1
DESAT
10Ω
10 nF
–
High Voltage Pulse
VCM = 1500V
Figure 20. CMR Vo High Test Circuit.
130Ω
130Ω
0.1F
− 20V
+
VE
/UVLO
Scope
VCC2
/FAULT
VEE2
NC
NC
VE
/UVLO
130Ω
VEE1
VEE2
Scope
VCC2
/FAULT
VO
AN
SSD/CLAMP
CA
VEE2
+
10Ω
10 nF
–
High Voltage Pulse
VCM = 1500V
Figure 21. CMR Vo Low Test Circuit.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Broadcom, the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of
Broadcom and/or its affiliates in the United States, certain other countries and/or the EU.
The term “Broadcom” refers to Broadcom Limited and/or its subsidiaries. For more information, please visit www.broadcom.com.
Data subject to change. Copyright © 2016 by Broadcom. All rights reserved.
AV02-4511EN - September 29, 2016
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product