AD AD8639 30 v zero-drift, rail-to-rail output precision amplifier Datasheet

FEATURES
PIN CONFIGURATIONS
ADA4638-1
Single supply operation: 4.5 V to 30 V
Dual supply operation: ±2.25 V to ±15 V
Low offset voltage: 4 μV maximum
Input offset voltage drift: 0.05 μV/°C maximum
High gain: 130 dB minimum
High PSRR: 120 dB minimum
High CMRR: 130 dB minimum
Input common-mode range includes lower supply rail
Rail-to-rail output
Low supply current: 0.95 mA maximum
NC 1
–IN 2
+IN 3
TOP VIEW
(Not to Scale)
V– 4
8
NC
7
V+
6
OUT
5
NC
NOTES
1. NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
10072-001
Figure 1. 8-Lead SOIC
ADA4638-1
NC 1
APPLICATIONS
–IN 2
Electronic weigh scale
Pressure and position sensors
Strain gage amplifiers
Medical instrumentation
Thermocouple amplifiers
+IN 3
8 NC
TOP VIEW
(Not to Scale)
V– 4
7 V+
6 OUT
5 NC
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE
CONNECTED TO V–.
10072-002
Data Sheet
30 V Zero-Drift, Rail-to-Rail Output
Precision Amplifier
ADA4638-1
Figure 2. 8-Lead LFCSP
GENERAL DESCRIPTION
The ADA4638-1 is a high voltage, high precision, zero-drift
amplifier featuring rail-to-rail output swing. It is guaranteed to
operate from 4.5 V to 30 V single supply or ±2.25 V to ±15 V
dual supplies while consuming less than 0.95 mA of supply
current at ±5 V.
With an offset voltage of 4 μV, offset drift less than 0.05 μV/°C,
no 1/f noise, and input voltage noise of only 1.2 μV p-p (0.1 Hz
to 10 Hz), the ADA4638-1 is suited for high precision applications
where large error sources cannot be tolerated. Pressure sensors,
medical equipment, and strain gage amplifiers benefit greatly
from nearly zero drift over the wide operating temperature
range. Many applications can take advantage of the rail-to-rail
output swing provided by the ADA4638-1 to maximize the signalto-noise ratio (SNR).
The ADA4638-1 is specified for the extended industrial (−40°C
to +125°C) temperature range and is available in 8-lead LFCSP
(3 mm × 3 mm) and SOIC packages.
Table 1. Analog Devices, Inc., Zero-Drift Op Amp Portfolio
Operating
Voltage
30 V
16 V
5V
Type
Single
Single
Dual
Single
Dual
Quad
Product
ADA4638-1
AD8638
AD8639
ADA4528-1
AD8628
AD8538
ADA4051-1
AD8629
AD8539
ADA4051-2
AD8630
Offset
Voltage
(μV) Max
4.5
9
9
2.5
5
13
15
5
13
15
5
Offset
Voltage Drift
(μV/°C) Max
0.08
0.06
0.06
0.015
0.02
0.1
0.1
0.02
0.1
0.1
0.02
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
ADA4638-1
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications....................................................................................... 1
Applications Information .............................................................. 16
Pin Configurations ........................................................................... 1
Differentiation ............................................................................ 16
General Description ......................................................................... 1
Theory of Operation .................................................................. 17
Revision History ............................................................................... 2
Input Protection ......................................................................... 17
Specifications..................................................................................... 3
No Output Phase Reversal ........................................................ 17
Electrical Characteristics—30 V Operation ............................. 3
Noise Considerations................................................................. 18
Electrical Characteristics—10 V Operation ............................. 4
Comparator Operation.............................................................. 18
Electrical Characteristics—5 V Operation................................ 5
Precision Low-Side Current Shunt Sensor.............................. 20
Absolute Maximum Ratings............................................................ 6
Printed Circuit Board Layout ................................................... 20
Thermal Resistance ...................................................................... 6
Outline Dimensions ....................................................................... 21
ESD Caution.................................................................................. 6
Ordering Guide .......................................................................... 21
REVISION HISTORY
10/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
Data Sheet
ADA4638-1
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—30 V OPERATION
VS = 30 V, VCM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Test Conditions/Comments
Min
VOS
Offset Voltage Drift
ΔVOS/ΔT
Input Bias Current
IB
Typ
Max
Unit
0.5
4.5
12.5
14.5
0.08
0.1
90
500
105
170
27
μV
μV
μV
μV/°C
μV/°C
pA
pA
pA
pA
V
dB
dB
dB
dB
GΩ
pF
pF
−40°C ≤ TA ≤ +125°C; SOIC
−40°C ≤ TA ≤ +125°C; LFCSP
−40°C ≤ TA ≤ +125°C; SOIC
−40°C ≤ TA ≤ +125°C; LFCSP
45
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
25
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Open-Loop Gain
AVO
Input Resistance, Common Mode
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Overload Recovery Time
Settling Time to 0.1%
Unity-Gain Crossover
Phase Margin
Gain-Bandwidth Product
−3 dB Closed-Loop Bandwidth
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
VCM = 0 V to 27 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = 1 V to 29 V
−40°C ≤ TA ≤ +125°C
0
130
130
140
140
RINCM
CINDM
CINCM
VOH
VOL
ISC
ZOUT
PSRR
ISY
SR
142
165
330
4
9
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
29.90
29.85
29.50
29.35
29.58
50
235
60
95
270
445
±38
220
f = 1 MHz, AV = +1
VS = 4.5 V to 30 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
−40°C ≤ TA ≤ +125°C
29.92
120
120
143
0.85
1.05
1.25
V
V
V
V
mV
mV
mV
mV
mA
Ω
dB
dB
mA
mA
tS
UGC
ΦM
GBP
f−3dB
RL = 10 kΩ, CL = 20 pF, AV = +1
RL = 10 kΩ, CL = 20 pF, AV = −100
VIN = 5 V step, RL = 10 kΩ, CL = 20 pF, AV = −1
VIN = 30 mV p-p, RL = 10 kΩ, CL = 20 pF, AV = +1
VIN = 30 mV p-p, RL = 10 kΩ, CL = 20 pF, AV = +1
VIN = 30 mV p-p, RL = 10 kΩ, CL = 20 pF, AV = +100
VIN = 30 mV p-p, RL = 10 kΩ, CL = 20 pF, AV = +1
1.5
8
4
1.3
69
1.5
2.5
V/μs
μs
μs
MHz
Degrees
MHz
MHz
en p-p
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
1.2
66
0.1
μV p-p
nV/√Hz
pA/√Hz
Rev. 0 | Page 3 of 24
ADA4638-1
Data Sheet
ELECTRICAL CHARACTERISTICS—10 V OPERATION
VS = 10 V, VCM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 3.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Test Conditions/Comments
Min
VOS
Offset Voltage Drift
ΔVOS/ΔT
Input Bias Current
IB
Typ
Max
Unit
0.1
4
9
12
0.05
0.08
50
250
80
140
7
μV
μV
μV
μV/°C
μV/°C
pA
pA
pA
pA
V
dB
dB
dB
dB
GΩ
pF
pF
−40°C ≤ TA ≤ +125°C; SOIC
−40°C ≤ TA ≤ +125°C; LFCSP
−40°C ≤ TA ≤ +125°C; SOIC
−40°C ≤ TA ≤ +125°C; LFCSP
20
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
20
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Open-Loop Gain
AVO
Input Resistance, Common Mode
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Overload Recovery Time
Settling Time to 0.1%
Unity-Gain Crossover
Phase Margin
Gain Bandwidth Product
−3 dB Closed-Loop Bandwidth
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
VCM = 0 V to 7 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = 1 V to 9 V
−40°C ≤ TA ≤ +125°C
0
130
130
130
130
RINCM
CINDM
CINCM
VOH
VOL
ISC
ZOUT
PSRR
ISY
SR
155
160
250
4
9
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
9.96
9.95
9.85
9.75
9.86
20
80
25
40
90
145
±22
300
f = 1 MHz, AV = +1
VS = 4.5 V to 30 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
−40°C ≤ TA ≤ +125°C
9.97
120
120
143
0.8
0.95
1.15
V
V
V
V
mV
mV
mV
mV
mA
Ω
dB
dB
mA
mA
tS
UGC
ΦM
GBP
f−3dB
RL = 10 kΩ, CL = 20 pF, AV = +1
RL = 10 kΩ, CL = 20 pF, AV = −100
VIN = 2 V step, RL = 10 kΩ, CL = 20 pF, AV = −1
VIN = 30 mV p-p, RL = 10 kΩ, CL = 20 pF, AV = +1
VIN = 30 mV p-p, RL = 10 kΩ, CL = 20 pF, AV = +1
VIN = 30 mV p-p, RL = 10 kΩ, CL = 20 pF, AV = +100
VIN = 30 mV p-p, RL = 10 kΩ, CL = 20 pF, AV = +1
1.5
14
3
1.1
67
1.4
1.9
V/μs
μs
μs
MHz
Degrees
MHz
MHz
en p-p
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
1.2
66
0.1
μV p-p
nV/√Hz
pA/√Hz
Rev. 0 | Page 4 of 24
Data Sheet
ADA4638-1
ELECTRICAL CHARACTERISTICS—5 V OPERATION
VS = 5 V, VCM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 4.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Test Conditions/Comments
Min
VOS
Offset Voltage Drift
ΔVOS/ΔT
Input Bias Current
IB
Typ
Max
Unit
1
13
18
21
0.05
0.08
90
230
170
200
3
μV
μV
μV
μV/°C
μV/°C
pA
pA
pA
pA
V
dB
dB
dB
dB
GΩ
pF
pF
−40°C ≤ TA ≤ +125°C; SOIC
−40°C ≤ TA ≤ +125°C; LFCSP
−40°C ≤ TA ≤ +125°C; SOIC
−40°C ≤ TA ≤ +125°C; LFCSP
30
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
60
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Open-Loop Gain
AVO
Input Resistance, Common Mode
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Overload Recovery Time
Settling Time to 0.1%
Unity-Gain Crossover
Phase Margin
Gain Bandwidth Product
−3 dB Closed-Loop Bandwidth
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
VCM = 0 V to 3 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = 0.5 V to +4.5 V
−40°C ≤ TA ≤ +125°C
0
118
118
125
125
RINCM
CINDM
CINCM
VOH
VOL
ISC
ZOUT
PSRR
ISY
SR
140
150
75
4
9
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
4.98
4.97
4.90
4.87
4.92
7.5
37
10
15
45
70
±22
340
f = 1 MHz, AV = +1
VS = 4.5 V to 30 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
−40°C ≤ TA ≤ +125°C
4.984
120
120
143
0.8
0.95
1.15
V
V
V
V
mV
mV
mV
mV
mA
Ω
dB
dB
mA
mA
tS
UGC
ΦM
GBP
f−3dB
RL = 10 kΩ, CL = 20 pF, AV = +1
RL = 10 kΩ, CL = 20 pF, AV = −100
VIN = 1 V step, RL = 10 kΩ, CL = 20 pF, AV = −1
VIN = 20 mV p-p, RL = 10 kΩ, CL = 20 pF, AV = +1
VIN = 20 mV p-p, RL = 10 kΩ, CL = 20 pF, AV = +1
VIN = 20 mV p-p, RL = 10 kΩ, CL = 20 pF, AV = +100
VIN = 20 mV p-p, RL = 10 kΩ, CL = 20 pF, AV = +1
1.5
22
3
1.0
64
1.3
1.8
V/μs
μs
μs
MHz
Degrees
MHz
MHz
en p-p
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
1.2
70
0.015
μV p-p
nV/√Hz
pA/√Hz
Rev. 0 | Page 5 of 24
ADA4638-1
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
Supply Voltage
Input Voltage1
Input Current
Differential Input Voltage
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
1
Rating
33 V
±VSY
±10 mA
±VSY
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
θJA is specified for a device soldered on a 4-layer JEDEC
standard board with zero airflow. For LFCSP packages, the
exposed pad is soldered to the board.
Table 6. Thermal Resistance
Package Type
8-Lead SOIC
8-Lead LFCSP
ESD CAUTION
Input voltage should always be limited to less than 30 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 24
θJA
120
75
θJC
45
12
Unit
°C/W
°C/W
Data Sheet
ADA4638-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
30
VSY = ±2.5V
VCM = VSY/2
150 UNITS
NUMBER OF AMPLIFIERS
25
8
6
4
20
15
10
OFFSET VOLTAGE (µV)
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10072-003
9
10
0
3
4
5
6
7
8
0
–2
–1
0
1
2
5
–8
–7
–6
–5
–4
–3
2
–10
–9
NUMBER OF AMPLIFIERS
10
VSY = ±15V
VCM = VSY/2
150 UNITS
OFFSET VOLTAGE (µV)
Figure 3. Input Offset Voltage Distribution
Figure 6. Input Offset Voltage Distribution
20
14
VSY = ±2.5V
VCM = VSY/2
–40°C < TA < +125°C
140 LFCSP UNITS
16
VSY = ±15V
VCM = VSY/2
–40°C < TA < +125°C
140 LFCSP UNITS
12
NUMBER OF AMPLIFIERS
18
NUMBER OF AMPLIFIERS
10072-006
12
14
12
10
8
6
10
8
6
4
4
2
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
TCVOS (µV/°C)
0
10072-004
0
0
Figure 4. Input Offset Voltage Drift Distribution
0.02
0.03
0.04
0.05
TCVOS (µV/°C)
0.06
0.07
0.08
Figure 7. Input Offset Voltage Drift Distribution
30
18
VSY = ±2.5V
VCM = VSY/2
–40°C ≤ TA ≤ +125°C
140 SOIC UNITS
VSY = ±15V
VCM = VSY/2
–40°C ≤ TA ≤ +125°C
140 SOIC UNITS
16
NUMBER OF AMPLIFIERS
25
20
15
10
14
12
10
8
6
4
5
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
TCVOS (µV/°C)
0.08
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
TCVOS (µV/°C)
Figure 8. Input Offset Voltage Drift Distribution
Figure 5. Input Offset Voltage Drift Distribution
Rev. 0 | Page 7 of 24
0.08
10072-108
2
0
10072-105
NUMBER OF AMPLIFIERS
0.01
10072-007
2
ADA4638-1
Data Sheet
10
10
VSY = ±2.5V
8
6
OFFSET VOLTAGE (µV)
4
2
0
–2
–4
4
2
0
–2
–4
–8
–10
–10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
COMMON-MODE VOLTAGE (V)
10072-005
–8
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
COMMON-MODE VOLTAGE (V)
Figure 12. Input Offset Voltage vs. Common-Mode Voltage
Figure 9. Input Offset Voltage vs. Common-Mode Voltage
150
200
VSY = ±2.5V
VSY = ±15V
100
INPUT BIAS CURRENT (pA)
100
50
IB–
0
IB+
–50
–100
50
0
IB–
–50
IB+
–100
–150
–200
–25
0
25
50
75
100
125
TEMPERATURE (°C)
–250
–50
10072-009
–150
–50
Figure 10. Input Bias Current vs. Temperature
–25
0
25
50
TEMPERATURE (°C)
100
125
Figure 13. Input Bias Current vs. Temperature
150
150
VSY = ±15V
VSY = ±2.5V
100
INPUT BIAS CURRENT (pA)
100
50
IB–
0
IB+
–50
–100
50
0
IB+
–50
IB–
–100
0
0.5
1.0
1.5
2.0
2.5
COMMON-MODE VOLTAGE (V)
3.0
–150
10072-010
INPUT BIAS CURRENT (pA)
75
10072-012
INPUT BIAS CURRENT (pA)
150
–150
10072-008
–6
–6
0
3
6
9
12
15
18
21
24
COMMON-MODE VOLTAGE (V)
Figure 11. Input Bias Current vs. Common-Mode Voltage
Figure 14. Input Bias Current vs. Common-Mode Voltage
Rev. 0 | Page 8 of 24
27
10072-013
OFFSET VOLTAGE (µV)
VSY = ±15V
8
6
Data Sheet
ADA4638-1
100
–40°C
+25°C
+85°C
+125°C
0.1
0.01
1m
0.1m
0.01m
0.001
0.01
0.1
1
10
VSY = ±15V
10
–40°C
+25°C
+85°C
+125°C
1
0.1
0.01
10072-014
1
OUTPUT VOLTAGE (VOL) TO SUPPLY RAIL (V)
VSY = ±2.5V
10072-011
0.001
0.001
100
0.01
0.1
LOAD CURRENT (mA)
Figure 15. Output Voltage (VOL) to Supply Rail vs. Load Current
–40°C
+25°C
+85°C
+125°C
0.1
0.01
1m
0.1m
0.01
0.1
1
10
VSY = ±15V
10
–40°C
+25°C
+85°C
+125°C
1
0.1
0.01
10072-018
OUTPUT VOLTAGE (VOH) TO SUPPLY RAIL (V)
1
10072-015
OUTPUT VOLTAGE (VOH) TO SUPPLY RAIL (V)
100
100
VSY = ±2.5V
0.01m
0.001
1m
0.001
100
0.01
0.1
LOAD CURRENT (mA)
OUTPUT VOLTAGE (VOL) TO SUPPLY RAIL (mV)
VSY = ±2.5V
60
50
40
RL = 2kΩ
30
20
RL = 10kΩ
0
25
50
75
100
100
125
TEMPERATURE (°C)
450
400
VSY = ±15V
350
300
250
200
RL = 2kΩ
150
100
RL = 10kΩ
50
0
–50
10072-016
RL = 100kΩ
–25
10
Figure 19. Output Voltage (VOH) to Supply Rail vs. Load Current
70
10
1
LOAD CURRENT (mA)
Figure 16. Output Voltage (VOH) to Supply Rail vs. Load Current
OUTPUT VOLTAGE (VOL) TO SUPPLY RAIL (mV)
10
Figure 18. Output Voltage (VOL) to Supply Rail vs. Load Current
10
0
–50
1
LOAD CURRENT (mA)
RL = 100kΩ
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 20. Output Voltage (VOL) to Supply Rail vs. Temperature
Figure 17. Output Voltage (VOL) to Supply Rail vs. Temperature
Rev. 0 | Page 9 of 24
10072-019
OUTPUT VOLTAGE (VOL) TO SUPPLY RAIL (V)
10
Data Sheet
100
RL = 2kΩ
60
40
RL = 10kΩ
RL = 100kΩ
0
–50
–25
0
25
50
75
100
125
400
RL = 2kΩ
300
200
RL = 100kΩ
0
–50
–25
0
25
50
75
100
125
Figure 21. Output Voltage (VOH) to Supply Rail vs. Temperature
Figure 24. Output Voltage (VOH) to Supply Rail vs. Temperature
1.2
1.2
1.0
0.8
0.6
–40°C
+25°C
+85°C
+125°C
0.4
0.2
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
SUPPLY VOLTAGE (V)
1.1
1.0
VSY = ±5V
0.9
0.8
0.6
0.5
–50
135
60
45
40
0
–45
–20
–90
10k
100k
1M
50
75
100
125
–135
10M
FREQUENCY (Hz)
135
VSY = ±15V
RL = 10kΩ
PHASE
90
45
GAIN
20pF
200pF
GAIN (dB)
0
PHASE (Degrees)
90
GAIN
20
–40
1k
25
80
10072-022
40
20pF
200pF
0
Figure 25. Supply Current vs. Temperature
VSY = ±2.5V
RL = 10kΩ
PHASE
60
–25
TEMPERATURE (°C)
Figure 22. Supply Current vs. Supply Voltage
80
VSY = ±2.5V
VSY = ±15V
0.7
10072-021
0
GAIN (dB)
RL = 10kΩ
100
TEMPERATURE (°C)
SUPPLY CURRENT PER AMPLIFIER (mA)
SUPPLY CURRENT PER AMPLIFIER (mA)
TEMPERATURE (°C)
500
0
20
0
–45
–20
–90
–40
1k
Figure 23. Open-Loop Gain and Phase vs. Frequency
10k
100k
1M
–135
10M
FREQUENCY (Hz)
Figure 26. Open-Loop Gain and Phase vs. Frequency
Rev. 0 | Page 10 of 24
PHASE (Degrees)
20
VSY = ±15V
10072-025
80
600
10072-024
VSY = ±2.5V
10072-020
OUTPUT VOLTAGE (VOH) TO SUPPLY RAIL (mV)
120
10072-017
OUTPUT VOLTAGE (VOH) TO SUPPLY RAIL (mV)
ADA4638-1
Data Sheet
ADA4638-1
60
VSY = ±2.5V
RL = 10kΩ
50
CLOSED-LOOP GAIN (dB)
40
30
AV = +10
10
–10
30
20
10
0
–20
–30
–30
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
AV = +1
–10
–20
–40
10
AV = +10
–40
10
100
1k
10k
100k
Figure 27. Closed-Loop Gain vs. Frequency
120
VSY = ±15V
VCM = VSY/2
100
80
80
CMRR (dB)
100
60
60
40
40
20
20
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0
100
10072-027
CMRR (dB)
VSY = ±2.5V
VCM = VSY/2
140
100k
140
1M
10M
VSY = ±15V
VCM = VSY/2
120
100
100
PSRR (dB)
80
PSRR+
60
40
80
PSRR+
60
40
PSRR–
PSRR–
20
20
0
0
1k
10k
100k
FREQUENCY (Hz)
1M
10M
10072-028
PSRR (dB)
10k
Figure 31. CMRR vs. Frequency
VSY = ±2.5V
VCM = VSY/2
120
1k
FREQUENCY (Hz)
Figure 28. CMRR vs. Frequency
–20
100
10M
Figure 30. Closed-Loop Gain vs. Frequency
120
0
100
1M
FREQUENCY (Hz)
10072-030
0
AV = +1
AV = +100
–20
100
1k
10k
100k
FREQUENCY (Hz)
Figure 32. PSRR vs. Frequency
Figure 29. PSRR vs. Frequency
Rev. 0 | Page 11 of 24
1M
10M
10072-031
20
VSY = ±15V
RL = 10kΩ
50
10072-023
CLOSED-LOOP GAIN (dB)
40
AV = +100
10072-026
60
ADA4638-1
Data Sheet
1k
1k
VSY = ±2.5V
VCM = VSY/2
VSY = ±15V
VCM = VSY/2
10
AV = +100
ZOUT (Ω)
1
AV = +1
1
0.1
0.01
0.01
1k
10k
100k
1M
10M
FREQUENCY (Hz)
10072-029
0.1
1m
100
1m
100
VOLTAGE (5V/DIV)
10072-033
VOLTAGE (0.5V/DIV)
100k
1M
10M
VSY = ±15V
VIN = 24V p-p
AV = +1
RL = 10kΩ
CL = 100pF
TIME (10µs/DIV)
Figure 37. Large Signal Transient Response
VOLTAGE (20mV/DIV)
Figure 34. Large Signal Transient Response
VSY = ±2.5V
VIN = 100mV p-p
AV = +1
RL = 10kΩ
CL = 100pF
10072-034
VOLTAGE (20mV/DIV)
10k
Figure 36. Closed-Loop Output Impedance vs. Frequency
VSY = ±2.5V
VIN = 1V p-p
AV = +1
RL = 10kΩ
CL = 100pF
TIME (1µs/DIV)
1k
FREQUENCY (Hz)
Figure 33. Closed-Loop Output Impedance vs. Frequency
TIME (1µs/DIV)
AV = +100
10072-036
ZOUT (Ω)
AV = +1
VSY = ±15V
VIN = 100mV p-p
AV = +1
RL = 10kΩ
CL = 100pF
TIME (1µs/DIV)
Figure 38. Small Signal Transient Response
Figure 35. Small Signal Transient Response
Rev. 0 | Page 12 of 24
10072-037
10
AV = +10
100
10072-032
AV = +10
100
Data Sheet
ADA4638-1
80
80
VSY = ±2.5V
VIN = 100mV p-p
AV = +1
RL = 10kΩ
60
40
OS+
OS–
40
20
20
10
10
0
1000
LOAD CAPACITANCE (pF)
0
1
INPUT VOLTAGE (V)
0.1
0
–0.1
2
1
0
TIME (10µs/DIV)
0
–0.5
–1
VSY = ±15V
AV = –100
VIN = 500mV p-p
RL = 10kΩ
CL = 100pF
–5
TIME (10µs/DIV)
INPUT VOLTAGE (V)
Figure 43. Positive Overload Recovery
0
1.0
0.5
0
5
–0.5
0
0
–1
–2
–3
OUTPUT VOLTAGE (V)
1
VSY = ±15V
AV = –100
VIN = 500mV p-p
RL = 10kΩ
CL = 100pF
10072-040
INPUT VOLTAGE (V)
10
0
0.1
TIME (10µs/DIV)
15
5
0.2
VSY = ±2.5V
AV = –100
VIN = 100mV p-p
RL = 10kΩ
CL = 100pF
20
–1.0
Figure 40. Positive Overload Recovery
–0.1
1000
0.5
3
OUTPUT VOLTAGE (V)
–0.2
100
Figure 42. Small Signal Overshoot vs. Load Capacitance
10072-039
INPUT VOLTAGE (V)
Figure 39. Small Signal Overshoot vs. Load Capacitance
VSY = ±2.5V
AV = –100
VIN = 100mV p-p
RL = 10kΩ
CL = 100pF
10
LOAD CAPACITANCE (pF)
OUTPUT VOLTAGE (V)
100
10072-042
10
Figure 41. Negative Overload Recovery
Rev. 0 | Page 13 of 24
–5
–10
–15
–20
TIME (10µs/DIV)
Figure 44. Negative Overload Recovery
OUTPUT VOLTAGE (V)
1
OS+
OS–
30
10072-043
30
50
10072-038
50
10072-035
OVERSHOOT (%)
60
VSY = ±15V
VIN = 100mV p-p
AV = +1
RL = 10kΩ
70
OVERSHOOT (%)
70
VOLTAGE (5V/DIV)
Data Sheet
VOLTAGE (1V/DIV)
ADA4638-1
INPUT
VSY = ±2.5V
AV = –1
RL = 10kΩ
OUTPUT
INPUT
VSY = ±15V
AV = –1
RL = 10kΩ
+5mV
+25mV
OUTPUT
–5mV
–25mV
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 48. Positive Settling Time to 0.1%
VOLTAGE (5V/DIV)
INPUT
VSY = ±2.5V
AV = –1
RL = 10kΩ
INPUT
VSY = ±15V
AV = –1
RL = 10kΩ
+25mV
+5mV
OUTPUT
–5mV
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 49. Negative Settling Time to 0.1%
Figure 46. Negative Settling Time to 0.1%
10k
1k
100
1
10
100
1k
FREQUENCY (Hz)
10k
100k
Figure 47. Voltage Noise Density vs. Frequency
VSY = ±15V
VCM = VSY/2
AV = +10
1k
100
10
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 50. Voltage Noise Density vs. Frequency
Rev. 0 | Page 14 of 24
100k
10072-046
VOLTAGE NOISE DENSITY (nV/√Hz)
VSY = ±2.5V
VCM = VSY/2
AV = +10
10072-049
VOLTAGE NOISE DENSITY (nV/√Hz)
10k
10
–25mV
ERROR BAND
POST GAIN = 5
10072-045
ERROR BAND
POST GAIN = 5
10072-048
VOLTAGE (1V/DIV)
Figure 45. Positive Settling Time to 0.1%
OUTPUT
10072-044
ERROR BAND
POST GAIN = 5
10072-041
ERROR BAND
POST GAIN = 5
Data Sheet
ADA4638-1
VSY = ±15V
VCM = VSY/2
AV = +100
TIME (1s/DIV)
Figure 54. 0.1 Hz to 10 Hz Noise
100
10
10
500kHz
FILTER
1
80kHz
FILTER
0.1
VSY = ±2.5V
f = 1kHz
AV = +1
RL = 10kΩ
0.001
0.001
1
0.1
0.01
0.01
0.1
1
VIN (V rms)
0.001
0.001
0.01
0.1
1
10
1
0.1
0.1
THD + N (%)
500kHz FILTER
0.01
80kHz FILTER
100
VSY = ±15V
VIN = 7V rms
AV = +1
RL = 10kΩ
0.01
500kHz FILTER
0.001
VSY = ±2.5V
VIN = 0.5V rms
AV = +1
RL = 10kΩ
80kHz FILTER
1k
10k
FREQUENCY (Hz)
100k
10072-052
THD + N (%)
VSY = ±15V
f = 1kHz
AV = +1
RL = 10kΩ
Figure 55. THD + N vs. Amplitude
1
0.0001
10
80kHz
FILTER
VIN (V rms)
Figure 52. THD + N vs. Amplitude
0.001
500kHz
FILTER
Figure 53. THD + N vs. Frequency
0.0001
10
100
1k
10k
FREQUENCY (Hz)
Figure 56. THD + N vs. Frequency
Rev. 0 | Page 15 of 24
100k
10072-054
0.01
THD + N (%)
100
10072-051
THD + N (%)
Figure 51. 0.1 Hz to 10 Hz Noise
10072-053
TIME (1s/DIV)
10072-050
10072-047
VOLTAGE (0.2µV/DIV)
VOLTAGE (0.2µV/DIV)
VSY = ±2.5V
VCM = VSY/2
AV = +100
ADA4638-1
Data Sheet
APPLICATIONS INFORMATION
The ADA4638-1, with its wide supply voltage range of 4.5 V to
30 V, is a precision, rail-to-rail output, zero-drift operational
amplifier that features a patented combination of auto-zeroing
and chopping technique. This unique topology allows the
ADA4638-1 to maintain its low offset voltage over a wide temperature range and over its operating lifetime. This amplifier offers
ultralow input offset voltage of 4.5 μV maximum and an input
offset voltage drift of 80 nV/°C maximum. Offset voltage errors
due to common-mode voltage swings and power supply variations are also corrected by the auto-zeroing and chopping technique, resulting in a superb typical CMRR figure of 142 dB and
a PSRR figure of 143 dB at a ±15 V supply voltage. With ultrahigh
dc accuracy and no 1/f noise component, the ADA4638-1 is
ideal for high gain amplification of low level signals in dc or low
frequency applications without the risk of excessive output
voltage errors.
DIFFERENTIATION
Traditionally, zero-drift amplifiers are designed using either the
auto-zeroing or chopping technique. Each technique has its
benefits and drawbacks. Auto-zeroing usually results in low
noise energy at the auto-zeroing frequency, at the expense of
higher low frequency noise due to aliasing of wideband noise
into the auto-zeroed frequency band. Chopping results in lower
low frequency noise at the expense of larger noise energy at the
chopping frequency. The ADA4638-1 uses both auto-zeroing
and chopping in a patented ping-pong arrangement to obtain
lower low frequency noise together with lower energy at the
chopping and auto-zeroing frequencies, maximizing the signalto-noise ratio for the majority of applications. The relatively
high chopping frequency of 16 kHz and auto-zeroing frequency
of 8 kHz simplifies filter requirements for a wide, useful
bandwidth.
Rev. 0 | Page 16 of 24
Data Sheet
ADA4638-1
THEORY OF OPERATION
While A1 is being auto-zeroed, A2 (nulled by A4, C3, and C4)
is used for signal amplification. The ADA4638-1 differs from
traditional auto-zero amplifiers in that the input offset voltage
is also chopped during signal amplification. During φ1, +IN
and −IN are applied to the noninverting and inverting inputs,
respectively, of A2. However, during φ2, both the inputs and
outputs of A2 are inverted, and the input offset voltage of A2 is
chopped.
The combination of auto-zeroing and chopping offers two major
benefits. First, any residual offset following the auto-zeroing
process is reduced. During φ1, the output offset voltage of A2 is
+VOSAZ2 and during φ2, it is –VOSAZ2, producing a theoretical
average of zero. Second, the aliased noise spectrum density at dc
due to auto-zeroing is modulated up to the chopping frequency,
and the prechopped noise spectrum density at the chopping
frequency is modulated down to dc. This noise transformation
lowers the noise spectrum density at dc, thus making zero-drift
amplifiers ideal for low frequency signal amplification.
During φ3 and φ4, the roles of A1 and A2 are reversed. A2
offset is nulled, and the input signal is chopped and amplified
using A1.
Ф1
+IN
–IN
OUT
Ф1
Ф4
Ф3
Ф3
Ф4
Ф1
Ф4
Ф1
Ф3
A1
Ф3
Ф4
AOUT
CC
A3
C1
C2
C3
C4
Ф3
Ф3
Ф2
Ф1
Ф1
Ф2
Ф3
Ф2
Ф1
Ф3
A2
A4
Ф1
Ф2
10072-157
Figure 57 shows the ADA4638-1 amplifier block diagram. The
noninverting and inverting amplifier inputs are +IN and –IN,
respectively. The transconductance amplifiers, A1 and A2, are
the two input gain stages; the A3 and A4 transconductance
amplifiers are the nulling amplifiers used to correct the offsets
of A1 and A2, and AOUT is the output amplifier. A four-phase
cycle (φ1 to φ4) controls the switches. In Phase 1 (φ1), A1 is
auto-zeroed where both the inputs of A1 are connected to +IN.
A1 produces a differential output current of VOS1 × gm1, where
VOS1 is the input offset voltage of A1, and gm1 is the differential
transconductance of A1. The outputs of A1 are then connected
to the inputs and outputs of A3. A3 is designed to have an
equivalent resistance of 1/gm3, where gm3 is the transconductance of A3. The amplified version of VOS1, which is VOS1 ×
gm1/gm3, is stored on Capacitors C1 and C2. These capacitors,
together with A3, are used to null out the offset of A1 when A1
amplifies the signal during the φ3 and φ4 phases.
Figure 57. ADA4638-1 Amplifier Block Diagram
INPUT PROTECTION
The ADA4638-1 has internal ESD protection diodes that are
connected between the inputs and each supply rail. These diodes
protect the input transistors in the event of electrostatic discharge and are reverse-biased during normal operation. However,
if either input exceeds one of the supply rails, these ESD diodes
become forward-biased and large amounts of current begin to
flow through them. Without current limiting, this excessive
fault current causes permanent damage to the device. If the
inputs are expected to be subject to overvoltage conditions,
insert a resistor in series with each input to limit the input
current to 10 mA maximum. However, consider the resistor
thermal noise effect on the entire circuit.
NO OUTPUT PHASE REVERSAL
An undesired phenomenon, phase reversal (also known as
phase inversion) occurs in many amplifiers when one or both of
the inputs are driven beyond the specified input common-mode
voltage range, in effect reversing the polarity of the output. In
some cases, phase reversal can induce lockups and cause
equipment damage as well as self destruction.
The ADA4638-1 has been carefully designed to prevent any
output phase reversal, provided that both inputs are maintained
within the supply voltages. If either one or both inputs may
exceed either supply voltage, place resistors in series with the
inputs to limit the current to less than 10 mA.
The ADA4638-1 features rail-to-rail output with a supply voltage from 4.5 V to 30 V. Figure 58 shows the input and output
waveforms of the ADA4638-1 configured as a unity-gain buffer
with a supply voltage of ±15 V and a resistive load of 10 kΩ.
The ADA4638-1 does not exhibit phase reversal.
Rev. 0 | Page 17 of 24
ADA4638-1
Data Sheet
+VSY
VSY = ±15V
RL = 10kΩ
A1
100kΩ
ADA4638-1
A2
10072-158
100kΩ
VOUT
ISY–
10072-059
VOUT
ISY+
–VSY
TIME (2µs/DIV)
Figure 59. Voltage Follower
Figure 58. No Phase Reversal
1.0
0.8
1/f Noise
0.6
The low frequency 1/f noise appears as a slow varying offset to
the ADA4638-1 and is greatly reduced by the combination of
auto-zeroing and chopping technique. This allows the ADA4638-1
to have a much lower noise at dc and low frequency in comparison
to standard low noise amplifiers that are susceptible to 1/f noise.
Figure 47 and Figure 50 show the voltage noise density of the
ADA4638-1 with no 1/f noise.
COMPARATOR OPERATION
Op amps are designed to operate in a closed-loop configuration
with feedback from its output to its inverting input. Figure 59
shows the ADA4638-1 configured as a voltage follower with an
input voltage, which is kept at midpoint of the power supplies.
A1 and A2 indicate the placement of ammeters to measure supply
currents. ISY+ refers to the current flowing into the positive
supply pin of the op amp, and ISY− refers to the current flowing
out of the negative supply pin of the op amp. From Figure 60, as
expected in normal operating condition, the current flowing
into the op amp is equivalent to the current flowing out of the op
amp, where ISY+ = ISY−.
ISY+
0.4
0.2
0
–0.2
–0.4
–0.6
ISY–
–0.8
–1.0
0
5
10
15
20
25
30
VSY (V)
10072-060
1/f noise, also known as pink noise or flicker noise, is inherent
in semiconductor devices and increases as frequency decreases.
At low frequency, 1/f noise is a major noise contributor and
causes a significant output voltage offset when amplified by the
noise gain of the circuit. However, the ADA4638-1 eliminates
the 1/f noise internally, thus making it an excellent choice for dc
or low frequency high precision applications. The 0.1 Hz to
10 Hz voltage noise is only 1.2 μV p-p at ±15 V of supply voltage.
ISY PER AMPLIFIER (mA)
NOISE CONSIDERATIONS
Figure 60. Supply Current vs. Supply Voltage (Voltage Follower)
In contrast to op amps, comparators are designed to work in an
open-loop configuration and to drive logic circuits. Although
op amps are different from comparators, occasionally an unused
section of a dual op amp is used as a comparator to save board
space and cost; however, this is not recommended.
Figure 61 and Figure 62 show the ADA4638-1 configured as
a comparator, with resistors RIN1 and RIN2 in series with the
input pins.
+VSY
RIN1
IINPUT+
A3
ITOTAL+
A1
ISY+
ADA4638-1
RIN2
IINPUT–
A2
ISY–
A4
ITOTAL–
–VSY
Figure 61. Comparator A
Rev. 0 | Page 18 of 24
VOUT
10072-061
VOLTAGE (10V/DIV)
VIN
Data Sheet
ADA4638-1
+VSY
A1
1.0
0.8
ITOTAL+
0.6
IINPUT +
A3
0.4
ISY+
ADA4638-1
CURRENT (mA)
RIN1
VOUT
0.2
ITOTAL+
ISY+
ISY–
ITOTAL–
0
–0.2
–0.4
IINPUT–
RIN2
A4
–0.6
ISY–
–0.8
0
–2
–4
ITOTAL+
ISY+
ISY–
ITOTAL–
–12
0
6
CURRENT (mA)
8
0.6
ITOTAL+
ISY+
ISY–
ITOTAL–
25
2
0
–2
–4
ITOTAL+
ISY+
ISY–
ITOTAL–
–8
–0.6
–10
–0.8
10072-063
–12
VSY (V)
20
4
–6
–0.4
30
15
12
10
25
10
Figure 65. Supply Current vs. Supply Voltage
(Comparator A, RIN1 = RIN2 = 0 kΩ)
0.8
–1.0
5
VSY (V)
1.0
0.4
CURRENT (mA)
2
–10
For more details on op amps as comparators, refer to the
AN-849 Application Note, Using Op Amps as Comparators.
20
30
4
–8
15
30
6
–6
10
30
8
Note that, at 30 V of supply voltage, 8 mA to 9 mA of current
flows through the input pins. This is undesirable. The ADA4638-1
is not recommended to be used as a comparator. If absolutely
necessary, place resistors in series with the inputs of the amplifier to limit input current to less than 10 mA.
5
25
10
ITOTAL = ISY + IINPUT
0
20
12
CURRENT (mA)
With smaller input series resistors, total supply current of the
system increases much more. Figure 65 and Figure 66 show the
supply currents with RIN1 = RIN2 = 0 Ω. The total current of the
system increases to 10 mA.
–0.2
15
Figure 64. Supply Current vs. Supply Voltage
(Comparator B, RIN1 = RIN2 = 100 kΩ)
Figure 63 and Figure 64 show the total supply current of the
system, ITOTAL, and the actual currents, ISY, that flow into and
out of the supply pins of the ADA4638-1. With RIN1 = RIN2 =
100 kΩ and supply voltage of 30 V, the total supply current of
the system is 800 μA to 900 μA.
0
10
VSY (V)
Figure 62. Comparator B
0.2
5
10072-064
0
10072-065
–VSY
–1.0
10072-066
ITOTAL–
10072-062
A2
Figure 63. Supply Current vs. Supply Voltage
(Comparator A, RIN1 = RIN2 = 100 kΩ)
Rev. 0 | Page 19 of 24
0
5
10
15
20
25
VSY (V)
Figure 66. Supply Current vs. Supply Voltage
(Comparator B, RIN1 = RIN2 = 0 kΩ)
ADA4638-1
Data Sheet
Many applications require the sensing of signals near the
positive or negative rails. Current shunt sensors are one such
application and are mostly used for feedback control systems.
They are also used in a variety of other applications, including
power metering, battery fuel gauging and feedback controls in
electrical power steering. In such application, it is desirable to
use a shunt with very low resistance to minimize series voltage
drop. This not only minimizes wasted power, but also allows the
measurement of high currents while saving power. A typical
shunt may be 100 mΩ. At a measured current of 1 A, the
voltage produced from the shunt is 100 mV, and the amplifier
error sources are not critical. However, at low measured current
in the 1 mA range, the 100 μV generated across the shunt
demands a very low offset voltage and drift amplifier to
maintain absolute accuracy. The unique attributes of a zerodrift amplifier provides a solution. The ADA4638-1, with its
input common-mode voltage that includes the lower supply rail,
can be used for implementing low-side current shunt sensors.
Figure 67 shows a low-side current sensing circuit using the
ADA4638-1. The ADA4638-1 is configured as a difference
amplifier with a gain of 1000. Although the ADA4638-1 has
high common-mode rejection, the CMR of the system is limited
by the external resistors. Therefore, the key to high CMR for the
system are resistors that are well matched from both the
resistive ratio and relative drift, where R1/R2 = R3/R4. The
resistors are important in determining the performance over
manufacturing tolerances, time, and temperature.
To avoid leakage currents, keep the surface of the board clean
and free of moisture. Coating the board surface creates a barrier
to moisture accumulation and reduces parasitic resistance on
the board.
Properly bypassing the power supplies and keeping the supply
traces short minimizes power supply disturbances caused by
output current variation. Connect bypass capacitors as close as
possible to the device supply pins. Stray capacitances are a
concern at the outputs and the inputs of the amplifier. It is
recommended that signal traces be kept at a distance of at least
5 mm from supply lines to minimize coupling.
A potential source of offset error is the Seebeck voltage on the
circuit board. The Seebeck voltage occurs at the junction of two
dissimilar metals and is a function of the temperature of the
junction. The most common metallic junctions on a circuit
board are solder-to-board trace and solder-to-component lead.
Figure 68 shows a cross section of a surface-mount component
soldered to a PCB. A variation in temperature across the board
(where TA1 ≠ TA2) causes a mismatch in the Seebeck voltages at
the solder joints thereby resulting in thermal voltage errors that
degrade the performance of the ultralow offset voltage of the
ADA4638-1.
COMPONENT
LEAD
VSC1 +
SURFACE-MOUNT
COMPONENT
VTS1 +
TA1
VSY
VOUT*
RS
0.1Ω
I
R2
100kΩ
TA2
IF TA1 ≠ TA2, THEN
VTS1 + VSC1 ≠ VTS2 + VSC2
To minimize these thermocouple effects, orient resistors so that
heat sources warm both ends equally. Where possible, the input
signal paths should contain matching numbers and types of
components to match the number and type of thermocouple
junctions. For example, dummy components, such as zero value
resistors, can be used to match the thermoelectric error source
(real resistors in the opposite input path). Place matching components in close proximity and orient them in the same manner to
ensure equal Seebeck voltages, thus cancelling thermal errors.
Additionally, use leads that are of equal length to keep thermal
conduction in equilibrium. Keep heat sources on the PCB as far
away from amplifier input circuitry as is practical.
R1
100Ω
ADA4638-1
10072-167
R3
100Ω
*VOUT = AMPLIFIER GAIN × VOLTAGE ACROSS RS
= 1000 × RS × I
= 100 × I
SOLDER
+ VTS2
Figure 68. Mismatch in Seebeck Voltages Causes Seebeck Voltage Error
RL
VSY
R4
100kΩ
VSC2
PC BOARD
COPPER
TRACE
I
+
10072-067
PRECISION LOW-SIDE CURRENT SHUNT SENSOR
Figure 67. Low-Side Current Sensing Circuit
PRINTED CIRCUIT BOARD LAYOUT
The ADA4638-1 is a high precision device with ultralow offset
voltage and offset voltage drift. Therefore, care must be taken in
the design of the printed circuit board (PCB) layout to achieve
optimum performance of the ADA4638-1 at board level.
It is highly recommended to use a ground plane. A ground plane
helps distribute heat throughout the board, maintains a constant
temperature across the board, and reduces EMI noise pickup.
Rev. 0 | Page 20 of 24
Data Sheet
ADA4638-1
OUTLINE DIMENSIONS
2.44
2.34
2.24
3.10
3.00 SQ
2.90
0.50 BSC
8
5
PIN 1 INDEX
AREA
1.70
1.60
1.50
EXPOSED
PAD
0.50
0.40
0.30
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.30
0.25
0.20
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION
SECTION OF THIS DATA SHEET.
01-24-2011-B
0.80
0.75
0.70
SEATING
PLANE
1
4
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
Figure 69. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-11)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
4.00 (0.1574)
3.80 (0.1497)
Figure 70. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model 1
ADA4638-1ACPZ-R7
ADA4638-1ACPZ-RL
ADA4638-1ARZ
ADA4638-1ARZ-R7
ADA4638-1ARZ-RL
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
Z = RoHS Compliant Part.
Rev. 0 | Page 21 of 24
Package Option
CP-8-11
CP-8-11
R-8
R-8
R-8
Branding
A2W
A2W
ADA4638-1
Data Sheet
NOTES
Rev. 0 | Page 22 of 24
Data Sheet
ADA4638-1
NOTES
Rev. 0 | Page 23 of 24
ADA4638-1
Data Sheet
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10072-0-10/11(0)
Rev. 0 | Page 24 of 24