Cypress CY7C1345G-100AXI 4-mbit (128 k x 36) flow-through sync sram Datasheet

CY7C1345G
4-Mbit (128 K × 36) Flow-Through Sync SRAM
4-Mbit (128 K × 36) Flow through Sync SRAM
Features
Functional Description
■
128 K × 36 common I/O
■
3.3 V core power supply (VDD)
■
2.5 V or 3.3 V I/O supply (VDDQ)
■
Fast clock-to-output times
❐ 8.0 ns (100 MHz version)
■
Provide high performance 2-1-1-1 access rate
■
User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self timed write
■
Asynchronous output enable
■
Available in Pb-free 100-pin TQFP package
■
ZZ sleep mode option
The CY7C1345G is a 128 K × 36 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. The maximum access delay from clock rise
is 8.0 ns (100 MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive edge triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining chip enable (CE1), depth expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWx, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
The CY7C1345G enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) is active. Subsequent burst addresses
are internally generated as controlled by the Advance pin (ADV).
The CY7C1345G operates from a +3.3 V core power supply
while all outputs operate with either a +2.5 or +3.3 V supply. All
inputs and outputs are JEDEC standard JESD8-5 compatible.
Selection Guide
Description
100 MHz
Unit
Maximum access time
8.0
ns
Maximum operating current
205
mA
Maximum standby current
40
mA
Errata: For information on silicon errata, see "Errata" on page 21. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05517 Rev. *L
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 25, 2013
CY7C1345G
Logic Block Diagram
ADDRESS
REGISTER
A 0, A1, A
A [1:0]
MODE
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADV
CLK
ADSC
ADSP
DQ D , DQP D
BW D
BYTE
WRITE REGISTER
DQ C, DQP C
BW C
BYTE
WRITE REGISTER
DQ D , DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B , DQP B
BW B
DQ B , DQP B
BYTE
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP A
DQP B
DQP C
DQP D
WRITE REGISTER
DQ A , DQP A
BW A
BWE
DQ A , DQPA
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
GW
ENABLE
REGISTER
CE1
CE2
INPUT
REGISTERS
CE3
OE
ZZ
SLEEP
CONTROL
Document Number: 38-05517 Rev. *L
Page 2 of 24
CY7C1345G
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 7
Sleep Mode ................................................................. 7
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read or Write .......................................... 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Neutron Soft Error Immunity ......................................... 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 12
Document Number: 38-05517 Rev. *L
Switching Characteristics .............................................. 13
Timing Diagrams ............................................................ 14
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Errata ............................................................................... 21
Part Numbers Affected .............................................. 21
Product Status ........................................................... 21
Ram9 Sync/NoBL ZZ Pin Issues Errata Summary .... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC® Solutions ...................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
Page 3 of 24
CY7C1345G
Pin Configurations
A
A
81
82
83
84
BWE
GW
OE
ADSC
ADSP
ADV
85
86
87
CLK
89
88
VDD
VSS
91
90
BWA
CE3
93
92
BWC
BWB
94
96
95
CE2
BWD
97
A
CE1
98
34
35
36
37
38
39
40
41
42
43
45
46
47
48
49
50
A
A1
A0
NC/72M
NC/36M
VSS
VDD
NC/18M
NC/9M
A
A
A
A
A
A
A
44
A
99
31
VSSQ
VDDQ
DQD
DQD
DQPD
A
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
CY7C1345G
33
BYTE D
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
A
BYTE C
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
32
VDDQ
VSSQ
DQC
DQC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
DQPC
DQC
DQC
100
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout[1]
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
BYTE B
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
BYTE A
VSSQ
VDDQ
DQA
DQA
DQPA
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 21.
Document Number: 38-05517 Rev. *L
Page 4 of 24
CY7C1345G
Pin Definitions
Name
A0, A1, A
I/O
Description
Input
Address inputs used to select one of the 128 K address locations. Sampled at the rising edge of
synchronous the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the two
bit counter.
BWA, BWB,
Input
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
BWC, BWD synchronous on the rising edge of CLK.
GW
Input
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write
synchronous is conducted (all bytes are written, regardless of the values on BW[A:D] and BWE).
BWE
Input
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal is asserted LOW
synchronous to conduct a byte write.
CLK
Input clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
Input
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
Input
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
Input
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE
Input
Output enable, asynchronous input, active LOW. Controls the direction of the IO pins. When LOW,
asynchronous the IO pins act as outputs. When deasserted HIGH, IO pins are tristated and act as input data pins. OE
is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input
Advance input signal, Sampled on the Rising Edge of CLK. When asserted, it automatically increments
synchronous the address in a burst cycle.
ADSP
Input
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
Input
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ[2]
Input
ZZ sleep input, active HIGH. When asserted HIGH places the device in a non-time critical sleep
asynchronous condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin has
an internal pull-down.
DQs,
DQPA,
DQPB,
DQPC,
DQPD
IO
Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and DQP[A:D]
are placed in a tristate condition.
VDD
Power supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
VDDQ
IO power
supply
Power supply for the IO circuitry.
VSSQ
IO ground
Ground for the IO circuitry.
Note
2. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 21.
Document Number: 38-05517 Rev. *L
Page 5 of 24
CY7C1345G
Pin Definitions (continued)
Name
MODE
I/O
Description
Input static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode pin has an internal pull up.
NC
–
No connects. Not Internally connected to the die.
NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–
No connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M, and NC/1G are address expansion pins and are not internally connected to the die.
Functional Overview
Single Write Accesses Initiated by ADSP
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t CO) is 8.0 ns (100 MHz device).
Single write access is initiated when the following conditions are
satisfied at clock rise:
1. CE1, CE2, and CE3 are all asserted active
2. ADSP is asserted LOW.
The CY7C1345G supports secondary cache in systems using
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486™ processors. The linear
burst sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable and is determined
by sampling the MODE input. Accesses are initiated with either
the processor address strobe (ADSP) or the controller address
strobe (ADSC). Address advancement through the burst
sequence is controlled by the ADV input. A two bit on-chip wrap
around burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BW[A:D]) inputs. A global write
enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Three synchronous chip selects (CE1, CE2, and CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise:
1. CE1, CE2, and CE3 are all asserted active.
2. ADSP or ADSC is asserted LOW (if the access is initiated by
ADSC, the write inputs are deasserted during this first cycle).
The address presented to the address inputs is latched into the
address register and the burst counter or control logic and
presented to the memory core. If the OE input is asserted LOW,
the requested data is available at the data outputs a maximum
to tCDV after clock rise. ADSP is ignored if CE1 is HIGH.
Document Number: 38-05517 Rev. *L
The addresses presented are loaded into the address register
and the burst inputs (GW, BWE, and BWx) are ignored during this
first clock cycle. If the write inputs are asserted active (see "Truth
Table for Read or Write" on page 9 for appropriate states that
indicate a write) on the next clock rise, the appropriate data is
latched and written into the device. Byte writes are allowed.
During byte writes, BWA controls DQA and BWB controls DQB,
BWC controls DQC, and BWD controls DQD. All IOs are tristated
during a byte write. Since this is a common IO device, the
asynchronous OE input signal is deasserted and the IOs are
tristated prior to the presentation of data to DQs. As a safety
precaution, the data lines are tristated after a write cycle is
detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise:
1. CE1, CE2, and CE3 are all asserted active.
2. ADSC is asserted LOW.
3. ADSP is deasserted HIGH
4. The write input signals (GW, BWE, and BWx) indicate a write
access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter or control logic and delivered to the
memory core. The information presented to DQ[D:A] is written
into the specified address location. Byte writes are allowed.
During byte writes, BWA controls DQA, BWB controls DQB, BWC
controls DQC, and BWD controls DQD. All IOs and even a byte
write are tristated when a write is detected. Since this is a
common IO device, the asynchronous OE input signal is
deasserted and the IOs are tristated prior to the presentation of
data to DQs. As a safety precaution, the data lines are tristated
after a write cycle is detected, regardless of the state of OE.
Page 6 of 24
CY7C1345G
Burst Sequences
The CY7C1345G provides an on-chip two bit wrap around burst
counter inside the SRAM. The burst counter is fed by A[1:0] and
follows either a linear or interleaved burst order. The burst order
is determined by the state of the MODE input. A LOW on MODE
selects a linear burst sequence. A HIGH on MODE selects an
interleaved burst order. Leaving MODE unconnected causes the
device to default to a interleaved burst sequence.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
Sleep Mode
01
00
11
10
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. In this
mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device is
deselected prior to entering the sleep mode. CEs, ADSP, and
ADSC must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
40
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 38-05517 Rev. *L
Page 7 of 24
CY7C1345G
Truth Table
The Truth Table for part CY7C1345G is as follows. [3, 4, 5, 6, 7]
Cycle Description
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselected cycle, power-down
None
H
X
X
L
X
L
X
X
X
L–H Tri-state
Deselected cycle, power-down
None
L
L
X
L
L
X
X
X
X
L–H Tri-state
Deselected cycle, power-down
None
L
X
H
L
L
X
X
X
X
L–H Tri-state
Deselected cycle, power-down
None
L
L
X
L
H
L
X
X
X
L–H Tri-state
L–H Tri-state
Deselected cycle, power-down
None
X
X
X
L
H
L
X
X
X
Sleep mode, power-down
None
X
X
X
H
X
X
X
X
X
X
Tri-state
Q
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
L
L–H
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
H
L–H Tri-state
Write cycle, begin burst
External
L
H
L
L
H
L
X
L
X
L–H
D
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
H
L–H Tri-state
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
L
L–H
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
H
L–H Tri-state
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
L
L–H
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
H
L–H Tri-state
Write cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L–H
Write cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L–H Tri-state
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L–H
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L–H Tri-state
Write cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Q
Q
D
Q
Notes
3. X = “Don’t Care,” H = Logic HIGH, and L = Logic LOW.
4. WRITE = L when any one or more byte write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all byte write enable signals (BWA,
BWB, BWC, BWD), BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE is driven HIGH prior to the start of the write cycle to enable the outputs to tristate. OE is a “Do Not Care” for
the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05517 Rev. *L
Page 8 of 24
CY7C1345G
Truth Table for Read or Write
The Truth Table for read or write for part CY7C1345G is as follows. [8, 9]
Read
Function
GW
H
BWE
H
BWD
X
BWC
X
BWB
X
BWA
X
Read
H
L
H
H
H
H
Write byte (A, DQPA)
H
L
H
H
H
L
Write byte (B, DQPB)
H
L
H
H
L
H
Write bytes (B, A, DQPA, DQPB)
H
L
H
H
L
L
Write byte (C, DQPC)
H
L
H
L
H
H
Write bytes (C, A, DQPC, DQPA)
H
L
H
L
H
L
Write bytes (C, B, DQPC, DQPB)
H
L
H
L
L
H
Write bytes (C, B, A, DQPC, DQPB, DQPA)
H
L
H
L
L
L
Write byte (D, DQPD)
H
L
L
H
H
H
Write bytes (D, A, DQPD, DQPA)
H
L
L
H
H
L
Write bytes (D, B, DQPD, DQPA)
H
L
L
H
L
H
Write bytes (D, B, A, DQPD, DQPB, DQPA)
H
L
L
H
L
L
Write bytes (D, B, DQPD, DQPB)
H
L
L
L
H
H
Write bytes (D, B, A, DQPD, DQPC, DQPA)
H
L
L
L
H
L
Write bytes (D, C, A, DQPD, DQPB, DQPA)
H
L
L
L
L
H
Write all bytes
H
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
Note
8. X = “Don’t Care,” H = Logic HIGH, and L = Logic LOW.
9. This table is only a partial listing of the byte write combinations. Any combination of BWx is valid. Appropriate write is done based on the active byte write.
Document Number: 38-05517 Rev. *L
Page 9 of 24
CY7C1345G
Maximum Ratings
Operating Range
Exceeding the maximum ratings may shorten the battery life of
the device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Commercial
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Industrial
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
DC input voltage ................................. –0.5 V to VDD + 0.5 V
0 °C to +70 °C
–40 °C to +85 °C
VDD
VDDQ
3.3 V5% / 2.5 V –5% to
+ 10%
VDD
Neutron Soft Error Immunity
Test
Conditions Typ
Parameter
Description
LSBU
Logical
single bit
upsets
25 °C
LMBU
Logical multi
bit upsets
SEL
Single event
latch up
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, method 3015) ................................. > 2001 V
Latch up current ..................................................... > 200 mA
Ambient
Temperature
Range
Max*
Unit
361
394
FIT/
Mb
25 °C
0
0.01
FIT/
Mb
85 °C
0
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to
Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”
Electrical Characteristics
Over the Operating Range
Parameter [10, 11]
Description
Test Conditions
Min
Max
Unit
VDD
Power supply voltage
3.135
3.6
V
VDDQ
IO supply voltage
2.375
VDD
V
VOH
Output HIGH voltage
For 3.3 V IO, IOH = –4.0 mA
2.4
–
V
For 2.5 V IO, IOH = –1.0 mA
2.0
–
V
VOL
VIH
VIL
IX
Output LOW voltage
Input HIGH voltage
For 3.3 V, IO, IOL= 8.0 mA
–
0.4
V
For 2.5 V IO, IOL = 1.0 mA
–
0.4
V
For 3.3 V IO
2.0
VDD + 0.3 V
V
For 2.5 V IO
1.7
VDD + 0.3 V
V
For 3.3 V IO
–0.3
0.8
V
For 2.5 V IO
–0.3
0.7
V
Input leakage current except ZZ GND  VI  VDDQ
and MODE
5
5
µA
Input current of MODE
Input LOW voltage
[10]
Input current of ZZ
Input = VSS
–30
–
µA
Input = VDD
–
5
µA
Input = VSS
–5
–
µA
Input = VDD
–
30
µA
IOZ
Output leakage current
GND  VI  VDDQ, output disabled
–5
5
µA
IDD
VDD operating supply current
VDD = Max, IOUT = 0 mA,
f = fMAX= 1/tCYC
–
205
mA
10 ns cycle,
100 MHz
Notes
10. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
11. TPower up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05517 Rev. *L
Page 10 of 24
CY7C1345G
Electrical Characteristics (continued)
Over the Operating Range
Parameter [10, 11]
Min
Max
Unit
ISB1
Automatic CE power-down
current – TTL inputs
Description
Max VDD, device deselected,
VIN  VIH or VIN  VIL, f = fMAX,
inputs switching
Test Conditions
10 ns cycle,
100 MHz
–
80
mA
ISB2
Automatic CE power-down
current – CMOS inputs
10 ns cycle,
Max VDD, device deselected,
VIN  VDD – 0.3 V or VIN  0.3 V, 100 MHz
f = 0, inputs static
–
40
mA
ISB3
Automatic CE power-down
current – CMOS inputs
10 ns cycle,
Max VDD, device deselected,
VIN  VDDQ – 0.3 V or VIN  0.3 V, 100 MHz
f = fMAX, inputs switching
–
65
mA
ISB4
Automatic CE power-down
current – TTL inputs
Max VDD, device deselected,
10 ns cycle,
VIN  VDD – 0.3 V or VIN  0.3 V, 100 MHz
f = 0, inputs static
–
45
mA
Capacitance
Parameter [12]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
Input or output capacitance
100-pin TQFP
Max
Unit
5
pF
5
pF
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
30.32
°C/W
6.85
°C/W
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 3.3 V
Thermal Resistance
Parameter [12]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Note
12. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05517 Rev. *L
Page 11 of 24
CY7C1345G
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317 
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50 
VT = 1.5 V
(a)
GND
5 pF
INCLUDING
JIG AND
SCOPE
2.5 V I/O Test Load
2.5 V
OUTPUT
R = 351 
VT = 1.25 V
(a)
Document Number: 38-05517 Rev. *L
5 pF
INCLUDING
JIG AND
SCOPE
10%
 1ns
 1ns
(c)
R = 1667 
ALL INPUT PULSES
VDDQ
GND
R = 1538 
(b)
90%
10%
90%
(b)
OUTPUT
RL = 50 
Z0 = 50 
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
 1 ns
 1 ns
(c)
Page 12 of 24
CY7C1345G
Switching Characteristics
Over the Operating Range
Parameter [13, 14]
Description
-100
Unit
Min
Max
VDD(typical) to the first access [15]
1
–
ms
tCYC
Clock cycle time
10
–
ns
tCH
Clock HIGH
4.0
–
ns
tCL
Clock LOW
4.0
–
ns
tPOWER
Clock
Output Times
tCDV
Data output valid after CLK rise
–
8.0
ns
tDOH
Data output hold after CLK rise
2.0
–
ns
0
–
ns
–
3.5
ns
–
3.5
ns
0
–
ns
–
3.5
ns
[16, 17, 18]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [16, 17, 18]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[16, 17, 18]
OE HIGH to output high Z
[16, 17, 18]
Setup Times
tAS
Address setup before CLK rise
2.0
–
ns
tADS
ADSP, ADSC setup before CLK rise
2.0
–
ns
tADVS
ADV setup before CLK rise
2.0
–
ns
tWES
GW, BWE, BWx setup before CLK rise
2.0
–
ns
tDS
Data input setup before CLK rise
2.0
–
ns
tCES
Chip enable setup
2.0
–
ns
tAH
Address hold after CLK rise
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.5
–
ns
tWEH
GW, BWE, BWx hold after CLK rise
0.5
–
ns
tADVH
ADV hold after CLK rise
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
ns
Hold Times
Notes
13. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
14. Test conditions shown in (a) of Figure 2 on page 12 unless otherwise noted.
15. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation is initiated.
16. tCHLZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of Figure 2 on page 12. Transition is measured ± 200 mV from steady state voltage.
17. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z
prior to low Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document Number: 38-05517 Rev. *L
Page 13 of 24
CY7C1345G
Timing Diagrams
Figure 3. Read Cycle Timing [19]
tCYC
CLK
t
t ADS
CH
t CL
tADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t
GW, BWE,BW
t
WES
WEH
[A:B]
t CES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t CDV
t OELZ
t CHZ
t DOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 38-05517 Rev. *L
Page 14 of 24
CY7C1345G
Timing Diagrams (continued)
Figure 4. Write Cycle Timing [20, 21]
t CYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW
[A:B]
t
WES
t
WEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
20. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
21. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWx LOW.
Document Number: 38-05517 Rev. *L
Page 15 of 24
CY7C1345G
Timing Diagrams (continued)
Figure 5. Read/Write Timing [22, 23, 24]
tCYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
ADSC
t AS
ADDRESS
A1
tAH
A2
A3
A4
t
BWE, BW
WES
t
A5
A6
D(A5)
D(A6)
WEH
[A:B]
t CES
tCEH
CE
ADV
OE
t DS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
t OELZ
D(A3)
t CDV
Q(A2)
Back-to-Back READs
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWx LOW.
23. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
24. GW is HIGH.
Document Number: 38-05517 Rev. *L
Page 16 of 24
CY7C1345G
Timing Diagrams (continued)
Figure 6. ZZ Mode Timing [25, 26]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
A LL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
25. Device must be deselected when entering ZZ mode. See "Truth Table" on page 8 for all possible signal conditions to deselect the device.
26. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05517 Rev. *L
Page 17 of 24
CY7C1345G
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices
Speed
(MHz)
100
Package
Diagram
Ordering Code
Part and Package Type
Operating
Range
CY7C1345G-100AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1345G-100AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
lndustrial
Ordering Code Definitions
CY
7
C
1345 G - 100
A
X
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type:
A = 100-pin TQFP
Speed Grade: 100 MHz
Process Technology: G 90 nm
Part Identifier: 1345 = FT, 128 Kb × 36 (4 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05517 Rev. *L
Page 18 of 24
CY7C1345G
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RAPackage Outline, 51-85050
51-85050 *D
Document Number: 38-05517 Rev. *L
Page 19 of 24
CY7C1345G
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
complementary metal oxide semiconductor
CE
chip enable
°C
degree Celsius
CEN
clock enable
MHz
megahertz
GW
global write
µA
microampere
I/O
input/output
mA
milliampere
OE
output enable
mm
millimeter
SRAM
static random access memory
ms
millisecond
TQFP
thin quad flat pack
MHz
megahertz
WE
write enable
ns
nanosecond
pF
picofarad
V
volt
W
watt
Document Number: 38-05517 Rev. *L
Symbol
Unit of Measure
Page 20 of 24
CY7C1345G
Errata
This section describes the Ram9 Sync/NoBL ZZ pin issues. Details include trigger conditions, the devices affected, proposed workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.
Part Numbers Affected
Density & Revision
Package Type
Operating Range
4Mb-Ram9 Synchronous SRAMs: CY7C134*G
All packages
Commercial/
Industrial
Product Status
All of the devices in the Ram9 4Mb Sync/NoBL family are qualified and available in production quantities.
Ram9 Sync/NoBL ZZ Pin Issues Errata Summary
The following table defines the errata applicable to available Ram9 4Mb Sync/NoBL family devices.
Item
1.
Issues
ZZ Pin
Description
Device
When asserted HIGH, the ZZ pin places
device in a “sleep” condition with data integrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
4M-Ram9 (90nm)
Fix Status
For the 4M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
1. ZZ Pin Issue
■ PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■
TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■
SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■
WORKAROUND
Tie the ZZ pin externally to ground.
■
FIX STATUS
Fix was done for the 72Mb RAM9 Synchronous SRAMs and 72M RAM9 NoBL SRAMs devices. Fixed devices have a new
revision. The following table lists the devices affected and the new revision after the fix.
Document Number: 38-05517 Rev. *L
Page 21 of 24
CY7C1345G
Document History Page
Document Title: CY7C1345G, 4-Mbit (128 K × 36) Flow-Through Sync SRAM
Document Number: 38-05517
Rev.
ECN
Orig. of
Change
Submission
Date
**
224365
RKF
See ECN
New data sheet.
*A
278513
VBL
See ECN
Updated Features (Removed 66 MHz frequency related information).
Updated Selection Guide (Removed 66 MHz frequency related information).
Updated Electrical Characteristics (Removed 66 MHz frequency related
information).
Updated Switching Characteristics (Removed 66 MHz frequency related
information).
Updated Ordering Information (Updated part numbers (Added Pb-free BGA
package), changed TQFP package to Pb-free TQFP package, added comment
on the BG Pb-free package availability below the table).
*B
333626
SYT
See ECN
Updated Features (Removed 117 MHz frequency related information).
Updated Selection Guide (Removed 117 MHz frequency related information).
Updated Pin Configurations (Updated Address Expansion balls in the pinouts
for 100-pin TQFP and 119-ball BGA Packages as per JEDEC standards).
Updated Pin Definitions.
Updated Functional Overview (Updated ZZ Mode Electrical Characteristics
(Replaced ‘Snooze’ with ‘Sleep’)).
Updated Truth Table (Replaced ‘Snooze’ with ‘Sleep’).
Updated Electrical Characteristics (Updated test conditions for VOL and VOH
parameters, removed 117 MHz frequency related information).
Updated Switching Characteristics (Removed 117 MHz frequency related
information).
Updated Thermal Resistance (Replaced TBDs for JA and JC to their
respective values).
Updated Ordering Information (By shading and unshading MPNs as per
availability, removed comment on the availability of BG Pb-free package).
*C
418633
RXU
See ECN
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Changed “Input Load Current except ZZ
and MODE” to “Input Leakage Current except ZZ and MODE”, updated Note 11
(Changed test condition from VIH < VDD to VIH VDD)).
Updated Ordering Information (Updated part numbers, replaced Package
Name column with Package Diagram in the Ordering Information table).
Replaced Package Diagrams.
*D
480124
VKN
See ECN
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
*E
1274724
VKN
See ECN
Updated Timing Diagrams (Updated Figure 4).
*F
2756998
VKN
08/28/09
Included Neutron Soft Error Immunity.
Modified Ordering Information (By including parts that are available, and
modified the disclaimer for the Ordering information).
*G
3034798
NJY
09/21/2010
Added Ordering Code Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*H
3353361
PRIT
08/24/2011
Updated Package Diagrams.
Document Number: 38-05517 Rev. *L
Description of Change
Page 22 of 24
CY7C1345G
Document History Page (continued)
Document Title: CY7C1345G, 4-Mbit (128 K × 36) Flow-Through Sync SRAM
Document Number: 38-05517
Rev.
ECN
Orig. of
Change
Submission
Date
Description of Change
*I
3587066
NJY / PRIT
05/10/2012
Updated Features (Removed 133 MHz frequency related information, removed
119-ball BGA package related information).
Updated Functional Description (Removed “For best practice
recommendations, refer to the Cypress application note SRAM System Design
Guidelines”).
Updated Selection Guide (Removed 133 MHz frequency related information).
Updated Pin Configurations (Removed 119-ball BGA package related
information).
Updated Functional Overview (Removed 133 MHz frequency related
information).
Updated Electrical Characteristics (Removed 133 MHz frequency related
information).
Updated Capacitance (Removed 119-ball BGA package related information).
Updated Thermal Resistance (Removed 119-ball BGA package related
information).
Updated Switching Characteristics (Removed 133 MHz frequency related
information).
Updated Package Diagrams (Removed 119-ball BGA package related
information).
*J
3753130
PRIT
09/24/2012
No technical updates. Completing sunset review.
*K
3980577
PRIT
04/24/2013
Added Errata.
*L
4039228
PRIT
06/25/2013
Added Errata Footnotes.
Updated in new template.
Document Number: 38-05517 Rev. *L
Page 23 of 24
CY7C1345G
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05517 Rev. *L
Revised June 25, 2013
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 24 of 24