CMT60N03 N-CHANNEL Logic Level Power MOSFET APPLICATION FEATURES Buck Converter High Side Switch Low ON Resistance Other Applications Low Gate Charge Peak Current vs Pulse Width Curve VDSS RDS(ON) Typ. ID Inductive Switching Curves 30V 10.8mΩ 50A Improved UIS Ruggedness PIN CONFIGURATION SYMBOL TO-252 TO-263 Front View Front View D SOURCE DRAIN GATE D G 1 2 3 S G 1 2 S N-Channel MOSFET 3 ABSOLUTE MAXIMUM RATINGS Rating Symbol Drain to Source Voltage (Note 1) Value Unit VDSS 30 V ID 50 A － Continuous Tc = 100℃, VGS@10V (Note 2) ID Fig.3 － Pulsed Tc = 25℃, VGS@10V (Note 3) IDM Fig.6 Gate-to-Source Voltage － Continue VGS ±20 V Total Power Dissipation PD 52 W 0.5 W/℃ Drain to Current － Continuous Tc = 25℃, VGS@10V (Note 2) Derating Factor above 25℃ Peak Diode Recovery dv/dt (Note 4) dv/dt 3.0 V/ns Operating Junction and Storage Temperature Range TJ, TSTG -55 to 150 ℃ Single Pulse Avalanche Energy L=1.1mH,ID=30 Amps EAS 500 mJ Maximum Lead Temperature for Soldering Purposes TL 300 ℃ TPKG 260 ℃ IAS Fig.8 Maximum Package Body for 10 seconds Pulsed Avalanche Rating THERMAL RESISTANCE Symbol RθJC Parameter Junction-to-case RθJA Junction-to-ambient (PCB Mount) Junction-to-ambient RθJA 2004/05/24 Preliminary Min Typ Max 2.4 Units ℃/W 50 ℃/W 62 ℃/W Test Conditions Water cooled heatsink, PD adjusted for a peak junction temperature of +150℃ Minimum pad area, 2-oz copper, FR-4 circuit board, double sided 1 cubic foot chamber, free air Champion Microelectronic Corporation Page 1 CMT60N03 N-CHANNEL Logic Level Power MOSFET ORDERING INFORMATION Part Number Package CMT60N03N252 TO-252 CMT60N03N263 TO-263 ELECTRICAL CHARACTERISTICS Unless otherwise specified, TJ = 25℃. CMT60N03 Characteristic Symbol Min VDSS 30 Typ Max Units OFF Characteristics Drain-to-Source Breakdown Voltage V (VGS = 0 V, ID = 250 μA) Breakdown Voltage Temperature Coefficient, Fig.11 ΔVDSS/∆TJ 27 mV/℃ (Reference to 25℃, ID = 250 μA) Drain-to-Source Leakage Current IDSS µA (VDS = 24 V, VGS = 0 V, TJ = 25℃) 1 (VDS = 24 V, VGS = 0 V, TJ = 125℃) 10 Gate-to-Source Forward Leakage IGSS 100 nA IGSS -100 nA 3.0 V (VGS = 20 V) Gate-to-Source Reverse Leakage (VGS = -20 V) ON Characteristics VGS(th) Gate Threshold Voltage,Fig.12 1.0 (VDS = VGS, ID = 250 μA) Static Drain-to-Source On-Resistance, Fig.9,10 (Note 5) RDS(on) (VGS = 10 V, ID = 15A) mΩ 10.8 (VGS = 4.5 V, ID = 12A) 12.5 15.4 Forward Transconductance (VDS = 15 V, ID = 12A) (Note 5) gFS 28 S (VDS = 15 V, VGS = 0 V, Ciss 1520 f = 1.0 MHz) Coss 314 pF pF Fig.14 Crss 152 pF Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge (VGS = 10 V) Total Gate Charge (VGS = 4.5 V) Gate-to-Source Charge Qg 27.9 35 (VDS = 15 V, ID = 12 A) (Note 6) Qg 14 19 Fig.15 Qgs 4.9 nC 4.3 nC td(on) 10 tr 3.4 ns ns td(off) 36 ns Gate-to-Drain Charge Qgd nC nC Resistive Switching Characteristics Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time (VDD = 15 V, ID = 12 A, VGS = 10 V, RG = 1.0Ω) (Note 6) (VDD = 15 V, ID = 12 A, VGS = 4.5V, RG = 1.0Ω) (Note 6) 6.0 ns td(on) 16 tr 7.2 ns ns td(off) 34 ns tf 14 ns tf Source-Drain Diode Characteristics Continuous Source Current (Body Diode Fig.16) IS 50 A ISM Fig.6 A Integral pn-diode in MOSFET Pulse Source Current (Body Diode) Forward On-Voltage (IS = 12 A, VGS = 0 V) VSD 1.0 V Forward Turn-On Time (IF = 12 A, VGS = 0 V, trr 25 38 ns di/dt = 100A/µs) Qrr 31 46 nC Reverse Recovery Charge 2004/05/24 Preliminary Champion Microelectronic Corporation Page 2 CMT60N03 N-CHANNEL Logic Level Power MOSFET Note 1: TJ = +25℃ to 150℃ Note 2: Current is calculated based upon maximum allowable junction temperature. Package current limitation is 30A. Note 3: Repetitive rating; pulse width limited by maximum junction temperature. Note 4: ISD = 12.0A, di/dt ≤100A/µs, VDD ≤ BVDSS, TJ = +150℃ Note 5: Pulse width ≤ 250µs; duty cycle ≤ 2% Note 6: Essentially independent of operating temerpature. 2004/05/24 Preliminary Champion Microelectronic Corporation Page 3 CMT60N03 N-CHANNEL Logic Level Power MOSFET Figure 1. Maximum Effective Thermal Impedance, Junction-to-Case ZθJC, Thermal Impedance 1.00 Duty Cycle 50% 20% PDM 10% 0.10 t1 5% t2 2% 1% 0.01 NOTES: DUTY FACTOR: D=t1/t2 PEAK TJ=PDM x ZθJC x RθJC+TC single pulse 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 tp, Rectangular Pulse Duration (Seconds) Figure 3. Maximum Continuous Drain Current vs Case Temperature Figure 2. Maximum Power Dissipation vs Case Temperature 35 50 ID, Drain Current (A) PD, Power Dissipation (W) 60 40 30 20 10 30 25 20 15 10 5 0 0 25 75 50 100 125 25 150 50 TC, Case Temperature (oC) 100 125 150 TC, Case Temperature (oC) Figure 5. Typical Drain-to-Source ON Resistance vs Gate Voltage and Drain Current Figure 4. Typical Output Characteristics 100 0.10 VGS = 10V 80 VGS = 4.5V 70 60 VGS = 4.0V 50 VGS = 3.7V 40 VGS = 3.5V VGS = 3.3V 30 VGS = 3.0V 20 VGS = 2.7V 10 10 20 15 VDS, Drain-to-Source Voltage (V) 2004/05/24 Preliminary 0.07 0.06 0.05 0.04 PULSE DURATION = 250 µS DUTY CYCLE = 0.5% MAX TC = 25 oC 0.03 0.02 0.00 0 5 0.08 0.01 VGS = 2.5V 0 ID = 7A ID = 14 A ID = 28 A ID = 55 A 0.09 ON Resistance (Ω) PULSE DURATION = 250 µS DUTY CYCLE = 0.5% MAX o TC = 25 C RDS(ON), Drain-to-Source 90 ID, Drain Current (A) 75 2 3 4 5 6 7 8 9 VGS, Gate-to-Source Voltage (V) Champion Microelectronic Corporation Page 4 10 CMT60N03 N-CHANNEL Logic Level Power MOSFET Figure 6. Maximum Peak Current Capability IDM, Peak Current (A) 10000 FOR TEMPERATURES o ABOVE 25 C DERATE PEAK CURRENT AS FOLLOWS: TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1000 I = I 25 100 150 – T C ---------------------125 VGS = 10V 10 1 1E-6 10E-6 100E-6 1E-3 10E-3 100E-3 1E+0 10E+0 tp, Pulse Width (Seconds) Figure 8. Unclamped Inductive Switching Capability Figure 7. Typical Transfer Characteristics 1000 PULSE DURATION = 250 µS DUTY CYCLE = 0.5% MAX VDS = 15 V 25 IAS, Avalanche Current (A) ID, Drain-to-Source Current (A) 30 20 +150 oC 15 +25 oC 10 -55 oC 5 0 1.5 2.0 2.5 3.0 4.0 3.5 100 STARTING TJ = 25 oC 10 STARTING TJ = 150 oC 1 1E-6 10E-6 100E-6 1E-3 10E-3 100E-3 VGS, Gate-to-Source Voltage (V) tAV, Time in Avalanche (Seconds) Figure 9. Typical Drain-to-Source ON Resistance vs Drain Current Figure 10. Typical Drain-to-Source ON Resistance vs Junction Temperature PULSE DURATION = 10 µS DUTY CYCLE = 0.5% MAX TC=25°C 100 1.6 1.5 RDS(ON), Drain-to-Source Resistance (Normalized) RDS(ON), Drain-to-Source ON Resistance (mΩ) 1.0 If R≠ 0: tAV= (L/R) ln[IAS×R)/(1.3BVDSS-VDD)+1] If R= 0: tAV= (L×IAS)/(1.3BVDSS-VDD) R equals total Series resistance of Drain circuit VGS = 4.5V VGS = 10 V 10 1.4 1.3 1.2 1.1 1.0 PULSE DURATION = 250 µS DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 15A 0.9 0.8 0.7 0 50 100 150 200 250 300 ID, Drain Current (A) 2004/05/24 Preliminary 350 400 -75 -50 -25 0 25 50 75 100 125 150 TJ, Junction Temperature (oC) Champion Microelectronic Corporation Page 5 CMT60N03 N-CHANNEL Logic Level Power MOSFET Figure 12. Typical Threshold Voltage vs Junction Temperature 1.10 VGS(TH), Threshold Voltage (Normalized) BVDSS, Drain-to-Source Breakdown Voltage (Normalized) Figure 11. Typical Breakdown Voltage vs Junction Temperature 1.05 1.00 0.95 VGS = 0V ID = 250 µA 0.90 -75 -50 -25 0.0 25 50 75 TJ, Junction Temperature 100 125 1.2 VGS = VDS, ID = 250 µA 1.1 1.0 0.9 0.8 0.7 0.6 0.5 150 -75 10 µ DS(ON) 1 .0 10 m 10 DC mS S TJ = MAX RATED, TC = 25 oC Single Pulse 50 75 100 125 150 (oC) CISS VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≅ CDS + CGD COSS 1000 CRSS 100 1 10 1 100 0.1 1 10 100 VDS, Drain-to-Source Voltage (V) VDS, Drain Voltage (V) Figure 15. Typical Gate Charge vs Gate-to-Source Voltage Figure 16. Typical Body Diode Transfer Characteristics 12 10 8 6 4 VDS = 15V 2 ID = 12A 0 0 0.01 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 QG , Total Gate Charge (nC) 2004/05/24 Preliminary IDR, Reverse Drain Current (A) VGS, Gate-to-Source Voltage (V) 25 10000 S 100 µS 100 0.0 Figure 14. Typical Capacitance vs Drain-to-Source Voltage C, Capacitance (pF) ID, Drain Current (A) OPERATION IN THIS AREA MAY BE LIMITED BY R -25 TJ, Junction Temperature Figure 13. Maximum Forward Bias Safe Operating Area Area 1000 -50 (oC) 180 160 140 VGS = 0V 120 100 80 60 15 o 0 C o 40 25 C 20 0 o -55 0.4 0.6 0.8 1.0 C 1.2 1.4 1.6 VSD, Source-to-Drain Voltage (V) Champion Microelectronic Corporation Page 6 1.8 CMT60N03 N-CHANNEL Logic Level Power MOSFET PACKAGE DIMENSION TO-252 C B PIN 1: GATE PIN 2: DRAIN PIN 3: SOURCE E V R S A 4 2 3 U K 1 L J D H G TO-263 PIN 1: GATE PIN 2: DRAIN PIN 3: SOURCE C B 2 3 K 1 S A V E G J D 2004/05/24 Preliminary H Champion Microelectronic Corporation Page 7 CMT60N03 N-CHANNEL Logic Level Power MOSFET IMPORTANT NOTICE Champion Microelectronic Corporation (CMC) reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. A few applications using integrated circuit products may involve potential risks of death, personal injury, or severe property or environmental damage. CMC integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of CMC products in such applications is understood to be fully at the risk of the customer. In order to minimize risks associated with the customer’s applications, the customer should provide adequate design and operating safeguards. HsinChu Headquarter Sales & Marketing 5F-1, No. 11, Park Avenue II, Science-Based Industrial Park, HsinChu City, Taiwan T E L : +886-3-567 9979 F A X : +886-3-567 9909 11F, No. 306-3, SEC. 1, Ta Tung Road, Hsichih, Taipei Hsien 221, Taiwan 2004/05/24 Preliminary T E L : +886-2-8692 1591 F A X : +886-2-8692 1596 Champion Microelectronic Corporation Page 8