Rohm BR93L66RFV-WE2 High reliability serial eeproms high reliability sery Datasheet

High Reliability Serial EEPROMs
High Reliability Series
EEPROMs Microwire BUS
BR93L□□-W Series, BR93A□□-WM Series, BR93H□□-WC Series
No.11001EGT03
ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides a
failsafe method of data reliability, while a double reset function prevents data miswriting. In addition, gold pads and gold
wires are used for internal connections, pushing the boundaries of reliability to the limit.
BR93L□□-W Series are assort 1Kbit～16Kbit. BR93A□□-WM Series are possible to operate at 105℃ and are assorted
with 1K～16Kbit. BR93H□□-WC Series are possible to operate at 125℃, are assorted with 2K～16Kbit.
Contents
BR93L□□-W Series
BR93L46-W, BR93L56-W, BR93L66-W, BR93L76-W, BR93L86-W
BR93A□□-WM Series
BR93A46-WM, BR93A56-WM, BR93A66-WM, BR93A76-WM, BR93A86-WM
・・・・P2
BR93H□□-WC Series
BR93H56-WC, BR93H66-WC, BR93H76-WC, BR93H86-WC
・・・P22
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1/40
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Serial EEPROM Series
High Reliability Series
EEPROMs Microwire BUS
BR93L□□-W Series, 93A□□-WM Series
●Description
BR93L□□-W Series, BR93A□□-WM Series are serial EEPROM of serial 3-line interface method
●Features
1) 3-line communications of chip select, serial clock, serial data input / output (the case where input and output are shared)
2) Actions available at high speed 2MHz clock(2.5~5.5V)
3) Speed write available (write time 5ms max.）
4) Same package and pin layout from 1Kbit to 16Kbit
5) 1.8~5.5V (BR93L□□-W Series), 2.5～5.5V(BR93A□□-WM Series) single power source action
6) Address auto increment function at read action
7) Write mistake prevention function
Write prohibition at power on
Write prohibition by command code
Write mistake prevention function at low voltage
8) Program cycle auto delete and auto end function
9) Program condition display by READY / BUSY
10) Low current consumption
At write action (at 5V) : 1.2mA (Typ.)
At read action (at 5V) : 0.3mA (Typ.)
At standby action (at 5V) : 0.1μA (Typ.)(CMOS input)
11) TTL compatible( input / output s)
12) Compact package SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/TSSOP-B8J*1
13) Data retention for 40 years
14) Endurance up to 1,000,000 times
15) Data at shipment all addresses FFFFh
*1 Only SOP8, SOP-J8, TSSOP-B8, MSOP8 for BR93A□□-WM
●BR93L, BR93A Series
Package type
SOP8
SOP-J8
SSOP-B8
TSSOP-B8
MSOP8
TSSOP-B8J
FVT RFVT
RFVM
RFVJ
Bit format
Type
Power source
voltage
F
RF
FJ
RFJ
FV
RFV
1Kbit
64×16
BR93L46-W
1.8～5.5V
●
●
●
●
●
●
●
●
●
●
2Kbit
128×16
BR93L56-W
1.8～5.5V
●
●
●
●
●
●
●
●
●
●
4Kbit
256×16
BR93L66-W
1.8～5.5V
●
●
●
●
●
●
●
●
●
●
Capacity
8Kbit
512×16
BR93L76-W
1.8～5.5V
●
●
●
●
●
●
●
●
16Kbit
1K×16
BR93L86-W
1.8～5.5V
●
●
●
●
●
●
●
●
1Kbit
64×16
BR93A46-WM
2.5～5.5V
●
●
●
●
●
●
2Kbit
128×16
BR93A56-WM
2.5～5.5V
●
●
●
●
●
●
4Kbit
256×16
BR93A66-WM
2.5～5.5V
●
●
●
●
●
●
8Kbit
512×16
BR93A76-WM
2.5～5.5V
●
●
●
●
●
●
16Kbit
1K×16
BR93A86-WM
2.5～5.5V
●
●
●
●
●
●
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2/40
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
●Absolute Maximum Ratings(Ta=25℃,BR93L□□-W)
Parameter
Symbol
Impressed voltage
VCC
Limits
Unit
-0.3～+6.5
V
450 (SOP8) *1
450 (SOP-J8) *2
Permissible dissipation
300 (SSOP-B8) *3
Pd
mW
330 (TSSOP-B8) *4
310 (MSOP8) *5
310 (TSSOP-B8J) *6
Storage temperature range
Tstg
-65～+125
℃
Action temperature range
Topr
-40～+85
℃
‐
-0.3～VCC+0.3
V
Limits
Unit
Terminal voltage
* When using at Ta=25℃ or higher, 4.5mW(*1,*2), 3.0mW(*3) 3.3mW(*4),
3.1mW(*5, 6), to be reduced per 1℃.
●Absolute Maximum Ratings (Ta=25℃,BR93A□□-WM)
Parameter
Symbol
Impressed voltage
VCC
-0.3～+6.5
450 (SOP8)
Permissible
dissipation
V
*1
450 (SOP-J8) *2
Pd
mW
330 (TSSOP-B8) *3
310 (MSOP8) *4
Storage temperature range
Tstg
-65～+125
℃
Action temperature range
Topr
-40～+105
℃
‐
-0.3～VCC+0.3
V
Terminal voltage
* When using at Ta=25℃ or higher, 4.5mW(*1,*2), 3.3mW(*3), 3.1 mW(*4) to be reduced per 1℃.
●Memory cell characteristics (VCC=1.8～5.5V,BR93L□□-W)
Limit
Parameter
Endurance *1
Data retention
Unit
Condition
-
Times
Ta=25℃
-
Years
Ta=25℃
Unit
Condition
Min.
Typ.
Max.
1,000,000
-
40
-
*1
○Shipment data all address FFFFh
*1 Not 100% TESTED
●Memory cell characteristics (VCC=2.5～5.5V,BR93A□□-WM)
Limit
Parameter
Endurance *1
Data retention *1
Min.
Typ.
Max.
1,000,000
Times
100,000
40
-
-
10
-
-
Years
Ta≦25℃
Ta≦105℃
Ta≦25℃
Ta≦105℃
○Shipment data all address FFFFh
*1 Not 100% TESTED
●Recommended action conditions (BR93L□□-W)
Parameter
Power source voltage
Input voltage
●Recommended action conditions (BR93A□□-WM)
Parameter
Power source voltage
Input voltage
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Symbol
Limits
VCC
1.8～5.5
VIN
0～VCC
Symbol
Limits
VCC
2.5～5.5
VIN
0～VCC
3/40
Unit
V
Unit
V
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
●Electrical characteristics
(Unless otherwise specified, VCC=2.5～5.5V, Ta=-40～+85℃, BR93L□□-W, Ta=-40～+105℃, BR93A□□-WM)
Limits
Parameter
Symbol
Unit
Condition
Min.
Typ.
Max.
“L” input voltage 1
VIL1
-0.3
-
+0.8
V
4.0V≦VCC≦5.5V
“L” input voltage 2
VIL2
“H” input voltage 1
VIH1
-0.3
-
0.2 x VCC
V
VCC≦4.0V
2.0
-
VCC+0.3
V
4.0V≦VCC≦5.5V
“H” input voltage 2
“L” output voltage 1
VIH2
0.7 x VCC
-
VCC+0.3
V
VCC≦4.0V
VOL1
0
-
0.4
V
IOL=2.1mA, 4.0V≦VCC≦5.5V
“L” output voltage 2
VOL2
0
-
0.2
V
IOL=100μA
“H” output voltage 1
“H” output voltage 2
VOH1
2.4
-
VCC
V
IOH=-0.4mA, 4.0V≦VCC≦5.5V
VOH2
VCC-0.2
-
VCC
V
IOH=-100μA
Input leak current
ILI
-1
-
+1
µA
VIN=0V～VCC
Output leak current
ILO
-1
-
+1
µA
VOUT=0V～VCC, CS=0V
ICC1
-
-
3.0
mA
fSK=2MHz, tE/W=5ms (WRITE)
ICC2
-
-
1.5
mA
fSK=2MHz (READ)
ICC3
-
-
4.5
mA
fSK=2MHz, tE/W=5ms (WRAL, ERAL)
ISB
-
-
2
µA
CS=0V, DO=OPEN
Current consumption
at action
Standby current
◎Radiation resistance design is not made.
(Unless otherwise specified, VCC=1.8～2.5V, Ta=-40～+85℃, BR93L□□-W)
Limits
Parameter
Symbol
Unit
Min.
Typ.
Max.
“L” input voltage
VIL
-0.3
-
0.2 x VCC
V
“H” input voltage
VIH
0.7 x VCC
-
VCC+0.3
V
Condition
“L” output voltage
VOL
0
-
0.2
V
IOL=100μA
“H” output voltage
VOH
VCC-0.2
-
VCC
V
IOH=-100μA
Input leak current
ILI
-1
-
+1
μA
VIN=0V～VCC
Output leak current
ILO
-1
-
+1
μA
VOUT=0V～VCC, CS=0V
ICC1
-
-
1.5
mA
fSK=500kHz, tE/W=5ms (WRITE)
ICC2
-
-
0.5
mA
fSK=500kHz (READ)
ICC3
-
-
2
mA
fSK=500kHz, tE/W=5ms (WRAL, ERAL)
ISB
-
-
2
μA
CS=0V, DO=OPEN
Current consumption
at action
Standby current
◎Radiation resistance design is not made.
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2011.09 - Rev.G
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
●Action timing characteristics
(BR93L□□-W, Ta=-40～+85℃, VCC=2.5～5.5V, BR93A□□-WM, Ta=-40～+105℃, VCC=2.5～5.5V)
2.5V≦VCC≦5.5V
Parameter
Symbol
Unit
Min.
Typ.
Max.
SK frequency
fSK
2
MHz
SK “H” time
tSKH
230
ns
SK “L” time
tSKL
230
ns
CS “L” time
tCS
200
ns
CS setup time
tCSS
50
ns
DI setup time
tDIS
100
ns
CS hold time
tCSH
0
ns
DI hold time
tDIH
100
ns
Data “1” output delay time
tPD1
200
ns
Data “0” output delay time
tPD0
200
ns
Time from CS to output establishment
tSV
150
ns
Time from CS to High-Z
tDF
150
ns
Write cycle time
tE/W
5
ms
(BR93L□□-W, Ta=-40～+85℃, VCC=1.8～2.5V)
Parameter
Symbol
SK frequency
SK “H” time
SK “L” time
CS “L” time
CS setup time
DI setup time
CS hold time
DI hold time
Data “1” output delay time
Data “0” output delay time
Time from CS to output establishment
Time from CS to High-Z
Write cycle time
Min.
0.8
0.8
1
200
100
0
100
-
fSK
tSKH
tSKL
tCS
tCSS
tDIS
tCSH
tDIH
tPD1
tPD0
tSV
tDF
tE/W
1.8V≦VCC≦2.5V
Typ.
Max.
500
0.7
0.7
0.7
200
5
Unit
kHz
us
us
us
ns
ns
ns
ns
us
us
us
ns
ms
●Sync data input / output timing
CS
tCSS
tSKH
tSKL
tCSH
SK
tDIS
tDI H
DI
tPD1
t PD0
DO(READ)
tDF
DO(WRITE)
STATUS VALID
Fig.1 Sync data input / output timing
○Data is taken by DI sync with the rise of SK.
○At read action, data is output from DO in sync with the rise of SK.
○The status signal at write (READY / BUSY) is output after tCS from the fall of CS after write command input, at the area
DO where CS is “H”, and valid until the next command start bit is input. And, while CS is “L”, DO becomes High-Z.
○After completion of each mode execution, set CS “L” once for internal circuit reset, and execute the following action mode.
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5/40
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
●BR93L□□-W Characteristic data (The following characteristic data are Typ. values.)
Fig.2 H output voltage VIH(CS,SK,DI)
Fig.3 H input voltage VIL(CS,SK,DI)
Fig.4
L output voltage VOL-IOL(Vcc=1.8V)
Fig.5 L output voltage VOL-IOL(Vcc=2.5V)
Fig.6 L output voltage VOL-IOL(Vcc=4.0V)
Fig.7 H output voltage VOH-IOH(Vcc=1.8V)
Fig.8 H output voltage VOH-IOH(Vcc=2.5V)
Fig.9 H output voltage VOH-IOH(Vcc=4.0V)
Fig.10
Fig.11 Output leak current ILO (DO)
Fig.14
Consumption current at WRAL action
ICC3 (WRAL, fSK=2MHz)
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Fig.12
Input leak current ILI(CS,SK,DI)
Current consumption at WRITE action
ICC1 (WRITE, fSK=2MHz)
Fig.13 Consumption current at READ action
Fig.15 Current consumption at WRITE action
Fig.16 Consumption current at READ action
ICC1 (WRITE, fSK=500kHz)
ICC2 (READ, fSK=500kHz)
6/40
ICC2 (READ, fSK=2MHz)
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
●BR93L□□-W
Fig.17
Characteristic data (The following characteristic data are Typ. values.)
Consumption current at WRAL action
ICC3 (WRAL, fSK=500kHz)
Fig.20
SK high time tSKH
Fig.23
CS hold time tCSH
Fig.26
DI setup time tDIS
Fig.29 Time from CS to output establishment tSV
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Fig.18
Consumption current at standby action ISB
Fig.21
Fig.24
Fig.27
Fig.19 SK frequency fSK
SK low time tSKL
Fig.22
CS low time tCS
CS setup time tCSS
Fig.25
DI hold time tDIH
Data “0” output delay time tPD0
Fig.30 Time from CS to High-Z tDF
7/40
Fig.28
Output data “1” delay time tPD1
Fig.31 Write cycle time tE/W
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
●BR93A□□-WM
Characteristic data (The following characteristic data are Typ. values.)
Fig.32 H output voltage VIH(CS,SK,DI)
Fig.35 L output voltage VOL-IOL(Vcc=4.0V)
Fig.38 Input leak current ILI(CS,SK,DI)
Fig.33 H input voltage VIL(CS,SK,DI)
Fig.36
H output voltage VOH-IOH(Vcc=2.5V)
Fig.39 Output leak current ILO(DO)
Fig.34
L output voltage VOL-IOL(Vcc=2.5V)
Fig.37 H output voltage VOH-IOH(Vcc=4.0V)
Fig.40
Current consumption at WRITE action
Icc1(WRITE, fSK=2MHz)
Fig.41 Consumption current at READ action
Icc2(READ, fSK=2MHz)
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Fig.42
Consumption current at WRAL action
Fig.43
Consumption current at standby action ISB
Icc3(WRAL, fSK=2MHz)
8/40
2011.09 - Rev.G
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
●BR93A□□-WM
Technical Note
Characteristic data (The following characteristic data are Typ. values.)
Fig.44 SK
SK frequency fSK
Fig.45 SK
SK high
high time
time tSKH
tSKH
Fig.46 SK low time tSKL
Fig.47 CS low time tCS
Fig.48 CS hold time
time tCSH
tCSH
Fig.49 CS setup time tCSS
Fig.50 DI hold time tDIH
Fig.53 Output
Output data
data “1”
“1” delay
delay time
time tPD1
tPD1
Fig.51 DI
DI setup
setup time
time tDIS
tDIS
Fig.54 Time
Time from CS to output establishment tSV
Fig.52 Data
Data “0”
“0” output
output delay
delay time
time tPD0
tPD0
Fig.55 Time
Time from
from CS
CS to
to High-Z
High-Z tDF
tDF
Fig.56 Write cycle time tE/W
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9/40
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
●Block diagram
CS
Power source voltage detection
Command decode
Control
SK
Clock generation
6bit
7bit
8bit
9bit
10bit
Address
buffer
Command
register
DI
High voltage occurrence
Write
prohibition
Data
register
Address
decoder
16bit
6bit
7bit
8bit
9bit
10bit
R/W
amplifier
16bit
1,024 bit
2,048 bit
4,096 bit
8,192 bit
16,384 bit
EEPROM
Dummy bit
DO
Fig.57 Block diagram
●Pin assignment and function
NC
GND
DO
DI
Vcc
NC
NC
GND
BR93LXXRF-W/AXXRF-WM:SOP8
BR93LXXF-W/AXXF-WM:SOP8
BR93LXXRFJ-W/AXXRFJ-WM:SOP-J8
BR93LXXFJ-W/AXXFJ-WM:SOP-J8
BR93LXXRFV-W:SSOP-B8
BR93LXXFV-W:SSOP-B8*
BR93LXXRFVT-W/AXXRFVT-WM:TSSOP-B8
BR93LXXFVT-W:TSSOP-B8*
BR93LXXRFVM-W/AXXRFVM-WM:MSOP8
BR93LXXRFVJ-W:TSSOP-B8J
NC
Vcc
CS
SK
CS
SK
DI
DO
*BR93L46/56/66-W
Fig.58 Pin assignment diagram
Pin name
VCC
GND
CS
SK
DI
DO
NC
I/O
Input
Input
Input
Output
-
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Function
Power source
All input / output reference voltage, 0V
Chip select input
Serial clock input
Start bit, ope code, address, and serial data input
Serial data output, READY / BUSY internal condition display output
Non connected terminal, Vcc, GND or OPEN
10/40
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
●Description of operations
Communications of the Microwire Bus are carried out by SK (serial clock), DI (serial data input),DO (serial data output) ,and
CS (chip select) for device selection.
When to connect one EEPROM to a microcontroller, connect it as shown in Fig.59(a) or Fig.59(b). When to use the input and
output common I/O port of the microcontroller, connect DI and DO via a resistor as shown in Fig.59(b) (Refer to pages
17/35.), and connection by 3 lines is available.
In the case of plural connections, refer to Fig. 59 (c).
Microcontroller
BR93LXX
/AXX
CS
SK
SK
SK
SK
DO
DI
DO
DI
DI
DO
CS3
CS1
CS0
SK
DO
DI
DO
Fig.59-(a) Connection by 4 lines
Fig.59-(b) Connection by 3 lines
CS
SK
DI
DO
Microcontroller
CS
CS
SK
DI
DO
BR93LXX
/AXX
CS
CS
SK
DI
DO
Microcontroller
CS
Device 1
Device 2
Device 3
Fig.59-(c) Connection example of plural devices
Fig.59 Connection method with microcontroller
Communications of the Microwire Bus are started by the first “1” input after the rise of CS. This input is called a start bit. After
input of the start bit, input ope code, address and data. Address and data are input all in MSB first manners.
“0” input after the rise of CS to the start bit input is all ignored. Therefore, when there is limitation in the bit width of PIO of the
microcontroller, input “0” before the start bit input, to control the bit width.
●Command mode
Start
Command
Ope
Address
BR93L56/66-W
BR93A56/66-WM
BR93L76/86-W
BR93A76/86-WM
A7,A6,A5,A4,A3,A2,A1,A0
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
bit
code
BR93L46-W
BR93A46-WM
1
10
A5,A4,A3,A2,A1,A0
1
00
1
01
1
00
0
1
****
0
1
******
0
1
********
Write disable (WDS)
1
00
0
0
****
0
0
******
0
0
********
Erase (ERASE)
1
11
Read (READ)
*1
Write enable (WEN)
Write (WRITE)
Write all (WRAL)
*2
*2
1
1
****
A5,A4,A3,A2,A1,A0
A5,A4,A3,A2,A1,A0
1
1
******
A7,A6,A5,A4,A3,A2,A1,A0
A7,A6,A5,A4,A3,A2,A1,A0
1
1
Data
D15~D0(READ DATA)
********
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
D15~D0(WRITE DATA)
D15~D0(WRITE DATA)
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
Chip erase (ERAL)
1
00
1 0 ****
1 0 ******
1 0 ********
・ Input the address and the data in MSB first manners.
A7 of BR93L56-W/A56-WM becomes Don't Care.
・ As for *, input either VIH or VIL.
A9 of BR93L76-W/A76-WM becomes Don't Care.
*Start bit
Acceptance of all the commands of this IC starts at recognition of the start bit.
The start bit means the first “1” input after the rise of CS.
*1 As for read, by continuous SK clock input after setting the read command, data output of the set address starts, and
address data in significant order are sequentially output continuously. (Auto increment function)
*2 When the read and the write all commands are executed, data written in the selected memory cell is automatically deleted, and input data is written.
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11/40
2011.09 - Rev.G
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
●Timing chart
1) Read cycle (READ)
～
～
～
～
～
～
CS
～
～
*1
1
4
n
～
～
DI
2
～
～
1
n+1
～
～
SK
Am
0
A1
～
～
1
A0
～
～
～
～
*2
BR93L46-W/A46-WM : n=25, m=5
BR93L56-W/A56-WM
: n=27, m=7
BR93L66-W/A66-WM
BR93L76-W/A76-WM
: n=29, m=9
BR93L86-W/A86-WM
～
～
D14
D1
D0
D15 D14
～
～
D15
～
～
0
DO
High-Z
*1 Start bit
When data “1” is input for the first time after the rise of CS, this is recognized as a start bit. And when “1” is input after plural “0” are input, it is recognized as a
start bit, and the following operation is started. This is common to all the commands to described hereafter.
Fig. 60 Read cycle
○When the read command is recognized, input address data (16bit) is output to serial. And at that moment, at taking A0, in
sync with the rise of SK, “0” (dummy bit) is output. And, the following data is output in sync with the rise of SK.
This IC has an address auto increment function valid only at read command. This is the function where after the above read
execution, by continuously inputting SK clock, the above address data is read sequentially. And, during the auto increment,
keep CS at “H”.
2) Write cycle (WRITE)
～
～
～
～
～
～
tCS
CS
～
～
A1
A0
D15
D14
D1
D0
～
～
Am
～
～
1
～
～
0
～
～
1
n
4
～
～
DI
2
～
～
1
～
～
～
～
SK
STATUS
tSV
BR93L46-W/A46-WM : n=25, m=5
BR93L56-W/A56-WM
: n=27, m=7
BR93L66-W/A66-WM
BR93L76-W/A76-WM
: n=29, m=9
BR93L86-W/A86-WM
BUSY READY
～
～
DO
High-Z
tE/W
Fig.61 Write cycle
○In this command, input 16bit data (D15~D0) are written to designated addresses (Am~A0). The actual write starts by the fall
of CS of D0 taken SK clock.
When STATUS is not detected, (CS=”L” fixed) Max. 5ms in conformity with tE/W, and when STATUS is detected (CS=”H”),
all commands are not accepted for areas where “L” (BUSY) is output from D0, therefore, do not input any command.
3) Write all cycyle (WRAL)
～
～
～
～
～
～
tCS
CS
1
D15
D14
D1
D0
～
～
0
～
～
0
～
～
0
～
～
1
～
～
DI
n
5
～
～
2
～
～
1
～
～
～
～
SK
STATUS
～
～
～
～
tSV
BR93L46-W/A46-WM : n=25
BR93L56-W/A56-WM
: n=27
BR93L66-W/A66-WM
BR93L76-W/A76-WM
: n=29
BR93L86-W/A86-WM
BUSY READY
～
～
DO
High-Z
Fig.62 Write all cycle
tE/W
○In this command, input 16bit data is written simultaneously to all adresses. Data is not written continuously per one word
but is written in bulk, the write time is only Max. 5ms in conformity with tE/W.
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12/40
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
4) Write enable (WEN) / disable (WDS) cycle
～
～
CS
2
1
3
4
5
6
7
8
～
～
SK
1
0
BR93L46-Ｗ/A46-WM : n=9
BR93L56-W/A56-WM
: n=11
BR93L66-W/A66-WM
BR93L76-W/A76-WM
: n=13
BR93L86-W/A86-WM
0
～
～
DI
n
～
～
ENABLE=1 1
DISABLE=0 0
DO
High-Z
Fig.63 Write enable (WEN) / disable (WDS) cycle
○ At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is
necessary to execute the write enable command. And, once this command is executed, it is valid unitl the write disable
command is executed or the power is turned off. However, the read command is valid irrespective of write enable / diable
command. Input to SK after 6 clocks of this command is available by either “H” or “L”, but be sure to input it.
○ When the write enable command is executed after power on, write enable status gets in. When the write disable command
is executed then, the IC gets in write disable status as same as at power on, and then the write command is canceled
thereafter in software manner. However, the read command is executable. In write enable status, even when the write
command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the write disable
command after completion of write.
5) Erase cycle timing (ERASE)
～
～
～
～
STATUS
～
～
～
～
1
～
～
DI
n
4
2
～
～
1
～
～
SK
A3
A2
A1
A0
BR93L46-W/A46-WM : n=9, m=5
BR93L56-W/A56-WM
: n=11, m=7
BR93L66-W/A66-WM
BR93L76-W/A76-WM
: n=13, m=9
BR93L86-W/A86-WM
～
～
tSV
～
～
BUSY READY
～
～
DO
～
～
Am
～
～
1
～
～
1
～ ～
～
～
tCS
CS
High-Z
tE/W
Fig.64 Erase cycle timing
○In this command, data of the designated address is made into “1”. The data of the designated address becomes “FFFFh”.
Actual ERASE starts at the fall of CS after the fall of A0 taken SK clock.
In ERASE, status can be detected in the same manner as in WRITE command.
6) Chip erase cycle timing (ERAL)
～
～
～
～
STATUS
0
tSV
～
～
1
BR93L46-W/A46-WM : n=9
BR93L56-W/A56-WM
: n=11
BR93L66-W/A66-WM
BR93L76-W/A76-WM
: n=13
BR93L86-W/A86-WM
BUSY READY
～
～
DO
0
～
～
0
～
～
1
n
～
～
DI
4
～
～
2
～
～
～
～
1
～
～
SK
～
～
tCS
CS
High-Z
tE/W
Fig.65 Chip erase cycle timing
○In this command, data of all addresses is erased. Data of all addresses becomes ”FFFFh”.
Actual ERASE starts at the fall of CS after the falll of the n-th clock from the start bit input.
In ERAL, status can be detected in the same manner as in WRITE command.
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13/40
2011.09 - Rev.G
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
●Application
1) Method to cancel each command
○READ
Start bit
1bit
Ope code
Address
2bit
6bit
*1
Data
(In the case of BR93L46-W/A46-WM)
16bit
＊1 Address is 8 bits in BR93L56-W/A56-WM, BR93L-66W/A66-WM
Address is 10 bits in BR93L76-W/A76-WM, BR93L86-W/A86-WM
Cancel is available in all areas in read mode.
・Method to cancel：cancel by CS=“L”
Fig.66 READ cancel available timing
○WRITE, WRAL
・25 Rise of clock
SK
DI
24
D1
*2
25
D0
Enlarged figure
Start bit
1bit
Ope code
Address
2bit
*1
Data
6bit
tE/W
(In the case of BR93L46-W/A46-WM)
16bit
a
b
a：From start bit to 25 clock rise＊2
Cancel by CS=“L”
*1
Address is 8 bits in BR93L56-W/A56-WM, BR93L66-W/A66-WM
Address is 10 bits in BR93L76-W/A76-WM BR93L86-W/A86-WM
*2 27 clocks in BR93L56-W/A56-WM, BR93L66-W/A66-WM
29 clocks in BR93L76-W/A76-WM BR93L86-W/A86-WM
b：25 clock rise and after＊2
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
And when SK clock is input continuously, cancellation is not available.
29 Rise of clock
*2
SK
30
DI
28
D1
29
31
D0
b
c
a
Enlarged figure
Start bit
1bit
Address *1
Ope code
2bit
10bit
Data
tE/W
(In the case of BR93L86-W/A86-WM)
16bit
a
b
c
a：From start bit to 29 clock rise
Cancel by CS=“L”
b：29 clock rise and after
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
c：30 clock rise and after
Cancel by CS=“L”
However, when write is started in b area (CS is ended), cancellation is not
available by any means.
And when SK clock is output continuously is not available.
Note 1) If Vcc is made OFF in this area, designated address data is
not guaranteed, therefore write once again.
Note 2) If CS is started at the same timing as that of the SK rise,
write execution/cancel becomes unstable, therefore, it is
recommended to fail in SK=”L” area.
As for SK rise, recommend timing of tCSS/tCSH or higher.
Fig.67 WRITE, WRAL cancel available timing
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2011.09 - Rev.G
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
9 Rise of clock＊2
○ERASE, ERAL
SK
8
9
A1
DI
A0
Enlarged figure
Start bit
1bit
Ope code
Address
2bit
6bit
*1
1/2
tE/W
(In the case of BR93L46-W/A46-WM)
b
a
＊1 Address is 8 bits in BR93L56-W/A56-WM, BR93L66-W/A66-WM
Address is 10 bits in BR93L76-W/A76-WM
a：From start bit to 9 clock rise＊2
Cancel by CS=“L”
b：9 clock rise and after＊2
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
And when SK clock is input continuously, cancellation is not available.
＊2 11 clocks in BR93L56-W/A56-WM, BR93L66-W/A66-WM
13 clocks in BR93L76-W/A76-WM
13 Rise of clock
SK
12
DI
1bit
Ope code
2bit
Address
*1
15
b
c
Enlarged figure
tE/W
(In the case of BR93L86-W/A86-WM)
10bit
b
a
14
D1
a
Start bit
13
*2
c
a：From start bit to 13 clock rise
Cancel by CS=“L”
b：13 clock rise and after
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
c：14 clock rise and after
Cancel by CS=“L”
However, when write is started in b area (CS is ended), cancellation is not
available by any means.
And when SK clock is output continuously is not available.
Note 1) If Vcc is made OFF in this area, designated address data is
not guaranteed, therefore write once again.
Note 2) If CS is started at the same timing as that of the SK rise,
write execution/cancel becomes unstable, therefore, it is
recommended to fail in SK=”L” area.
As for SK rise, recommend timing of tCSS/tCSH or higher.
Fig.68 ERASE, ERAL cancel available timing
2) At standby
○Standby current
When CS is “L”, SK input is “L”, DI input is “H”, and even with middle electric potential, current does not increase.
○Timing
As shown in Fig.69, when SK at standby is “H”, if CS is started, DI status may be read at the rise edge.
At standby and at power ON/OFF, when to start CS, set SK input or DI input to “L” status. (Refer to Fig.70)
If CS is started when SK=”L” or DI=”L”, a start
bit is recognized correctly.
CS=SK=DI=”H”
Wrong recognition as a start bit
CS
CS
Start bit input
SK
SK
DI
DI
Fig.70 Normal action timing
Fig.69 Wrong action timing
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Start bit input
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2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
3) Equivalent circuit
Output circuit
Input citcuit
RESET int.
CSint.
CS
DO
OEint.
Fig.72 Input circuit (CS)
Fig.71 Output circuit (DO)
Input circuit
Input circuit
CS int.
CS int.
DI
SK
Fig.73 Input circuit (DI)
Fig.74 Input circuit (SK)
4) I/O peripheral circuit
4-1) Pull down CS.
By making CS=“L” at power ON/OFF, mistake in operation and mistake write are prevented.
○Pull down resistance Rpd of CS pin
To prevent mistake in operation and mistake write at power ON/OFF, CS pull down resistance is necessary. Select an
appropriate value to this resistance value from microcontroller VOH, IOH, and VIL characteristics of this IC.
Rpd ≧
Microcontroller
VOHM
“H” output
VOHM ≧
EEPROM
Rpd
IOHM
VIHE
・・・①
・・・②
Example) When VCC =5V, VIHE=2V, VOHM=2.4V, IOHM=2mA,
from the equation ①,
VIHE
IOHM
VOHM
Rpd ≧
“L” input
∴
Rpd ≧
2.4
-3
2×10
1.2 [kΩ]
With the value of Rpd to satisfy the above equation, VOHM becomes
2.4V or higher, and VIHE (=2.0V), the equation ② is also satisfied.
Fig.75 CS pull down resistance
・VIHE
: EEPROM VIH specifications
・VOHM : Microcontroller VOH specifications
・IOHM : Microcontroller IOH specifications
4-2) DO is available in both pull up and pull down.
Do output become “High-Z” in other READY / BUSY output timing than after data output at read command and write
command. When malfunction occurs at “High-Z” input of the microcontroller port connected to DO, it is necessary to
pull down and pull up DO. When there is no influence upon the microcontroller actions, DO may be OPEN.
If DO is OPEN, and at timing to output status READY, at timing of CS=“H”, SK=“H”, DI=“H”, EEPROM recognizes this
as a start bit, resets READY output, and DO=”High-Z”, therefore, READY signal cannot be detected. To avoid such
output, pull up DO pin for improvement.
CS “H”
CS
SK
SK
Enlarged
DI
D0
DI
High-Z
READY
DO BUSY
DO
BUSY
High-Z
CS=SK=DI=”H”
When DO=OPEN
Improvement by DO pull up
DO
READY
BUSY
CS=SK=DI=”H”
When DO=pull up
Fig.76 READY output timing at DO=OPEN
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2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
○Pull up resistance Rpu and pull down resistance Rpd of DO pin
As for pull up and pull down resistance value, select an appropriate value to this resistance value from microcontroller
VIH, VIL, and VOH, IOH, VOL, IOL characteristics of this IC.
Microcontroller
Rpu ≧
EEPROM
Rpu
VILM
VOLE ≦
IOLE
VOLE
Vcc－VOLE
・・・③
IOLE
・・・④
VILM
Example) When VCC =5V, VOLE=0.4V, IOLE=2.1mA, VILM=0.8V,
from the equation ③,
“L” input
Rpu ≧
“L” output
∴
Rpu ≧
5－0.4
-3
2.1×10
2.2 [kΩ]
With the value of Rpu to satisfy the above equation, VOLE becomes 0.4V
or below, and with VILM(=0.8V), the equation ④ is also satisfied.
Fig.77 DO pull up resistance
・VOLE
・IOLE
・VILM
Rpd ≧
EEPROM
Microcontroller
VOHE ≧
VIHM
Rpd
IOHE
VOHE
・・・⑤
IOHE
・・・⑥
VIHM
Example) When VCC =5V, VOHE=Vcc－0.2V, IOHE=0.1mA,
VIHM=Vcc×0.7V from the equation ⑤,
VOHE
“H” input
: EEPROM VOL specifications
: EEPROM IOL specifications
: Microcontroller VIL specifications
“H” output
Rpd ≧
∴
Rpd ≧
5－0.2
-3
0.1×10
48 [kΩ]
With the value of Rpd to satisfy the above equation, VOHE becomes 2.4V
or below, and with VIHM (=3.5V), the equation ⑥ is also satisfied.
Fig.78 DO pull down resistance
・VOHE
・IOHE
・VIHM
: EEPROM VOH specifications
: EEPROM IOH specifications
: Microcontroller VIH specifications
5) READY / BUSY status display (DO terminal)
(common to BR93L46-W/A46-WM,BR93L56-W/A56-WM, BR93L66-W/A66-WM, BR93L76-W/A76-WM, BR93L86-W/A86-WM)
This display outputs the internal status signal. When CS is started after tCS (Min.200ns)
from CS fall after write command input, “H” or “L” is output.
R/B display＝“L” (BUSY) = write under execution
After the timer circuit in the IC works and creates the period of tE/W, this time circuit completes automatically.
And write to the memory cell is made in the period of tE/W, and during this period, other command is not accepted.
（DO status）
R/B display = “H” (READY) = command wait status
（DO status） Even after tE/W (max.5ms) from write of the memory cell, the following command is accepted.
Therefore, CS=“H” in the period of tE/W, and when input is in SK, DI, malfunction may occur, therefore, DI=“L” in the area
CS=“H”. (Especially, in the case of shared input port, attention is required.)
*Do not input any command while status signal is output. Command input in BUSY area is cancelled, but command input in READY area is accepted.
Therefore, status READY output is cancelled, and malfunction and mistake write may be made.
STATUS
CS
SK
CLOCK
DI
WRITE
INSTRUCTION
DO
tSV
High-Z
READY
BUSY
Fig.79 R/B status output timing chart
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2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
6) When to directly connect DI and DO
This IC has independent input terminal DI and output terminal DO, and separate signals are handled on timing chart,
meanwhile, by inserting a resistance R between these DI and DO terminals, it is possible to carry out control by 1 control line.
Microcontroller
EEPROM
DI/O PORT
DI
R
DO
Fig.80 DI, DO control line common connection
○Data collision of microcontroller DI/O output and DO output and feedback of DO output to DI input.
Drive from the microcontroller DI/O output to DI input on I/O timing, and signal output from DO output occur at the same
time in the following points.
(1) 1 clock cycle to take in A0 address data at read command
Dummy bit “0” is output to DO terminal.
→When address data A0 = “1” input, through current route occurs.
EEPROM CS input
“H”
EEPROM SK input
A1
EEPROM DI input
A0
Collision of DI input and DO output
EEPROM DO output
0
High-Z
Microcontroller DI/O port
A1
D15 D14 D13
A0
Microcontroller output
High-Z
Microcontroller input
Fig.81 Collision timing at read data output at DI, DO direct connection
(2) Timing of CS = “H” after write command. DO terminal in READY / BUSY function output.
When the next start bit input is recognized, “HIGH-Z” gets in.
→Especially, at command input after write, when CS input is started with microcontroller DI/O output “L”,
READY output “H” is output from DO terminal, and through current route occurs.
Feedback input at timing of these (1) and (2) does not cause disorder in basic operations, if resistance R is inserted.
～
～
EEPROM SK input
Write command
EEPROM DI input
Write command
EEPROM DO output
Write command
～
～
Write command
～
～
EEPROM CS input
～
～
～
～
～
～
READY
～
～
～
～
BUSY
READY
High-Z
Collision of DI input and DO output
BUSY
Microcontroller output
Microcontroller input
～
～
READY
Write command
～
～
Microcontroller DI/O port
Microcontroller output
Fig.82 Collision timing at DI, DO direct connection
Note) As for the case (2), attention must be paid to the following.
When status READY is output, DO and DI are shared, DI=”H” and the microcontroller DI/O=”High-Z” or the microcontroller DI/O=”H”,if SK clock is
input, DO output is input to DI and is recognized as a start bit, and malfunction may occur. As a method to avoid malfunction, at status READY
output, set SK=“L”, or start CS within 4 clocks after “H” of READY signal is output.
Start bit
CS
Because DI=”H”, set
SK=”L” at CS rise.
SK
DI
READY
DO
High-Z
Fig.83 Start bit input timing at DI, DO direct connection
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2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
○Selection of resistance value R
The resistance R becomes through current limit resistance at data collision. When through current flows, noises of
power source line and instantaneous stop of power source may occur. When allowable through current is defined as I,
the following relation should be satisfied. Determine allowable current amount in consideration of impedance and so
forth of power source line in set. And insert resistance R, and set the value R to satisfy EEPROM input level VIH/VIL
even under influence of voltage decline owing to leak current and so forth. Insertion of R will not cause any influence
upon basic operations.
(1) Address data A0 = “1” input, dummy bit “0” output timing
(When microcontroller DI/O output is “H”, EEPROM DO outputs “L”, and “H” is input to DI)
・Make the through current to EEPROM 10mA or below.
・See to it that the level VIH of EEPROM should satisfy the following.
Conditions
Microcontroller
VOHM ≦ VIHE
EEPROM
VOHM ≦ IOHM×R + VOLE
DI/O PORT
At this moment, if VOLE=0V,
DI
VOHM ≦ IOHM×R
VOHM
“H” output
R
IOHM
∴
DO
R ≧
VOHM
IOHM
・・・⑦
VOLE
・VIHE
・VOLE
・VOHM
・IOHM
“L” output
Fig.84
: EEPROM VIH specifications
: EEPROM VOL specifications
: Microcontroller VOH specifications
: Microcontroller IOH specifications
Circuit at DI, DO direct connection (Microcontroller DI/O “H” output, EEPROM “L” output)
(2) DO status READY output timing
(When the microcontroller DI/O is “L”, EEPROM DO output “H”, and “L” is input to DI)
・Set the EEPROM input level VIL so as to satisfy the following.
Conditions
Microcontroller
“L” output
VOLM ≧ VILE
EEPROM
DI/O PORT
DI
VOLM ≧ VOHE – IOLM×R
VOLM
As this moment, VOHE=Vcc
VOLM ≧ Vcc – IOLM×R
R
IOHM
DO
VOHE
Vcc – VOLM
∴
IOLM
“H” output
・VILE
・VOHE
・VOLM
・IOLM
・・・⑧
: EEPROM VIL specifications
: EEPROM VOH specifications
: Microcontroller VOL specifications
: Microcontroller IOL specifications
Example) When Vcc=5V, VOHM=5V, IOHM=0.4mA, VOLM=5V, IOLM=0.4mA,
From the equation ⑦,
R ≧
R ≧
From the equation⑧,
VOHM
R ≧
IOHM
IOLM
5
5 – 0.4
R ≧
-3
0.4×10
∴
R ≧
Vcc – VOLM
12.5 [kΩ]
-3
2.1×10
・・・⑨
∴
R ≧
2.2 [kΩ]
・・・⑩
Therefore, from the equations ⑨ and ⑩,
∴
R ≧
12.5 [kΩ]
Fig.85 Circuit at DI, DO direct connection (Microcontroller DI/O “L” output, EEPROM “H” output)
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2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
7) Notes on power ON/OFF
・At power ON/OFF, set CS “L”.
When CS is “H”, this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may
cause malfunction, mistake write or so. To prevent these, at power ON, set CS “L”. (When CS is in “L” status, all inputs
are cancelled.) And at power decline, owing to power line capacity and so forth, low power status may continue long. At
this case too, owing to the same reason, malfunction, mistake write may occur, therefore, at power OFF too, set CS “L”.
VCC
VCC
GND
VCC
CS
GND
Bad example
Good example
Fig.86 Timing at power ON/OFF
（Bad example）CS pin is pulled up to Vcc.
（Good example）It is “L” at power ON/OFF.
In this case, CS becomes “H” (active status), and EEPROM may have malfunction,
mistake write owing to noise and the likes.
Even when CS input is High-Z, the status becomes like this case, which please note.
Set 10ms or higher to recharge at power OFF.
When power is turned on without observing this condition,
IC internal circuit may not be reset, which please note.
○POR citcuit
This IC has a POR (Power On Reset) circuit as a mistake write countermeasure. After POR action, it gets in write
disable status. The POR circuit is valid only when power is ON, and does not work when power is OFF. However, if CS is
“H” at power ON/OFF, it may become write enable status owing to noises and the likes. For secure actions, observe the
follwing conditions.
1. Set CS=”L”
2. Turn on power so as to satisfy the recommended conditions of tR, tOFF, Vbot for POR circuit action.
tR
VCC
Recommended conditions of tR, tOFF, Vbot
tR
tOFF
10m s or below
Vbot
V bot
100m s or below 10m s or higher 0.2V or below
0
○LVCC circuit
t O FF
10m s or higher 0.3V or below
Fig.87 Rise waveform diagram
LVCC (VCC-Lockout) circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ.=1.2V) or below, it prevent data rewrite.
8) Noise countermeasures
○VCC noise (bypass capacitor)
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a by pass capacitor (0.1μF) between IC VCC and GND, At that moment, attach it as close to IC
as possible.And, it is also recommended to attach a bypass capacitor between board VCC and GND.
○SK noise
When the rise time (tR) of SK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock
bit displacement.To avoid this, a Schmitt trigger circuit is built in SK input. The hysteresis width of this circuit is set about
0.2V, if noises exist at SK input, set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time
(tR) of SK 100ns or below. In the case when the rise time is 100ns or higher, take sufficient noise countermeasures.
Make the clock rise, fall time as small as possible.
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2011.09 - Rev.G
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
●Note ofn use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in
consideration of static characteristics and transition characteristics and fluctuations of external parts and our IC.
(3) Absolute Maximum Ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, IC
may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear
exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to IC.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is not lower than that
of GND terminal in consideration of transition status.
(5) Heat design
In consideration of allowable loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package IC onto a board, pay sufficient attention to IC direction and displacement. Wrong packaging may
destruct IC. And in the case of shortcircuit between IC terminals and terminals and power source, terminal and GND
owing to foreign matter, IC may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently
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21/40
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Serial EEPROM Series
High Reliability Series
EEPROMs Microwire BUS
BR93H□□-WC Series
●Description
BR93H□□-WC Series is a serial EEPROM of serial 3-line interface method.
●Features
1) Withstands electrostatic voltage 8kV, (twice more than other series)（HBM method typ.,except BR93H66RFVM-WC）
2) Wide action range -40℃～+125℃（-40℃～+85℃, -40℃～+105℃ in other series）
3) Conforming to Microwire BUS
4) Address auto increment function at read action
5) Write mistake prevention function
Write prohibition at power on
Write prohibition by command code
Write mistake prevention circuit at low voltage
6) Program cycle auto delete and auto end function
7) Program condition display by READY / BUSY
8) Low current consumption
At write action (at 5V) : 0.6mA (Typ.)
At read action (at 5V) : 0.6mA (Typ.)
At standby action (at 5V) : 0.1μA (Typ.)(CMOS input)
9) Built-in noise filter CS, SK, DI terminals
10) Compact package SOP8/SOP-J8/MSOP8
11) High reliability by ROHM original Double-Cell structure
12) High reliability ultrafine CMOS process
13) Easily connectable with serial port BR93H series
14) Data retention for 20 years (Ta≦125℃)
15) Endurance up to 1,000,000 times (Ta≦125℃)
16) Data at shipment all address FFFFh
●BR93H Series
Package type
SOP8
SOP-J8
MSOP8
RF
RFJ
RFVM
●
●
●
●
Capacity
Bit format
Type
2Kbit
128×16
BR93H56-WC
Power source
voltage
2.7～5.5V
4Kbit
256×16
BR93H66-WC
2.7～5.5V
8Kbit
512×16
BR93H76-WC
2.7～5.5V
●
●
16Kbit
1K×16
BR93H86-WC
2.7～5.5V
●
●
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22/40
●
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
●Absolute Maximum Ratings (Ta=25℃)
Parameter
Impressed voltage
Symbol
Limits
VCC
-0.3～+6.5
560 (SOP8)
Permissible dissipation
Storage temperature range
Action temperature range
Terminal voltage
Pd
Unit
V
*1
560 (SOP-J8)
*2
380 (MSOP8)
*3
mW
Tstg
-65～+150
℃
Topr
-40～+125
℃
‐
-0.3～VCC+0.3
V
*When using at Ta=25℃ or higher, 4.5mW(*1,*2), 3.1mW(*3), to be reduced per 1℃.
●Memory cell characteristics (VCC=2.7～5.5V)
Parameter
Endurance *1
Data retention *1
*1
Min.
1,000,000
500,000
300,000
40
20
Limit
Typ.
-
Max.
-
Limit
Limit
Times
Times
Times
Years
Years
Ta≦85℃
Ta≦105℃
Ta≦125℃
Ta≦25℃
Ta≦125℃
Not 100% TESTED
●Recommended action conditions
Parameter
Power source voltage
Input voltage
Symbol
VCC
VIN
Limits
2.7～5.5
0～VCC
Unit
V
●Electrical characteristics (Unless otherwise specified, Ta=-40～+125℃, VCC=2.7～5.5V)
Limits
Parameter
Symbol
Unit
Conditions
Min.
Typ.
Max.
“L” input voltage
VIL
-0.3
0.3xVCC
V
“H” input voltage
VIH
0.7xVCC
VCC+0.3
V
“L” output voltage 1
VOL1
0
0.4
V
IOL=2.1mA, 4.0V≦VCC≦5.5V
“L” output voltage 2
VOL2
0
0.2
V
IOL=100μA
“H” output voltage 1
VOH1
2.4
VCC
V
IOH=-0.4mA, 4.0V≦VCC≦5.5V
“H” output voltage 2
VOH2
VCC-0.2
VCC
V
IOH=-100μA
Input leak current
ILI
-10
10
μA
VIN=0V～VCC
Output leak current
ILO
-10
10
μA
VOUT=0V～VCC, CS=0V
ICC1
3.0
mA
fSK=1.25MHz, tE/W=10ms (WRITE)
Current consumption at
ICC2
1.5
mA
fSK=1.25MHz (READ)
action
ICC3
4.5
mA
fSK=1.25MHz, tE/W=10ms (WRAL)
Standby current
ISB
0.1
10
μA
CS=0V, DO=OPEN
◎Radiation resistance design is not made.
●Action timing characteristics (Unless otherwise specified, Ta=-40～+125℃, VCC=2.7～5.5V)
Parameter
Symbol
Min.
Typ.
SK frequency
fSK
SK “H” time
tSKH
250
SK “L” time
tSKL
250
CS “L” time
tCS
200
CS setup time
tCSS
200
DI setup time
tDIS
100
CS hold time
tCSH
0
DI hold time
tDIH
100
Data “1” output delay time
tPD1
Data “0” output delay time
tPD0
Time from CS to output establishment
tSV
Time from CS to High-Z
tDF
Write cycle time
tE/W
7
Write cycle time(BR93H66RFVM-WC)
tE/W
-
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Max.
1.25
300
300
200
200
10
5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
2011.09 - Rev.G
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
●Sync data input / output timing
CS
tCSS
tSKH
tSKL
tCSH
SK
tDIS
tDIH
DI
tPD1
tPD0
DO
(READ)
tDF
DO (WRITE)
STATUS VALID
Fig.1 Sync data input / output timing diagram
○Data is taken by DI sync with the rise of SK.
○At read action, data is output from DO in sync with the rise of SK.
○The status signal at write (READY / BUSY) is output after tCS from the fall of CS after write command input, at the area
DO where CS is “H”, and valid until the next command start bit is input. And, white CS is “L”, DO becomes High-Z.
○After completion of each mode execution, set CS “L” once for internal circuit reset, and execute the following action mode.
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2011.09 - Rev.G
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
●BR93H□□-WC
Technical Note
Characteristic data
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25/40
2011.09 - Rev.G
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
●BR93H□□-WC
Technical Note
Characteristic data
W R ITE C Y C LE TIM E : tE/W (m s)
6
SPEC
5
Ta=125℃
4
3
Ta=25℃
Ta=-40℃
2
1
0
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Fig.26-1 Write cycle time tE/W
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2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
●Block diagram
Power source voltage detection
Command decode
CS
Control
SK
Clock generation
Address
buffer
Command
register
DI
High voltage occurrence
Write
prohibition
Data
register
Address
decoder
7bit
8bit
9bit
10bit
7bit
8bit
9bit
10bit
R/W
amplifier
16bit
16bit
2,048 bit
4,096 bit
8,192 bit
16,384 bit
EEPROM
Dummy bit
DO
Fig. 27 Block diagram
●Pin assignment and function
VCC
NC
TEST
GND
VCC
SK
DI
TEST1
GND
BR93H66RF-WC:SOP8
BR93H66RFJ-WC:SOP-J8
BR93H66RFVM-WC:MSOP8
BR93H76RF-WC:SOP8
BR93H76RFJ-WC:SOP-J8
BR93H86RF-WC:SOP8
BR93H86RFJ-WC:SOP-J8
BR93H56RF-WC:SOP8
BR93H56RFJ-WC:SOP-J8
CS
TEST2
CS
DO
SK
DI
DO
Fig.28 Pin assignment diagram
Pin name
Vcc
GND
CS
SK
DI
DO
NC
TEST1
TEST2
TEST
I/O
Input
Input
Input
Output
-
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Function
Power source
All input / output reference voltage, 0V
Chip select input
Serial clock input
Start bit, ope code, address, and serial data input
Serial data output, READY / BUSY internal condition display output
Non connected terminal, Vcc, GND or OPEN
TEST terminal, GND or OPEN
TEST terminal, Vcc, GND or OPEN
TEST terminal, GND or OPEN
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2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
●Description of operations
Communications of the Microwire Bus are carried out by SK (serial clock), DI (serial data input),DO (serial data output) ,and
CS (chip select) for device selection.
When to connect one EEPROM to a microcontroller, connect it as shown in Fig.29-(a) or Fig.29-(b). When to use the input
and output common I/O port of the microcontroller, connect DI and DO via a resistor as shown in Fig.29-(b) (Refer to pages
31/35.), and connection by 3 lines is available.
In the case of plural connections, refer to Fig. 29-(c).
CS
CS
CS
CS
SK
SK
SK
SK
DO
DI
DO
DI
DI
DO
DO
Fig.29-(a) Connection by 4 lines Fig.29-(b) Connection by 3 lines
CS
SK
DI
DO
CS3
CS1
CS0
SK
DO
DI
BR93HXX
CS
SK
DI
DO
BR93HXX
Microcontroller
Microcontroller
CS
SK
DI
DO
Microcontroller
Device 1
Device 2
Device 3
Fig.29-(c) Connection example of plural devices
Fig.29 Connection method with microcontroller
Communications of the Microwire Bus are started by the first “1” input after the rise of CS. This input is called a start bit. After
input of the start bit, input ope code, address and data. Address and data are input all in MSB first manners.
“0” input after the rise of CS to the start bit input is all ignored. Therefore, when there is limitation in the bit width of PIO of the
microcontroller, input “0” before the start bit input, to control the bit width.
●Command mode
Command
*1
Read (READ)
Write enable (WEN)
*2
Write (WRITE)
*2,3
Write all (WRAL)
Write disable (WDS)
Address
BR93H76/86-WC
Start
bit
1
Ope
code
10
1
1
1
00
01
00
1 1 ******
1 1 ********
A7,A6,A5,A4,A3,A2,A1,A0
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
D15~D0(WRITE DATA)
0 1 * * * * * B0
0 1 * * * * * B2,B1,B0
D15~D0(WRITE DATA)
1
00
0 0 ******
0 0 ********
BR93H56/66-WC
A7,A6,A5,A4,A3,A2,A1,A0
・ Input the address and the data in MSB first manners.
・ As for *, input either VIH or VIL.
*Start bit
Acceptance of all the commands of this IC starts at recognition of the start bit.
The start bit means the first “1” input after the rise of CS.
Data
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
D15~D0(READ DATA)
A7 and B0 of BR93H56-WC becomes Don't Care.
A9 and B2 of BR93H76-WC becomes Don't Care.
*1 As for read, by continuous SK clock input after setting the read command, data output of the set address starts, and
address data in significant order are sequentially output continuously. (Auto increment function)
*2 When the read and the write all commands are executed, data written in the selected memory cell is automatically deleted, and input data is written.
*3 For the write all command, data written in memory cell of the areas designated by B2, B1, and B0, are automatically
deleted, and input data is written in bulk.
●Write all area
B2
0
0
0
0
1
1
1
1
B1 B0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Write area
000h～07Fh
080h～0FFh
100h～17Fh
180h～1FFh
200h～27Fh
280h～2FFh
300h～37Fh
380h～3FFh
Designation of B2, B1, and B0
H56
＊
＊
＊
H66
＊
＊
B0
H76
＊
B1
B0
H86
B2
B1
B0
・The write all command is written in bulk in 2Kbit unit.
The write area can be selected up to 3bit. Confirm the settings and write areas of the above B2, B1, and B0.
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2011.09 - Rev.G
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
●Timing chart
～
～
～
～
～
～
1) Read cycle (READ)
CS
～
～
*1
1
4
n
～
～
DI
2
～
～
1
n+1
～
～
SK
Am
0
A1
～
～
1
A0
～
～
～
～
*2
～
～
D14
D0
D1
D15 D14
～
～
D15
～
～
0
DO
High-Z
BR93H56/66-WC : n=27, m=7
BR93H76/86-WC : n=29, m=9
*2 The following address data output
（auto increment function）
*1 Start bit
When data “1” is input for the first time after the rise of CS, this is recognized as a start bit. And when “1” is input after plural “0” are input, it is recognized as a
start bit, and the following operation is started. This is common to all the commands to described hereafter.
Fig. 30 Read cycle
○When the read command is recognized, input address data (16bit) is output to serial. And at that moment, at taking A0, in
sync with the rise of SK, “0” (dummy bit) is output. And, the following data is output in sync with the rise of SK.
This IC has address auto increment function valid only at read command. This is the function where after the above read
execution, by continuously inputting SK clock, the above address data is read sequentially. And, during the auto increment,
keep CS at “H”.
2) Write cycle (WRITE)
～
～
～
～
～
～
tCS
CS
2
n
4
A1
A0
D15
D14
D1
D0
～
～
Am
BR93H56/66-WC : n=27, m=7
BR93H76/86-WC : n=29, m=9
～
～
1
～
～
0
～
～
1
～
～
～
～
DI
～
～
1
～
～
～
～
SK
STATUS
tSV
READY
～
～
DO
BUSY
High-Z
tE/W
Fig. 31 Write cycle
○In this command, input 16bit data (D15~D0) are written to designated addresses (Am~A0). The actual write starts by the fall
of CS of D0 taken SK clock(n-th clock from the start bit input), to the rise of the (n+1)-th clock.
When STATUS is not detected, (CS="L" fixed) Max. 10ms(Max.5ms:BR93H66RFVM-WC) in conformity with tE/W, and
when STATUS is detected (CS="H"), all commands are not accepted for areas where "L" (BUSY) is output from D0,
therefore, do not input any command.
Write is not made even if CS is started after input of clock after (n+1)-th clocks.
Note) Take tSKH or more from the rise of the n-th clock to the fall of CS.
3) Write all cycyle (WRAL)
tCS
CS
SK
1
DI
1
2
0
5
0
0
1
m
B2
STATUS
BR93H56/66-WC : n=27, m=9
BR93H76/86-WC : n=29, m=11
n
B1
B0
D15
D1
D0
tSV
DO
BUSY
READY
High-Z
Fig. 32 Write all cycle
tE/W
○In this command, input 16bit data is written simultaneously to designated block for 128 words. Data is writen in bulk at a
write time of only Max. 10ms(Max.5ms:BR93H66RFVM-WC) in conformity with tE/W. When writing data to all addresses,
designate each block by B2, B1, and B0, and execute write. Write time is Max.10ms(Max.5ms:BR93H66RFVM-WC). The
actual write starts by the fall of CS from the rise of D0 taken at SK clock (n-th clock from the start bit input), to the rise of the
(n+1)-th clock. When CS is ended after clock input after the rise of the (n+1)-th clock, command is cancelled, and write is
not completed.
Note)Take tSKH or more from the rise of the n-th clock to the fall of CS.
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2011.09 - Rev.G
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
4) Write enable (WEN) / disable (WDS) cycle
～
～
CS
1
2
3
4
5
6
7
8
～
～
SK
1
0
BR93H56/66-WC : n=11
BR93H76/86-WC : n=13
0
～
～
DI
n
～
～
ENABLE=1 1
DISABLE=0 0
DO
High-Z
Fig. 33 Write enable (WEN) / disable (WDS) cycle
○At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is
necessary to execute the write enable command. And, once this command is executed, it is valid unitl the write disable
command is executed or the power is turned off. However, the read command is valid irrespective of write enable /
disable command. Input to SK after 6 clocks of this command is available by either “H” or “L”, but be sure to input it.
○When the write enable command is executed after power on, write enable status gets in. When the write disable
command is executed then, the IC gets in write disable status as same as at power on, and then the write command is
cancelled thereafter in software manner. However, the read command is executable. In write enable status, even when
the write command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the
write disable command after completion of write.
●Application
1) Method to cancel each command
○READ
Start bit
Ope code
Address
1bit
2bit
8bit
*1
*1 Address is 8 bits in BR93H56-WC, and BR93H66-WC.
Address is 10 bits in BR93H76-WC, and BR93H86-WC.
Data
16bit
Cancel is available in all areas in read mode.
●Method to cancel：cancel by CS=“L”
Fig.34 READ cancel available timing
○WRITE, WRAL
・Rise of 27clock
SK
DI
27
26
D1
a
*2
29
28
D0
b
c
Enlarged figure
Start bit
1bit
Ope code
Address
2bit
8bit
*1
Data
tE/W
16bit
a
b
a：From start bit to 27 clock rise
Cancel by CS=“L”
b：27 clock rise and after *2
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
c：28 clock rise and after *3
Cancel by CS=“L”
However, when write is started in b area (CS is ended), cancellation is not
available by any means.
And when SK clock is input continuously, cancellation is not available.
Fig.35 WRITE, WRAL cancel available timing
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30/40
C
*1 Address is 8 bits in BR93H56/66-WC
Address is 10 bits in BR93H76/86-WC
*2 27 clocks in BR93H56/66-WC
29 clocks in BR93H76/86-WC
*3 28 clocks in BR93H56/66-WC
30 clocks in BR93H76/86-WC
Note 1) If Vcc is made OFF in this area,
designated address data is not guaranteed,
therefore write once again.
Note 2) If CS is started at the same timing as that of
the SK rise, write execution/cancel becomes
unstable, therefore, it is recommended to fail in
SK=”L” area. As for SK rise, recommend timing of
tCSS/tCSH or higher.
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
2) Equivalent circuit
○Output circuit
DO
OEint.
Fig.36 Output circuit (DO)
○Input circuit
RESET int.
TEST1
(TEST)
LPF
CS
TESTint.
CSint.
EN
Fig.37 Input circuit (CS)
Fig.38
Input circuit (TEST1, TEST)
EN
TEST2
SK
DI
LPF
Fig.39
3)
SK(DI)int.
Fig.40 Input circuit (TEST2)
Input circuit (SK, DI)
I/O peripheral circuit
3-1) Pull down CS.
By making CS=“L” at power ON/OFF, mistake in operation and mistake write are prevented.
Refer to the item 6) Notes at power ON/OFF in page 34/35.
○Pull down resistance Rpd of CS pin
To prevent mistake in operation and mistake write at power ON/OFF, CS pull down resistance is necessary.
Select an appropriate value to this resistance value from microcontroller VOH, IOH, and VIL characteristics of this IC.
Rpd ≧
Microcontroller
VOHM
“H” output
VOHM ≧
EEPROM
VIHE
IOHM
Rpd
VOHM
IOHM
VIHE
・・・①
・・・②
Example) When VCC =5V, VIHE=2V, VOHM=2.4V, IOHM=2mA,
from the equation ①,
Rpd ≧
“L” input
∴
Rpd ≧
2.4
-3
2×10
1.2 [kΩ]
With the value of Rpd to satisfy the above equation, VOHM becomes
2.4V or higher, and VIHE (=2.0V), the equation ② is also satisfied.
Fig.41 CS pull down resistance
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・VIHE
・VOHM
・IOHM
31/40
: EEPROM VIH specifications
: Microcontroller VOH specifications
:Microcontroller IOH specifications
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
3-2) DO is available in both pull up and pull down.
Do output become “High-Z” in other READY / BUSY output timing than after data output at read command and write
command. When malfunction occurs at “High-Z” input of the microcontroller port connected to DO, it is necessary to
pull down and pull up DO. When there is no influence upon the microcontroller actions, DO may be OPEN. If DO is
OPEN, and at timing to output status READY, at timing of CS=“H”, SK=“H”, DI=“H”, EEPROM recognizes thisas a
start bit, resets READY output, and DO=”High-Z”, therefore, READY signal cannot be detected. To avoid such output,
pull up DO pin for improvement.
CS “H”
CS
SK
SK
Enlarged
D0
DI
DI
High-Z
High-Z
READY
DO BUSY
DO
BUSY
CS=SK=DI=”H”
When DO=OPEN
Improvement by DO pull up
DO
READY
BUSY
CS=SK=DI=”H”
When DO=pull up
Fig.42 READY output timing at DO=OPEN
○Pull up resistance Rpu and pull down resistance Rpd of DO pin
As for pull up and pull down resistance value, select an appropriate value to this resistance value from microcontroller
VIH, VIL, and VOH, IOH, VOL, IOL characteristics of this IC.
Rpu ≧
Microcontroller
EEPROM
Rpu
VILM
IOLE
VOLE
Vcc－VOLE
VOLE ≦
・・・③
・・・④
VILM
Example) When VCC =5V, VOLE=0.4V, IOLE=2.1mA, VILM=0.8V,
from the equation ③,
“L” input
Rpu ≧
“L” output
∴
Rpu ≧
5－0.4
-3
2.1×10
2.2 [kΩ]
With the value of Rpu to satisfy the above equation, VOLE becomes 0.4V or
below, and with VILM(=0.8V), the equation ④ is also satisfied.
・VOLE
・IOLE
・VILM
・VOLE : EEPROM VOL specifications
・IOLE : EEPROM IOL specifications
・VILM : Microcontroller VIL specifications
Fig.43 DO pull up resistance
Rpd ≧
EEPROM
Microcontroller
VOHE ≧
VOHE
Rpd
IOHE
VOHE
・・・⑤
IOHE
・・・⑥
VIHM
Example) When VCC =5V, VOHE=Vcc－0.2V, IOHE=0.1mA,
VIHM=Vcc×0.7V from the equation ⑤
VIHM
“H” input
IOLE
“H” output
Rpd ≧
∴
Rpd ≧
5－0.2
-3
0.1×10
48 [kΩ]
With the value of Rpd to satisfy the above equation, VOHE becomes 2.4V or
below, and with VIHM (=3.5V), the equation ⑥ is also satisfied.
Fig.44 DO pull down resistance
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・VOHE : EEPROM VOH specifications
・IOHE : EEPROM IOH specifications
・VIHM : Microcontroller VIH specifications
32/40
2011.09 - Rev.G
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
○READY / BUSY status display (DO terminal)
(common to BR93H56-WC, BR93H66-WC, BR93H76-WC, BR93H86-WC)
This display outputs the internal status signal. When CS is started after tCS (Min.200ns)
from CS fall after write command input, “H” or “L” output.
R/B display＝“L” (BUSY) = write under execution
After the timer circuit in the IC works and creates the period of tE/W, this time circuit completes automatically.
And write to the memory cell is made in the period of tE/W, and during this period, other command is not
accepted.
（DO status）
R/B display = “H” (READY) = command wait status
Even after tE/W (max.10ms) (Max.5ms:BR93H66RFVM-WC) from write of the memory cell, the following
command is accepted.
Therefore, CS=“H” in the period of tE/W, and when input is in SK, DI, malfunction may occur, therefore,
（DO status）
DI=“L” in the area
CS=“H”. (Especially, in the case of shared input port, attention is required.)
*Do not input any command while status signal is output. Command input in BUSY area is cancelled, but command input in READY area is accepted.
Therefore, status READY output is cancelled, and malfunction and mistake write may be made.
STATUS
CS
SK
CLOCK
DI
WRITE
INSTRUCTION
DO
tSV
High-Z
READY
BUSY
Fig.45 R/B status output timing chart
4) When to directly connect DI and DO
This IC has independent input terminal DI and output terminal DO, and separate signals are handled on timing chart,
meanwhile, by inserting a resistance R between these DI and DO terminals, it is possible to carry out control by 1 control line.
Microcontroller
EEPROM
DI/O PORT
DI
R
DO
Fig.46 DI, DO control line common connection
○Data collision of microcontroller DI/O output and DO output and feedback of DO output to DI input.
Drive from the microcontroller DI/O output to DI input on I/O timing, and signal output from DO output occur at the
same time in the following points.
4-1) 1 clock cycle to take in A0 address data at read command
Dummy bit “0” is output to DO terminal.
→When address data A0 = “1” input, through current route occurs.
EEPROM CS input
“H”
EEPROM SK input
A1
EEPROM DI input
A0
Collision of DI input and DO output
EEPROM DO output
Microcontroller DI/O port
0
High-Z
A1
D15 D14 D13
A0
Microcontroller output
High-Z
Microcontroller input
Fig.47 Collision timing at read data output at DI, DO direct connection
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33/40
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
4-2) Timing of CS = “H” after write command. DO terminal in READY / BUSY function output.
When the next start bit input is recognized, “HIGH-Z” gets in.
→Especially, at command input after write, when CS input is started with microcontroller DI/O output “L”,
READY output “H” is output from DO terminal, and through current route occurs.
Feedback input at timing of these 4-1) and 4-2) does not cause disorder in basic operations, if resistance R is inserted.
～
～
EEPROM SK input
Write command
EEPROM DI input
Write command
EEPROM DO output
Write command
～
～
Write command
～
～
EEPROM CS input
～
～
～
～
～
～
READY
～
～
～
～
BUSY
High-Z
READY
Collision of DI input and DO output
BUSY
Microcontroller output
Microcontroller input
～
～
READY
Write command
～
～
Microcontroller DI/O port
Microcontroller output
Fig.48 Collision timing at DI, DO direct connection
○Selection of resistance value R
The resistance R becomes through current limit resistance at data collision. When through current flows, noises of
power source line and instantaneous stop of power source may occur. When allowable through current is defined as I,
the following relation should be satisfied. Determine allowable current amount in consideration of impedance and so
forth of power source line in set. And insert resistance R, and set the value R to satisfy EEPROM input level VIH/VIL,
even under influence of voltage decline owing to leak current and so forth. Insertion of R will not cause any influence
upon basic operations.
4-3) Address data A0 = “1” input, dummy bit “0” output timing
(When microcontroller DI/O output is “H”, EEPROM DO outputs “L”, and “H” is input to DI)
・Make the through current to EEPROM 10mA or below.
・See to it that the input level VIH of EEPROM should satisfy the following.
Conditions
Microcontroller
VOHM ≦ VIHE
EEPROM
VOHM ≦ IOHM×R + VOLE
DI/O PORT
“H” output
At this moment, if VOLE=0V,
DI
VOHM ≦ IOHM×R
VOHM
IOHM
R
∴
DO
R ≧
VOHM
IOHM
・・・⑦
VOLE
・VIHE
・VOLE
・VOHM
・IOHM
“L” output
Fig.49
: EEPROM VIH specifications
: EEPROM VOL specifications
: Microcontroller VOH specifications
: Microcontroller IOH specifications
Circuit at DI, DO direct connection (Microcontroller DI/O “H” output, EEPROM “L” output)
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34/40
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
4-4) DO status READY output timing
(When the microcontroller DI/O is “L”, EEPROM DO outputs “H”, and “L” is input to DI)
・Set the EEPROM input level VIL so as to satisfy the following.
Conditions
Microcontroller
“L” output
VOLM ≧ VILE
EEPROM
DI/O PORT
DI
VOLM ≧ VOHE – IOLM×R
VOLM
As this moment, if VOHE=Vcc,
VOLM ≧ Vcc – IOLM×R
R
IOHM
DO
∴
VOHE
R ≧
Vcc – VOLM
“H” output
・VILE
・VOHE
・VOLM
・IOLM
IOLM
・・・⑧
: EEPROM VIL specifications
: EEPROM VOH specifications
: Microcontroller VOL specifications
: Microcontroller IOL specifications
Example) When Vcc=5V, VOHM=5V, IOHM=0.4mA, VOLM=5V, IOLM=0.4mA,
From the equation ⑦,
R ≧
From the equation ⑧,
VOHM
R ≧
Vcc – VOLM
IOHM
R ≧
IOLM
5
∴
R ≧
12.5 [kΩ]
5 – 0.4
R ≧
-3
0.4×10
-3
2.1×10
・・・⑨
∴
R ≧
2.2 [kΩ]
・・・⑩
Therefore, from the equations ⑨ and ⑩,
∴
Fig.50
R ≧
12.5 [kΩ]
Circuit at DI, DO direct connection (Microcontroller DI/O “L” output, EEPROM “H” output)
5) Notes at test pin wrong input
There is no influence of external input upon TEST2 pin.
For TEST1 (TEST)pin, input must be GND or OPEN. If H level is input, the following may occur,
1.
At WEN, WDS, READ command input
There is no influence by TEST1 (TEST) pin.
2. WRITE, WRAL command input
* BR93H56-WC, BR93H66-WC, address 8 bits
BR93H76-WC, BR93H86-WC, address 10 bits
Start bit
Ope code
1bits
2bits
Address*
8bits
Data
tE/W
16bits
a
Write start
CS rise timing
Fig.51 TEST1(TEST) pin wrong input timing
a：There is no influence by TEST1 (TEST) pin.
b：If H during write execution, it may not be written correctly. And H area remains BUSY and READY does not go back.
Avoid noise input, and at use, be sure to connect it to GND terminal or set it OPEN.
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35/40
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
6) Notes on power ON/OFF
・At power ON/OFF, set CS “L”.
When CS is “H”, this IC gets in input accept status (active). At power ON, set CS “L” to prevent malfunction from noise.
(When CS is in “L” status, all inputs are cancelled.) At power decline low power status may prevail. Therefore, at power
OFF, set CS “L” to prevent malfunction from noise.
VCC
VCC
GND
VCC
CS
GND
Bad example
Good example
Fig.52 Timing at power ON/OFF
（Bad example）CS pin is pulled up to Vcc.
In this case, CS becomes “H” (active status), EEPROM may
malfunction or have write error due to noises. This is true even
when CS input is High-Z.
（Good example）It is “L” at power ON/OFF.
Set 10ms or higher to recharge at power OFF.
When power is turned on without observing this condition,
IC internal circuit may not be reset.
○POR citcuit
This IC has a POR (Power On Reset) circuit as a mistake write countermeasure. After POR action, it gets in write
disable status. The POR circuit is valid only when power is ON, and does not work when power is OFF. However, if CS is
“H” at power ON/OFF, it may become write enable status owing to noises and the likes. For secure actions, observe the
follwing conditions.
1. Set CS=”L”
2. Turn on power so as to satisfy the recommended conditions of tR, tOFF, Vbot for POR circuit action.
tR
VCC
Recommended conditions of tR, tOFF, Vbot
tR
10m s or below
tOFF
t O FF
V bot
10m s or higher 0.3V or below
100m s or below 10m s or higher 0.2V or below
Vbot
0
Fig.53 Rise waveform diagram
○LVCC circuit
LVCC (VCC-Lockout) circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ.=1.9V) or below, it prevent data rewrite.
7) Noise countermeasures
○VCC noise (bypass capacitor)
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a by pass capacitor (0.1μF) between IC VCC and GND, At that moment, attach it as close to IC
as possible.And, it is also recommended to attach a bypass capacitor between board VCC and GND.
○SK noise
When the rise time (tR) of SK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock
bit displacement.
To avoid this, a Schmitt trigger circuit is built in SK input. The hysteresis width of this circuit is set about 0.3, if noises
exist at SK input, set the noise amplitude 0.3p-p or below. And it is recommended to set the rise time (tR) of SK 100ns or
below. In the case when the rise time is 100ns or higher, take sufficient noise countermeasures. Make the clock rise, fall
time as small as possible.
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36/40
2011.09 - Rev.G
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
●Cautions on use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in
consideration of static characteristics and transition characteristics and fluctuations of external parts and our IC.
(3) Absolute Maximum Ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, IC
may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear
exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to IC.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is not lower than that
of GND terminal in consideration of transition status.
(5) Heat design
In consideration of allowable loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package IC onto a board, pay sufficient attention to IC direction and displacement. Wrong packaging may
destruct IC. And in the case of shortcircuit between IC terminals and terminals and power source, terminal and GND
owing to foreign matter, IC may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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37/40
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
B
R
9
ROHM Type
name
3
L
4
BUSType
Operating
93：Microwire temperature
L:-40℃~+85℃
A:-40℃~+105℃
H:-40℃~+125℃
6
F
Capacity
J
-
Package type
F,RF
:SOP8
FJ,RFJ
:SOP-J8
FV,RFV
: SSOP-B8
FVT,RFVT
: TSSOP-B8
RFVJ
: TSSOP-B8J
RFVM
: MSOP8
46=1K
56=2K
66=4K
76=8K
86=16K
W
Double cell
L:W
A:WM
H:WC
E
2
Package specifications
E2：reel shape emboss taping
TR：reel shape emboss taping
SOP8
<Tape and Reel information>
7
6
5
+6°
4° −4°
6.2±0.3
4.4±0.2
0.3MIN
8
1 2
3
0.9±0.15
5.0±0.2
(MAX 5.35 include BURR)
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
4
0.595
1.5±0.1
+0.1
0.17 -0.05
0.11
S
1.27
0.42±0.1
1pin
Reel
(Unit : mm)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
SOP-J8
<Tape and Reel information>
4.9±0.2
(MAX 5.25 include BURR)
+6°
4° −4°
6
5
0.45MIN
7
3.9±0.2
6.0±0.3
8
1
2
3
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
4
0.545
0.2±0.1
0.175
1.375±0.1
S
1.27
0.42±0.1
0.1 S
1pin
Reel
(Unit : mm)
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Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2011.09 - Rev.G
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
Technical Note
SSOP-B8
<Tape and Reel information>
3.0 ± 0.2
(MAX 3.35 include BURR)
0.3MIN
4.4±0.2
6.4±0.3
8 76 5
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1.15±0.1
1 23 4
0.15 ± 0.1
0.1
S
0.1
+0.06
0.22 -0.04
(0.52)
0.08
M
0.65
1pin
Reel
(Unit : mm)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
TSSOP-B8
<Tape and Reel information>
3.0 ± 0.1
(MAX 3.35 include BURR)
8
7
6
4±4
3000pcs
2
3
4
1PIN MARK
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1.0±0.2
0.5±0.15
6.4±0.2
4.4±0.1
1
+0.05
0.145 –0.03
S
0.1±0.05
1.2MAX
Embossed carrier tape
Quantity
Direction
of feed
0.525
1.0±0.05
Tape
5
0.08 S
+0.05
0.245 –0.04
0.08
Direction of feed
M
1pin
0.65
Reel
(Unit : mm)
∗ Order quantity needs to be multiple of the minimum quantity.
TSSOP-B8J
<Tape and Reel information>
3.0 ± 0.1
(MAX 3.35 include BURR)
5
4.9±0.2
0.45±0.15
2
3
4
1PIN MARK
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
0.95±0.2
6
+0.05
0.145 – 0.03
0.525
S
0.1±0.05
0.85±0.05
1
1.1MAX
7
3.0±0.1
8
4±4
0.08 S
+0.05
0.32 –0.04
0.08
M
1pin
0.65
Reel
(Unit : mm)
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39/40
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2011.09 - Rev.G
Technical Note
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
MSOP8
<Tape and Reel information>
2.8±0.1
4.0±0.2
8 7 6 5
0.6±0.2
+6°
4° −4°
0.29±0.15
2.9±0.1
(MAX 3.25 include BURR)
Tape
Embossed carrier tape
Quantity
3000pcs
Direction
of feed
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1 2 3 4
1PIN MARK
1pin
+0.05
0.145 –0.03
0.475
0.08±0.05
0.75±0.05
0.9MAX
S
+0.05
0.22 –0.04
0.08 S
Direction of feed
0.65
Reel
(Unit : mm)
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40/40
∗ Order quantity needs to be multiple of the minimum quantity.
2011.09 - Rev.G
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
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