bq2058 Lithium Ion Pack Supervisor for 3- and 4-Cell Packs Features General Description ➤ Protects and individually monitors three or four Li-Ion series cells for overvoltage, undervoltage The bq2058 Lithium Ion Pack Supervisor is designed to control the charge and discharge cell voltages for three or four lithium ion (Li-Ion) series cells, accommodating battery packs containing series/parallel configurations. The low operating current does not overdischarge the cells during periods of storage and does not significantly increase the system discharge load. The bq2058 can be part of a low-cost Li-Ion charge control system within the battery pack. ➤ Monitors pack for overcurrent ➤ Designed for battery pack integration ➤ Minimal external components ➤ Drives external FET switches ➤ Selectable overvoltage (V OV ) thresholds - Mask-programmable by Unitrode - Standard version–4.25V ➤ Supply current: 25µA typical ➤ Sleep current: 0.7µA typical The bq2058 controls two external FETs to limit the charge and discharge potentials. The bq2058 allows charging when each individual cell voltage is below VOV (overvoltage limit). If the voltage on any cell exceeds VOV for a user-configurable delay period (tOVD), the CHG pin is driven high, shutting off charge to the battery pack. This safety feature pre- vents overcharge of any cell within the battery pack. After an overvoltage condition occurs, each cell must fall below VCE (charge enable voltage) for the bq2058 to re-enable charging. The bq2058 protects batteries from overdischarge. If the voltage on any cell falls below VUV (undervoltage limit) for a user-configurable delay period (tUVD), the DSG output is driven high, shutting off the battery discharge. This safety feature prevents overdischarge of any cell within the battery pack. The bq2058 also stops discharge on detection of an overcurrent condition, such as a short circuit. If an overcurrent condition occurs for a userconfigurable delay period (tOCD), the DSG output is driven high, disconnecting the load from the pack. DSG remains high until removal of the short circuit or overcurrent condition. ➤ 16-pin 150-mil narrow SOIC Pin Names Pin Connections CHG Charge control output CTL Pack disable input DSG Discharge control output NSEL 3- or 4-cell selection UVD Undervoltage delay input OVD Overvoltage delay input OCD Overcurrent delay input CHG 1 16 DSG CTL 2 15 NSEL VSS 3 14 UVD VSS Low potential input CSL 4 13 OVD CSL BAT4N 5 12 OCD Current sense low-side input BAT3N 6 11 VCC BAT4N Battery 4 negative input VCC High potential input BAT2N 7 10 CSH BAT3N Battery 3 negative input CSH BAT1N 8 9 BAT2N Battery 2 negative input Current sense high-side input BAT1N Battery 1 negative input BAT1P Battery 1 positive input BAT1P 16-Pin Narrow SOIC PN205801.eps 1/99 I 1 bq2058 This input is connected to BAT1P in a threecell configuration. Pin Descriptions CHG Charge control output DSG This push-pull output controls the charge path to the battery pack. Charging is allowed when low. CTL This push-pull output controls the discharge path to the battery pack. Discharge is allowed when low. Pack disable input NSEL When high, this input allows an external source to disable the pack by making both DSG and CHG inactive. For normal operation, the CTL pin is low. Low potential input CSL Overcurrent sense low-side input BAT4N BAT2N This input is connected between the low-side discharge FET (or sense resistor) and BAT4N to enable overcurrent sensing in the battery pack’s ground path. OVD Battery 4 negative input OCD Overvoltage delay input This input uses an external capacitor to VCC to set the overvoltage delay timing. Overcurrent delay input This input uses an external capacitor to VCC to set the overcurrent delay timing. Battery 3 negative input VCC High potential input This input is connected to the negative terminal of the cell designated BAT3 in Figure 2. CSH Overcurrent sense high-side input T h is in p u t is c on n ec t ed b et w een t h e high-side discharge FET (or sense resistor) and BAT1P to enable overcurrent sense in the battery pack’s positive supply path. Battery 2 negative input This input is connected to the negative terminal of the cell designated BAT2 in Figure 2. BAT1N Undervoltage delay input This input uses an external capacitor to VCC to set the undervoltage delay timing. This input is connected to the negative terminal of the cell designated BAT4 in Figure 2. BAT3N Number of cells input This input selects the number of series cells in the pack. NSEL should connect to VCC for four cells and to VSS for three cells. UVD VSS Discharge control output BAT1P Battery 1 negative input Battery 1 positive input This input is connected to the positive terminal of the cell designated BAT1 in Figure 2. This input is connected to the negative terminal of the cell designated BAT1 in Figure 2. Table 1. Pin Configuration for 3- and 4-Series Cells Number of Cells Configuration Pins Battery Pins BAT1N – Positive terminal of first cell 3 cells BAT1N tied to BAT1P NSEL = VSS BAT2N – Negative terminal of first cell BAT3N – Negative terminal of second cell BAT4N – Negative terminal of third cell BAT1P – Positive terminal of first cell BAT1N – Negative terminal of first cell 4 cells NSEL = VCC BAT2N – Negative terminal of second cell BAT3N – Negative terminal of third cell BAT4N – Negative terminal of fourth cell 2 bq2058 Cell Inputs Sel4 Sel3 Sel2 Sel1 Pin 9 B1P Pin 8 B1N Number of Cells Select + Pin 15 NSEL NSEL Clock Pin 7 B2N Sleep Pin 6 B3N Sleep Sel4 Sel3 Sel2 Sel1 Sel4 Sel3 Sel2 Sel1 Pin 5 B4N Pin 3 VOV + D CK D Q Chip Negative Supply Sel4 CK Any_Above_VOV CK Pin 1 CHG Charge Control Output Capacitor Pin 13 OVD Discharge Off Delay Capacitor Input QB D Q Sel2 Reset Non-Retrigger Oneshot Reset D Q Sel3 Out Edge QB Overcharge QB CK All_Below_VCE QB D Q Sel1 CK Any_Below_VUV QB Sleep D CK D Q Sel4 QB D Q Sel3 VCE Pin 10 CSH Pin 9 B1P D Q Sel1 Pin 4 CSL Pin 5 B4N QB VUV D Q CK Sel3 QB D Q Sel2 CK QB Pin 10 CSH + 70mV + Out Pin 9 B1P Pin 4 CSL Pin 5 B4N Non-Retrigger Oneshot Reset Capacitor 160mV + 160mV + Pin 2 CTL D Q Sel1 70mV Edge Overcurrent Delay Capacitor Input Pin 12 OCD CK QB + Discharge Control Output Sense Low-side Input CK D Q Sel4 Reset Charge Off Delay Capacitor Input Sense High-side Input CK QB + Non-Retrigger Oneshot Reset DSG Pin 14 QB D Q Sel2 QB Capacitor UVD CK Pin 16 Out Edge CK CK External Output Control QB Figure 1. Block Diagram 3 D CK Q QB Reset Overcurrent bq2058 The bq2058 samples a cell every 40ms (typical). Every sample is a fully differential measurement of each cell. During this sample period, the bq2058 compares the measurements with these thresholds to determine if any of the these conditions exist: VOV, VUV, and VCE. Functional Description Figure 1 is a block diagram outlining the major components of the bq2058. Figure 2 shows a 3- or 4-cell pack supervisor circuit. The following sections detail the various functional aspects of the bq2058. Overcurrent and charge detect are conditions that are not sampled, but are continuously monitored. Thresholds Initialization The bq2058 monitors the lithium ion pack for the conditions listed below. Shown with these conditions are the respective thresholds used to determine if that condition exists: ■ Overvoltage (VOV) ■ Undervoltage (VUV) ■ Overcurrent (VOCH, VOCL) ■ Charge Enable (VCE) ■ Charge Detect (VCD) On initial power-up, such as connecting the battery pack for the first time to the bq2058, the bq2058 enters the low-power sleep mode, disabling the DSG output. It is recommended that a top to bottom cell connection be made at pack assembly for proper initialization. A charging supply must be applied to the bq2058 circuit to enable the pack. See Low-Power Sleep Mode and Charge Detect sections. C8 0.1uF * See note 1. Q4 ZVP3306F R2 6.98K Q2 Si4435DY * See note 2. C6 0.1uF Q1 Si4435DY POS R10 0 Ohm R11 0 Ohm 4-Cell R9 1M R6 100K 3-Cell Q3 2N7002 U1 bq2058 C9 0.1uF R3 10K B1P C1 0.001uF R4 10K B1N C2 0.001uF R5 10K B2N C3 0.001uF R7 10K NSEL 15 11 VCC OVD 13 9 BAT1P UVD 14 8 BAT1N OCD 12 7 BAT2N DSG 16 6 BAT3N CSH 10 5 BAT4N CHG 1 3 VSS CTL 2 CSL 4 B3N C10 0.1uF C5 0.1uF C7 0.01uF TP1 C4 0.001uF R8 10K B4N R1 2.7K D1 BAT54 NEG Notes: 1. For automatic short circuit recovery. 2. Remove R11 for 4-cell. Remove R10 and connect B1P to B1N for 3-cells. Figure 2. 3- or 4-Cell Li-Ion Battery Pack Supervisor 4 bq2058 Low-Power Sleep Mode Table 2. Overvoltage Threshold Options The bq2058 enters the low-power sleep mode in two different ways: 1. On initial power-up. 2. After the detection of an undervoltage condition–VUV. Part No. VOV Limit bq2058 When the bq2058 enters the low-power sleep mode, DSG is driven high and the device consumes 0.7µA (typical). The bq2058 only comes out of low-power sleep mode when a valid charge-detect condition exists. 4.25V bq2058C 4.325 bq2058D 4.30V bq2058G* 4.375V bq2058R 4.35V bq2058W 3.4V The overvoltage threshold limits are programmed at Unitrode. The bq2058 is the standard option that is more readily available for sampling and prototyping purposes. Please contact Unitrode for other voltage threshold and tolerance options. Charge Detect The bq2058 continuously monitors for a charge-detect condition. A valid charge-detect condition exists when either of the conditions are true: CSL < BAT4N - 70mV (VCD) Charge Enable CSH > BAT1P + 70mV (VCD) A valid charge enable indicates that an overvoltage (overcharge) condition no longer exists and that the pack is ready to accept further charge. Once overvoltage protection is asserted, charging will not be enabled until all cell voltages fall below VCE. The VCE threshold is a function of VOV, and changes with different VOV limits. A valid charge-detect enables the DSG output, allowing charging of the lithium ion cells. This is accomplished by applying the charging supply to the pack. Undervoltage Undervoltage (or overdischarge) protection is asserted when any cell voltage drops below the VUV threshold and remains below the V UV threshold for a time exceeding a user-configurable delay (tUVD). The DSG output is driven high disabling the discharge of the pack. The bq2058 then enters the low-power sleep mode. VCE = VOV - 150mV Overcurrent The bq2058 detects an overcurrent (or short circuit) condition only in the discharge direction. Overcurrent protection is asserted when either of the conditions occurs and remain for a time exceeding a user-configurable delay (tOCD): Overvoltage Overvoltage (or overcharge) protection is asserted when any cell voltage exceeds the VOV threshold and remains above the VOV threshold for a time exceeding a userconfigurable delay (tOVD). The CHG pin is driven high, disabling charge into the battery pack. Charging is disabled until a valid charge enable exists. See Charge Enable section. CSL > BAT4N + VOCL CSH < BAT1P - VOCH where: VOCL = 160mV (low-side detect) VOCH = 160mV (high-side detect) Important note: If any battery pin floats (BAT1P, BAT1N–4N), the bq2058 assumes an overvoltage has occurred. When either of these conditions occurs, DSG is driven high, disconnecting the load from the pack. DSG remains high until both of the voltage conditions are false, indicating removal of the short-circuit condition. The user can facilitate clearing these conditions by inserting the battery pack into a charger. Because of different manufacturers specifications for overvoltage thresholds, the bq2058 can be available with different VOV options. Table 2 summarizes these different voltage thresholds. The low-side overcurrent sense can be disabled by connecting CSL to BAT4N. This ensures that CSL is never greater than BAT4N. If low-side detection is disabled, high-side detection must be used with CSH. 5 bq2058 The FETs in the charge/discharge path controlled by the CHG and DSG pins affect the overcurrent level. The on-resistance of these FETs need to be taken into account when determining overcurrent levels. Condition Normal operation Overvoltage Undervoltage Overcurrent Floating battery input CTL = high CHG pin Low High Low Low High High Pack Disable Input–CTL The CTL pin is used to electrically disconnect the battery from the pack terminals through an externally supplied signal. When CTL is taken high, CHG and DSG are driven high. Any load on the pack terminals will be interpreted as an overcurrent condition by the bq2058 with the overcurrent delay timer held in reset. When the CTL pin is driven low, the overcurrent delay timer is allowed to start. If the programmed delay (tOCD) is too short, the overcurrent recovery circuit, if implemented, will be unable to correct the overcurrent situation prior to the delay time-out. It is recommended that a delay time of greater than 10ms (COCD ≥ 0.01µF) be used if the CTL pin function is used. DSG pin Low Low High High Indeterminate High Important note: If CTL floats, it is internally pulled high making both DSG and CHG inactive, thus disabling the pack. If CTL is not used, it should be tied to VSS. CHG and DSG States The CHG and DSG output truth table is shown below. The polarity of CTL is mask programmable at Unitrode. Please contact Unitrode for other polarity options. The polarities of CHG and DSG are mask programmable at Unitrode. Push-pull vs. open-drain configuration is also mask-configurable at Unitrode. Please contact Unitrode for availability of these variations. Protection Delay Timers The delay time between the detection of an overcurrent, overvoltage, or undervoltage condition and the deactivation of the CHG and/or DSG outputs is user-configurable by the selection of capacitor values between VCC and OCD, OVD, and UVD pins (respectively). See Table 3 below. Number of Cells The user must configure the bq2058 for three- or fourseries cell operation. For a three-cell pack, NSEL should be tied directly to VSS. For a four-cell pack, NSEL should be connected directly to VCC. Number of Series Cells 3-cell 4-cell The fault condition must persist through the entire delay period, or the bq2058 may not deactivate either FET control output. NSEL Tied to VSS Tied to VCC Figure 3 shows a step-by-step event cycle for the bq2058. Table 3. Protection Delay Timers Protection Feature Overcurrent Typical Delay Period Capacitor from VCC to: Capacitor Time tOCD OCD 0.010µF 12ms Tolerance ±40% Overvoltage tOVD OVD 0.100µF 950ms ±40% Undervoltage tUVD UVD 0.100µF 950ms ±40% Notes: 1. The delay time versus capacitance can be approximated by the following equations:. For tOCD: t(s) ≈ 1.2 ∗ C(µf), where C ≥ 0.001µF For tOVD, tUVD: t(s) ≈ 9.5 ∗ C(µf), where C ≥ 0.01µF 2. Overvoltage and undervoltage conditions are sampled by the bq2058. The delay in Table 2 is in addition to the time required for the bq2058 to detect the violation, which may vary from 0 to 160 ms depending on where in the sampling period the violation occurs. Overcurrent is continuously monitored and is subject to a delay of approximately 1.5ms. 6 bq2058 0 1 2 3 4 5 VOV 6 7 8 9 10 11 12 VCE VUV Cell Voltage BAT1P + 70mV (VCD) CSH BAT1P - 160mV (VOCH) DSG tOCD tUVD CHG tOVD CTL TD205801.eps Figure 3. Protector Event Diagram Event Definition: 0: The bq2058 is in the low-power sleep mode because one or more of the cell voltages are below VUV. 1: A charger is applied to the pack, causing the difference between CSH and BAT1P to become greater than 70mV. This awakens the bq2058, and the discharge pin DSG goes low. 2: One or more cells charge to a voltage equal to VOV, initiating the overvoltage delay timer. 3: The overvoltage delay time expires, causing CHG to be driven high. 4: All cell voltages fall below VCE, causing CHG to be driven low. 5: Stop charging, apply a load. 6: An overcurrent condition is detected, initiating the overcurrent delay timer. 7: The overcurrent delay time expires, causing DSG to be driven high. 8: The overcurrent condition is no longer present; DSG is driven low. 9: Pin CTL is driven high; both DSG and CHG are driven high. 10: Pin CTL is driven low; both DSG and CHG resume their normal function. 11: One or more cells fall below VUV, initiating the overdischarge delay timer. 12: Once the overdischarge delay timer expires, if any of the cells is below VUV, the bq2058 drives DSG high and enters the low-power sleep mode. 7 bq2058 Absolute Maximum Ratings Symbol Parameter Value Unit 18 V Conditions VCC Supply voltage TOPR Operating temperature -30 to +70 °C TSTG Storage temperature -55 to +125 °C TSOLDER Soldering temperature 260 °C For 10 seconds IIN Maximum input current ±100 µA All pins except VCC, VSS Notes: Relative to VSS 1 Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. 2. Internal protection diodes are in place on every pin relative to VCC and VSS. See Figure 4. VCC Any pin VSS FG2058x .eps Figure 4. Internal Protection Diodes 8 bq2058 DC Electrical Characteristics (TA = TOPR) Symbol Parameter Minimum Typical Maximum Unit VCC - 0.5 - - V Conditions/Notes VOH Output high voltage VOL Output low voltage - - VSS + 0.5 V IOL = 10µA, CHG, DSG VOP Operating voltage 4 - 18.0 V VCC relative to VSS VIL Input low voltage - - VSS + 0.5 V Pin CTL VIH Input high voltage VSS + 2.0 - - V Pin CTL VIL Input low voltage - - VSS + 0.5 V Pin NSEL VIH Input high voltage VCC - 0.5 - - - Pin NSEL ICCA Active current - 25 40 µA ICCS Sleep current - 0.7 1.5 µA IOH = 10µA, CHG, DSG DC Thresholds (TA = TOPR) Symbol VOV Parameter Overvoltage threshold (See Figure 5) Value Unit Tolerance 4.25 V ±50mV See note 1 4.375 V ±55mV For bq2058G only See note 3 Table 2 VCE Charge enable threshold VUV Undervoltage threshold VOCH Conditons Customer option VOV - 150mV V ±50mV VOV - 200mV V ±50mV For bq2058W only 2.25 V ±100mV 2.10 V ±100mV Overcurrent detect high-side 160 mV ±35mV VOCL Overcurrent detect low-side 160 mV ±35mV VCD Charge detect threshold 70 mV -60mV, +80mV tOVD Overvoltage delay threshold 950 ms ±40% COVD = 0.100µF, TA = 30°C See note 2 tUVD Undervoltage delay threshold 950 ms ±40% CUVD = 0.100µF, TA = 30°C See note 2 tOCD Overcurrent delay threshold 12 ms ±40% COCD = 0.01µF, TA = 30°C Notes: For bq2058W only 1. Standard device. Contact Unitrode for different thresholds and tolerance options. 2. Does not include cell sampling delay, which may add up to 160ms of additional delay until the condition is detected. 3. bq2058G is designed only for 3-cell applications. 9 bq2058 Impedance RCELL Parameter Minimum Typical Maximum Unit - 10 - MΩ Input impedance Notes Pins BAT1P, BAT1N-4N, CSH, CSL 4.280 4.270 VOV – Overvoltage – V Symbol 4.260 4.250 4.240 4.230 Measurement accuracy ± 2mV 4.220 4.210 -30 -20 -10 0 10 20 30 40 50 60 70 TA – Free-Air Temperature – ˚C Gr2058.eps Figure 5. bq2058 4.25V Overvoltage Threshold vs. Free-Air Temperature 10 bq2058 Data Sheet Revision History Change No. Page No. 1 1, 2, 5 PACK+, PACK- Pins renamed to CSH and CSL respectively 1 1 Pin description Added CSH/CSL description 1 3 Block diagram Update Block diagram 1 4 Figure 2 Update typical application circuit 1 4 Configuration description Correction to description 1, 2 5 Overcurrent limits Was: VOCH = 150mV ± 25mV VOCL = 85mV ± 25mV Is: VOCH = 160mV ± 25mV VOCL = 100mV ± 25mV 1 7 Figure 3 Update Event diagram DC threshold Was: VOCH = 150mV ± 25mV VOCL = 100mV ± 80mV VCD = 70mV -60, +50mV Is: VOCH = 160mV ± 25mV VOCL = 100mV ± 25mV VCD = 70mV -60, +80mV High-side overcurrent monitored Was: Between VCC and CSH, Is: Between BAT1P and CSH Overvoltage threshold options Added bq2058R Overcurrent limit Was: VOCL = 100mV, Is: VOCL = 150mV Figure 2 Corrected schematic Protection Delay Times Was: tOCD = 10ms ±30% tOVD = 800ms ±30% tUVD = 800ms ±40% Is: tOCD = 12ms ±40% tOVD = 950ms ±40% tUVD = 950ms ±40% 1, 2 9 3 1, 3, 5 3 4 3 3, 5 4 4 4 6, 8 Description Nature of Change 4 10 Overcurrent limits Was: VOCH = 160mV ±25mV VOCL = 150mV ±25mV Is: VOCH = 160mV ±35mV VOCL = 160mV ±35mV 5 5, 9 Overvoltage threshold Charge enable threshold Undervoltage threshold Added bq2058W 6 9 7 5, 9 8 4 Notes: DC electrical characteristics Was: Minimum VOP = 0V, Is: Minimum VOP = 4V Overvoltage threshold Added bq2058C and bq2058G Reference circuit amended Moved D1 to new location Change 1 = Feb. 1997 B changes from Jan. 1997 A. Change 2 = April 1997 C changes from Feb. 1997 B. Change 3 = June 1997 D changes from April 1997 C. Change 4 = July 1997 E changes from June 1997 D. Change 5 = Feb. 1998 F changes from July 1997 E. Change 6 = May 1998 G changes from Feb. 1998 F. Change 7 = June 1998 H changes from May 1998 G. Change 8 = Jan. 1999 I changes from June 1998 H. 11 bq2058 SN: 16-Pin SN (0.150" SOIC) 16-Pin SN (0.150" SOIC) Inches D e E H A C Min. Max. Min. Max. A 0.060 0.070 1.52 1.78 A1 0.004 0.010 0.10 0.25 B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.18 0.25 D 0.385 0.400 9.78 10.16 E 0.150 0.160 3.81 4.06 Dimension B A1 .004 L 12 Millimeters e 0.045 0.055 1.14 1.40 H 0.225 0.245 5.72 6.22 L 0.015 0.035 0.38 0.89 bq2058 Ordering Information bq2058 XXXX Standard Device: Blank = Standard device XXXX = Customer code assigned by Benchmarq Package Option: SN = 16-pin narrow SOIC Overvoltage Threshold Blank = 4.25V (Standard device) Contact Factory for availability of other thresholds Device: bq2058 Lithium Ion Pack Supervisor Package Devices TA -30°C To +70°C VOV Threshold 3.4V 16-pin Narrow SOIC (SN) 4.15V bq2058MSN bq2058WSN 4.20V bq2058FSN 4.225V bq2058KSN 4.25V bq2058SN 4.325V bq2058CSN 4.30V bq2058DSN 4.35V bq2058RSN 4.36V bq2058JSN 4.375V bq2058GSN Notes: bq2058SN is Standard Device. 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