AD ADATE320KCPZ 1.25 ghz dual integrated dcl Datasheet

1.25 GHz Dual Integrated DCL with PPMU, Level
Setting DACs, and On-Chip Calibration Registers
ADATE320
Data Sheet
FEATURES
GENERAL DESCRIPTION
1.25 GHz, 2.5 Gbps data rate
3-level driver with high-Z and reflection clamps
Window and differential comparators
±25 mA active load
Per pin parametric measurement unit (PMU) with a −1.5 V to
+4.5 V range
Low leakage mode (typically <5 nA)
Integrated 16-bit DACs with offset and gain correction
1.2 W power dissipation per channel (ADATE320)
1.3 W power dissipation per channel (ADATE320-1)
Driver
Voltage range: −1.5 V to +4.5 V
Precision trimmed termination: 50.0 Ω
Unterminated swing: 50 mV minimum to 6.0 V maximum
400 ps minimum pulse width, 1.0 V programmed swing
25 ps deterministic jitter
Comparator
Differential and single-ended window modes
100 ps equivalent input rise/fall time (ERT/EFT)
250 mV current mode logic (CML) outputs (ADATE320)
400 mV CML outputs (ADATE320-1)
Load
Per pin PMU (PPMU)
Force voltage/compliance range: −1.5 V to +4.5 V
5 current ranges
±40 mA, ±1 mA, ±100 μA, ±10 µA, ±2 µA
Dedicated go/no-go comparators
DC levels
Fully integrated and dedicated 16-bit DACs
On-chip gain and offset calibration registers with
automatic add/multiply function
84-lead, 10 mm × 10 mm LFCSP (0.4 mm pitch)
The ADATE320 is a complete, single-chip ATE solution that
performs the pin electronics functions of a driver, comparator,
and active load (DCL), and a four quadrant per pin parametric
measurement unit (PPMU). Dedicated 16-bit digital-to-analog
converters (DACs) with on-chip calibration registers provide all
the necessary dc levels for operation of the device.
APPLICATIONS
Automatic test equipment (ATE)
Semiconductor/board test systems
Instrumentation and characterization equipment
Rev. B
The driver features three active modes: high, low, and terminate, as
well as a high impedance inhibit state. The inhibit state, in
conjunction with the integrated dynamic clamps, facilitates
significant attenuation of transmission line reflections when the
driver is not actively terminating the line. The open-circuit drive
capability is −1.5 V to +4.5 V to accommodate a standard range
of ATE and instrumentation applications.
The ADATE320 can be used as a dual, single-ended pin
electronics channel or as a single differential channel. In
addition to per channel high speed window comparators, the
ADATE320 provides a programmable threshold differential
comparator for differential ATE applications.
All dc levels for DCL and PPMU functions are generated by
dedicated, on-chip, 16-bit DACs. To facilitate the programming
of accurate levels, the ADATE320 includes an integrated
calibration function to correct for the gain and offset errors of
each functional block. Correction coefficients can be stored on
chip, and any values written to the DACs adjust automatically
using the appropriate correction factors.
The ADATE320 uses a serial programmable interface (SPI) bus
to program all functional blocks, DACs, and on-chip calibration
constants. It also has an on-chip temperature sensor and overvoltage/undervoltage fault clamps that monitor and report the
device temperature and any output pin or transient PPMU
voltage faults that may occur during operation.
The ADATE320 is available in two options. The standard option
has high speed comparator outputs with 250 mV output swing.
The ADATE320-1 has 400 mV output swing. See the Ordering
Guide for more information.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADATE320* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
DISCUSSIONS
View a parametric search of comparable parts.
View all ADATE320 EngineerZone Discussions.
DOCUMENTATION
SAMPLE AND BUY
Data Sheet
Visit the product page to see pricing options.
• ADATE320: 1.25 GHz Dual Integrated DCL with PPMU,
Level Setting DACs, and On-Chip Calibration Registers
Data Sheet
TECHNICAL SUPPORT
DESIGN RESOURCES
Submit a technical question or find your regional support
number.
• ADATE320 Material Declaration
DOCUMENT FEEDBACK
• PCN-PDN Information
Submit feedback for this data sheet.
• Quality And Reliability
• Symbols and Footprints
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
ADATE320
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Characteristics ............................................................ 25
Applications ....................................................................................... 1
Explanation of Test Levels ......................................................... 25
General Description ......................................................................... 1
ESD Caution................................................................................ 25
Revision History ............................................................................... 2
User Information and Truth Tables ......................................... 26
Functional Block Diagram .............................................................. 3
Pin Configuration and Function Descriptions........................... 28
Specifications..................................................................................... 4
Typical Performance Characteristics ........................................... 30
Electrical Specifications ............................................................... 4
Theory of Operation ...................................................................... 50
Driver Specifications .................................................................... 5
Serial Programmable Interface (SPI) ....................................... 50
Reflection Clamp Specifications ................................................. 7
Level Setting DACs .................................................................... 52
Normal Window Comparator (NWC) Specifications ............. 8
Alarm Functions ......................................................................... 59
Differential Mode Comparator (DMC) Specifications ......... 10
Applications Information .............................................................. 62
Active Load Specifications ........................................................ 11
PPMU Specifications ................................................................. 13
Power Supply, Grounding, and Typical Decoupling Strategy
....................................................................................................... 62
PPMU Go/No-Go Comparators Specifications ..................... 18
Power Supply Sequencing ......................................................... 64
PPMU External Sense Pins Specifications .............................. 18
Detailed Functional Block Diagrams ........................................... 65
VREF, VREFGND, and DUTGND Reference Input Pins
Specifications .............................................................................. 19
SPI Register Memory Map and Details ....................................... 71
Temperature Monitor Specifications ....................................... 19
Register Details ........................................................................... 74
Alarm Functions Specifications................................................ 19
Default Test Conditions ................................................................. 80
Serial Programmable Interface (SPI) Specifications .............. 20
External Components .................................................................... 81
SPI Timing Specifications ......................................................... 20
Outline Dimensions ....................................................................... 82
SPI Timing Diagrams................................................................. 21
Ordering Guide .......................................................................... 82
Memory Map .............................................................................. 71
Absolute Maximum Ratings .......................................................... 25
REVISION HISTORY
9/2016—Rev. A to Rev. B
Changes to Time Constant 1 Parameter and Time Constant 2
Parameter, Table 2............................................................................. 7
Changes to IOx Offset Parameter, and IOHx Offset
Parameter, Table 6........................................................................... 11
Change to AGND Pin Number Column ..................................... 29
Change to SPI Reset Sequence and the RST Pin Section .......... 50
Changes to the SPI Clock Cycles and BUSY Pin Section .......... 51
Changes to Table 24 ........................................................................ 54
Changes to Figure 137 .................................................................... 65
10/2015—Revision A: Initial Version
Rev. B | Page 2 of 82
Data Sheet
ADATE320
FUNCTIONAL BLOCK DIAGRAM
POH0
OVDH
PPMU
GO/NO-GO
PPMU_CMP0
TO ALARM
(HIGH/LOW
CLAMP FAULT)
TO ALARM
(HIGH/LOW
VOLTAGE FAULT)
OVDL
POL0
MUX
PPMU_M0
PPMU_S0
OVER
VOLTAGE
THERM
PMU0
PCH0
PCL0
OUT
PMU
MUX
F
S
VCH0
VCL0
VIH0
VIT0/VCOM0
VIL0
VTTD0
50Ω
DRIVER
DAT0/DAT0
50Ω
MUX
DUT0
RCV0/RCV0
LOAD
+
–
IOH0
VOH0
NWC
CMPH0/CMPH0
COMPARATOR
CMPL0/CMPL0
DIFF
NWC
VOL0
CHANNEL 0
VTHERM
TEMP
SENSOR
ALARM
ALARM
VCC
VDD
SDI
DGND
SCLK
SPI
GAIN/OFFSET
CORRECTION
MUX
SDO
2 × 16
16-BIT DACs
BUSY
RST
AGND
PGND
VEE
COMMON
CHANNEL 1
(SAME AS CHANNEL 0 EXCEPT WHERE NOTED ABOVE)
Figure 1.
Rev. B | Page 3 of 82
12160-001
CS
CH0 ONLY
(FROM DUT)
50Ω
IOL0
DAT1
RCV1
(FROM CHANNEL 1)
VTTC0
DAT0
RCV0
(TO CHANNEL 1)
MUX
ADATE320
Data Sheet
SPECIFICATIONS
VCC = 8.0 V, VDD = 1.8 V, VEE = −5.0 V, VTTCx = VTTDx = 1.2 V, VREF = 2.500 V, VREFGND = 0.000 V. All default test conditions are as defined in
Table 30. All specified values are at TJ = 60°C, where TJ corresponds to the typical internal temperature sensor reading (VTHERM pin), unless
otherwise noted. Temperature coefficients are measured around TJ = 40°C, 60°C, 80°C, and 100°C. Typical values are based on the
statistical mean of the design, simulation analyses, and/or limited bench evaluation data. Typical values are neither tested nor guaranteed.
Test level codes are defined in the Explanation of Test Levels section.
ELECTRICAL SPECIFICATIONS
Table 1.
Parameter
DUTx PIN CHARACTERISTICS
Output Leakage Current
DCL Disable
PPMU Range E
PPMU Range A to
Range D
Driver High-Z Mode
Capacitance
Voltage Range
POWER SUPPLIES
Positive DCL Supply, VCC
Negative DCL Supply, VEE
Digital Supply, VDD
Comparator Termination,
VTTCx
Driver Termination, VTTDx
Positive DCL Supply
Current, ICC
ADATE320
ADATE320-1
Negative DCL Supply
Current, IEE
ADATE320
ADATE320-1
Digital Core Supply
Current, IDD
Comparator Termination
Supply Current, VTTCx
ADATE320
ADATE320-1
Driver Termination Supply
Current, VTTDx
Total Power Dissipation
ADATE320
ADATE320-1
Min
Typ
Max
Unit
Test Level
Test Conditions/Comments
−10.0
+5.0
+10.0
nA
P
nA
CT
+0.4
µA
P
+4.5
pF
V
S
D
−1.5 V < VDUTx < +4.5 V, PPMU and DCL disabled, PPMU
Range E, VCLx = −2.5 V, VCHx = +7.5 V
−1.5 V < VDUTx < +4.5 V, PPMU and DCL disabled, PPMU Range A,
Range B, Range C, and Range D, VCLx = −2.5 V, VCHx = +7.5 V
−1.5 V < VDUTx < +4.5 V, PPMU disabled and DCL enabled,
RCV active, VCLx = −2.5 V, VCHx = +7.5 V
Drive VITx = 0.0 V
5.0
−0.4
0.4
−1.5
7.6
−5.25
1.7
0.5
8.0
−5.0
1.8
1.2
8.4
−4.75
1.9
1.8
V
V
V
V
D
D
D
D
0.0
1.2
1.8
V
D
145
145
169
169
185
185
mA
mA
P
P
Power measured with the DUTx pin high-Z, 10 K to 0.0 V
Defines dc power supply rejection (PSR) conditions
Defines dc PSR conditions
VTTC0 is not electrically connected to VTTC1
VTTD0 is not electrically connected to VTTD1
Load and PPMU power-down
Load and PPMU power-down
190
220
−125
222
247
+10
235
265
+125
mA
mA
μA
P
P
P
Quiescent (SPI is static)
0.5 V ≤ VTTCx ≤ 1.8 V
41
66
0
mA
mA
mA
CT
CT
CT
W
W
P
P
0.0 V ≤ VTTDx ≤ 1.8 V, (DATx + DATx)/2 = (RCVx + RCVx)/2 = VTTDx
Load and PPMU power-down
2.10
2.25
2.52
2.66
2.75
2.90
Rev. B | Page 4 of 82
Data Sheet
ADATE320
DRIVER SPECIFICATIONS
VIH − VIL ≥ 100 mV to meet dc and ac performance specifications.
Table 2.
Parameter
DC SPECIFICATIONS
High Speed Differential Input
Characteristics
High Speed Input Termination
Resistance: DATx/DATx,
RCVx/RCVx
Input Voltage Range:
DATx/DATx, RCVx/RCVx
Input Voltage Differential
Output Characteristics
Output Range
High, VIH
Low, VIL
Output Term Range, VIT
Functional Amplitude (VIH −
VIL)
DC Output Current Limit
Source
Sink
Output Resistance, ±40 mA
Min
Typ
Max
Unit
Test
Level
48
50
52
Ω
P
1.8
V
PF
1.0
V
PF
−1.4
−1.5
−1.5
0.05
+4.5
+4.4
+4.5
6.0
V
V
V
V
D
D
D
D
75
−120
46
120
−75
52
mA
mA
Ω
P
P
P
Drive high, VIH = 4.5 V, VDUTx = −2.0 V, measure current
Drive low, VIL = −1.5 V, VDUTx = 5.0 V, measure current
∆VDUTx/∆IDUTx; source: VIHx = 3.0 V, IDUTx = 1 mA, 40 mA;
sink: VIL = 0.0 V, IDUTx = −1 mA, −40 mA
VIH tests with VIL = −2.5 V, VIT = −2.5 V; VIL tests with VIH =
7.5 V, VIT = 7.5 V; VIT tests with VIL = −2.5 V, VIH = 7.5 V,
unless otherwise noted within this parameter
+500
mV
µV/°C
P
CT
Measured at DAC Code 0x4000 (0.0 V), uncalibrated
1.1
V/V
P
Gain derived from measurement at DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V); based on an ideal
DAC transfer function (see Table 24)
ppm/°C
µV
CT
CT
0.0
0.2
0.4
48.5
DC ACCURACY
VIH, VIL, VIT
Offset Error
Offset Temperature Coefficient
(TC)
Gain
−500
±200
1.0
Gain TC
Differential Nonlinearity
(DNL)
±50
±250
Integral Nonlinearity (INL)
Focused Range
−5
+5
mV
P
INL Full Range
−20
+20
mV
P
+5
µV
mV
D
P
Resolution
DUTGND Voltage Accuracy
−5
153
±1
DC Levels Interaction
VIH vs. VIL
±1.0
mV
CT
VIH vs. VIT
±1.0
mV
CT
VIL vs. VIH
±1.0
mV
CT
Rev. B | Page 5 of 82
Test Conditions/Comments
Impedance between VTTDx and respective DATx and
RCVx pins; force 4 mA into each pin, measure voltage
from VTTDx; calculate resistance (∆V/∆I)
|DATx − DATx|, |RCVx − RCVx|
After two-point gain/offset calibration; calibration
points at 0x4000 (0.0 V) output; 0x8CCC (3.0 V);
measured over full specified output range
After two-point gain/offset calibration; calibration
points at 0x4000 (0.0 V) and 0x8CCC (3.0 V); measured
over −0.5 V to +3.5 V output range
After two-point gain/offset calibration; calibration
points at 0x4000 (0.0 V) and 0x8CCC (3.0 V); measured
over full specified output range
Over ±0.1 V range; measured over −0.5 V to +3.5 V
focused driver output range
DC interaction on VIL, VIH, and VIT output levels while
other driver DAC levels are varied
Monitor interaction on VIH = +4.5 V; sweep VIL = −1.5 V
to +4.4 V, VIT = +1.0 V
Monitor interaction on VIH = +4.5 V; sweep VIT = −1.5 V
to +4.5 V, VIL = 0.0 V
Monitor interaction on VIL = −1.5 V; sweep VIH = −1.4 V
to +4.5 V, VIT = +1.0 V
ADATE320
Parameter
VIL vs. VIT
Data Sheet
Min
Typ
±1.0
Max
Unit
mV
Test
Level
CT
Test Conditions/Comments
Monitor interaction on VIL = −1.5 V; sweep VIT = −1.5 V
to +4.5 V, VIH = +2.0 V
Monitor interaction on VIT = 1.0 V; sweep VIH = −1.4 V to
+4.5 V, VIL = −1.5 V
Monitor interaction on VIT = 1.0 V; sweep VIL = −1.5 V to
+4.4 V, VIH = +4.5 V
VIH − VIL ≥ 100 mV; sum of INL, dc interaction, DUTGND
and TC errors over ±5°C, after calibration
Measured at calibration points, see Table 1 for power
supply ranges
All ac specifications performed after dc calibration
Toggle DATx, VIL = 0.0 V, terminated
VIT vs. VIH
±2.0
mV
CT
VIT vs. VIL
±2.0
mV
CT
±5
mV
CT
+15
mV/V
CT
150
170
ps
ps
CB
CB
20% to 80%, VIH = 0.2 V
20% to 80%, VIH = 0.2 V
150
170
ps
ps
CB
CB
20% to 80%, VIH = 0.5 V
20% to 80%, VIH = 0.5 V
150
170
ps
ps
CB
CB
20% to 80%, VIH = 1.0 V
20% to 80%, VIH = 1.0 V
ps
ps
P
P
20% to 80%, VIH = 2.0 V
20% to 80%, VIH = 2.0 V
320
320
−20
ps
ps
ps
CB
CB
CB
±15
±15
±15
±15
ps
ps
ps
ps
CB
CB
CB
CB
2.8
3.2
3.2
2.8
Gbps
Gbps
Gbps
Gbps
CB
CB
CB
CB
10% to 90%, VIH = 4.0 V, unterminated
10% to 90%, VIH = 4.0 V, unterminated
tRISE − tFALL (20% to 80%) within one channel, VIH = 2.0 V,
VIL = 0.0 V, terminated
Toggle DATx
VIL = 0.0 V, terminated, 400 ps ≤ pulse width (PW) ≤ 10 ns
VIH = 0.2 V
VIH = 0.5 V
VIH = 1.0 V
VIH = 2.0 V
Toggle DATx
VIL = 0.0 V, terminated ≤10% amplitude loss
VIH = 0.2 V
VIH = 0.5 V
VIH = 1.0 V
VIH = 2.0 V
Toggle DATx, drive VIL to/from VIH
VIH = 2.0 V, VIL = 0.0 V, terminated
750
2
ps
ps/°C
CB
CT
10
35
±7
50
ps
ps
ps
mV
CB
CB
CB
CB
1
10
ns
ns
CB
CB
Overall Voltage Accuracy Focused
Range
VIH, VIL, VIT DC PSR
AC SPECIFICATIONS
Rise/Fall Times
0.2 V Programmed Swing
tRISE
tFALL
0.5 V Programmed Swing
tRISE
tFALL
1.0 V Programmed Swing
tRISE
tFALL
2.0 V Programmed Swing
tRISE
tFALL
4.0 V Programmed Swing
tRISE
tFALL
tRISE to tFALL Mismatch
Trailing Edge Timing Error
Programmed Swing
0.2 V
0.5 V
1.0 V
2.0 V
Maximum Toggle Rate
Programmed Swing
0.2 V
0.5 V
1.0 V
2.0 V
Dynamic Performance
Propagation Delay
Time
TC
Delay Matching
Edge to Edge
Channel to Channel
Delay Change vs. Duty Cycle
Overshoot and Undershoot
Settling Time (VIH to VIL)
To Within 3% of Final Value
To Within 1% of Final Value
120
120
160
180
230
230
Rev. B | Page 6 of 82
VIH = 2.0 V, VIL = 0.0 V, terminated
tLH0 − tHL0; tLH1 − tHL1
tLH0 − tLH1; tHL0 − tHL1
VIH = 2.0 V, VIL = 0.0 V, terminated, 1 MHz, 5% to 95%
VIH = 2.0 V, VIL = 0.0 V, terminated, minimum driver CLC
Toggle DATx
VIH = 2.0 V, VIL = 0.0 V, from 50% crossing, terminated
VIH = 2.0 V, VIL = 0.0 V, from 50% crossing, terminated
Data Sheet
Parameter
Dynamic Performance
Drive Active to/from VIT
Transition Time
Active to VIT
VIT to Active
Propagation Delay
TC
Drive Active to/from Inhibit
Transition Time
Inhibit to Active
Active to Inhibit
Propagation Delay
Inhibit to VIH
Inhibit to VIL
Matching Inhibit to VIL vs.
Inhibit to VIH
VIH to Inhibit
VIL to Inhibit
Input/Output Spike
Cable Loss Compensation (CLC)
Amplitude
Resolution
Time Constant 1
Time Constant 2
ADATE320
Min
Typ
Max
Test
Level
Unit
Test Conditions/Comments
Toggle RCVx, VIH = 2.0 V, VIT = 1.0 V, VIL = 0.0 V, terminated
20% to 80%
200
170
1.0
2
ps
ps
ns
ps/°C
CB
CB
CB
CT
Toggle RCVx, VIH = 1.0 V, VIL = −1.0 V, terminated
20% to 80%
250
850
ps
ps
CB
CB
2.1
2.5
0.4
ns
ns
ns
CB
CB
CB
2.5
2.1
125
ns
ns
mV p-p
CB
CB
CB
20
3
400
1.5
%
Bits
ps
ns
CB
D
S
S
VIH = 0.0 V, VIL = 0.0 V, terminated, toggle RCVx
VIH = 2.0 V, VIL = 0.0 V, terminated
Maximum CLC setting
Maximum CLC setting
Maximum CLC setting
REFLECTION CLAMP SPECIFICATIONS
Clamp accuracy specifications apply only when VCHx − VCLx > 0.8 V.
Table 3.
Parameter
VCH
Functional Range
Offset Error
Offset TC
Gain
Min
−0.5
−300
VCL
Functional Range
Offset Error
Offset TC
Max
Unit
Test
Level
+5.0
+300
V
mV
D
P
1.1
mV/°C
V/V
CT
P
ppm/°C
µV
µV
CT
D
CT
±0.25
1.0
Gain TC
Resolution
DNL
INL
Typ
±25
153
±250
−20
+20
mV
P
−2.0
−300
+3.5
+300
V
mV
D
P
mV/°C
CT
±0.25
Rev. B | Page 7 of 82
Test Conditions/Comments
Driver high-Z, sinking 1 mA, measured at DAC Code 0x4000
(0.0 V), uncalibrated
Driver high-Z, sinking 1 mA, gain derived from measurements
at DAC Code 0x4000 (0.0 V) and DAC Code 0x8CCC (3.0 V),
based on an ideal DAC transfer function (see Table 24)
Driver high-Z, sinking 1 mA, after two-point gain/offset
calibration; calibration points at DAC Code 0x4000 (0.0 V)
and DAC Code 0x8CCC (3.0 V), measured over the
functional range
Driver high-Z, sinking 1 mA, after two-point gain/offset
calibration; calibration points at DAC Code 0x4000 (0.0 V)
and DAC Code 0x8CCC (3.0 V), measured over the
functional range
Driver high-Z, sourcing 1 mA, measured at DAC Code 0x4000
(0.0 V), uncalibrated
ADATE320
Data Sheet
Parameter
Gain
Min
1.0
Gain TC
Resolution
DNL
Typ
Max
1.1
±25
153
±250
INL
DC CLAMP CURRENT LIMIT
VCHx
VCLx
DUTGND VOLTAGE ACCURACY
Unit
V/V
Test
Level
P
ppm/°C
µV
µV
CT
D
CT
−20
+20
mV
P
−105
+60
−10
−60
+105
+10
mA
mA
mV
P
P
P
±2
Test Conditions/Comments
Drive high-Z, sourcing 1 mA, gain derived from measurements at DAC Code 0x4000 (0.0 V) and DAC Code 0x8CCC
(3.0 V), based on an ideal DAC transfer function (see Table 24)
Drive high-Z, sourcing 1 mA, after two-point gain/offset
calibration; calibration points at DAC Code 0x4000 (0.0 V)
and DAC Code 0x8CCC (3.0 V), measured over the
functional range
Drive high-Z, sourcing 1 mA, after two-point gain/offset
calibration; calibration points at DAC Code 0x4000 (0.0 V)
and DAC Code 0x8CCC (3.0 V), measured over the
functional range
Drive high-Z
VCHx = −1.0 V, VCLx = −2.0 V, VDUTx = 4.5 V
VCHx = 5.0 V, VCLx = 4.0 V, VDUTx = −1.5 V
Over ±0.1 V range, measured at end points of VCHx and
VCLx functional range
NORMAL WINDOW COMPARATOR (NWC) SPECIFICATIONS
Table 4.
Parameter
DC SPECIFICATIONS
Input Voltage Range
Differential Voltage Range
Input Offset Voltage
Input Offset Voltage TC
Gain
Min
Typ
−1.5
±0.1
−250
Max
Unit
Test
Level
Test Conditions/Comments
+4.5
±6.0
+250
V
V
mV
D
D
P
Measured at DAC Code 0x4000 (0.0 V); uncalibrated
1.1
µV/°C
V/V
CT
P
ppm/°C
µV
mV
CT
D
CT
mV
mV
mV
P
P
P
±150
1.0
Gain TC
Threshold Resolution
Threshold DNL
±10
153
±0.25
Threshold INL
Focused Range
Full Range
DUTGND Voltage Accuracy
−5
−7
−5
±1
+5
+7
+5
Uncertainty Band
10
mV
CB
Programmable Hysteresis
Hysteresis Resolution
DC PSR
100
4
±5
mV
Bits
mV/V
CB
D
CT
Ω
P
Digital Output
Characteristics
Internal Pull-up
Resistance to
Comparator, VTTCx
46
50
54
Rev. B | Page 8 of 82
Gain derived from measurements at DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V); based on an ideal
DAC transfer function (see Table 24)
Measured over −1.5 V to +4.5 V functional range after
two-point gain/offset calibration; calibration points at
DAC Code 0x4000 (0.0 V) and DAC Code 0x8CCC (3.0 V)
After two-point gain/offset calibration; calibration points
at DAC Code 0x4000 (0.0 V) and DAC Code 0x8CCC (3.0 V)
Measured over −0.5 V to +3.5 V range
Measured over −1.5 V to +4.5 V range
Over ±0.1 V range; measured over −0.5 V to +3.5 V focused
NWC input range
VDUTx = 0.0 V, sweep comparator threshold to determine
the uncertainty band
Measured at DAC Code 0x4000 (0.0 V) and DAC Code 0x8CCC
(3.0 V) calibration points
Source 1 mA and 10 mA from the output pin in high state,
measure ∆V to calculate resistance; R = ∆V/9 mA; repeat
for all output pins
Data Sheet
Parameter
Common-Mode Voltage
ADATE320
ADATE320-1
Differential Mode Voltage
100 Ω Differential
Termination
ADATE320
ADATE320-1
No External Termination
ADATE320
ADATE320-1
AC SPECIFICATIONS
ADATE320
Min
Typ
Max
−250
−400
Unit
Test
Level
mV
mV
CT
CT
Test Conditions/Comments
Measured relative to VTTCx, with 100 Ω differential termination
Measured differentially
250
400
450
700
500
800
550
900
mV
mV
CT
CT
mV
mV
P
P
Unless otherwise specified, all ac tests are performed after
dc levels calibration; input transition time: 50 ps 20% to
80%; outputs terminated 50 Ω to 0.0 V; comparator CLC set
to ¼ scale (010)
Measured with 50 Ω to 0.0 V
VDUTx = 0.0 V to 1.0 V swing, drive term mode, VIT = 0.0 V,
comparator threshold = 0.5 V
VDUTx = 0.0 V to 1.0 V swing, drive term mode, VIT = 0.0 V,
comparator threshold = 0.5 V
VDUTx = 0.0 V to 1.0 V swing, drive term mode, VIT = 0.0 V,
comparator threshold = 0.5 V
Rise/Fall Times, 20% to 80%
Propagation Delay
100
580
ps
ps
CB
CB
Propagation Delay TC
1
ps/°C
CT
Propagation Delay Matching
High Transition to Low
Transition
Propagation Delay Matching
High to Low Comparator
Propagation Delay
Dispersion
Slew Rate: 400 ps vs.
1.0 ns (20% to 80%)
Overdrive: 250 mV vs.
1.0 V
1.0 V Pulse Width: 0.4 ns,
0.5 ns, 1 ns, 5 ns, 10 ns
0.5 V Pulse Width: 0.4 ns,
0.5 ns, 1 ns, 5 ns, 10 ns
Duty Cycle: 5% to 95%
10
ps
CB
10
ps
CB
VDUTx = 0.0 V to 1.0 V swing, drive term mode, VIT = 0.0 V,
comparator threshold = 0.5 V
Drive term mode, VIT = 0.0 V
20
ps
CB
VDUTx = 0.0 V to 0.5 V swing, comparator threshold = 0.25 V
25
ps
CB
25
ps
CB
25
ps
CB
10
ps
CB
Minimum Detectable Pulse
Width
Input Equivalent Rise/Fall
Time, 1.0 V, Terminated
200
ps
CB
110
ps
CB
Input Equivalent Rise/Fall
Time, 2.0 V, Unterminated
500
ps
CB
For 250 mV: VDUTx: 0.0 V to 0.50 V swing; for 1.0 V: VDUTx: 0.0 V
to 1.25 V swing, comparator threshold = 0.25 V
VDUTx = 0.0 V to 1.0 V swing, 32 MHz, comparator threshold =
0.5 V
VDUTx = 0.0 V to 0.5 V swing, 32 MHz, comparator threshold =
0.25 V
VDUTx = 0.0 V to 1.0 V swing, 32 MHz, comparator threshold =
0.5 V
VDUTx = 0.0 V to 1.0 V swing, 32 MHz, greater than 50%
output differential amplitude
VDUTx = 0.0 V to 1.0 V swing, drive term mode, VIT = 0.0 V,
CLC = 010, measured from digitized plot, 20% to 80%
transition time of digitized plot is root-sum square (RSS) of
input equivalent rise/fall and 50 ps input stimulus
VDUTx = 0.0 V to 2.0 V swing, drive high-Z, measured from
digitized plot, 20% to 80% transition time of digitized plot
is root-sum square (RSS) of input equivalent rise/fall and
50 ps input stimulus
VDUTx = 0.0 V to 1.0 V swing, drive term mode, VIT = 0.0 V,
maximum CLC setting
20
3
280
4.8
%
Bits
ps
ns
CB
D
S
S
Cable Loss Compensation
(CLC)
CLC Amplitude
CLC Resolution
CLC Time Constant 1
CLC Time Constant 2
Rev. B | Page 9 of 82
ADATE320
Data Sheet
DIFFERENTIAL MODE COMPARATOR (DMC) SPECIFICATIONS
Table 5.
Parameter
DC SPECIFICATIONS
Input Voltage Range
Functional Differential Range
Maximum Differential Input
Input Offset Voltage
Input Offset Voltage TC
Gain
Min
−1.5
±0.05
−250
Max
Unit
Test
Level
+4.5
±1.1
±6.0
+250
V
V
V
mV
D
D
D
P
1.1
µV/°C
V/V
CT
P
ppm/°C
µV
µV
CT
D
CT
mV
P
±150
1.0
Gain TC
VOHx, VOLx Resolution
VOHx, VOLx DNL
VOHx, VOLx INL
Typ
±40
153
±250
−8
+8
Uncertainty Band
11
mV
CB
Programmable Hysteresis
Hysteresis Resolution
Common-Mode Rejection Ratio
(CMRR)
DC PSR
200
4
mV
Bits
mV/V
CB
D
P
±5
mV/V
CT
Propagation Delay
580
ps
CB
Propagation Delay TC
2
ps/°C
CT
Propagation Delay Matching
High Transition to Low
Transition
Propagation Delay Matching
High to Low Comparator
15
ps
CB
15
ps
CB
30
ps
CB
25
ps
CB
25
ps
CB
25
ps
CB
−1.0
+1.0
AC SPECIFICATIONS
Propagation Delay Dispersion
Slew Rate: 400 ps vs. 1 ns
(20% to 80%)
Overdrive: 250 mV vs. 750 mV
1.0 V Pulse Width: 0.7 ns,
1.0 ns, 5.0 ns, 10 ns
0.5 V Pulse Width: 0.6 ns,
1.0 ns, 5.0 ns, 10 ns
Rev. B | Page 10 of 82
Test Conditions/Comments
VOHx tests at VOLx = −1.5 V, VOLx tests at VOHx = 1.5 V
Offset interpolated from measurements at DAC Code 0x2666
(−1.0 V) and DAC Code 0x5999 (1.0 V), with VCM = 0.0 V
Gain derived from measurements at DAC Code 0x2666
(−1.0 V) and DAC Code 0x5999 (1.0 V); based on an ideal
DAC transfer function (see Table 24)
After two-point gain/offset calibration; VCM = 0.0 V;
calibration points at DAC Code 0x2666 (−1.0 V) and
DAC Code 0x5999 (1.0 V)
After two-point gain/offset calibration; VCM = 0.0 V;
calibration points DAC Code 0x2666 (−1.0 V) and
DAC Code 0x5999 (1.0 V), measured over VOHx/VOLx
range of −1.1 V to +1.1 V
VDUTx = 0.0 V, sweep comparator threshold to determine
the uncertainty band
∆Offset measured at VCM = −1.5 V and +4.5 V, VDM = 0.0 V
∆Offset measured at VCM = 0.0 V, VDM = calibration points
DAC Code 0x2666 (−1.0 V) and DAC Code 0x5999 (1.0 V)
All ac tests are performed after dc levels calibration; input
transition time = 50 ps 20% to 80%; outputs terminated
50 Ω to VTTCx, comparator CLC set to ¼ scale (010)
VDUT0 = 0.0 V, VDUT1 = −0.5 V to +0.5 V swing, drive
termination mode, VIT = 0.0 V, comparator threshold =
0.0 V, repeat with VDUTx inputs reversed
VDUT0 = 0.0 V, VDUT1 = −0.5 V to +0.5 V swing, drive
termination mode, VIT = 0.0 V, comparator threshold =
0.0 V, repeat with VDUTx inputs reversed
VDUT0 = 0.0 V, VDUT1 = −0.5 V to +0.5 V swing, drive
termination mode, VIT = 0.0 V, comparator threshold =
0.0 V, repeat with VDUTx inputs reversed
VDUT0 = 0.0 V, VDUT1 = −0.5 V to +0.5 V swing, drive
termination mode, VIT = 0.0 V, comparator threshold =
0.0 V, repeat with VDUTx inputs reversed
VDUT0 = 0.0 V, VIT = 0.0 V, drive termination mode, repeat
with VDUTx inputs reversed
VDUT1 = −0.5 V to +0.5 V swing, comparator threshold = 0.0 V
For 250 mV: VDUT1 = 0.0 V to 0.5 V swing; for 750 mV: VDUT1 =
0.0 V to 1.0 V swing, comparator threshold = −0.25 V,
repeat with VDUTx inputs reversed with comparator
threshold = +0.25 V
VDUT1 = −0.5 V to +0.5 V swing, 32 MHz, comparator
threshold = 0.0 V
VDUT1 = −0.25 V to +0.25 V swing, 32 MHz, comparator
threshold = 0.0 V
Data Sheet
Parameter
Duty Cycle: 5% to 95%
ADATE320
Min
Typ
5
Max
Unit
ps
Test
Level
CB
Minimum Detectable Pulse
Width
200
ps
CB
Input Equivalent Rise/Fall Time
110
ps
CB
20
3
280
4.8
%
Bits
ps
ns
CB
D
S
S
Cable Loss Compensation (CLC)
CLC Amplitude
CLC Resolution
CLC Time Constant 1
CLC Time Constant 2
Test Conditions/Comments
VDUT1 = −0.5 V to +0.5 V swing, 32 MHz, comparator
threshold = 0.0 V
VDUT0 = 0.0 V, VDUT1 = −0.5 V to +0.5 V swing, 32 MHz, drive
term mode, VIT = 0.0 V, comparator threshold = 0.0 V,
greater than 50% output differential amplitude, repeat
with VDUTx inputs reversed
VDUT0 = 0.0 V, VDUT1 = −0.5 V to +0.5 V swing, drive term mode,
VIT = 0.0 V, comparator threshold = 0.0 V, CLC = ¼ scale,
measured from digitized plot, t = √(tCMP2 − tIN2)
VDUT0 = 0.0 V, VDUT1 = −0.8 V to +0.8 V swing, drive term
mode, VIT = 0.0 V, comparator threshold = 0.0 V,
comparator CLC set to maximum CLC setting, repeat with
VDUTx inputs reversed
ACTIVE LOAD SPECIFICATIONS
Table 6.
Parameter
DC SPECIFICATIONS
Input Characteristics
Active Load Commutation
Voltage (VCOMx) Range
VCOMx Offset
VCOMx Offset TC
VCOMx Gain
Min
Typ
−1.5
−200
Max
Unit
Test
Level
+4.5
V
D
IOHx = IOLx = 1 mA, VDUTx open circuit
+200
mV
µV/°C
V/V
P
CT
P
Measured at DAC Code 0x4000 (0.0 V), uncalibrated
ppm/°C
µV
µV
CT
D
CT
mV
mV
mV
P
P
P
mA
D
+600
µA
P
+25
µA/°C
%
CT
P
ppm/°C
CT
±100
1.0
VCOMx Gain TC
VCOMx Resolution
VCOMx DNL
1.1
±20
153
±250
VCOMx INL
Focused Range
Full Range
DUTGND Voltage Accuracy
Output Characteristics
Maximum Source Current
(IOLx)
IOLx Offset
IOLx Offset TC
IOLx Gain Error
IOLx Gain TC
−5
−10
−5
±1
+5
+10
+5
25
−600
±1
0
±100
Rev. B | Page 11 of 82
Test Conditions/Comments
Load in active on state, RCVx active
Gain derived from measurements at DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V)
IOHx = IOLx = 12.5 mA, after two-point gain/offset
calibration; measured over VCOMx range −1.5 V to
+4.5 V; calibration points DAC Code 0x4000 (0.0 V)
and DAC Code 0x8CCC (3.0 V)
IOHx = IOLx = 12.5 mA; after two-point gain/offset
calibration; calibration points DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V)
Measured over VCOMx range of −0.5 V to +3.5 V
Measured over VCOMx range of −1.5 V to +4.5 V
Over ±0.1 V range; measured over −0.5 V to +3.5 V
focused VCOMx range
VDUTx ≤ 3.5 V (a compliance limit is set by a 50 Ω
internal resistor as illustrated in Figure 142)
IOHx = −2.5 mA, VCOMx = 1.5 V, VDUTx = 0.0 V; offset
extrapolated from measurements at DAC Code 0x451F
(1 mA) and DAC Code 0xA666 (20 mA)
IOHx = −2.5 mA, VCOMx = 1.5 V, VDUTx = 0.0 V; gain
derived from measurements at DAC Code 0x451F
(1 mA) and DAC Code 0xA666 (20 mA); based on an
ideal dc transfer function
ADATE320
Data Sheet
Unit
nA
µA
Test
Level
D
CT
+100
µA
P
0.4
V
P
V
CT
mA
D
+600
µA
P
+25
µA/°C
%
CT
P
ppm/°C
nA
µA
CT
D
CT
+100
µA
P
0.4
V
P
0.1
V
CT
Propagation Delay, Load
Active On to Load Active Off
1.7
ns
CB
Propagation Delay, Load
Active Off to Load Active On
2.9
ns
CB
Propagation Delay Matching
1.2
ns
CB
Load Spike
Settling Time to Within 5%
140
2.5
mV
ns
CB
CB
Parameter
IOLx Resolution
IOLx DNL
IOLx INL
Min
Typ
763
±1.25
−100
IOLx 90% Commutation
Voltage
0.25
Max
0.1
Maximum Sink Current (IOHx)
25
IOHx Offset
−600
IOHx Offset TC
IOHx Gain Error
0
±1
IOHx Gain TC
IOHx Resolution
IOHx DNL
IOHx INL
IOHx 90% Commutation
Voltage
±100
763
±1.25
−100
0.25
AC SPECIFICATIONS
Dynamic Performance
Rev. B | Page 12 of 82
Test Conditions/Comments
IOHx = −2.5 mA, VCOMx = 1.5 V, VDUTx = 0.0 V; after
two-point gain/offset calibration; measured over IOLx
range 0 mA to 25 mA; calibrated at DAC Code
0x451F (1 mA) and DAC Code 0xA666 (20 mA)
IOHx = −2.5 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after
two-point gain/offset calibration
IOHx = IOLx = 25 mA, VCOM = 2.0 V, measure IOLx
reference at VDUTx = −1.0 V, measure IOLx current at
VDUTx = 1.6 V, check > 90% of reference current
IOHx = IOLx = 1 mA, VCOM = 2.0 V, measure IOLx
reference at VDUTx = −1.0 V, measure IOLx current at
VDUTx = 1.9 V, check > 90% of reference current
VDUTx ≥ −0.5 V (a compliance limit is set by a 50 Ω
internal resistor as illustrated in Figure 142)
IOLx = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V, offset
extrapolated from measurements at DAC Code 0x451F
(1 mA) and DAC Code 0xA666 (20 mA)
IOLx = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V, gain
derived from measurements at DAC Code 0x451F
(1 mA) and DAC Code 0xA666 (20 mA); based on an
ideal DAC transfer function
IOLx = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after
two-point gain/offset calibration; measured over
IOHx range of 0 mA to 25 mA; calibrated at DAC
Code 0x451F (1 mA) and DAC Code 0xA666 (20 mA)
IOLx = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after
two-point gain/offset calibration
IOHx = IOLx = 25 mA, VCOM = 2.0 V, measure IOHx
reference at VDUTx = 4.0 V, measure IOHx current at
VDUTx = 2.4 V, ensure > 90% of reference current
IOHx = IOLx = 1 mA, VCOM = 2.0 V, measure IOHx
reference at VDUTx = 4.0 V, measure IOHx current at
VDUTx = 2.1 VDUTx, ensure > 90% of reference current
All ac measurements are performed after dc
calibration unless noted, load active on
Toggle RCVx; DUTx terminated 50 Ω to 0.0 V; IOLx =
IOHx = 20 mA, VIH = VIL = 0.0 V; VCOM = +1.5 V for
IOLx and −1.5 V for IOHx
Measured from zero crossing of RCVx − RCVx to
50% of final output value; repeat for drive low and
drive high
Measured from zero crossing of RCVx − RCVx to
50% of final output value; repeat for drive low and
drive high
Active on vs. active off; repeat for drive low and
drive high
Repeat for drive low and drive high
Measured from output crossing 50% final value to
output within 5% final value
Data Sheet
ADATE320
PPMU SPECIFICATIONS
PPMU enabled in force voltage mode unless noted.
Table 7.
Parameter
FORCE VOLTAGE (FV)
Current Range A
Current Range B
Current Range C
Current Range D
Current Range E
FV Range at Output, Range A
FV Range at Output, Range B,
Range C, Range D, and Range E
FV Offset, Range C
Max
Unit
Test
Level
Test Conditions/Comments
−40
−1
−100
−10
−2
−1.0
−1.5
−1.5
+40
+1
+100
+10
+2
+4.0
+4.5
+4.5
mA
mA
µA
µA
µA
V
V
V
D
D
D
D
D
D
D
D
Output range for full-scale source/sink
Output range for ±25 mA or less
Output range for full-scale source/sink
−100
+100
mV
P
mV
CT
µV/°C
V/V
CT
P
Min
FV Offset, All Ranges
FV Offset TC, All Ranges
FV Gain, Range C
Typ
±30
±100
1.0
1.1
FV Gain, All Ranges
1.05
V/V
CT
FV Gain TC, All Ranges
±10
ppm/°C
CT
FV INL
Range A
±1.5
mV
CT
Range C, Focused Range
−1.7
+1.7
mV
P
Range C, Full Range
−5
+5
mV
P
±1.0
mV
CT
FV Compliance vs. Source/Sink
Current, Range A (±40 mA)
±1
mV
CT
FV Compliance vs. Source/Sink
Current, Range A (±25 mA)
±1
mV
CT
Range B, Range D, and Range E
Rev. B | Page 13 of 82
Measured at DAC Code 0x4000 (0.0 V) in
Range C
Measured at DAC Code 0x4000 (0.0 V)
applies to all other ranges
Measured at DAC Code 0x4000 (0.0 V)
Gain derived from measurements at DAC
Code 0x4000 (0.0 V) and DAC Code 0x8CCC
(3.0 V); based on an ideal DAC transfer
function
Gain derived from measurements at DAC
Code 0x4000 (0.0 V) and DAC Code 0x8CCC
(3.0 V); based on an ideal DAC transfer
function
Gain derived from measurements at DAC
Code 0x4000 (0.0 V) and DAC Code 0x8CCC
(3.0 V)
After two-point gain/offset calibration,
output range of −1.5 V to +4.5 V; calibration
points DAC Code 0x4000 (0.0 V) and DAC
Code 0x8CCC (3.0 V), PPMU Current Range A
After two-point gain/offset calibration,
output range of −0.5 V to +3.5 V; calibration
points DAC Code 0x4000 (0.0 V) and DAC
Code 0x8CCC (3.0 V)
After two-point gain/offset calibration,
output range of −1.5 V to +4.5 V; calibration
points DAC Code 0x4000 (0.0 V) and DAC
Code 0x8CCC (3.0 V)
After two-point gain/offset calibration,
output range of −1.5 V to +4.5 V; calibration
points DAC Code 0x4000 (0.0 V) and DAC
Code 0x8CCC (3.0 V)
Force −1.0 V; measure voltage while
sinking 0.0 mA and full-scale current;
measure ∆V; force 4.0 V; measure voltage
while sourcing 0.0 mA and full-scale
current; measure ∆V
Force −1.5 V; measure voltage while sinking
0.0 mA and 25 mA; measure ∆V; force 4.5 V;
measure voltage while sourcing 0.0 mA
and 25 mA; measure ∆V
ADATE320
Data Sheet
Parameter
FV Compliance vs. Source/Sink
Current, Range B, Range C,
Range D, and Range E
Min
Typ
±1
Max
Unit
mV
Test
Level
CT
DUTGND Voltage Accuracy
−5
±1
+5
mV
P
−1.0
−1.5
−1.5
+4.0
+4.5
+4.5
V
V
V
D
D
D
−14.5
+14.5
% FSR
P
30
% FSR/°C
%
CT
P
±50
ppm/°C
CT
±50
±50
ppm/°C
ppm/°C
CT
CT
FORCE CURRENT (FI)
DUTx Pin Voltage Range, Range A
DUTx Pin Voltage Range, Range B,
Range C, Range D, and Range E
Zero-Current Offset, All Ranges
Zero-Current Offset TC
Gain Error, All Ranges
±0.02
0
Gain Drift
Range A
Range B
Range C, Range D, and Range E
INL
Range A
−0.12
+0.12
% FSR
P
Range B, Range C, and Range D
−0.04
+0.04
% FSR
P
Range E
−0.045
+0.045
% FSR
P
−0.3
+0.3
% FSR
P
−0.1
+0.1
% FSR
P
−0.3
+0.3
% FSR
P
−0.06
+0.06
% FSR
P
Range D
−0.3
+0.3
% FSR
P
Range E
−0.85
+0.85
% FSR
P
FI Compliance vs. Voltage Load
Range A
Range B and Range C
Rev. B | Page 14 of 82
Test Conditions/Comments
Force −1.5 V; measure voltage while sinking
0.0 mA and full-scale current; measure ∆V;
force 4.5 V; measure voltage while sourcing
0.0 mA and full-scale current; measure ∆V
Over ±0.1 V range; measured over −0.5 V
to +3.5 V focused PPMU output range
PPMU enabled in force current/measure
current (FIMI)
Full-scale source and sink current
DUTx pin source and sink 25 mA or less
Full-scale source and sink current
Interpolated from measurements at PPMU
DAC Code 0x4CCC (−80% FS) and DAC
Code 0xB333 (80% FS) for each range
Derived from measurements at PPMU DAC
Code 0x4CCC (−80% FS) and DAC Code
0xB333 (80% FS) for each range
PPMU self heating effects in Range A can
influence gain drift measurements
After two-point gain/offset calibration
Measured over FSR output of Range A
(±40 mA)
Measured over FSR output of Range B
(±1 mA), Range C (±100 µA), and Range D
(±10 µA)
Measured over FSR output of Range E
(±2 µA)
Force positive full-scale current driving
−1.0 V and +4.0 V, measure ∆I at DUTx pin;
force negative full-scale current driving
−1.0 V and +4.0 V, measure ∆I at DUTx pin
Force positive full-scale current driving 0.0 V
and 3.0 V, measure ∆I at DUTx pin; force
negative full-scale current driving 0.0 V
and 3.0 V, measure ∆I at DUTx pin
Force positive full-scale current driving
−1.5 V and +4.5 V, measure ∆I at DUTx pin;
force negative full-scale current driving
−1.5 V and +4.5 V, measure ∆I at DUTx pin
Force positive full-scale current driving 0.0 V
and 3.0 V, measure ∆I at DUTx pin; force
negative full-scale current driving 0.0 V
and 3.0 V, measure ∆I at DUTx pin
Force positive full-scale current driving
−1.5 V and +4.5 V, measure ∆I at DUTx pin;
force negative full-scale current driving
−1.5 V and +4.5 V, measure ∆I at DUTx pin
Force positive full-scale current driving
−1.5 V and +4.5 V, measure ∆I at DUTx pin;
force negative full-scale current driving
−1.5 V and +4.5 V, measure ∆I at DUTx pin;
allows 10 nA DUTx pin leakage
Data Sheet
Parameter
MEASURE VOLTAGE (MV)
ADATE320
Max
Unit
Test
Level
+4.5
+25
V
mV
D
P
1.02
µV/°C
V/V
CT
P
−1.7
+1.7
ppm/°C
mV
CT
P
−1.0
−1.5
+4.0
+4.5
V
V
D
D
−4
+4
%FSR
P
±0.5
%FSR
CT
±0.01
±0.01
±0.02
%FSR/°C
%FSR/°C
%FSR/°C
CT
CT
CT
Min
Range
Offset
−1.5
−25
Offset TC
Gain
0.98
Gain TC
INL
MEASURE CURRENT (MI)
DUTx Pin Voltage Range
Range A
Range B, Range C, Range D, and
Range E
Zero-Current Offset
Range B
±50
±5
All Ranges
Zero-Current Offset TC
Range A
Range B, Range C, and Range D
Range E
Gain Error
Range B
All Ranges
Gain TC
Range A
Range B, Range C, and Range D
Range E
INL
DUTx Pin Voltage Rejection
Test Conditions/Comments
PPMU enabled, force voltage/measure
voltage (FVMV)
Range B, VDUTx = 0.0 V, offset = (PPMU_Mx −
VDUTx)
Range B, derived from measurements at
VDUTx = 0.0 V and 3.0 V
Range B, measured over −1.5 V to +4.5 V
PPMU enabled in FIMI
Full-scale source and sink current
Interpolated from measurements sourcing
and sinking 80% FS current each range; for
example, 2% FSR is 40 µA in Range B
Derived from measurements sourcing and
sinking 80% FS current
−30
Range A
Range B
Range C, Range D, and Range E
Typ
−10
+5
%
%
P
CT
±50
±50
±50
ppm/°C
ppm/°C
ppm/°C
CT
CT
CT
±0.02
−0.02
%FSR
CT
+0.02
%FSR
%FSR
P
CT
+1.3
µA
P
+5
mV
P
+5.0
200
V
Ω
D
P
±0.01
−1.3
DUTGND Voltage Accuracy
MEASURE PIN DC CHARACTERISTICS
Output Range
Output Impedance
−5
Output Leakage Current When
Tristated
Output Short Circuit Current
−1
+1
µA
P
−10
+10
mA
P
−1.5
±1
Rev. B | Page 15 of 82
After two-point gain/offset calibration at
±80% FS current
Measured over FSR output of −40 mA to
+40 mA
Measured over FSR output of −1 mA to +1 mA
Measured over FSR output of Range C,
Range D, and Range E
Range B, FVMI, force −1.0 V and +4.0 V into
0.5 mA load, measure ∆I reported at
PPMU_Mx pin
Over ±0.1 V range
PPMU enabled in FVMV, source resistance:
PPMU force 4.5 V into 0.0 mA, −1.0 mA, sink
resistance: PPMU force −1.5 V into 0.0 mA,
1.0 mA, resistance = ∆V/∆I at PPMU_Mx pin
Tested at −1.7 V and +5.2 V
PPMU enabled in FVMV, source: PPMU
force +4.5 V, PPMU_Mx = −1.5 V, sink:
PPMU force −1.5 V, PPMU_Mx = 5.0 V
ADATE320
Parameter
PPMU_Mx Pin, Parasitic Output
Capacitance
PPMU_Mx Pin, External Load
Capacitance
PPMU VOLTAGE CLAMPS (FI)
Data Sheet
Min
Typ
Unit
pF
Test
Level
S
pF
S
+3.5
+4.5
+300
V
V
mV
D
D
P
1.1
mV/°C
V/V
CT
P
Max
2
100
Low Voltage Clamp Range (PCLx)
High Voltage Clamp Range (PCHx)
Offset, Voltage Clamps (PCHx/PCLx)
−1.5
−0.5
−300
Offset TC, Voltage Clamps (PCHx/PCLx)
Gain, Voltage Clamps (PCHx/PCLx)
1.0
Gain TC, Voltage Clamps (PCHx/PCLx)
INL, Voltage Clamps (PCHx/PCLx)
−20
+20
ppm/°C
mV
CT
P
Positive Voltage Clamp, Voltage
Droop (Source)
−50
+50
mV
P
Negative Voltage Clamp, Voltage
Droop (Sink)
−50
+50
mV
P
DUTGND Voltage Accuracy
−5
+5
mV
P
−120
−20
%FS
S
20
120
%FS
S
−100
−30
%FS
D
30
100
%FS
D
±160
%FS
P
+10
%FSR
%FSR/°C
P
CT
±0.5
±25
±1
PPMU CURRENT CLAMPS (FV)
Functional Range
Low Current Clamp (PCLx)
High Current Clamp (PCHx)
DC Accuracy Range
Low Current Clamp (PCLx)
High Current Clamp (PCHx)
Static Current Limit, Source and
Sink, All Ranges
±120
Offset, Current Clamps (PCHx/PCLx)
Offset TC, Current Clamps
(PCHx/PCLx)
−10
±140
±0.02
Rev. B | Page 16 of 82
Test Conditions/Comments
Parasitic capacitance contributed by pin
External capacitance tolerated by pin
(exceeding this value may cause instability)
PPMU enabled in FIMI, PPMU clamps
enabled; clamp accuracy applies only
when |PCHx − PCLx| ≥ 1.0 V
Range B, PPMU force ±0.5 mA into open;
PCHx measured at DAC Code 0x4000 (0.0 V)
with PCLx at DAC Code 0x0000 (−2.5 V); PCLx
measured at DAC Code 0x4000 (0.0 V) with
PCHx at DAC Code 0xFFFF (+7.5 V)
Range B, PPMU force ±0.5 mA into open; PCHx
gain derived from measurements at DAC
Code 0x4000 (0.0 V) and DAC Code 0x8CCC
(3.0 V) with PCLx at DAC Code 0x0000
(−2.5 V); PCLx gain derived from measurements at DAC Code 0x4000 (0.0 V) and
DAC Code 0x8CCC (3.0 V) with PCHx at
DAC Code 0xFFFF (7.5 V)
Range B, PPMU force ±0.5 mA into open
after two-point gain/offset calibration;
measured over PPMU clamp functional
range
∆V at DUTx pin, Range A, PCHx = +4.0 V,
PCLx = −1.0 V, PPMU force 5.0 mA and
40 mA into open circuit, calibrated
∆V at DUTx pin, Range A, PCHx = +4.0 V,
PCLx = −1.0 V, PPMU force −5.0 mA and
−40 mA into open circuit, calibrated
Over ±0.1 V range; measured at end points
of clamp functional range
PPMU enabled in FVMV, dc accuracy of the
current clamps only applies over the
following conditions: 30% FS ≤ PCHx ≤
100% FS or −100% FS ≤ PCLx ≤ −30% FS
For example, −120% FS in Range A is
−48 mA and −20% FS in Range A is −8 mA
For example, 20% FS in Range A is 8 mA
and 120% FS in Range A is 48 mA
For example, −100% FS in Range A is
−40 mA and −30% FS in Range A is −12 mA
For example, 30% FS in Range A is 12 mA
and 100% FS in Range A is 40 mA
PCLx at DAC Code 0x0000 (−2.5 V), PCHx
at DAC Code 0xFFFF (7.5 V), sink: force
−1.5 V, short DUTx to 4.5 V, source: force
4.5 V, short DUTX to −1.5 V
All ranges; PPMU force ±1.0 V into 0.0 V 1
All ranges
Data Sheet
Parameter
Gain Error, Current Clamps
(PCHx/PCLx)
Gain TC, Current Clamps
(PCHx/PCLx)
INL, Current Clamps (PCHx/PCLx)
ADATE320
Min
0
Typ
Max
30
±50
Unit
%
Test
Level
P
Test Conditions/Comments
All ranges; PPMU force ±1.0 V into 0.0 V 2
ppm/°C
CT
All ranges
−0.15
+0.15
%FSR
P
All ranges; PPMU force ±1.0 V into 0.0 V,
after two-point gain/offset calibration;
PCHx calibration at DAC Code 0xA000
(3.75 V or 50% FS) and DAC Code 0xB333
(4.50 V or 80% FS); PCLx calibration at DAC
Code 0x6000 (1.25 V or −50% FS) and DAC
Code 0x4CCC (0.50 V or −80% FS);
measured over dc accuracy range
−2
+2
%FSR
P
−2
+2
%FSR
P
PCLx = 0.5 V (−80% FS), PCHx = 4.5 V (80%
FS), PPMU force −0.5 V and +3.5 V into
VDUTx = 4.5 V, measure ∆I at the DUTx pin in
Range A
PCLx = 0.5 V (−80% FS), PCHx = 4.5 V (80%
FS), PPMU force −0.5 V and +3.5 V into
VDUTx = −1.5 V, measure ∆I at the DUTx pin
in Range A
20
µs
S
25
µs
S
25
µs
S
65
µs
S
FV Settling Time to 1.0% of Final
Value
Range A, 200 pF and 2000 pF Load
16
µs
CB
Range B, 200 pF and 2000 pF Load
14
µs
CB
Range C, 200 pF and 2000 pF Load
18
µs
CB
16
µs
S
10
µs
S
40
µs
S
8
µs
CB
8
µs
CB
8
µs
CB
Current Droop
Low Current Clamp (PCLx), Sink
High Current Clamp (PCHx),
Source
SETTLING/SWITCHING TIMES
FV Settling Time to 0.1% of Final
Value
Range A, 200 pF and 2000 pF
Load
Range B, 200 pF and 2000 pF
Load
Range C, 200 pF Load
Range C, 2000 pF Load
FI Settling Time to 0.1% of Final
Value
Range A, 200 pF in Parallel with
120 Ω
Range B, 200 pF in Parallel with
1.5 kΩ
Range C, 200 pF in Parallel with
15.0 kΩ
FI Settling Time to 1.0% of Final
Value
Range A, 200 pF in Parallel with
120 Ω
Range B, 200 pF in Parallel with
1.5 kΩ
Range C, 200 pF in Parallel with
15.0 kΩ
Rev. B | Page 17 of 82
PPMU enabled in FV, Range A, step from
0.0 V to 4.0 V
PPMU enabled in FV, Range B, DCL
disabled, step from 0.0 V to 4.0 V
PPMU enabled in FV, Range C, DCL
disabled, step from 0.0 V to 4.0 V
PPMU enabled in FV, Range C, DCL
disabled, step from 0.0 V to 4.0 V
PPMU enabled in FV, Range A, DCL
disabled, step from 0.0 V to 4.0 V
PPMU enabled in FV, Range B, DCL
disabled, step from 0.0 V to 4.0 V
PPMU enabled in FV, Range C, DCL
disabled enabled, step from 0.0 V to 4.0 V
PPMU enabled in FI, Range A, DCL
disabled, step from 0.0 mA to 40 mA
PPMU enabled in FI, Range B, DCL
disabled, step from 0.0 mA to 1 mA
PPMU enabled in FI, Range C, DCL
disabled, step from 0.0 mA to 100 µA
PPMU enabled in FI, Range A, DCL
disabled, step from 0.0 mA to 40 mA
PPMU enabled in FI, Range B, DCL
disabled, step from 0.0 mA to 1 mA
PMU enabled in FI, Range C, DCL disabled,
step from 0.0 mA to 100 µA
ADATE320
Data Sheet
Parameter
INTERACTION AND CROSSTALK
Measure Voltage Channel to
Channel Crosstalk
Min
Measure Current Channel to
Channel Crosstalk
1
2
Unit
Test
Level
10
µV
CT
0.0001
%FSR
CT
Typ
Max
Test Conditions/Comments
PPMU enabled in FIMV, Range B, channel
under test: force 0.0 mA into 0.0 V; other
channel: force 0.0 mA into VDUTx; sweep
VDUTx from −1.5 V to +4.5 V; measure ∆V at
PPMU_Mx under test
PPMU enabled in FVMI, Range B; channel
under test: force 0.0 V into open circuit;
other channel: force 0.0 V into IDUTx; sweep
IDUTx from −1.0 mA to +1.0 mA; measure ∆V
at PPMU_Mx under test
PCHx offset is derived from measurements at DAC Code 0xA000 (3.75 V or 50% FS) and DAC Code 0xB333 (4.50 V or 80% FS), with PCLx at DAC Code 0x0000 (−2.5 V).
PCLx offset is derived from measurements at DAC Code 0x6000 (1.25 V or −50% FS) and DAC Code 0x4CCC (0.50 V or −80% FS), with PCHx at DAC Code 0xFFFF (7.5 V).
PCHx gain is derived from the measurements at DAC Code 0xA000 (3.75 V or 50% FS) and DAC Code 0xB333 (4.50 V or 80% FS), with PCLx at DAC Code 0x0000
(−2.5 V). PCLx gain is derived from measurements at DAC Code 0x6000 (1.25 V or −50% FS) and DAC Code 0x4CCC (0.50 V or −80% FS), with PCHx at DAC Code 0xFFFF
(7.5 V). For example, the ideal gain is ±FS per 2.5 V in all ranges; in Range B, the ideal gain is ±400 µA/V; therefore, 30% error is ±520 µA/V.
PPMU GO/NO-GO COMPARATORS SPECIFICATIONS
Table 8.
Parameter
DC SPECIFICATIONS
Compare Voltage Range
Input Offset Voltage
Input Offset Voltage TC
Gain
Min
Typ
−1.5
−250
Max
Unit
Test
Level
+5.0
+250
V
mV
μV/°C
V/V
D
P
CT
P
±100
1.0
1.1
Gain TC
±10
ppm/°C
CT
Comparator Threshold Resolution
Comparator Threshold DNL
153
±250
µV
µV
D
CT
+7
mV
P
+5
mV
P
Comparator Threshold INL
−7
DUTGND Voltage Accuracy
−5
±1
Test Conditions/Comments
Measured at DAC Code 0x4000 (0 V)
Gain derived from measurements at DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V)
Gain derived from measurements at DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V)
After two-point calibration; measured over POHx/POLx
range −1.5 V to +5.0 V; calibration points DAC Code
0x4000 (0.0 V) and DAC Code 0x8CCC (3.0 V)
After two-point calibration; measured over POHx/POLx
range −1.5 V to +5.0 V; calibration points DAC Code
0x4000 (0.0 V) and DAC Code 0x8CCC (3.0 V)
Over ±0.1 V range
PPMU EXTERNAL SENSE PINS SPECIFICATIONS
Table 9.
Parameter
DC SPECIFICATIONS
Voltage Range
Leakage
Maximum Load Capacitance
Min
Typ
Max
Unit
Test
Level
Test Conditions/Comments
−1.5
−2
2000
0.0
+4.5
+2
V
nA
pF
D
P
S
PPMU input select, in all states
Tested at −1.5 V and +4.5 V
Capacitive load tolerated at DUTx sense pins
Rev. B | Page 18 of 82
Data Sheet
ADATE320
VREF, VREFGND, AND DUTGND REFERENCE INPUT PINS SPECIFICATIONS
Table 10.
Parameter
DC SPECIFICATIONS
VREF Input Voltage Range
VREF Input Bias Current
DUTGND Input Voltage Range,
Referenced to AGND
DUTGND Input Bias Current
Min
Typ
Max
Unit
Test
Level
2.475
2.500
2.525
V
D
−0.1
10
+0.1
µA
V
P
D
−10
+10
µA
P
Tested at −100 mV and +100 mV
Unit
Test
Level
Test Conditions/Comments
mV/K
°C
D
CT
3.00 V at room temperature, 300 K (23°C)
20°C < TC < 80°C, VCCTHERM only (TJ = TC)
Test Conditions/Comments
Provided externally, VREF = 2.500 V, VREFGND =
0.000 V
Tested with 2.500 V applied
TEMPERATURE MONITOR SPECIFICATIONS
Table 11.
Parameter
DC SPECIFICATIONS
Temperature Sensor Gain
Temperature Sensor Accuracy
Min
Typ
Max
10
±10
ALARM FUNCTIONS SPECIFICATIONS
Table 12.
Parameter
DC SPECIFICATIONS
Overvoltage Alarm High, OVDH
Functional Voltage Range
Uncalibrated Error at −1.0 V
Uncalibrated Error at 5.0 V
Offset Voltage TC
Gain
Min
Hysteresis
Thermal Alarm
Setpoint Error
Thermal Hysteresis
Unit
Test
Level
+5.0
+200
500
±0.5
1.05
V
mV
mV
mV/°C
V/V
D
P
P
CT
CT
140
mV
CT
±0.5
1.05
V
mV
mV
mV/°C
V/V
D
P
P
CT
CT
140
mV
CT
±10
15
°C
°C
CT
CT
−1.0
−300
0
Hysteresis
Overvoltage Alarm Low, OVDL
Functional Voltage Range
Uncalibrated Error at −2.0 V
Uncalibrated Error at 4.0 V
Offset Voltage TC
Gain
Max
Typ
−2.0
−350
−50
+4.0
+150
+450
Rev. B | Page 19 of 82
Test Conditions/Comments
OVDL DAC set to DAC Code 0x0000 (−2.5 V)
Includes 5% uncalibrated gain ±250 mV offset
Includes 5% uncalibrated gain ±250 mV offset
Gain derived from measurements at DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V); based on an
ideal DAC transfer function (see Table 24)
Hysteresis is only applied coming out of alarm
OVDH DAC set to DAC Code 0xFFFF (7.5 V)
Includes 5% uncalibrated gain ±250 mV offset
Includes 5% uncalibrated gain ±250 mV offset
Gain derived from measurements at DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V); based on an
ideal DAC transfer function (see Table 24)
Hysteresis is only applied coming out of alarm
Relative to default alarm value, TJ = 100°C
ADATE320
Data Sheet
Parameter
ALARM Output Characteristics
Off State Leakage
Min
Maximum On Voltage at 200 µA
AC SPECIFICATIONS
Propagation Delay
Typ
Max
Unit
Test
Level
10
500
nA
P
0.1
0.7
V
P
µs
CB
0.5
Test Conditions/Comments
Disable alarm, apply VDD to ALARM pin, and
measure leakage current
ALARM pin asserted, force 200 µA into pin and
measure voltage
For OVDH: VDUTx = 0.0 V to 4.5 V step, OVDH = 4.0 V,
OVDL = −1.0 V; for OVDL: VDUTx = 0.0 V to −1.5 V step,
OVDH = 4.0 V, OVDL = −1.0 V
SERIAL PROGRAMMABLE INTERFACE (SPI) SPECIFICATIONS
Table 13.
Parameter
DC SPECIFICATIONS
Input Voltage
Logic High
Logic Low
Input Bias Current
Min
Typ
Max
Unit
Test
Level
1
VDD
0.7
+10
V
V
µA
PF
PF
P
mV
CB
VDD
0.5
V
V
PF
PF
10
500
nA
P
0.01
0.7
V
P
Test Conditions/Comments
RST, CS, SCLK, SDI
VDD − 0.7
0.0
−10
SCLK Crosstalk on DUTx Pin
Serial Output
Logic High
Logic Low
BUSY Output Characteristics
Off State Leakage
1
VDD − 0.5
0.0
Maximum On Voltage at 2 mA
Tested at 0.0 V and VDD; RST tested at VDD; RST has an internal
50 kΩ pull-up to VDD
DCL disabled, PPMU forcing 0.0 V
SDO, sourcing 2 mA
Sinking 2 mA
Open-drain output
BUSY pin not asserted, apply VDD to pin and measure
leakage current
BUSY pin asserted, force 2 mA into pin and measure voltage
SPI TIMING SPECIFICATIONS
Table 14.
Parameter
SCLK Operating Frequency
Symbol
fCLK
Min
SCLK High Time
SCLK Low Time
CS to SCLK Setup at Assert
CS to SCLK Hold at Assert
CS to SCLK Setup at
Release
CS to SCLK Hold at Release
tCH
tCL
tCSAS
tCSAH
tCSRS
0.5
4.5
4.5
1.5
1.5
1.5
tCSRH
1.5
CS Assert to SDO Active
CS Release to SDO High-Z
tCSO
tCSZ
0
0
CS Release to Next Assert
tCSAM
3
Typ
50
Max
100
4
11
Unit
MHz
MHz
ns
ns
ns
ns
ns
Test
Level
PF
S
S
S
S
S
S
ns
S
ns
ns
S
S
Cycles
D
Rev. B | Page 20 of 82
Description
Setup time of CS assert to next rising edge of SCLK.
Hold time of CS assert to next rising edge of SCLK.
Setup time of CS release to next rising edge of SCLK.
Hold time of CS release to next rising edge of SCLK. This parameter
is only critical if the number of SCLK cycles from previous release of
CS is the minimum specified by the tCSAM parameter.
Delay time from CS assert to SDO active state.
Delay from CS release to SDO high-Z state, strongly influenced
by external SDO pin loading.
Minimum release time of CS between consecutive assertions of
CS. This parameter is specified in units of SCLK cycles, more
specifically in terms of rising edges of the SCLK input.
Data Sheet
ADATE320
Parameter
SDI to SCLK Setup
SDI to SCLK Hold
SCLK to Valid SDO
BUSY Assert from CS/RST
Symbol
tDS
tDH
tDO
tBUSA
BUSY Width
Following CS
tBUSW
Min
3
4
0
0
6
6
Unit
ns
ns
ns
ns
Test
Level
S
S
S
S
21
Cycles
D
Cycles
D
ns
ns
ns
Cycles
S
S
S
D
µs
CB
Max
3
Following RST
744
BUSY Release from SCLK
Width of RST Assert
RST to SCLK Setup at Assert
SCLK Cycles per SPI Word
tBUSR
tRMIN
tRS
tSPI
Internal DAC Settling to
Within ±2 mV from
BUSY Release
tDAC
1
Typ
0
5
1.5
29
10
10
Description
Setup time of SDI data prior to next rising edge of SCLK.
Hold time of SDI data following previous rising edge of SCLK.
Propagation delay from rising edge of SCLK to valid SDO data.
Propagation delay from first rising SCLK following valid CS release
(or RST release in the case of hardware reset) to BUSY assert.
Delay time from first rising SCLK after valid CS release to BUSY
release. Satisfies the requirements detailed in the SPI Clock
Cycles and the Pin section, except following RST or software reset.
Delay time from first rising SCLK after RST release (or valid CS
release in the case of software reset) to BUSY release. Satisfies
the requirement of synchronous reset sequence detailed in the
SPI Clock Cycles and the Pin section.
Propagation delay from qualifying SCLK edge to BUSY release.
Minimum width of asynchronous RST assert, 5 pF external loading.
Minimum setup time of RST release to next rising edge of SCLK.
Minimum number of SCLK rising edge cycles required per valid
SPI operation, including the minimum tCSAM requirement between
consecutive CS assertions.
Settling time of internal analog DAC levels to within ±2 mV.
Settling time is relative to the release of BUSY. 1
The overall settling time may be dominated by the characteristics of an analog block (such as the PPMU or driver) and its respective mode setting (such as Range A or
Range B).
SPI TIMING DIAGRAMS
tCSAM
tCH
SCLK
0
1
2
3
4
5
6
7
8
9
10
11
24
25
0
tCL
tCSAS
1
2
3
4
5
6
7
tCSRS
CS
tCSAH
C1
SDI
C0
A6
NOTE 1
A5
A4
A3
tDH
tCSO
SDO
tCSRH
tDS
C1
C0
A6
A2
A1
A0
R/W D15 D14
D1
D0
A4
A3
C0
A6
A5
A4
A3
A2
A1
tCSZ
tDO
A5
C1
A2
A1
A0
R/W D15 D14
D1
D0
NOTE 1
C1
C0
tBUSA
A6
A4
A3
A2
A1
A0
tBUSR
NOTES
1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE
FOLLOWING THE ASSERTION OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE
SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS ACTIVE INDEPENDENT OF CS.
Figure 2. SPI Detailed Read/Write Timing Diagram
Rev. B | Page 21 of 82
tBUSW
12160-002
BUSY
ADATE320
Data Sheet
SCLK
CS
CH[1:0]
SDI
SDO
NOTE 1
ADDR[6:0]
DATA[15:0]
W
ACTIVE – OUTPUT IS THE PREVIOUS SPI WORD SHIFTED INTO SDI
NOTE 1
FROM PREVIOUS SPI INSTRUCTIONS
BUSY
12160-003
NOTES
1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE
FOLLOWING THE ASSERTION OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE
SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS ACTIVE INDEPENDENT OF CS.
Figure 3. SPI Write Instruction Timing Diagram
SCLK
CS
CH[1:0]
SDI
BUSY
NOTE 1
R
DATA[15:0] = DON’T CARE
ACTIVE – OUTPUT IS THE PREVIOUS SPI WORD SHIFTED INTO SDI
NOTE 1
FROM PREVIOUS SPI INSTRUCTIONS
NOTES
1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE FOLLOWING THE ASSERTION
OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN ALWAYS
REMAINS ACTIVE INDEPENDENT OF CS.
Figure 4. SPI Read Request Instruction Timing Diagram (Prior to Readout Instruction)
Rev. B | Page 22 of 82
12160-004
SDO
ADDR[6:0]
Data Sheet
ADATE320
SCLK
CS
SDI
DATA[15:0] = (IF NOP, THEN DON’T CARE)
CH[1:0] ADDR[6:0] (COULD BE NOP) R/W
NOTE 2
SDO
NOTE 1
CH[1:0]
ADDR[6:0]
READ OUT DATA[15:0]
0 D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
NOTE 1
BUSY
12160-005
NOTES
1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE FOLLOWING THE ASSERTION
OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS
ACTIVE INDEPENDENT OF CS.
2. THE FIRST 10 BITS OF SDO FOLLOWING A READ REQUEST ECHO ADDRESS AND CHANNEL BITS OF THE PRECEDING REQUEST.
THE R/W BIT POSITION IS SET LOW. THE FOLLOWING 16 BITS CONTAIN DATA FROM THE REQUESTED ADDRESS AND CHANNEL.
Figure 5. SPI Readout Instruction Timing Diagram (Subsequent to Read Request Instruction)
tCH
SCLK
tCL
tRMIN
RST
tRS
ASYNCHRONOUS
ASSERT
tBUSA
tBUSR
BUSY
3µs
(DAC DEGLITCH
PERIOD)
DAC0
PREVIOUS CODE
VDUTGND
DEFAULT DAC0 CODE
DAC1
PREVIOUS CODE
VDUTGND
DEFAULT DAC1 CODE
DAC31
PREVIOUS CODE
VDUTGND
DEFAULT DAC31 CODE
RESET
CONDITION
INITIALIZED
CONDITION
Figure 6. SPI Detailed Hardware Reset Timing Diagram
Rev. B | Page 23 of 82
12160-006
tBUSW
ADATE320
Data Sheet
tCH
SCLK
tCL
CS
SDI
SPI RESET
tBUSA
tBUSR
BUSY
tBUSW
DAC0
PREVIOUS CODE
VDUTGND
DEFAULT DAC0 CODE
DAC1
PREVIOUS CODE
VDUTGND
DEFAULT DAC1 CODE
DAC31
PREVIOUS CODE
VDUTGND
DEFAULT DAC31 CODE
RESET
CONDITION
INITIALIZED
CONDITION
Figure 7. SPI Detailed Software Reset Timing Diagram
Rev. B | Page 24 of 82
12160-007
3µs
(DAC DEGLITCH PERIOD)
Data Sheet
ADATE320
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 15.
Parameter
Supply Voltages
Positive Supply Voltage (VCC to PGND)
Positive Supply Voltage (VDD to DGND)
Negative Supply Voltage (VEE to PGND)
Supply Voltage Difference (VCC to VEE)
Reference Ground (DUTGND to AGND)
Supply Sequence or Dropout Condition
Input/Output Voltages
Digital Input Voltage Range
VREF Input Voltage Range
VREFGND, DUTGND Input Voltage Range
DUTx Output Short-Circuit Voltage1
High Speed Termination (VTTCx,
VTTDx) Input Voltage Range
High Speed DATx/RCVx CommonMode Input Voltage Range2
High Speed DATx/RCVx Differential
Mode Input Voltage Range2
High Speed CMPHx/CHPLx, PPMU_
CMPHx/PPMU_CMPLx Absolute
Output Voltage Range
DUTx Input/Output Pin Current Limit
DCL Maximum Short-Circuit Current3
Operating Temperature, Junction
Storage Temperature Range
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Rating
−0.5 V to +9.0 V
−0.5 V to +2.2 V
−6.0 V to +0.5 V
−1.0 V to +15.0 V
−0.5 V to +0.5 V
No limitations
−0.5 V to VDD + 0.5 V
−0.5 V to +3.5 V
−0.5 V to +0.5 V
−3.0 V to +6.0 V
−0.5 V to +2.2 V
Table 16. Thermal Resistance
Package Type
84-Lead
LFCSP
1
Airflow Velocity (m/sec)
N/A1
0
1
2
θJA
N/A1
45
40
37
θJC
3.2
N/A1
N/A1
N/A1
N/A means not applicable.
EXPLANATION OF TEST LEVELS
D
Definition.
S
Design verification simulation.
−0.5 V to +2.2 V
P
100% production tested.
−1.0 V to +1.0 V
PF
Functionally checked during production test.
CT
Characterized on tester.
CB
Characterized on bench.
−0.5 V to +2.2 V
±120 mA
125°C
−65°C to +150°C
ESD CAUTION
RL = 0 Ω, VDUTx continuous short-circuit condition (VIH, VIL, VIT), high-Z,
VCOM, and all clamp modes.
2
DATx, DATx, RCVx, RCVx, RSOURCE = 0 Ω, no pin to exceed either maximum
common-mode input range or differential mode input range.
3
RL = 0 Ω, VDUTx = −3 V to +6 V; DCL current limit. Continuous short-circuit condition.
The ADATE320 is designed to withstand continuous short-circuit fault.
1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 25 of 82
Unit
°C/W
°C/W
°C/W
°C/W
ADATE320
Data Sheet
USER INFORMATION AND TRUTH TABLES
Table 17. Driver Truth Table 1
DRIVE_ENABLE_x,
Address 0x19, Bit 0
0
1
1
1
1
1
1
1
1
1
2
DRV Control Register
DRIVE_FORCE_x,
DRIVE_FORCE_STATE_x,
Address 0x19, Bit 1 Address 0x19, Bits[3:2]
X
XX
1
00
1
01
1
10
1
11
0
XX
0
XX
0
XX
0
XX
High Speed Inputs 2
DRIVE_VT_HIZ_x,
Address 0x19, Bit 4
X
X
X
X
X
0
1
X
X
DATx
X
X
X
X
X
X
X
0
1
RCVx
X
X
X
X
X
1
1
0
0
Driver State
Low leakage
Active VIL
Active VIH
Active high-Z
Active VIT
Active high-Z
Active VIT
Active VIL
Active VIH
X means don’t care.
See Figure 139 for more detailed information about high speed DATx/RCVx input multiplexing.
Table 18. Comparator Truth Table
DMC_ENABLE,
Address 0x1A, Bit 0
0
11
1
CMPH0
VDUT0 < VOH0
VOH0 < VDUT0
VDUT0 − VDUT1 < VOH0
VOH0 < VDUT0 − VDUT1
State
0
1
0
1
Comparator State
CMPL0
State CMPH1
VDUT0 < VOL0
0
VDUT1 < VOH1
VOL0 < VDUT0
1
VOH1 < VDUT1
VDUT0 − VDUT1 < VOL0 0
VDUT1 < VOH1
VOL0 < VDUT0 − VDUT1 1
VOH1 < VDUT1
State
0
1
0
1
CMPL1
VDUT1 < VOL1
VOL1 < VDUT1
VDUT1 < VOL1
VOL1 < VDUT1
State
0
1
0
1
Note that the Channel 1 normal window comparator continues to function while the device is in differential compare mode, but at a greatly reduced bandwidth.
Table 19. Active Load Truth Table 1
LOAD_ENABLE_x,
Address 0x1B, Bit 0
0
1
1
1
1
1
2
LOAD/DRV Control Registers
LOAD_FORCE_x,
DRIVE_VT_HIZ_x, Address 0x19, Bit
Address 0x1B, Bit 1 4
X
X
1
X
0
X
0
0
0
1
High Speed Inputs 2
DATx
X
X
X
X
X
RCVx
X
X
0
1
1
Load State
Low leakage
Active on
Active off
Active on
Active off
X means don’t care.
See Figure 139 for more detailed information about high speed DATx/RCVx input multiplexing.
Table 20. PPMU Go/No-Go Comparator Truth Table 1
PPMU Control Register
PPMU_ENABLE_x,
PPMU_STANDBY_x,
Address 0x1C, Bit 0
Address 0x1C, Bit 1
0
X
1
X
1
X
1
2
PPMU Go/No-Go Comparator State 2
PPMU_CMPHx
X
PPMUx MV/MI < POHx
POHx < PPMUx MV/MI
State
0
0
1
PPMU_CMPLx
X
PPMUx MV/MI < POLx
POLx < PPMUx MV/MI
State
0
0
1
X means don’t care.
The PPMUx MV/MI inputs to the PPMU go/no-go comparators always come directly from the respective internal PPMU instrumentation amplifiers, not from the
PPMU_Mx output pins (see Figure 144). The internal instrumentation amplifiers are independently configured for either measure voltage (MV) or measure current (MI),
depending on the settings of the PPMU_MEAS_VI_x control bit, as described in Figure 151. When PPMU power is not enabled, the respective go/no-go comparator
outputs are locked to a static low state (see Table 21).
Rev. B | Page 26 of 82
Data Sheet
ADATE320
Table 21. PPMU Measure Pin Truth Table 1
PPMU_ENABLE_x,
Address 0x1C, Bit 0
X
0
0
PPMU_STANDBY_x,
Address 0x1C, Bit 1
X
X
X
PPMU Control Register
PPMU_MEAS_ENABLE_x,
Address 0x1C, Bit 13
0
1
1
PPMU_MEAS_SEL_x,
Address 0x1C, Bit 14
X
0
1
PPMU_MEAS_VI_x,
Address 0x1C, Bit 6
X
X
X
1
1
1
X
X
X
1
1
1
0
0
1
0
1
X
1
2
PPMU_Mx,
Pin State
High-Z
Active MV
Active
VTHERM 2
Active MV
Active MI
Active
VTHERM2
X means don’t care.
When applicable, PPMU_M0 is connected to the internal temperature sensor node (VTHERM), and PPMU_M1 is connected to the internal temperature sensor
reference ground node (AGND) (see Figure 144).
Rev. B | Page 27 of 82
ADATE320
Data Sheet
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
VEE
PPMU_S1
VCC
VCCD1
DUT1
VEED1
VEE
PGND
VCC
VEE
AGND
VEE
VCC
PGND
VEE
VEED0
DUT0
VCCD0
VCC
PPMU_S0
VEE
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PIN 1
IDENTIFIER
ADATE320
TOP VIEW
(Not to Scale)
84-LEAD 10mm × 10mm LFCSP
(HEATSINK FACE UP,
DIE FACE DOWN)
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
NC
CFFB0
CFFA0
PGND
DAT0
DAT0
VTTDO
RCV0
RCV0
PGND
CMPL0
CMPL0
VTTC0
CMPH0
CMPH0
VCC
VEE
PGND
VCCTHERM
VTHERM
PGND
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD IS INTERNALLY CONNECTED VIA A HIGH IMPEDANCE DIE ATTACHED TO VEE (SUBSTRATE).
12160-008
AGND
PPMU_M1
DUTGND
PPMU_CMPH1
PPMU_CMPL1
VDD
DGND
ALARM
CS
SDO
SCLK
SDI
RST
BUSY
DGND
VDD
PPMU_CMPL0
PPMU_CMPH0
AGND
PPMU_M0
AGND
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NC
CFFB1
CFFA1
PGND
DAT1
DAT1
VTTD1
RCV1
RCV1
PGND
CMPL1
CMPL1
VTTC1
CMPH1
CMPH1
VCC
VEE
PGND
VREF
VREFGND
PGND
Figure 8. Pin Configuration
Table 22. Pin Function Descriptions
Pin No.
59
58
57
55
56
5
6
7
9
8
53
52
51
49
50
11
12
13
15
14
61
62
65
41
38
Mnemonic
DAT0
DAT0
VTTD0
RCV0
RCV0
DAT1
DAT1
VTTD1
RCV1
RCV1
CMPL0
CMPL0
VTTC0
CMPH0
CMPH0
CMPL1
CMPL1
VTTC1
CMPH1
CMPH1
CFFA0
CFFB0
PPMU_S0
PPMU_M0
PPMU_CMPL0
Description
Driver High Speed Data Input, Channel 0.
Driver High Speed Data Input Complement, Channel 0.
Driver High Speed Input Termination, Channel 0.
Driver High Speed Receive Input, Channel 0.
Driver High Speed Receive Input Complement, Channel 0.
Driver High Speed Data Input, Channel 1.
Driver High Speed Data Input Complement, Channel 1.
Driver High Speed Input Termination, Channel 1.
Driver High Speed Receive Input, Channel 1.
Driver High Speed Receive Input Complement, Channel 1.
Comparator High Speed Output Low, Channel 0.
Comparator High Speed Output Low Complement, Channel 0.
Comparator High Speed Output Termination, Channel 0.
Comparator High Speed Output High, Channel 0.
Comparator High Speed Output High Complement, Channel 0.
Comparator High Speed Output Low, Channel 1.
Comparator High Speed Output Low Complement, Channel 1.
Comparator High Speed Output Termination, Channel 1.
Comparator High Speed Output High, Channel 1.
Comparator High Speed Output High Complement, Channel 1.
PPMU External Compensation Capacitor Pin A, Channel 0.
PPMU External Compensation Capacitor Pin B, Channel 0.
PPMU External Sense Connect, Channel 0.
PPMU Analog Measure Output, Channel 0.
PPMU Go/No-Go Comparator Output Low, Channel 0.
Rev. B | Page 28 of 82
Data Sheet
ADATE320
Pin No.
39
3
2
83
23
26
25
34
32
30
33
31
29
35
Mnemonic
PPMU_CMPH0
CFFA1
CFFB1
PPMU_S1
PPMU_M1
PPMU_CMPL1
PPMU_CMPH1
RST
SCLK
CS
SDI
SDO
ALARM
BUSY
19
20
24
68
80
45
44
16, 48, 66, 67, 72, 76, 81, 82
27, 37
22, 40, 42, 74
28, 36
4, 10, 18, 21, 43, 46, 54, 60, 71, 77
17, 47, 64, 69, 70, 73, 75, 78, 79, 84
1, 63
VREF
VREFGND
DUTGND
DUT0
DUT1
VCCTHERM
VTHERM
VCC, VCCD0, VCCD1
VDD
AGND
DGND
PGND
VEE, VEED0, VEED1
NC
EP
Description
PPMU Go/No-Go Comparator Output High, Channel 0.
PPMU External Compensation Capacitor Pin A, Channel 1.
PPMU External Compensation Capacitor Pin B, Channel 1.
PPMU External Sense Connect, Channel 1.
PPMU Analog Measure Output, Channel 1.
PPMU Go/No-Go Comparator Output Low, Channel 1.
PPMU Go/No-Go Comparator Output High, Channel 1.
Reset Input (Active Low).
Serial Programmable Interface (SPI) Clock Input.
Serial Programmable Interface (SPI) Chip Select Input (Active Low).
Serial Programmable Interface (SPI) Serial Data Input.
Serial Programmable Interface (SPI) Serial Data Output.
Fault Alarm Open-Drain Output (Open-Collector, Active Low).
Serial Programmable Interface (SPI) Busy Output (Open-Collector, Active
Low).
DAC Precision 2.500 V Reference Input.
DAC Precision 0.000 V Reference Input.
DUT Ground Sense Input.
DUT Pin, Channel 0.
DUT Pin, Channel 1.
Temperature Sensor VCC Supply (8.0 V).
Temperature Sensor Analog Output.
Analog Supply (8.0 V).
Digital Supply (1.8 V).
Analog Ground (Quiet).
Digital Ground.
Power Ground.
Analog Supply (−5.0 V).
No Connect. These pins can be grounded or left floating.
Exposed Pad. The exposed pad is internally connected via a high impedance
die attached to VEE (substrate).
Rev. B | Page 29 of 82
ADATE320
Data Sheet
70
3.0
65
2.5
60
2.0
1.5
1.0
50
45
0.5
40
0
35
–0.5
–2
–1
0
1
2
3
4
5
VDUTx (V)
30
54
56
62
60
58
64
66
TIME (ns)
Figure 9. DUTx Pin Leakage in High-Z Mode
Figure 12. DUTx Pin Time-Domain Reflectometry (TDR) Response
0.35
2
0.30
1
VIL
VIH
VIT
0
DRIVER OFFSET (mV)
0.25
LEAKAGE (nA)
55
12160-112
IMPEDANCE (5Ω/DIV)
3.5
12160-109
LEAKAGE (nA)
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.15
0.10
–1
–2
–3
–4
0.05
–1
0
1
2
3
4
5
VDUTx (V)
–6
12160-110
0
–2
0
2
3
4
5
6
7
8
DRIVER CLC SETTING, 3-BIT VALUE
Figure 10. DUTx Pin Leakage in Low Leakage Mode
Figure 13. Driver Offset vs. Driver CLC Setting, 3-Bit Value
8
51.0
50.5
6
LINEARITY ERROR (mV)
50.0
49.5
49.0
48.5
48.0
47.5
4
2
0
–2
–4
47.0
46.0
–60
–40
–30
0
20
40
60
DRIVER OUTPUT CURRENT (mA)
Figure 11. Driver Output Resistance vs. Driver Output Current
–8
–2
–1
0
1
2
Figure 14. Driver VIH INL
Rev. B | Page 30 of 82
3
DRIVER OUTPUT VOLTAGE (V)
4
5
12160-114
–6
46.5
12160-111
DRIVER OUTPUT RESISTANCE (Ω)
1
12160-113
–5
ADATE320
8
2.0
6
1.5
VIL INTERACTION ERROR (mV)
4
2
0
–2
–4
–1
0
1
2
3
4
5
DRIVER OUTPUT VOLTAGE (V)
–0.5
–1.0
–2.0
–2
2.0
6
1.5
4
2
0
–2
–4
1
2
3
4
5
1.0
0.5
0
–0.5
–1.0
0
1
2
3
4
5
DRIVER OUTPUT VOLTAGE (V)
–2.0
–2
12160-116
–1
Figure 16. Driver VIT INL
–1
0
1
2
3
4
5
VIL PROGRAMMED DAC VOLTAGE (V)
12160-119
–1.5
–6
Figure 19. Driver VIT Interaction Error vs. VIH Programmed DAC Voltage
2.0
1.5
1.5
VIT INTERACTION ERROR (mV)
2.0
1.0
0.5
0
–0.5
–1.0
–1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–1
0
1
2
3
VIL PROGRAMMED DAC VOLTAGE (V)
4
5
–2.0
–2
12160-117
–2.0
–2
0
Figure 18. Driver VIL Interaction Error vs. VIH Programmed DAC Voltage
8
–8
–2
–1
VIH PROGRAMMED DAC VOLTAGE (V)
VIT INTERACTION ERROR (mV)
LINEARITY ERROR (mV)
Figure 15. Driver VIL INL
VIH INTERACTION ERROR (mV)
0
–1.5
12160-115
–8
–2
0.5
12160-118
–6
1.0
Figure 17. Driver VIH Interaction Error vs. VIL Programmed DAC Voltage
–1
0
1
2
3
VIL PROGRAMMED DAC VOLTAGE (V)
4
5
12160-120
LINEARITY ERROR (mV)
Data Sheet
Figure 20. Driver VIT Interaction Error vs. VIL Programmed DAC Voltage
Rev. B | Page 31 of 82
ADATE320
Data Sheet
20
1.6
1.2
–20
1.0
VOLTAGE (V)
DRIVER OUTPUT CURRENT (mA)
1.4
0
–40
–60
1V RISE
1V FALL
2V RISE
2V FALL
3V RISE
3V FALL
0.8
0.6
0.4
0.2
–80
–1
0
1
2
3
4
5
6
VDUTx (V)
12160-121
–2
–0.2
38
40
41
42
43
44
45
46
47
TIME (ns)
Figure 21. Driver Output Current Limit, Sink
Figure 24. Driver Large Swing Response
0.14
100
200mV
100mV
50mV
0.12
80
0.10
60
VOLTAGE (V)
DRIVER OUTPUT CURRENT (mA)
39
12160-124
0
–100
–3
40
20
0.08
0.06
0.04
0.02
0
–2
–1
0
1
2
3
4
5
6
VDUTx (V)
–0.02
38
12160-122
–20
–3
42
40
44
46
Figure 25. Driver 100 MHz Response, Small Swing
Figure 22. Driver Output Current Limit, Source
1.8
0.12
3V
2V
1V
1.6
0.10
1.4
50mV RISE
50mV FALL
100mV RISE
100mV FALL
200mV RISE
200mV FALL
0.06
1.2
VOLTAGE (V)
0.08
0.04
1.0
0.8
0.6
0.4
0.02
0.2
0
39
40
41
42
43
44
45
TIME (ns)
46
47
–0.2
38
43
48
53
TIME (ns)
Figure 26. Driver 100 MHz Response, Large Swing
Figure 23. Driver Small Swing Response
Rev. B | Page 32 of 82
58
12160-126
0
–0.02
38
12160-123
VOLTAGE (V)
48
TIME (ns)
12160-125
0
Data Sheet
ADATE320
1.8
0.14
200mV
100mV
50mV
0.12
3V
2V
1V
1.6
1.4
0.10
VOLTAGE (V)
VOLTAGE (V)
1.2
0.08
0.06
0.04
1.0
0.8
0.6
0.4
0.02
0.2
0
38.5
39.0
39.5
40.0
40.5
41.0
TIME (ns)
38.5
39.0
40.0
39.5
TIME (ns)
Figure 27. Driver 800 MHz Response, Small Swing
12160-130
0
–0.2
38.0
12160-127
–0.02
38.0
Figure 30. Driver 1.25 GHz Response, Large Swing
1.8
1.2
3V
2V
1V
1.6
VIH TO/FROM VIT
1.0
1.4
0.8
VOLTAGE (V)
VOLTAGE (V)
1.2
1.0
0.8
0.6
0.4
0.6
0.4
0.2
0.2
0
0
38.5
39.0
39.5
40.0
40.5
41.0
TIME (ns)
Figure 28. Driver 800 MHz Response, Large Swing
40.5
42.5
44.5
46.5
48.5
50.5
52.5
TIME (ns)
12160-131
VIL TO/FROM VIT
–0.2
38.5
12160-128
–0.2
38.0
Figure 31. Driver VIL/VIH to/from VIT, VIH = 2.0 V, VIL = 0.0 V, VIT = 1.0 V; 50 Ω
Terminated
1.0
0.14
200mV
100mV
50mV
0.12
0.8
0.6
VIH TO/FROM HIGH-Z
0.10
VOLTAGE (V)
0.06
0.04
0.2
0
–0.2
–0.4
0.02
–0.6
0
38.5
39.0
39.5
TIME (ns)
Figure 29. Driver 1.25 GHz Response, Small Swing
40.0
–1.0
39
41
43
45
47
TIME (ns)
49
51
53
12160-132
–0.02
38.0
VIL TO/FROM HIGH-Z
–0.8
12160-129
VOLTAGE (V)
0.4
0.08
Figure 32. Driver VIL/VIH to/from High-Z, VIH = 1.0 V, VIL = −1.0 V; 50 Ω
Terminated
Rev. B | Page 33 of 82
ADATE320
Data Sheet
0.20
50
HIGH-Z TO/FROM VIH
HIGH-Z TO/FROM VIL
VIH TO/FROM HIGH-Z
VIL TO/FROM HIGH-Z
TRAILING EDGE ERROR (ps)
0.15
VOLTAGE (V)
0.10
0.05
0
–0.05
–0.10
VIH = 1V POSITIVE PULSE
VIH = 1V NEGATIVE PULSE
VIH = 2V POSITIVE PULSE
VIH = 2V NEGATIVE PULSE
30
10
–10
–30
39.5
40.0
40.5
41.0
41.5
42.0
42.5
43.0
TIME (ns)
Figure 33. Driver to/from High-Z Transient Spike, VIH = VIL = 0.0 V; 50 Ω
Terminated
0.6
–50
0.4
12160-133
–0.20
39.0
1.4
2.4
3.4
4.4
5.4
6.4
7.4
8.4
12160-136
–0.15
9.4
PULSE WIDTH (ns)
Figure 36. Driver Pulse Width (Positive/Negative) Trailing Edge Timing Error,
VIH = 1.0 V, 2.0 V; VIL = 0.0 V; CLC = Midscale; 50 Ω Terminated
CLC = 7
0.5
CLC = 0
VOLTAGE (V)
0.4
0.3
0.2
C7
0.1
CLC = 0
0
–0.1
40.5
41.5
42.5
43.5
44.5
TIME (ns)
Figure 34. Driver Transition vs. CLC, VIH = 1.0 V, VIL = 0.0 V; 50 Ω Terminated
200ps/DIV
Figure 37. Driver Eye Diagram, 800 Mbps, PRBS31, VIH = 50 mV, VIL = 0.0 V;
50 Ω Terminated
VIH = 200mV POSITIVE PULSE
VIH = 200mV NEGATIVE PULSE
VIH = 500mV POSITIVE PULSE
VIH = 500mV NEGATIVE PULSE
30
10
C7
–10
–50
0.4
1.4
2.4
3.4
4.4
5.4
6.4
PULSE WIDTH (ns)
7.4
8.4
9.4
Figure 35. Driver Pulse Width (Positive/Negative) Trailing Edge Timing Error,
VIH = 0.2 V, 0.5 V; VIL = 0.0 V; CLC = Midscale; 50 Ω Terminated
100mV/DIV
500ps/DIV
12160-138
–30
12160-135
TRAILING EDGE ERROR (ps)
50
5.0mV/DIV
12160-137
39.5
12160-134
–0.2
38.5
CLC = 7
Figure 38. Driver Eye Diagram, 800 Mbps, PRBS31, VIH = 1.0 V, VIL = 0.0 V;
50 Ω Terminated
Rev. B | Page 34 of 82
Data Sheet
ADATE320
5.0mV/DIV
100ps/DIV
100mV/DIV
Figure 39. Driver Eye Diagram, 2.5 Gbps, PRBS31, VIH = 50 mV, VIL = 0.0 V;
50 Ω Terminated
12160-142
C7
12160-139
C7
50ps/DIV
Figure 42. Driver Eye Diagram, 4.0 Gbps, PRBS31, VIH = 1.0 V, VIL = 0.0 V;
50 Ω Terminated
5
4
LINEARITY ERROR (mV)
3
C7
2
1
0
–1
–2
–3
–4
–5
–2.0 –1.5 –1.0 –0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V)
Figure 40. Driver Eye Diagram, 2.5 Gbps, PRBS31, VIH = 1.0 V, VIL = 0.0 V;
50 Ω Terminated
12160-143
100ps/DIV
12160-140
100mV/DIV
Figure 43. Reflection Clamp VCLx INL
5
4
LINEARITY ERROR (mV)
3
C7
2
1
0
–1
–2
–3
–5
–0.5
Figure 41. Driver Eye Diagram, 4.0 Gbps, PRBS31, VIH = 50 mV, VIL = 0.0 V;
50 Ω Terminated
Rev. B | Page 35 of 82
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT VOLTAGE (V)
Figure 44. Reflection Clamp VCHx INL
12160-144
50ps/DIV
12160-141
5.0mV/DIV
–4
ADATE320
Data Sheet
10
1.0
0
0.5
0
LINEARITY ERROR (mV)
–30
–40
–50
–0.5
–1.0
–1.5
–60
–2.0
–70
–2.5
–2
0
–1
1
2
3
4
5
6
VDUT (V)
–3.0
–1.5
0
0.5
1.0
1.5
Figure 48. Differential Mode Comparator Threshold INL
1.0
DIFFERENTIAL COMPARATOR OFFSET (mV)
80
70
60
OUTPUT CURRENT (mA)
–0.5
THRESHOLD VOLTAGE (V)
Figure 45. Reflection Clamp Current Limit, VCHx = 5.0 V, VCLx = 4.0 V;
VDUTx Swept from −2.0 V to +5.0 V
50
40
30
20
10
–2
–1
0
1
2
3
4
5
6
VDUT (V)
Figure 46. Reflection Clamp Current Limit, VCHx = −1.0 V, VCLx = −2.0 V;
VDUTx Swept from −2.0 V to +5.0 V
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–2
12160-146
0
–10
–3
–1.0
–1
0
1
2
3
4
5
INPUT COMMON-MODE VOLTAGE (V)
12160-149
–80
–3
12160-148
–20
12160-145
OUTPUT CURRENT (mA)
–10
Figure 49. Differential Mode Comparator Common-Mode Rejection Error
2.0
3
1.5
1
OFFSET (mV)
0.5
0
–0.5
0
–1
–1.0
–2.0
–2
–1
0
1
2
3
4
THRESHOLD VOLTAGE (V)
5
Figure 47. Normal Window Comparator Threshold INL
–3
0
1
2
3
4
5
6
7
COMPARATOR CLC SETTING 3-BIT VALUE
Figure 50. Normal Window Comparator Offset Error vs. CLC Setting
Rev. B | Page 36 of 82
12160-150
–2
–1.5
12160-147
LINEARITY ERROR (mV)
2
1.0
Data Sheet
ADATE320
1.3
3
CMPHx/CMPLx
CMPHx/CMPLx
1.2
2
1.1
VOLTAGE (V)
OFFSET (mV)
1
0
1.0
0.9
–1
0.8
–2
0
1
2
3
4
5
6
7
DIFFERENTIAL COMPARATOR CLC SETTING 3-BIT VALUE
0.6
60
12160-151
–3
62
63
66
Figure 54. Comparator CML Output Waveform (ADATE320)
1.3
140
CMPHx/CMPLx
CMPHx/CMPLx
VOL, SINGLE-ENDED, CH0
VOL, SINGLE-ENDED, CH1
VOH, SINGLE-ENDED, CH0
VOH, SINGLE-ENDED, CH1
120
1.2
100
1.1
VOLTAGE (V)
80
60
40
1.0
0.9
0.8
20
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
PROGRAMMED HYSTERESIS VALUE
0.6
60
12160-152
–20
61
62
63
64
65
66
TIME (ns)
Figure 52. Normal Window Comparator Hysteresis vs. Programmed
Hysteresis Value
12160-155
0.7
0
Figure 55. Comparator CML Output Waveform (ADATE320-1)
250
50
FALLING EDGE
RISING EDGE
VOH, DIFFERENTIAL, CH0
VOL, DIFFERENTIAL, CH0
200
30
150
TPD ERROR (ps)
100
50
10
–10
–30
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
PROGRAMMED HYSTERESIS VALUE
–50
0.4
12160-153
–50
Figure 53. Differential Mode Comparator Hysteresis vs. Programmed
Hysteresis Value
0.5
0.6
0.7
0.8
INPUT WAVEFORM RISE TIME (ns)
0.9
1.0
12160-156
MEASURED HYSTERESIS (mV)
65
64
TIME (ns)
Figure 51. Differential Mode Comparator Offset Error vs. CLC Setting
MEASURED HYSTERESIS (mV)
61
12160-154
0.7
Figure 56. Normal Window Comparator Propagation Delay vs. Input Rise
Time, 1.0 V Input Swing
Rev. B | Page 37 of 82
ADATE320
Data Sheet
NEGATIVE PULSE
POSITIVE PULSE
30
10
M1
–10
–50
0.4
1.4
2.4
3.4
4.4
5.4
6.4
7.4
8.4
9.4
200mV/DIV
PULSE WIDTH (ns)
Figure 57. Normal Window Comparator Pulse Width (Positive/Negative)
Trailing Edge Timing Error, 1.0 V Input Swing
200ps/DIV
12160-160
–30
12160-157
TRAILING EDGE ERROR (ps)
50
Figure 60. Normal Window Comparator Eye Diagram, 800 Mbps, PRBS31,
1.0 V Input Swing; 50 Ω Terminated
1.2
1.0
VOLTAGE (V)
0.8
0.6
M1
0.4
0.2
ERT RISE
INPUT EDGE RISE
1
2
3
4
5
6
7
8
TIME (ns)
Figure 58. Normal Window Comparator Equivalent Rise Time (ERT), 1.0 V
Input Swing, 50 ps 20% to 80%; 50 Ω Terminated
1.2
200mV/DIV
12160-158
–0.2
100ps/DIV
12160-161
0
Figure 61. Normal Window Comparator Eye Diagram, 2.5 Gbps, PRBS31,
1.0 V Input Swing; 50 Ω Terminated
ERT FALL
INPUT EDGE FALL
1.0
VOLTAGE (V)
0.8
0.6
M1
0.4
0.2
1
2
3
4
5
TIME (ns)
6
7
8
200mV/DIV
12160-159
–0.2
Figure 59. Normal Window Comparator Equivalent Fall Time (EFT), 1.0 V
Input Swing, 50 ps 20% to 80%; 50 Ω Terminated
50ps/DIV
12160-162
0
Figure 62. Normal Window Comparator Eye Diagram, 4.0 Gbps, PRBS31,
1.0 V Input Swing; 50 Ω Terminated
Rev. B | Page 38 of 82
Data Sheet
ADATE320
3.0
2.5
LINEARITY ERROR (mV)
2.0
M1
1.5
1.0
0.5
0
–0.5
–1.5
–2
–1
0
1
2
3
4
5
VCOM VOLTAGE (V)
Figure 63. Differential Mode Comparator Eye Diagram, 800 Mbps, PRBS31,
1.0 V Input Swing; 50 Ω Terminated
12160-166
200ps/DIV
12160-163
200mV/DIV
–1.0
Figure 66. Active Load VCOM INL
ACTIVE LOAD CURRENT (mA)
25
M1
10
5
0
0
5
10
15
20
25
PROGRAMMED CURRENT (mA)
12160-167
100ps/DIV
15
LOAD CURRENT =
DAC VOLTAGE/[2×(VREF – VREFGND )] × 25mA
~5mA/1V
12160-164
200mV/DIV
20
Figure 67. Active Load IOHx/IOLx Transfer Function
Figure 64. Differential Mode Comparator Eye Diagram, 2.5 Gbps, PRBS31,
1.0 V Input Swing; 50 Ω Terminated
50
40
LINEARITY ERROR (µA)
30
M1
20
10
0
–10
–20
–40
0
5
10
15
ACTIVE LOAD CURRENT (mA)
Figure 65. Differential Mode Comparator Eye Diagram, 4.0 Gbps, PRBS31,
1.0 V Input Swing; 50 Ω Terminated
Rev. B | Page 39 of 82
Figure 68. Active Load IOHx INL
20
25
12160-168
50ps/DIV
12160-165
200mV/DIV
–30
ADATE320
Data Sheet
25
1.5
20
1.0
10
VIH TO IOH
VIL TO IOH
IOH TO VIH
IOH TO VIL
0.5
VOLTAGE (V)
LINEARITY ERROR (µA)
15
5
0
–5
0
–0.5
–10
–15
–1.0
0
15
10
5
25
20
ACTIVE LOAD CURRENT (mA)
–1.5
35
12160-169
–25
40
45
50
55
TIME (ns)
Figure 69. Active Load IOLx INL
12160-172
–20
Figure 72. Active Load IOHx to/from Driver Transient Response,
VIH = VIL = 0.0 V, IOHx = IOLx = 20 mA; 50 Ω Terminated
1.0
30
0.8
LINEARITY ERROR (mV)
0.6
10
0
–10
–20
–30
–2
–1
0
1
2
3
IOL
IOL
IOL
IOL
IOL
IOL
=
=
=
=
=
=
1mA
5mA
10mA
15mA
20mA
25mA
4
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
5
VDUTx (V)
–1.0
–2
0.08
VOLTAGE (V)
3
5
4
60
PPMU OUTPUT CURRENT (mA)
0.10
2
Figure 73. PPMU Force Voltage INL, All Ranges
IOH TO VIH
IOL TO VIH
VIH TO IOH
VIH TO IOL
0.12
1
0
PMU OUTPUT VOLTAGE (V)
Figure 70. Active Load Commutation Response, VCOM = 2.0 V
0.14
–1
12160-173
IOH =
IOH =
IOH =
IOH =
IOH =
IOH =
12160-170
LOAD CURRENT (mA)
20
0.06
0.04
0.02
0
40
20
0
–20
–40
40
45
TIME (ns)
50
55
–60
–3
12160-171
–0.04
35
Figure 71. Active Load to/from Driver Input/Output Spike, VIH = VIL = 0.0 V,
IOHx = IOLx = 0.0 mA; 50 Ω Terminated
–2
–1
0
1
2
VDUTx (V)
3
4
5
6
12160-174
–0.02
Figure 74. PPMU Force Voltage Output Current Limit, Range A, FV = −1.5 V,
VDUTx Swept −2.0 V to +5.0 V
Rev. B | Page 40 of 82
Data Sheet
ADATE320
60
0.5
0.4
0.3
20
0.2
ERROR (mV)
PPMU OUTPUT CURRENT (mA)
40
0
–20
0.1
0
–0.1
–0.2
–40
–0.3
–60
–1
0
1
2
3
4
5
6
VDUTx (V)
–0.5
–40
12160-175
–2
Figure 75. PPMU Force Voltage Output Current Limit, Range A, FV = 4.5 V,
VDUTx Swept −2.0 V to +5.0 V
–10
0
10
20
30
40
Figure 78. PPMU Force Voltage Compliance Error, Range A, FV = −1.0 V vs.
Output Current, Internal Sense
0.5
0.4
0.003
0.3
0.002
0.2
0.001
ERROR (mV)
0
–0.001
0.1
0
–0.1
–0.2
–0.002
–0.3
–0.003
–2
–1
0
1
2
3
4
5
6
VDUTx (V)
–0.5
–40
Figure 76. PPMU Force Voltage Output Current Limit, Range E, FV = −1.5 V,
VDUTx Swept −2.0 V to +5.0 V
–30
–20
–10
0
10
20
30
40
IDUTx (mA)
12160-179
–0.4
12160-176
–0.004
–3
Figure 79. PPMU Force Voltage Compliance Error, Range A, FV = 4.0 V vs.
Output Current (IDUTx) , Internal Sense
0.004
0.5
0.4
0.003
0.3
0.002
0.2
ERROR (mV)
0.001
0
–0.001
0.1
0
–0.1
–0.2
–0.002
–0.3
–0.003
–2
–1
0
1
2
VDUTx (V)
3
4
5
6
–0.5
–1.0
12160-177
–0.004
–3
–0.4
Figure 77. PPMU Force Voltage Output Current Limit, Range E, FV = 4.5 V,
VDUTx Swept −2.0 V to +5.0 V
–0.8
–0.6
–0.4
–0.2
0
0.2
IDUTx (mA)
0.4
0.6
0.8
1.0
12160-180
PPMU OUTPUT CURRENT (mA)
–20
IDUTx (mA)
0.004
PPMU OUTPUT CURRENT (mA)
–30
12160-178
–0.4
–80
–3
Figure 80. PPMU Force Voltage Compliance Error, Range B, FV = −1.5 V vs.
Output Current(IDUTx), Internal Sense
Rev. B | Page 41 of 82
ADATE320
Data Sheet
0.025
0.4
0.020
0.3
0.015
ERROR (mV)
0.2
0.1
0
–0.1
–0.2
0.010
0.005
0
–0.005
–0.010
–0.3
–0.015
–0.4
–0.020
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
IDUTx (mA)
–0.025
–1.0
12160-181
–0.5
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
PMU OUTPUT CURRENT (mA)
Figure 81. PPMU Force Voltage Compliance Error, Range B, FV = 4.5 V vs.
Output Current (IDUTx), Internal Sense
12160-184
LINEARITY ERROR (µA)
0.5
Figure 84. PPMU Force Current INL, Range C
25
0.0025
20
0.0015
LINEARITY ERROR (µA)
LINEARITY ERROR (µA)
15
10
5
0
–5
–10
–15
0.0005
–0.0005
–0.0015
–30
–20
–10
0
10
30
20
40
PMU OUTPUT CURRENT (mA)
–0.0025
–0.010
12160-182
–25
–40
–0.005
0
0.005
0.010
PMU OUTPUT CURRENT (mA)
12160-185
–20
Figure 85. PPMU Force Current INL, Range D
Figure 82. PPMU Force Current INL, Range A
0.0005
0.25
0.20
0.0003
LINEARITY ERROR (µA)
0.10
0.05
0
–0.05
–0.10
0.0001
–0.0001
–0.0003
–0.15
–0.25
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
PMU OUTPUT CURRENT (mA)
0.8
1.0
–0.0005
–0.0020
–0.0010
0
0.0010
PMU OUTPUT CURRENT (mA)
Figure 86. PPMU Force Current INL, Range E
Figure 83. PPMU Force Current INL, Range B
Rev. B | Page 42 of 82
0.0020
12160-186
–0.20
12160-183
LINEARITY ERROR (µA)
0.15
Data Sheet
ADATE320
0.5
50
0.4
40
0.3
30
ERROR (µA)
ERROR (µA)
0.2
20
10
0
0.1
0
–0.1
–0.2
–10
–0.3
–20
–1
0
1
2
3
4
5
VDUTx (V)
Figure 87. PPMU Force Current Compliance Error, Range A, FI = −40 mA vs.
Output Voltage (VDUTx)
–1
0
1
2
3
4
12160-190
–0.4
–0.5
–2
12160-187
–30
–2
5
VDUTx (V)
Figure 90. PPMU Force Current Compliance Error, Range B, FI = 1 mA vs.
Output Voltage (VDUTx)
20
0.05
0.04
15
0.03
10
ERROR (µA)
ERROR (µA)
0.02
5
0
–5
0.01
0
–0.01
–0.02
–10
–0.03
–15
0
1
2
3
4
5
VDUTx (V)
Figure 88. PPMU Force Current Compliance Error, Range A, FI = 40 mA vs.
Output Voltage (VDUTx)
0.04
0.3
0.03
0.2
0.02
ERROR (µA)
0.05
0.4
0
–0.1
–0.03
–0.4
–0.04
1
2
VDUTx (V)
3
4
5
Figure 89. PPMU Force Current Compliance Error, Range B, FI = −1 mA vs.
Output Voltage (VDUTx)
3
4
5
–0.01
–0.3
0
2
0
–0.02
–1
1
0.01
–0.2
–0.5
–2
0
Figure 91. PPMU Force Current Compliance Error, Range C, FI = −100 µA vs.
Output Voltage (VDUTx)
0.5
0.1
–1
VDUTx (V)
–0.05
–2
12160-189
ERROR (µA)
–0.05
–2
–1
0
1
2
VDUTx (V)
3
4
5
12160-192
–1
12160-191
–0.04
12160-188
–20
–2
Figure 92. PPMU Force Current Compliance Error, Range C, FI = 100 µA vs.
Output Voltage (VDUTx)
Rev. B | Page 43 of 82
ADATE320
Data Sheet
1.0
0.0010
0.5
LINEARITY ERROR (mV)
ERROR (µA)
0.0005
0
–0.0005
0
–0.5
–1.0
–1
0
1
2
3
4
5
VDUTx (V)
–2.0
–0.5
12160-193
–0.0010
–2
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
OUTPUT VOLTAGE (V)
Figure 93. PPMU Force Current Compliance Error, Range E, FI = −2 µA vs.
Output Voltage (VDUTx)
12160-196
–1.5
Figure 96. PPMU Voltage Clamp PCHx INL
0.0010
20
15
LINEARITY ERROR (µA)
ERROR (µA)
0.0005
0
–0.0005
10
5
0
–5
–10
–1
0
1
2
3
4
5
VDUTx (V)
–20
–40
12160-194
–0.0010
–2
–30
–25
–20
–15
–10
–5
0
OUTPUT CURRENT (mA)
Figure 94. PPMU Force Current Compliance Error, Range E, FI = 2 µA vs.
Output Voltage (VDUTx)
Figure 97. PPMU Current Clamp PCLx INL, Range A
1.0
20
15
LINEARITY ERROR (µA)
0.5
0
–0.5
–1.0
10
5
0
–5
–10
–1.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
OUTPUT VOLTAGE (V)
3.0
3.5
Figure 95. PPMU Voltage Clamp PCLx INL
–20
0
5
10
15
20
25
30
35
OUTPUT CURRENT (mA)
Figure 98. PPMU Current Clamp PCHx INL, Range A
Rev. B | Page 44 of 82
40
12160-198
–15
12160-195
LINEARITY ERROR (mV)
–35
12160-197
–15
Data Sheet
ADATE320
0.05
0.5
0.4
0.03
LINEARITY ERROR (µA)
LINEARITY ERROR (µA)
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
0.01
–0.01
–0.03
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
OUTPUT CURRENT (mA)
–0.05
12160-199
–0.5
–1.0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
OUTPUT CURRENT (mA)
Figure 99. PPMU Current Clamp PCLx INL, Range B
12160-202
–0.4
Figure 102. PPMU Current Clamp PCHx INL, Range C
0.005
0.5
0.4
0.003
LINEARITY ERROR (µA)
LINEARITY ERROR (µA)
0.3
0.2
0.1
0
–0.1
–0.2
0.001
–0.001
–0.003
–0.3
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
OUTPUT CURRENT (mA)
–0.005
–0.10 –0.09 –0.08 –0.07 –0.06 –0.05 –0.04 –0.03 –0.02 –0.01
Figure 100. PPMU Current Clamp PCHx INL, Range B
Figure 103. PPMU Current Clamp PCLx INL, Range D
0.005
0.03
0.003
LINEARITY ERROR (µA)
0.05
0.01
–0.01
–0.03
0.001
–0.001
–0.003
–0.05
–0.10 –0.09 –0.08 –0.07 –0.06 –0.05 –0.04 –0.03 –0.02 –0.01
OUTPUT CURRENT (mA)
0
12160-201
LINEARITY ERROR (µA)
0
OUTPUT CURRENT (mA)
Figure 101. PPMU Current Clamp PCLx INL, Range C
–0.005
0
0.002
0.004
0.006
0.008
OUTPUT CURRENT (mA)
Figure 104. PPMU Current Clamp PCHx INL, Range D
Rev. B | Page 45 of 82
0.010
12160-204
0
12160-200
–0.5
12160-203
–0.4
ADATE320
Data Sheet
0.0010
0.10
0.08
LINEARITY ERROR (µA)
LINEARITY ERROR (µA)
0.06
0.0005
0
0.04
0.02
0
–0.02
–0.04
–0.0005
–0.06
–0.0015
–0.0010
–0.0005
0
OUTPUT CURRENT (mA)
–0.10
–1.0
12160-205
–0.0010
–0.0020
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
IDUTx (mA)
12160-208
–0.08
Figure 108. PPMU Measure Current INL, Range B
Figure 105. PPMU Current Clamp PCLx INL, Range E
0.0010
0
PPMU MEASURE PIN CMRR (mV)
LINEARITY ERROR (µA)
–0.05
0.0005
0
–0.0005
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
0
0.0005
0.0010
0.0015
0.0020
OUTPUT CURRENT (mA)
–0.50
–1.0
12160-206
–0.0010
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VDUTx (V)
12160-209
–0.45
Figure 109. PPMU Measure Current Common-Mode Rejection Error, Force
Voltage Measure Current (FVMI), Source 0.5 mA
Figure 106. PPMU Current Clamp PCHx INL, Range E
0.6
0.10
0.08
0.5
0.4
VOLTAGE (V)
0.04
0.02
0
–0.02
–0.04
0.3
RANGE A RISE
RANGE A FALL
0.2
0.1
–0.06
–0.10
–2
–1
0
1
2
3
4
VDUTx (V)
Figure 107. PPMU Measure Voltage INL, Range B
5
–0.1
0
5
10
TIME (µs)
15
20
12160-210
0
–0.08
12160-207
LINEARITY ERROR (mV)
0.06
Figure 110. PPMU Force Voltage Transient Response, Range A, 0.0 V to 0.5 V,
Uncalibrated, CLOAD = 200 pF
Rev. B | Page 46 of 82
Data Sheet
ADATE320
0.6
0.7
0.6
0.5
0.5
0.4
VOLTAGE (V)
VOLTAGE (V)
0.4
0.3
RANGE B RISE
RANGE B FALL
0.2
0.3
RANGE B RISE
RANGE B FALL
0.2
0.1
0.1
0
0
0
5
10
15
20
TIME (µs)
–0.2
12160-211
–0.1
Figure 111. PPMU Force Voltage Transient Response, Range B, 0.0 V to 0.5 V,
Uncalibrated, CLOAD = 200 pF
5
0
20
15
10
TIME (µs)
12160-214
–0.1
Figure 114. PPMU Force Voltage Transient Response, Range B, 0.0 V to 0.5 V,
Uncalibrated, CLOAD = 2000 pF
0.6
0.7
0.6
0.5
0.5
0.4
VOLTAGE (V)
VOLTAGE (V)
0.4
0.3
RANGE C RISE
RANGE C FALL
0.2
0.3
RANGE C RISE
RANGE C FALL
0.2
0.1
0.1
0
0
0
10
20
30
40
50
TIME (µs)
–0.2
12160-212
–0.1
Figure 112. PPMU Force Voltage Transient Response, Range C, 0.0 V to 0.5 V,
Uncalibrated, CLOAD = 200 pF
10
0
20
30
40
50
60
TIME (µs)
12160-215
–0.1
Figure 115. PPMU Force Voltage Transient Response, Range C, 0.0 V to 0.5 V,
Uncalibrated, CLOAD = 2000 pF
0.6
4.9
4.4
0.5
3.9
3.4
VOLTAGE (V)
VOLTAGE (V)
0.4
0.3
RANGE A RISE
RANGE A FALL
0.2
2.9
RANGE A RISE
RANGE A FALL
2.4
1.9
1.4
0.1
0.9
0
0
5
10
TIME (µs)
15
20
–0.1
12160-213
–0.1
Figure 113. PPMU Force Voltage Transient Response, Range A, 0.0 V to 0.5 V,
Uncalibrated, CLOAD = 2000 pF
0
10
20
30
40
TIME (µs)
50
60
70
80
12160-216
0.4
Figure 116. PPMU Force Voltage Transient Response, Range A, 0.0 V to 4.0 V,
Uncalibrated, CLOAD = 200 pF
Rev. B | Page 47 of 82
Data Sheet
4.9
4.9
4.4
4.4
3.9
3.9
3.4
3.4
VOLTAGE (V)
RANGE B RISE
RANGE B FALL
2.4
1.9
1.9
1.4
0.9
0.9
0.4
0.4
10
20
30
40
50
60
70
–0.1
12160-217
0
80
TIME (µs)
Figure 117. PPMU Force Voltage Transient Response, Range B, 0.0 V to 4.0 V,
Uncalibrated, CLOAD = 200 pF
0
4.4
3.9
3.9
3.4
3.4
VOLTAGE (V)
4.4
2.4
1.9
0.9
0.4
0.4
150
TIME (µs)
Figure 118. PPMU Force Voltage Transient Response, Range C, 0.0 V to 4.0 V,
Uncalibrated, CLOAD = 200 pF
140
RANGE C RISE
RANGE C FALL
–0.1
300
12160-218
130
110
120
1.9
0.9
90
100
80
2.4
1.4
70
60
2.9
1.4
–0.1
50
40
Figure 120. PPMU Force Voltage Transient Response, Range B, 0.0 V to 4.0 V,
Uncalibrated, CLOAD = 2000 pF
4.9
RANGE C RISE
RANGE C FALL
20
TIME (µs)
4.9
2.9
RANGE B RISE
RANGE B FALL
2.4
1.4
–0.1
VOLTAGE (V)
2.9
12160-220
2.9
600
500
400
700
800
TIME (µs)
12160-221
VOLTAGE (V)
ADATE320
Figure 121. PPMU Force Voltage Transient Response, Range C, 0.0 V to 4.0 V,
Uncalibrated, CLOAD = 2000 pF
4.9
5.9
4.4
4.9
3.9
3.9
VOLTAGE (V)
VOLTAGE (V)
3.4
2.9
RANGE A RISE
RANGE A FALL
2.4
1.9
RANGE A RISE
RANGE A FALL
2.9
1.9
1.4
0.9
0.9
0
20
40
60
80
TIME (µs)
100
120
140
–0.1
12160-219
–0.1
0
50
100
TIME (µs)
Figure 119. PPMU Force Voltage Transient Response, Range A, 0.0 V to 4.0 V,
Uncalibrated, CLOAD = 2000 pF
150
200
12160-222
0.4
Figure 122. PPMU Force Current Transient Response, Range A, Full-Scale
Transition, Uncalibrated, CLOAD = 200 pF, RLOAD = 127 Ω
Rev. B | Page 48 of 82
Data Sheet
ADATE320
2.4
1.0
POH MV
POL MV
0.8
0.6
LINEARITY ERROR (mV)
VOLTAGE (V)
1.9
1.4
RANGE B RISE
RANGE B FALL
0.9
0.4
0.4
0.2
0
–0.2
–0.4
–0.6
0
50
100
150
200
TIME (µs)
–1.0
–2
12160-223
–0.1
–1
0
1
2
3
4
12160-225
–0.8
5
THRESHOLD VOLTAGE (V)
Figure 123. PPMU Force Current Transient Response, Range B, Full-Scale
Transition, Uncalibrated, CLOAD = 200 pF, RLOAD = 1.8 kΩ
Figure 125. PPMU Go/No-Go Comparator Threshold INL
2.4
6
5
1.9
4
ERROR (mV)
VOLTAGE (V)
3
1.4
RANGE C RISE
RANGE C FALL
0.9
2
1
0
–1
0.4
0
50
100
TIME (µs)
150
200
–3
–0.15
12160-224
–0.1
Figure 124. PPMU Force Current Transient Response, Range C, Full-Scale
Transition, Uncalibrated, CLOAD = 200 pF, RLOAD = 18.5 kΩ
–0.10
–0.05
0
0.05
DUTGND VOLTAGE (V)
0.10
0.15
12160-226
–2
Figure 126. Typical DUTGND Transfer Function Voltage Error, Drive Low,
VIL = 0.0 V
Rev. B | Page 49 of 82
ADATE320
Data Sheet
THEORY OF OPERATION
SERIAL PROGRAMMABLE INTERFACE (SPI)
SPI Hardware Interconnect Details
ADATE320
ADATE320
ADATE320
(CHIP 0)
(CHIP 1)
(CHIP n)
SCLK
SDI
SDI
SDO
SDO
SDO
BUSY
BUSY
BUSY
CS
CS
CS
CS1
CSn
SCLK
SDI
CS0
SCLK
SCLK
SDI
SDO
CS[n:0]
12160-015
BUSY
n
Figure 127. Multiple SPI with a Shared SDO Line
SPI Reset Sequence and the RST Pin
The internal state of the ADATE320 is indeterminate following
power-up. For this reason, it is necessary to perform a valid
hardware reset sequence as soon as the power supplies are
stabilized. The ADATE320 provides an active low reset pin
(RST) for this purpose. Asserting RST asynchronously initiates
a reset sequence. Furthermore, the RST pin must be asserted
before and during the power-up cycling sequence, and released
only after all power supplies are guaranteed to be stable.
A soft reset sequence can also be initiated under SPI software
control by writing to the SPI_RESET bit (see Figure 147). In the
case of a soft reset, the sequence begins on the first rising edge
of SCLK following the release of CS, subject to the normal setup
and hold times. Certain actions occur immediately upon the
initiation of the reset request, whereas other actions require
several cycles of SCLK.
The following asynchronous actions occur immediately following
the detection of the reset request, whether it was hardware (RST) or
software (SPI) initiated:
•
•
•
•
•
Assert open-drain BUSY pin
Force all control registers to their default reset states as
defined in Table 29
Clear all calibration registers to their default reset states as
defined in Table 29
Override all DAC analog outputs and force dc levels to
VDUTGND, disable the driver and PPMU functions
Enable active loads with IOHx = IOLx = 100 µA
(uncalibrated and expected to vary with offset from device
to device); soft connect DUTx pins to VCOM = VDUTGND
The device remains in this static reset state indefinitely until the
clocked portion of the sequence begins with either the first rising
edge of SCLK following the release of RST in the case of an
asynchronous hardware reset, or the second rising edge of
SCLK following the release of CS in the case of a software SPI
reset. Regardless of how the reset sequence was initiated, the
clocked portion of the sequence requires 744 SCLK cycles to
run through to completion, and the open-drain BUSY pin (if
available) remains asserted until all clock cycles are received.
The following actions occur during the clocked portion of the
reset sequence:
•
•
•
•
Complete initialization of internal SPI controller
Write default values to appropriate DAC X2 registers
Enable the thermal alarm with a 100°C threshold
Disable the PPMU clamp and overvoltage detect (OVD)
alarms
The 744 rising edges of SCLK release BUSY and start a self
timed DAC deglitch period of approximately 3 µs. DAC voltages
begin to change as soon as the deglitch circuits time out. An
additional 10 µs is required to settle to the final values. A full
reset sequence thus requires approximately 30 µs, comprising 16 µs
(744 cycles × 20 ns) for post reset initialization, 3 µs for DAC
deglitch, and another 10 µs for DAC analog level settling.
Rev. B | Page 50 of 82
Data Sheet
ADATE320
SPI Clock Cycles and the BUSY Pin
The ADATE320 offers a digital BUSY output pin to indicate that
the SPI controller requires more SCLK cycles to be input on the
SCLK pin. The device may be operated without this pin, but care
must be exercised to ensure that the required number of SCLK
cycles are provided in each case to complete each SPI instruction.
After any valid SPI instruction is written to the ADATE320, the
BUSY pin is asserted to indicate a busy status of the DAC update
and calibration routines. The BUSY pin is an open-drain output
capable of sinking a minimum of 2 mA from the VDD supply. It
is recommended to tie the BUSY pin to VDD with an external 1 kΩ
pull-up resistor.
It is not a requirement to wait for release of BUSY prior to a
subsequent assertion of the CS pin. As long as the minimum
number of SCLK cycles following the previous release of CS is
met according to the tCSAM parameter, the CS pin can again be
asserted for another SPI operation. With the one exception of
recovery from a reset request (either by hardware assertion of
RST pin or software setting of the internal SPI_RESET control bit),
there is no scenario in normal operation of the ADATE320 in
which the user must wait for release of BUSY before asserting
the CS pin for a subsequent SPI operation. The only requirement
on the assertion of CS is that the tCSAM parameter has been met
as defined in Figure 2 and Table 14.
It is very important, however, that the SCLK pin continue to
operate for as long as the BUSY pin state remains active. This
period of time is defined by the parameter tBUSW and is defined in
Figure 2, Table 14, and Table 23. If the SCLK pin does not remain
active for at least the number of cycles specified, operations
pending to the internal processor may not fully complete. In
such a case, a temporary malfunction of the ADATE320 may
occur, or unexpected results may be obtained. After the device
releases the BUSY pin (or the required minimum number of clock
cycles is satisfied), SCLK may again be stopped to prevent any
unwanted digital noise from coupling into the analog functions.
In every case (with no exception for reset recovery), it is the
purpose of the BUSY pin to notify the supervisory ASIC or FGPA
that it is again safe to stop the SCLK signal. Running SCLK for
extra periods when BUSY is not active is never a problem except
for the possibility of adding unwanted digital switching noise
into analog functions.
The required length of the BUSY period (tBUSW) is variable
depending on the particular preceding SPI instruction, but it is
always deterministic. It depends only on factors such as whether
the previous instruction involved a write to one or more DAC
addresses, and, if so, how many channels were involved and
whether calibration was enabled. Table 23 details the length of
the tBUSW requirement in units of rising edge SCLK cycles for
each possible SPI instruction scenario, including recovery from
a hardware RST reset.
Because tBUSW is deterministic, it is therefore possible to predict
in advance the minimum number of rising edge SCLK cycles
that are required to complete any given SPI instruction, which
makes it possible to operate the device without a need to monitor
the BUSY pin. For applications in which it is neither possible
nor desirable to monitor the pin, it is acceptable to use the
deterministic information provided in Table 23 to guarantee the
minimum number of cycles is provided. Either way, it is necessary
to honor the minimum number of required rising edge SCLK
cycles, as defined by tBUSW, following the release of CS for each
of the SPI instruction scenarios listed.
Table 23. BUSY Minimum SCLK Cycle Requirements
SPI Instruction Type (Single- or Dual-Channel Operation)
Following Release of Asynchronous RST Reset Pin (Hardware Reset)
Following Assertion of the SPI_RESET Control Bit (Software Reset)
Write to No Operation (NOP) (Address 0x00, Address 0x20, Address 0x50, Address 0x60)
Write to a Valid Address That Is Not a DAC (Address > 0x10)
Write to Any DAC Except VILx or VIHx (Address 0x01 to Address 0x0F, Except Address 0x01 and
Address 0x03)
Write to VILx or VIHx DAC (Address 0x01 or Address 0x03)
Rev. B | Page 51 of 82
Minimum tBUSW (SCLK Cycles)
744
744
3
3
18
21
ADATE320
Data Sheet
SPI Read/Write Register Definition
SPI CLOCK INDEX
0
1
2
3
4
5
6
7
SPI WORD INDEX
C1
C0
A6
A5
A4
A3
A2
A1
15
16
17
18
19
20
21
22
23
24
25
A0 R/W D15 D14 D13 D12 D11 D10
8
9
10
11
12
13
14
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CHANNEL SELECT
00 = NOP
01 = READ/WRITE CHANNEL 0
10 = READ/WRITE CHANNEL 1
11 = READ NOP
11 = WRITE CHANNEL 0 AND 1
ADDRESS FIELD
12160-016
READ/WRITE SELECT
0 = READ: THE CONTENTS OF REGISTER SPECIFIED BY ADDR[6:0]
AND CH[1:0] ARE SHIFTED OUT ON THE SDO PIN
DURING THE NEXT SPI INSTRUCTION CYCLE.
1 = WRITE: DATA[15:0] IS WRITTEN TO THE REGISTER
SPECIFIED BY ADDR[6:0] AND CH[1:0].
DATA FIELD
Figure 128. SPI Word Definition
The ADATE320 is configured through a collection of 16-bit
registers as defined in Table 29. Mode configuration, DAC level
settings, calibration constants, and alarm flags status can all be
controlled and monitored by accessing the respective registers.
Specific access to any 16-bit register is made through a serial
programmable interface (SPI). A single SPI control register is
exposed to the user by this hardware SPI interface. The format
of the SPI Control Register is illustrated in Figure 128. The SPI
control register includes address and channel information,
read/write direction, and a 16-bit data field. Any valid SPI write
instruction cycle populates all these fields, and the ADATE320
subsequently operates on the addressed channel and register
using the data provided. Any valid SPI read instruction cycle
populates only the address and channel fields, and the
ADATE320 makes the addressed register contents in the 16-bit
data field available for subsequent readout at the SDO pin.
Detailed SPI timing diagrams for each read/write operation
type are provided in Figure 2 through Figure 7. Respective dc
and ac timing parameters are provided in Table 13 and Table 14,
respectively.
A typical hardware wiring diagram for the SPI is illustrated in
Figure 127.
LEVEL SETTING DACS
DAC Update Modes
The ADATE320 provides 32 16-bit integrated level setting
DACs organized as two channel banks of 16 DACs each. The
detailed mapping of each DAC register to each pin electronics
function is shown in Table 29. Each DAC can be individually
programmed by writing data to the respective SPI register address
and channel.
The ADATE320 provides two methods for updating analog DAC
levels: DAC immediate update mode and DAC deferred update
mode. At the release of the CS pin associated with any valid SPI
write to a DAC address, the update of the analog levels can start
immediately or can be deferred, depending on the state of the
DAC_LOAD_MODE control bit in the DAC control register (see
Figure 146). Initiation of the analog level update sequence (and
triggering of the on-chip deglitch circuit) begins four SCLK cycles
following the associated release of CS pin. For the purpose of this
data sheet, the analog level update sequence is assumed to start
coincident with the release of CS. The DAC update mode can be
selected independently for each channel bank.
If the DAC_LOAD_MODE control bit for a given channel bank
is cleared, the DACs assigned to that channel bank are placed in
the DAC immediate update mode. Writing to any DAC within
that channel causes the corresponding analog levels to be updated
immediately following the associated release of CS. Because all
analog levels are updated on a per channel basis, any previously
pending DAC writes queued to that channel (while in an earlier
deferred update mode) are also updated at this time. This situation
can arise if DAC writes are queued to the channel while in deferred
update mode, and then the DAC_LOAD_MODE bit is subsequently changed to immediate update mode before writing to the
respective DAC_LOAD control bit (see Figure 146). The queued
data is not lost. Note that writing to the DAC_LOAD control bit
has no effect while in immediate update mode.
If the DAC_LOAD_MODE control bit for a given channel is set,
then the DACs assigned to that channel bank is in the deferred
update mode. Writing to any DAC of that channel only queues the
DAC data into that channel. The analog update of queued DAC
levels is deferred until the respective DAC_LOAD control bit is set
(see Figure 146). The DAC deferred update mode, in conjunction
with the respective DAC_LOAD control bit, provides the means
to queue all DAC level writes to a given channel bank before synchronously updating the analog levels with a single SPI command.
Rev. B | Page 52 of 82
Data Sheet
ADATE320
The OVDH and OVDL DAC levels do not fit neatly within a
particular channel bank. However, they must be updated as a
part of the channel bank to which they are assigned, as shown
in Table 29.
The ADATE320 provides a feature in which a single SPI write
operation can address two channels at one time. With this feature,
a single SPI write operation can address corresponding DACs
on both channels at the same time, even though the channels may
be configured with different DAC update modes. In such a case, the
device behaves as expected. For example, if both channels are in
immediate update mode, the update of analog levels of both
channel banks begins following the associated release of the CS pin.
If both channels are in deferred update mode, the update of analog
levels is deferred for both channels until the corresponding DAC_
LOAD control bit is set. If one channel is in deferred update mode
and the other is in immediate update mode, the deferred channel
defers analog updates until the corresponding DAC_LOAD bit
is written, and the immediate channel begins analog updates
immediately following release of the CS pin.
bank has its own dedicated deglitch circuitry, and each channel
may therefore operate independently.
A deglitch circuit can be retriggered if an analog level update is
initiated before a previous update operation on that channel
completes. Analog transitions at the DAC outputs do not begin
until after the deglitch circuit times out. Final settling to full
precision requires an additional 7 µs beyond the end of the 3 µs
deglitch interval. The total DAC settling time following the
release of the associated CS pin is approximately 10 µs maximum.
Note that an extended retriggering sequence of the deglitch
circuit on one channel may cause the apparent settling time of
analog levels on that channel to appear delayed longer than the
specified 10 µs.
A typical DAC update sequence is illustrated in Figure 129. In
this example, consecutive immediate mode DAC updates are
written in direct succession. This example was chosen to
illustrate what happens when a DAC update command is
written before the previous update command finishes its
deglitch and settling sequence.
An on-chip deglitch circuit with a period of approximately 3 µs
is provided to prevent DAC-to-DAC crosstalk within a channel
whenever an analog update is processed. Each DAC channel
tSPI
SCLK
CS
SDI
WRITE DAC 1
WRITE DAC 0
BUSY
±0.5 LSB
DAC0
DAC1
DAC2
DAC3
BEGINNING OF 3µs
DEGLITCH PERIOD
RETRIGGER OF 3µs
DEGLITCH PERIOD
COMPLETION OF 3µs
DEGLITCH PERIOD
tSPI
3µs
tDAC
Figure 129. SPI DAC Write Timing Diagram and Settling of DC Levels
Rev. B | Page 53 of 82
12160-026
DAC15
ADATE320
Data Sheet
DAC Levels and VTHERM Pin Transfer Function
Table 24. Detailed DAC Code to/from Voltage Level Transfer Functions
Level
VILx, VIHx, VITx/VCOMx, VOLx, VOHx, POLx,
POHx, VCHx, VCLx, PCHx, PCLx, OVDHx,
OVDLx, PPMUx (FV), PCHx (FI), PCLx (FI)
IOHx, IOLx
PPMUx (FI, Range A), PCHx and PCLx (FV,
Range A)
PPMUx (FI, Range B), PCHx and PCLx (FV,
Range B)
PPMUx (FI, Range C), PCHx and PCLx (FV,
Range C)
PPMUx (FI, Range D) PCHx and PCLx (FV,
Range D)
PPMUx (FI, Range E) PCHx and PCLx (FV,
Range E)
Programmable Range
(0x0000 to 0xFFFF)
−2.5 V to +7.5 V
−12.5 mA to +37.5 mA
−80 mA to +80 mA
−2 mA to +2 mA
−200 µA to +200 µA
−20 µA to +20 µA
−4 µA to +4 µA
DAC-to-Level and Level-to-DAC Transfer Functions
VDUTx = (4 × (DAC/216) − 1) × (VREF − VREFGND) + VDUTGND
DAC = ((VDUTx − VDUTGND) + (VREF − VREFGND))/(4 × (VREF −VREFGND)) × 216
IDUTx = (4 × (DAC/216) − 1) × (VREF − VREFGND) × (25 mA/5)
DAC = ((IDUTx × (5/25 mA)) + (VREF − VREFGND))/(4 × (VREF − VREFGND)) × 216
IDUTx = (4 × (DAC/216) − 2) × (VREF − VREFGND) × (80 mA/5)
DAC = ((IDUTx/80 mA × 5) + 2 × (VREF − VREFGND))/(4 × (VREF − VREFGND)) × 216
IDUTx = (4 × (DAC/216) − 2) × (VREF − VREFGND) × (2 mA/5)
DAC = ((IDUTx/2 mA × 5) + 2 × (VREF − VREFGND))/(4 × (VREF − VREFGND)) × 216
IDUTx = (4 × (DAC/216) − 2) × (VREF − VREFGND) × (200 µA/5)
DAC = ((IDUTx/200 µA × 5) + 2 × (VREF − VREFGND))/(4 × (VREF − VREFGND)) × 216
IDUTx = (4 × (DAC/216) − 2) × (VREF − VREFGND) × (20 µA/5)
DAC = ((IDUTx/20 µA × 5) + 2 × (VREF − VREFGND))/(4 × (VREF − VREFGND)) × 216
IDUTx = (4 × (DAC/216) − 2) × (VREF − VREFGND) × (4 µA/5)
DAC = ((IDUTx/4 µA × 5) + 2 × (VREF − VREFGND))/(4 × (VREF − VREFGND)) × 216
Table 25. Load Transfer Functions
Load Level
IOLx
IOHx
Transfer Functions
VIOLx/(2 × (VREF − VREFGND)) × 25 mA
VIOHx/(2 × (VREF − VREFGND)) × 25 mA
Notes
VIOLx DAC levels are not referenced to VDUTGND
VIOHx DAC levels are not referenced to VDUTGND
Table 26. PPMU Transfer Functions
PPMU Mode
FV
FI
MV
MV
MI
1
Transfer Functions 1
VDUTx = PPMUx
IDUTx = (PPMUx − (VREF − VREFGND))/(5 × RPPMU)
VPPMU_Mx = VDUTx (internal sense path)
VPPMU_Mx = VPPMU_Sx (external sense path)
VPPMU_Mx = (VREF − VREFGND) + (5 × IDUTx × RPPMU) + VDUTGND
Uncalibrated PPMU DAC Settings to Achieve Specified PPMU Range
−1.5 V < PPMUx < +4.5 V
0.0 V < PPMUx < 5.0 V
Not applicable
Not applicable
Not applicable
RPPMU = 12.5 Ω for Range A, 500 Ω for Range B, 5.0 kΩ for Range C, 50 kΩ for Range D, and 250 kΩ for Range E.
Table 27. Temperature Sensor Transfer Function
Temperature
0K
300 K
TKELVIN
Output
0.00 V
3.00 V
0.00 V + (TKELVIN ) × 10 mV/K
Rev. B | Page 54 of 82
Data Sheet
ADATE320
DAC Gain and Offset Correction
DAC X2 Registers and SPI Readback
Each analog function within the ADATE320 has independent
gain (m) and offset (c) calibration registers that allow digital
trim of first-order errors in the analog signal chain. These registers
correct errors in the pin electronics transfer functions as well as
errors intrinsic to the DAC itself.
When data is written via the SPI to a particular DAC, that data
is operated on in accordance with Equation 1. The results are stored
in an X2 register associated with that DAC (see Figure 130).
The m and c registers are volatile and must be reloaded after
each power-on cycle as part of a calibration routine if values
other than the defaults are required. The registers are not cleared
by any reset operation (although the DAC_CAL_ENABLE bit
is cleared following reset).
The gain and offset calibration function can be bypassed by
clearing the DAC_CAL_ENABLE bit in the DAC control
register (see Figure 146). This bypass mode is available only on
a per chip basis. In other words, it is not possible to bypass the
calibration function for a specific subset of the DACs.
The calibration function, when enabled, adjusts the numerical
data sent to each DAC according to the following equation:
 m + 1

X 2 =   16  × X1  + (c − 215 )
 2 

(1)
where:
X2 is the 16-bit data-word gated into the physical DAC, and
returned by subsequent SPI read from that same DAC.
m is the code in the respective DAC gain calibration register
(the default code is 0xFFFF = 216 − 1).
X1 is the 16-bit data-word written by the user to the DAC via
the SPI.
c is the code in the respective DAC offset calibration register
(the default code is 0x8000 = 215).
From Equation 1, it can be seen that the gain applied to any
written X1 data is always ≤1.0, with the effect that the effective
output of a DAC can only be made smaller in magnitude by the
calibration mechanism. To compensate for this imposed limitation,
each of the analog signal paths in the pin electronics functions
are guaranteed by designed to have a gain ≥1.0 when the default
m register values are applied. A signal path gain ≥1.0 guarantees
that proper gain calibration can always be achieved by
multiplying down.
There is only a single physical X2 register per DAC, and it is the
value of this X2 register that is eventually gated into the physical
DAC at the time of analog update, which can be either in immediate or deferred mode. It is also this register value that is returned
to the user during an SPI read operation addressed to that DAC
channel. In the special case of a dual channel write to a DAC, both
of the associated X2 registers are sequentially updated using the
appropriate m register and c register for each channel.
When enabled, the calibration function applies this operation to
the X2 registers only after a SPI write to the respective X1 registers.
The X2 registers are not updated after write operations to either
m register or c register or following any changes to functional
modes or range settings of the device. For this reason, to ensure
that calibration data is recalculated for any particular DAC, it is
necessary to write fresh data to that DAC after changes are first
made to the associated m register and c register, and any associated
functional modes and ranges for that DAC function.
For each DAC, there is only a single X2 register, and generally
there is one dedicated and unique set of m calibration register
and c calibration register assigned. In several special cases (for
example, the PPMU DAC) there is still only one X2 register per
DAC, but there are several different choices for m register and c
register depending on the particular configuration of mode and
range control settings for the function. For those DACs, a
choice of calibration register is made automatically based on the
respective mode and range control settings in place for that
function when the DAC is written.
Table 28 describes detailed m register and c register selection
as a function of mode and range control settings. For all DAC
functions, it is necessary to ensure that the respective m register
and c register values are put in place first, and that the desired
mode and range settings are updated prior to sending data to the
DAC. It is only during the DAC write sequence that the
calibration constants are selected and applied.
Rev. B | Page 55 of 82
ADATE320
Data Sheet
Table 28. m and c Calibration Register Selection 1
SPI
Address
[Channel]
0x01[0]
0x01[1]
0x02[0]
0x02[1]
DAC
Name
VIH0
VIH1
VIT0/
VCOM0
VIT1/
VCOM0
0x03[0]
0x03[1]
0x04[0]
VIL0
VIL1
VCH0
0x04[1]
VCH1
0x05[0]
VCL0
0x05[1]
VCL1
0x06[0]
VOH0
0x06[1]
VOH1
0x07[0]
VOL0
0x07[1]
VOL1
0x08[0]
0x08[1]
0x09[0]
0x09[1]
0x0A[0]
VIOH0
VIOH1
VIOL0
VIOL1
PPMU0
0x0A[1]
PPMU1
Functional (DAC Usage)
Description
Driver high level, Channel 0
Driver high level, Channel 1
Driver term level, Channel 0
Load commutation voltage,
Channel 0
Driver termination level,
Channel 1
Load commutation voltage,
Channel 1
Driver low level, Channel 0
Driver low level, Channel 1
Reflection clamp high level,
Channel 0
Reflection clamp high level,
Channel 1
Reflection clamp low level,
Channel 0
Reflection clamp low level,
Channel 1
Normal window comparator
high level, Channel 0
Differential mode comparator
high level, Channel 0
Normal window comparator
high level, Channel 1
Normal window comparator
low level, Channel 0
Differential mode comparator
low level, Channel 0
Normal window comparator
low level, Channel 1
Load IOHx level, Channel 0
Load IOHx level, Channel 1
Load IOL level, Channel 0
Load IOL level, Channel 1
PPMU VIN FV level, Channel 0
PPMU VIN FI level Range A,
Channel 0
PPMU VIN FI level Range B,
Channel 0
PPMU VIN FI level Range C,
Channel 0
PPMU VIN FI level Range D,
Channel 0
PPMU VIN FI level Range E,
Channel 0
PPMU VIN FV level, Channel 1
PPMU VIN FI level Range A,
Channel 1
PPMU VIN FI level Range B,
Channel 1
PPMU VIN FI level Range C,
Channel 1
PPMU VIN FI level Range D,
Channel 1
PPMU VIN FI level Range E,
Channel 1
LOAD_
ENABLE_x
(Address
0x1B[0])
X
X
0
1
PPMU_
MEAS_VI_x
(Address
0x1C[6])
X
X
X
X
PPMU_
FORCE_VI_x
(Address
0x1C[5])
X
X
X
X
PPMU_
RANGE_x
(Address
0x1C[4:2])
XXX
XXX
XXX
XXX
m
Register
0x21[0]
0x21[1]
0x22[0]
0x42[0]
c
Register
0x31[0]
0x31[1]
0x32[0]
0x52[0]
DMC_
ENABLE
(Address
0x1A[0])
X
X
X
X
0x22[1]
0x32[1]
X
0
X
X
XXX
0x42[1]
0x52[1]
X
1
X
X
XXX
0x23[0]
0x23[1]
0x24[0]
0x33[0]
0x33[1]
0x34[0]
X
X
X
X
X
X
X
X
X
X
X
X
XXX
XXX
XXX
0x24[1]
0x34[1]
X
X
X
X
XXX
0x25[0]
0x35[0]
X
X
X
X
XXX
0x25[1]
0x35[1]
X
X
X
X
XXX
0x26[0]
0x36[0]
0
X
X
X
XXX
0x46[0]
0x56[0]
1
X
X
X
XXX
0x26[1]
0x36[1]
X
X
X
X
XXX
0x27[0]
0x37[0]
0
X
X
X
XXX
0x47[0]
0x57[0]
1
X
X
X
XXX
0x27[1]
0x37[1]
X
X
X
X
XXX
0x28[0]
0x28[1]
0x29[0]
0x29[1]
0x2A[0]
0x4A[0]
0x38[0]
0x38[1]
0x39[0]
0x39[1]
0x3A[0]
0x5A[0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
XXX
XXX
XXX
XXX
XXX
111
0x4B[0]
0x5A[0]
X
X
X
1
110
0x4C[0]
0x5A[0]
X
X
X
1
101
0x4D[0]
0x5A[0]
X
X
X
1
100
0x4E[0]
0x5A[0]
X
X
X
1
0XX
0x2A[1]
0x4A[1]
0x3A[1]
0x5A[1]
X
X
X
X
X
X
0
1
XXX
111
0x4B[1]
0x5A[1]
X
X
X
1
110
0x4C[1]
0x5A[1]
X
X
X
1
101
0x4D[1]
0x5A[1]
X
X
X
1
100
0x4E[1]
0x5A[1]
X
X
X
1
0XX
Rev. B | Page 56 of 82
Data Sheet
SPI
Address
[Channel]
0x0B[0]
0x0B[1]
0x0C[0]
0x0C[1]
0x0D[0]
0x0D[1]
0x0E[0]
DAC
Name
PCH0
PCH1
PCL0
PCL1
POH0
POH1
POL0
ADATE320
Functional (DAC Usage)
Description
PPMU current clamp (FV) high
level, Channel 0
PPMU voltage clamp (FI) high
level, Channel 0
PPMU current clamp (FV) high
level, Channel 1
PPMU voltage clamp (FI) high
level, Channel 1
PPMU current clamp (FV) low
level, Channel 0
PPMU voltage clamp (FI) low
level, Channel 0
PPMU current clamp (FV) low
level, Channel 1
PPMU voltage clamp (FI) low
level, Channel 1
PPMU go/no-go MV high level,
Channel 0
PPMU go/no-go MI Range A
high level, Channel 0
PPMU go/no-go MI Range B
high level, Channel 0
PPMU go/no-go MI Range C
high level, Channel 0
PPMU go/no-go MI Range D
high level, Channel 0
PPMU go/no-go MI Range E
high level, Channel 0
PPMU go/no-go MV high level,
Channel 1
PPMU go/no-go MI Range A
high level, Channel 1
PPMU go/no-go MI Range B
high level, Channel 1
PPMU go/no-go MI Range C
high level, Channel 1
PPMU go/no-go MI Range D
high level, Channel 1
PPMU go/no-go MI Range E
high level, Channel 1
PPMU go/no-go MV low level,
Channel 0
PPMU go/no-go MI Range A
low level, Channel 0
PPMU go/no-go MI Range B
low level, Channel 0
PPMU go/no-go MI Range C
low level, Channel 0
PPMU go/no-go MI Range D
low level, Channel 0
PPMU go/no-go MI Range E
low level, Channel 0
DMC_
ENABLE
(Address
0x1A[0])
X
LOAD_
ENABLE_x
(Address
0x1B[0])
X
PPMU_
MEAS_VI_x
(Address
0x1C[6])
X
PPMU_
FORCE_VI_x
(Address
0x1C[5])
0
PPMU_
RANGE_x
(Address
0x1C[4:2])
XXX
m
Register
0x44[0]
c
Register
0x54[0]
0x2B[0]
0x3B[0]
0x44[1]
0x54[1]
0x2B[1]
0x3B[1]
0x45[0]
0x55[0]
0x2C[0]
0x3C[0]
0x45[1]
0x55[1]
X
X
X
0
0x2C[1]
0x3C[1]
X
X
X
1
0x2D[0]
0x3D[0]
X
X
0
X
XXX
0x61[0]
0x5D[0]
X
X
1
X
111
0x62[0]
0x5D[0]
X
X
1
X
110
0x63[0]
0x5D[0]
X
X
1
X
101
0x64[0]
0x5D[0]
X
X
1
X
100
0x65[0]
0x5D[0]
X
X
1
X
0XX
0x2D[1]
0x3D[1]
X
X
0
X
XXX
0x61[1]
0x5D[1]
X
X
1
X
111
0x62[1]
0x5D[1]
X
X
1
X
110
0x63[1]
0x5D[1]
X
X
1
X
101
0x641[]
0x5D[1]
X
X
1
X
100
0x65[1]
0x5D[1
X
X
1
X
0XX
0x2E[0]
0x3E[0]
X
X
0
X
XXX
0x66[0]
0x5E[0]
X
X
1
X
111
0x67[0]
0x5E[0]
X
X
1
X
110
0x68[0]
0x5E[0]
X
X
1
X
101
0x69[0]
0x5E[0]
X
X
1
X
100
0x6A[0]
0x5E[0]
X
X
1
X
0XX
1
X
X
X
0
XXX
1
X
X
X
0
XXX
1
Rev. B | Page 57 of 82
XXX
ADATE320
SPI
Address
[Channel]
0x0E[1]
0x0F[0]
0x0F[1]
OVDL
OVDH
Functional (DAC Usage)
Description
PPMU go/no-go MV low level,
Channel 1
PPMU go/no-go MI Range A
low level, Channel 1
PPMU go/no-go MI Range B
low level, Channel 1
PPMU go/no-go MI Range C
low level, Channel 1
PPMU go/no-go MI Range D
low level, Channel 1
PPMU go/no-go MI Range E
low level, Channel 1
Overvoltage detect low level
Overvoltage detect high level
LOAD_
ENABLE_x
(Address
0x1B[0])
X
PPMU_
MEAS_VI_x
(Address
0x1C[6])
0
PPMU_
FORCE_VI_x
(Address
0x1C[5])
X
PPMU_
RANGE_x
(Address
0x1C[4:2])
XXX
m
Register
0x2E[1]
c
Register
0x3E[1]
DMC_
ENABLE
(Address
0x1A[0])
X
0x66[1]
0x5E[1]
X
X
1
X
111
0x67[1]
0x5E[1]
X
X
1
X
110
0x68[1]
0x5E[1]
X
X
1
X
101
0x69[1]
0x5E[1]
X
X
1
X
100
0x6A[1]
0x5E[1]
X
X
1
X
0XX
0x2F[0]
0x2F[1]
0x3F[0]
0x3F[1]
X
X
X
X
X
X
X
X
XXX
XXX
X means don’t care.
WRITE
SPI
READ
DAC X1 REGISTER
EXAMPLE: VOL0 (ADDR: 0x07, CH0)
M REGISTER A
M REGISTER B
M REGISTER C
A
B
C
×
C REGISTER A
C REGISTER B
C REGISTER C
A
B
C
+
PIN ELECTRONICS FUNCTIONAL
MODE AND RANGE SETTINGS
EXAMPLE: DMC_ENABLE (ADDR: 0x1A[0])
1
DAC_CAL_ENABLE (ADDR: 0x11[0])
0
DAC X2 REGISTER
DAC
n × SCLK
DELAY
DAC IMMEDIATE
MODE ONE-SHOT
DAC_LOAD_MODE (ADDR: 0x11[1])
0 = IMMEDIATE
1 = DEFERRED
DAC_LOAD (ADDR: 0x11[2])
Figure 130. DAC X2 Registers and Calibration Diagram
Rev. B | Page 58 of 82
12160-027
1
DAC
Name
POL1
Data Sheet
Data Sheet
ADATE320
ALARM FUNCTIONS
The ADATE320 contains per channel overvoltage detectors
(OVDL/OVDH), per channel PPMU voltage/current clamps
(PCLx/PCHx), and a thermal alarm to detect and signal these
respective fault conditions. Any of these functions may flag an
alarm independently in the alarm state register (see Figure 153).
The status of the alarms may be determined at any time by
reading the SPI alarm state register. This register is read only,
and its contents are cleared by the read operation. The alarm flag
bits can then become set by any of the respective alarm functions.
The individual fault condition flags are logically OR'ed together
to drive the open-drain ALARM output pin to indicate that a
fault condition has occurred (see Figure 134).
The various alarm flags can be either enabled or disabled
(masked) using the alarm mask register (see Figure 152). The
thermal alarm is enabled by default (mask bit clear), and the
overvoltage and PPMU clamp alarms are all disabled by default
(mask bits set).
The PPMU clamp alarm behavior depends on the mode of the
PPMU. When in FI mode, the PPMU clamps behave as programmable voltage clamps. The high and low voltage clamp levels are
set by the respective PCHx and PCLx level setting DACs. If the
voltage on the DUTx pin reaches either the PCHx or PCLx setting,
a PPMU clamp alarm is generated, but only if the clamps are
enabled with the PPMU_CLAMP_ENABLE_x control bit in the
PPMU control register (see Figure 151). Note that if the PPMU
clamps are enabled and a PPMU clamp alarm is generated, the
alarm can still be masked with the alarm mask register.
However, if the voltage clamps are disabled, no PPMU clamp
alarm is generated.
When the PPMU is in FV mode, the PPMU clamps behave as
programmable current clamps. The source and sink current
clamp levels are set with the respective PCHx and PCLx level
setting DACs. The current clamps cannot be disabled by setting
or clearing the PPMU_CLAMP_ENABLE_x control bit—the
clamps are always active when in PPMU FV mode. If the PCHx
and PCLx levels are set outside their functional range, a ±140%
static current limit is left in effect. If the current on a DUTx pin
reaches either the PCHx or PCLx clamp setting, or, alternatively,
one of the static current limits, a PPMU clamp alarm results.
The PPMU clamp alarm can be masked separately in the alarm
mask register.
Refer to Figure 131 through Figure 134 for more information
about PPMU clamp functions.
The only purpose of the various alarm circuits is to detect and
indicate the presence of a fault condition of interest to the user.
The only action the ADATE320 takes upon detection of a fault
is to set the appropriate alarm state register flag bits in the alarm
state register and then activate the open-drain ALARM pin. No
other action is taken.
VDUTx
(VOLTS)
+4.5V
−1.5V
−0.5V
UNCLAMPED V
(DUTx) VOLTAGE REGION
+3.5V
+4.5V +5.0V
PCHx
PCLx = −1.5V FIXED
–1.5V
Figure 131. PPMU Voltage Clamp High, Functional Diagram
(Voltage Clamp Low Fixed at −1.5 V)
Rev. B | Page 59 of 82
12160-028
MINIMUM 1.0V
SEPARATION
FOR ACCURACY
−0.5V < PCHx < +4.5V
ADATE320
Data Sheet
VDUTx
(VOLTS)
PCHx = +4.5V FIXED
UNCLAMPED V
(DUTx) VOLTAGE REGION
−1.5V
−0.5V
−1.5V < PCLx < +3.5V
+3.5V
+4.5V
PCLx
12160-029
MINIMUM 1.0V
SEPARATION
FOR ACCURACY
Figure 132. PPMU Voltage Clamp Low, Functional Diagram
(Voltage Clamp High Fixed at 4.5 V)
IDUTx
(%FULL SCALE)
+140% STATIC CURRENT LIMIT
+120%
+110%
DC ACCURACY RANGE
+3.0V < PCHx < +5.5V
FUNCTIONAL RANGE
UNCLAMPED I DUTx
PCHx CURRENT REGION
+30%
+20%
−1.0V
−0.5V
+2.0V
+3.0V
+5.5V
+6.0V
PCHx/PCLx
DAC SETTING
−20%
−30%
THE PCL CLAMP MUST BE < −20% FULL SCALE AND ALWAYS REMAIN IN
THE LOWER (SINK) QUADRANT. THE PCH CLAMP MUST BE > +20% FULL
SCALE AND ALWAYS REMAIN IN THE UPPER (SOURCE) QUADRANT.
−0.5V < PCLx < +2.0V
ANY CURRENT CLAMP CONDITION (WHETHER PROGRAMMED OR ±140%
STATIC CURRENT LIMIT) SETS THE PPMU CLAMP ALARM FLAG
INDEPENDENT OF PPMU_CLAMP_ENABLE_x BIT IN THE PPMU
CONTROL REGISTER.
UNCLAMPED I DUTx
PCLx CURRENT REGION
−110%
12160-030
−120%
−140% STATIC CURRENT LIMIT
Figure 133. PPMU Current Clamp High and Low, Functional Diagram
Rev. B | Page 60 of 82
Data Sheet
ADATE320
ADATE320
DAC OVDH
ADDR: 0x0F, CH1
NOTE: DEDICATED OVERVOLTAGE COMPARATORS
ARE PROVIDED FOR EACH CHANNEL. ONLY ONE
CHANNEL IS SHOWN HERE. THE OVDH/OVDL
LEVELS ARE SHARED BETWEEN THE CHANNELS.
–
+
DUTx
DVDD
–
DACOVDL
+
ADDR: 0x0F, CH0
ALARM
DVDD
ALARM_OVD_MASK_x
ADDR: 0x1D[0], CHx
D
ALARM_THERM_MASK
Q
Q
ADDR: 0x1D[3], CH0
ALARM_THERM_THRES
–
RESET BY READING
FROM SPI ALARM
STATE REGISTER
ADDR: 0x1E, CHx
ADDR: 0x1D[7:5], CH0
+
TEMPERATURE
SENSOR
(10mV/K)
ALARM_PPMU_MASK_x
ADDR: 0x1D[2], CHx
NOTE: DEDICATED PPMU CLAMP INDICATORS
ARE PROVIDED FOR EACH CHANNEL. ONLY
ONE CHANNEL IS SHOWN HERE.
FROM PPMUx
CLAMP INDICATOR
Figure 134. Fault Alarm Functional Block Diagram
Rev. B | Page 61 of 82
12160-031
VTHERM
(10mV/K)
ADATE320
Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY, GROUNDING, AND TYPICAL
DECOUPLING STRATEGY
The ADATE320 is internally divided into a digital core and an
analog core.
The VDD and DGND pins provide power and ground for the
digital core that includes the SPI, certain logic functions, and
the digital calibration functions. DGND is the logic ground
reference for the VDD supply. Therefore, bypass VDD adequately
to DGND with good quality, low effective series resistance (ESR)
bypass capacitors. To reduce transient digital switching noise
coupling to the analog core, connect DGND to a dedicated
external ground plane that is separated from the analog ground
domains. If the application permits, the DGND pins can share a
digital ground domain with the supervisory FPGA or ASIC that
interfaces with the ADATE320 SPI. All CMOS inputs and
outputs are referenced between VDD and DGND, and their
valid levels must be guaranteed relative to these power supply
pins.
The analog core of the device includes all analog ATE functional
blocks such as the DACs, the driver, the comparator, the load,
and the PPMU. The VCC and VEE supplies provide power to the
analog core. AGND and PGND are analog ground and power
ground references, respectively. PGND is generally noisier with
analog switching transients, and it may also have large static dc
currents. AGND is generally quieter and has relatively smaller
static dc currents. These two grounds can be connected together
outside the chip to a single shared analog ground plane.
Regardless, keep PGND and AGND (whether separated or
shared) separated from the DGND ground plane if system
design constraints permit.
The transient frequencies generated by the analog core can be a
full order of magnitude greater than those generated by the SPI
and on-chip digital circuitry. Therefore, pay close attention to
the decoupling of the VCC and VEE supplies. Each supply must
be adequately bypassed to the PGND ground domain using the
highest quality bypass capacitors available. Locate the
decoupling capacitors as close to the device as practically possible.
The decoupling capacitors must have very low ESR and effective
series inductance (ESL). Commonly available ceramic capacitors
may provide only a marginally low impedance path to ground
at the frequencies encountered in the ADATE320. Therefore,
consider only the highest performance decoupling capacitors if
possible. In accordance with generally accepted practices, a
typical 10 µF tantalum capacitor must also be shared across
each power supply domain.
Pay particularly close attention to decoupling the VCC and VEE
supplies in proximity to the transmission line at the DUTx pins
of the device. To avoid undesired waveform aberrations and
degradation of performance, it is important that all return
currents to and from the transmission line have a direct and low
impedance path back to the VCCDx and VEEDx pins adjacent
to the respective DUTx pins. See Figure 135 for a typical
transmission line decoupling strategy.
The ADATE320 has a DUTGND reference input pin that senses
the remote low frequency ground potential at the target device
under test (DUT). With the exception of the VIOH and VIOL
active load currents and VPMU when in PPMU FI mode, all
DAC levels are adjusted on-chip relative to this DUTGND input.
Furthermore, the PPMU measure output pins (PPMU_Mx) are
also referenced to DUTGND. The off-chip system analog-todigital converter (ADC) that measures the PPMU_Mx pins
must therefore be referenced to DUTGND as well. Referencing
the system ADC to AGND results in errors unless DUTGND is
tied directly to AGND as close as possible to the ADATE320.
For applications that do not distinguish between DUT ground
reference and system analog ground reference, the DUTGND pin
may be connected to the same ground plane as AGND.
Avoid routing digital lines under the device, because these lines
can couple noise into the device. Generous use of an analog ground
plane under the device shields noise coupling that can otherwise
enter the device. The power supply distribution lines must provide
very wide and low inductance paths to the respective supply
planes. This is especially true for VCC and VEE. Attention to
via inductance is extremely important in these supplies—it cannot
be neglected. Fast switching signals routed in proximity to the
ADATE320 must be adequately shielded, preferably with their
proper ground returns to avoid radiating noise to other parts of
the board. Route such lines as far away as possible from the
analog inputs to the device, such as the AGND, DUTGND,
VREF, and VREFGND reference inputs.
Rev. B | Page 62 of 82
Data Sheet
ADATE320
ADATE320
VTT TERMINATION
VCCDx
VTTDx
+8.0V
DUT
20pF
DATx/RCVx
50Ω
DRIVER
DATx/RCVx
DUTx
TO ASIC/FPGA
50Ω
VEEDx
−5.0V
PGND
VTT TERMINATION
VTTCx
CMPHx/CMPLx
CMPHx/CMPLx
VCC
ANALOG +8.0V
VEE
ANALOG –5.0V
COMP
10mA
DIGITAL +1.8V
VDD
PGND
SCLK
SDI
SDO
TO ASIC/FPGA
CS
SPI
DUTGND
BUSY
ALARM
AGND
DGND
DIGITAL POWER GROUND
ANALOG POWER GROUND
Figure 135. Power Supply and Transmission Path Decoupling Detail
Rev. B | Page 63 of 82
ANALOG 0.0V
12160-032
DIGITAL 0.0V
ADATE320
Data Sheet
POWER SUPPLY SEQUENCING
The ADATE320 is designed to tolerate sequencing of power
supplies in any order. It is therefore not critical that the power
supplies be sequenced in any particular order; however, there
are recommended best practices.
The ADATE320 has two analog power supplies (VCC, VEE)
and one digital power supply (VDD). The analog supplies
service all of the analog functions on the chip such as level
setting DACs, driver, comparator, load, and PPMU. The digital
supply services the SPI and all digital CMOS control circuitry.
There is careful separation between the analog and digital partitions
of the chip, and significant effort has been made to decouple
these two partitions both functionally and electrically. The analog
partition remains in the default configuration in the absence of
VDD, and similarly, the digital partition remains in the default
configuration in the absence of either (or both) VCC and VEE.
It is not possible to guarantee predictable behavior of the analog
partition if either the VEE or VCC supply is poorly conditioned or
absent. It is therefore recommended that any externally connected
device be disconnected from the DUTx pin to prevent potential
damage to that device while either of the VEE or VCC supplies is
out of specification.
Assuming the VEE and VCC analog supplies are both applied and
within specification, the analog partition ensures that all functions
remain in the default configuration. This is true even when the
VDD supply is absent and digital CMOS control circuitry is not yet
functioning. In such a case (or whenever the RST pin is asserted),
all of the level setting DACs takes the voltage present at the
DUTGND input pin, and all SPI control bits assume their reset
default values. The analog functions remain in this safe condition
as long as VDD remains absent or as long as the RST pin remains
asserted.
It is recommended that the RST pin always be asserted during
the time that the VDD supply is being brought up. If this condition
is met, the level setting DACs continue to hold the DUTGND
potential after VDD stabilizes and after the RST pin is released. A
fully clocked reset sequence then initializes the level setting
DACs to the reset default conditions as specified in Table 29.
The reset sequence is described in more detail in the SPI Reset
Sequence and the Pin section.
In light of these considerations, it is recommended that the two
analog supplies be applied first. It is preferable that the smaller
valued supply (VEE) be applied before the larger valued supply
(VCC). Bring up the digital VDD supply next while the RST pin
is asserted. After VDD is stable and the RST pin is subsequently
released, a fully clocked reset sequence must follow. This power
supply sequence ensures that analog functions and all level
setting DACs receive the proper configuration information
during the digital partition reset sequence.
The power supplies must be removed in the reverse order.
Note that VREF and the high speed transmission line termination
pins (VTTDx, VTTCx) are all part of the analog partition, but they
are not treated as supplies. VREF can be managed independent of
VCC and VEE, provided its potential never goes outside those of
the VEE and VCC supply buses to prevent ESD protection diodes
from becoming forward biased. The VTTDx and VTTCx pins
do not have this restriction relative to VCC and VEE, but they
must never go outside the absolute maximum ratings as
measured with respect to PGND.
Rev. B | Page 64 of 82
Data Sheet
ADATE320
DETAILED FUNCTIONAL BLOCK DIAGRAMS
Figure 142 through Figure 145 illustrate the top-level functionality of the capabilities of the ADATE320 for the driver, comparator, active
load, and PPMU.
TRANSMISSION LINE
REFLECTION CLAMPS
DACVIH
HIGH-Z
ADDR: 0x01, CHx
DACVIL
ADDR: 0x03, CHx (IDEAL CLAMP DIODES)
DRV_RCV_MODE
(SEE DRIVER LOGIC DIAGRAM)
0
DACVIT/VCOM
ADDR: 0x02, CHx
DACVIH
ADDR: 0x01, CHx
DACVIL
ADDR: 0x03, CHx
TERM
1
1
0
DRV
1
50Ω
DUTx
DRV_RCV_SW
(SEE DRIVER LOGIC DIAGRAM)
DRV_ENABLE
(SEE DRIVER LOGIC DIAGRAM)
12160-033
DATx
Figure 136. Driver Functional Block Diagram
DRV_ENABLE = DRIVE_ENABLE
DRIVE_ENABLE_x
ADDR: 0x19[0], CHx
DRV_ENABLE
(SEE DRIVER FUNCTIONAL BLOCK DIAGRAM)
DRIVE_FORCE_x
ADDR: 0x19[1], CHx
DRIVE_FORCE_STATE_x(1)
ADDR: 0x19[3], CHx
DRIVE_FORCE_STATE_x(2)
ADDR: 0x19[2], CHx
DRIVE_VT_HIZ_x
ADDR: 0x19[4], CHx
RCVx
DRV_RCV_MODE = DRIVE_FORCE_x × DRIVE_FORCE_STATE_x(0) + DRIVE_FORCE × DRIVE_VT_HIZ
DRV_RCV_MODE
(SEE DRIVER FUNCTIONAL BLOCK DIAGRAM)
DRV_CRV_SW
(SEE DRIVER FUNCTIONAL BLOCK DIAGRAM)
Figure 137. Driver Logic Diagram
Rev. B | Page 65 of 82
12160-034
DRV_RCV_SW = DRIVE_FORCE_x × DRIVE_FORCE_STATE_x(1) + DRIVE_FORCE × RCVx
ADATE320
Data Sheet
ADATE320
VIRTUAL 1.8V RAIL
1.8V ESD
CLAMP
DATx
TO DATx
INPUT MUX
DATx
50Ω
50Ω
50Ω
50Ω
ESD DIODES: ALL DATx/RCVx INPUTS
AND VTTDx (ONLY SHOWN ON VTTDx
AND DATx INPUTS FOR CLARITY)
VTTDx
NOTE: VTTD0 AND VTTD1 PINS ARE
NOT ELECTRICALLY CONNECTED
RCVx
TO RCVx
INPUT MUX
RCVx
PGND 0.0V RAIL
12160-035
PGND
Figure 138. Driver Equivalent Input Stage Diagram
DAT0
0
DAT0
1
DRIVER DAT
CHANNEL 0
DRIVE_DAT_MUX
ADDR: 0x19[15:14], CH0
RCV0
0
RCV0
1
DRIVER RCV
CHANNEL 0
DRIVE_RCV_MUX
ADDR: 0x19[13:12], CH0
DAT1
0
DAT1
1
DRIVER DAT
CHANNEL 1
DRIVE_DAT_MUX
ADDR: 0x19[15:14], CH1
RCV1
0
1
DRIVE_RCV_MUX
ADDR: 0x19[13:14], CH1
Figure 139. Driver Input Multiplex Diagram
Rev. B | Page 66 of 82
DRIVER RCV
CHANNEL 1
12160-036
RCV1
Data Sheet
ADATE320
DACVOH
ADDR: 0x06, CH0
0
CMPH0
CMPH0
1
DUT0
DACVOL
ADDR: 0x07, CH0
DMC_ENABLE
ADDR: 0x1A[0], CH0
DACVOH
A=1
0
CMPL0
CMPL0
1
DACVOL
12160-037
DIFFERENTIAL
COMPARATOR ON
CHANNEL 0 ONLY
TO DUT1
Figure 140. Comparator Functional Block Diagram
ADATE320
VIRTUAL 1.8V RAIL
EXTERNAL
TERMINATION
1.8V ESD
CLAMP
VTTCx
50Ω
50Ω
CMPx
CMPx
50Ω
50Ω
50Ω
≥200mV
(TYPICAL = 250mV)
PGND
PGND 0.0V RAIL
ESD DIODES: ALL CMPH/Lx
OUTPUTS AND VTTCx (ONLY
SHOWN ON VTTCx AND CMPHx
OUTPUT FOR CLARITY)
10mA
NOTE: VTTC0 AND VTTC1 PINS
ARE NOT ELECTRICALLY
CONNECTED
Figure 141. Comparator Equivalent Output Stage Diagram
Rev. B | Page 67 of 82
12160-038
50Ω
ADATE320
Data Sheet
50Ω
FROM DRIVER
LOAD_POWER_DOWN
(SEE LOAD LOGIC DIAGRAM)
LOAD_CONNECT
(SEE LOAD LOGIC DIAGRAM)
DUTx
POWER
CONTROL
DACVIOL
ADDR: 0x09, CHx
DACVIT/VCOM
ADDR: 0x02, CHx
ACTIVE LOAD
12160-039
DACVIOH
ADDR: 0x08, CHx
Figure 142. Active Load Functional Block Diagram
LOAD_ENABLE_x
ADDR: 0x1B[0], CHx
LOAD_PWR_DOWN
(SEE ACTIVE LOAD FUNCTIONAL BLOCK DIAGRAM)
LOAD_FORCE_x
ADDR: 0x1B[1], CHx
LOAD_PWR_DOWN = LOAD_ENABLE_x
LOAD_CONNECT = LOAD_ENABLE_x × (RCVx × DRIVE_VT_HIZ_x + LOAD_FORCE_x)
DRIVE_VT_HIZ_x
ADDR: 0x19[4], CHx
RCVx
12160-040
LOAD_CONNECT
(SEE ACTIVE LOAD FUNCTIONAL BLOCK DIAGRAM)
Figure 143. Active Load Functional Logic Diagram
Rev. B | Page 68 of 82
Data Sheet
ADATE320
PPMU_CLAMP_ENABLE_x
ADDR: 0x1C[10], CHx
DACPCH
ADDR: 0x1B, CHx
PPMU VOLTAGE CLAMPS
(PPMU FORCE-I MODE)
NOTE THAT PPMU_CLAMP_ENABLE ONLY APPLIES TO
VOLTAGE CLAMP FUNCTIONALITY (WHEN FORCE-I MODE).
PPMU CURRENT CLAMPS (WHEN FORCE-V MODE) CAN
NOT BE DISABLED WITH THIS CONTROL BIT.
DACPCL
ADDR: 0x0C, CHx
PPMU_INPUT_SEL_x
ADDR: 0x1C[8:7], CHx
VOUTGND
(VREF – VREFGND ) + VOUTGND
DACPPMU
ADDR: 0x0A, CHx
PPMU_ENABLE_x
ADDR: 0x1C[0], CHx
0
1
2
3
RPPMU
DUTx
F-AMP
PPMU_RANGE_x
ADDR: 0x1C[4:2], CHx
DACPCH
ADDR: 0x0B, CHx
CURRENT
(VREF – VREFGND ) + VOUTGND
I-AMP
DACPCL
ADDR: 0x0C, CHx
AV = 5.0
PPMU_FORCE_VI_x
ADDR: 0x1C[5], CHx
VOLTAGE
PPMU_MEAS_VI_x
ADDR: 0x1C[6], CHx
AV = 1.0
PPMU_SENSE_PATH_x
ADDR: 0x1C[9], CHx
PPMU_MEAS_SEL
ADDR: 0x1[15:14], CHx
PPMU_Mx
(RELATIVE TO VDUTGND )
0
×1
1
CH0: THERM OUT
CH0: THERM GND
PPMU_MEAS_ENABLE_x
ADDR: 0x1C[13], CHx
DACPOH
ADDR: 0x0D, CHx
PPMU_CMPHx
PPMU_Sx
RANGE
RPPMU
40mA
12.5Ω
1mA
500Ω
100µA
5kΩ
10µA
20kΩ
2µA
250kΩ
PPMU_CMPHx
DACPOL
ADDR: 0x0E, CHx
PPMU_ENABLE_x
ADDR: 0x1C[0], CHx
X
0 PPMU IS POWERED DOWN.
0
1 PPMU IS IN FULL POWER STANDBY MODE,
BUT NOT YET ENABLED TO FORCE V/I. USE
THIS MODE FOR FAST INTERNAL SETTLING OF
LEVELS PRIOR TO ENABLING ACTIVE MODE
TO MINIMIZE PPMU TRANSIENT GLITCH.
1
1 PPMU IS IN FULL POWER ACTIVE MODE.
Figure 144. PPMU Functional Block Diagram
Rev. B | Page 69 of 82
12160-041
PPMU_STANDBY_x
ADDR: 0x1C[1], CHx
ADATE320
Data Sheet
PPMU_MEAS_SEL_x
ADDR: 0x1C[15:14], CHx
CH0: THERM OUT
CH0: THERM GND
1
×1
PPMU_Mx
0
FROM PPMU CIRCUIT
PPMU_MEAS_ENABLE_x
ADDR: 0x1C[13], CHx
PPMU_CMPHx
DACPOH
ADDR: 0x0D, CHx
PPMU GO/NO-GO
COMPARATOR
DC DAC LEVELS
PPMU_CMPLx
DACPOL
ADDR: 0x0E, CHx
VOHx
PPMU GO/NO-GO COMPARATOR TRUTH TABLE
PIN
CONDITION
STATE
PPMU_CMPHx
VOLx
PPMU_Mx
PPMU_CMPLx
PPMU_Mx < VOHx
LOW
PPMU_Mx < VOHx
HIGH
PPMU_Mx < VOLx
LOW
PPMU_Mx < VOLx
HIGH
12160-042
PPMU_CMPHx
PPMU_CMPLx
Figure 145. PPMU Go/No-Go Comparator Functional Block Diagram
Rev. B | Page 70 of 82
Data Sheet
ADATE320
SPI REGISTER MEMORY MAP AND DETAILS
MEMORY MAP
Table 29. SPI Register Memory Map 1
CH[1:0] 2
XX
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
01
10
XX
CC
01
XX
CC
CC
CC
CC
01
10
CC
CC
XX
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
01
10
Address (ADDR[6:0])
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x0F
0x10
0x11
0x12
0x13 to 0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x2F
R/W
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
R/W
R/W
X
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DATA[15:0] 3
XXXX
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
XXXX
DDDD
DDDD
XXXX
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
XXXX
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
Register Description
NOP
VIH DAC level (reset value = 0.0 V)
VIT/VCOM DAC level (reset value = 0.0 V)
VIL DAC level (reset value = 0.0 V)
VCHx DAC level (reset value = VMAX)
VCLx DAC level (reset value = VMIN)
VOHx DAC level (reset value = 4.0 V)
VOLx DAC level (reset value = −1.0 V)
VIOH DAC level (reset value ≥ 0 µA) 4
VIOL DAC level (reset value ≥ 0 µA)4
PPMU DAC level (reset value = 0.0 V)
PCHx DAC level (reset value = VMAX)
PCLx DAC level (reset value = VMIN)
POHx DAC level (reset value = 4.0 V)
POLx DAC level (reset value = −1.0 V)
OVDL DAC level (reset value = VMIN)
OVDH DAC level (reset value = VMAX)
Reserved
DAC control register
SPI control register
Reserved
DRV control register
CMP control register
Load control register
PPMU control register
Alarm mask register
Alarm mask register
Alarm state register
Product serialization code register
NOP
VIH (driver high level) m coefficient
VIT (driver term level) m coefficient
VIL (driver low level) m coefficient
VCHx (driver reflection clamp) m coefficient
VCLx (driver reflection clamp) m coefficient
VOHx (normal window comparator) m coefficient
VOLx (normal window comparator) m coefficient
VIOH (active load IOHx) m coefficient
VIOL (active load IOL) m coefficient
PPMU (PPMU FV) m coefficient
PCHx (PPMU voltage clamp, FI) m coefficient
PCLx (PPMU voltage clamp, FI) m coefficient
POHx (PPMU comparator MV) m coefficient
POLx (PPMU comparator MV) m coefficient
OVDL m coefficient
OVDH m coefficient
Rev. B | Page 71 of 82
Reset Value
0x4000
0x4000
0x4000
0xFFFF
0x0000
0xA666
0x2666
0x4000
0x4000
0x4000
0xFFFF
0x0000
0xA666
0x2666
0x0000
0xFFFF
0x0000
0x0000
0x0000
0xFF00
0x0003
0x0000
0x0085
0x0005
0x0000
Unique
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
ADATE320
CH[1:0] 2
XX
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
01
10
XX
CC
XX
CC
CC
01
01
XX
CC
CC
CC
CC
CC
XX
XX
CC
XX
CC
CC
01
01
XX
CC
XX
CC
CC
XX
XX
CC
CC
CC
CC
CC
CC
Address (ADDR[6:0])
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x3F
0x40 to 0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48 to 0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50 to 0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58 to 0x59
0x5A
0x5B to 0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
Data Sheet
R/W
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
R/W
X
R/W
R/W
R/W
R/W
X
R/W
R/W
R/W
R/W
R/W
X
X
R/W
X
R/W
R/W
R/W
R/W
X
R/W
X
R/W
R/W
X
X
R/W
R/W
R/W
R/W
R/W
R/W
DATA[15:0] 3
XXXX
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
XXXX
DDDD
XXXX
DDDD
DDDD
DDDD
DDDD
XXXX
DDDD
DDDD
DDDD
DDDD
DDDD
XXXX
XXXX
DDDD
XXXX
DDDD
DDDD
DDDD
DDDD
XXXX
DDDD
XXXX
DDDD
DDDD
XXXX
XXXX
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
Register Description
Reserved
VIH (driver high level) c coefficient
VIT (driver term level) c coefficient
VIL (driver low level) c coefficient
VCHx (driver reflection clamp) c coefficient
VCLx (driver reflection clamp) c coefficient
VOHx (normal window comparator) c coefficient
VOLx (normal window comparator) c coefficient
VIOH (active load IOHx) c coefficient
VIOL (active load IOL) c coefficient
PPMU (PPMU FV) c coefficient
PCHx (PPMU voltage clamp, FI) c coefficient
PCLx (PPMU voltage clamp, FI) c coefficient
POHx (PPMU comparator MV) c coefficient
POLx (PPMU comparator MV) c coefficient
OVDL c coefficient
OVDH c coefficient
Reserved
VCOM (active load) m coefficient
Reserved
PCHx (PPMU current clamp, FV) m coefficient
PCLx (PPMU current clamp, FV) m coefficient
VOHx (differential comparator) m coefficient
VOLx (differential comparator) m coefficient
Reserved
PPMU FI Range A m coefficient
PPMU FI Range B m coefficient
PPMU FI Range C m coefficient
PPMU FI Range D m coefficient
PPMU FI Range E m coefficient
Reserved
Reserved
VCOM (active load) c coefficient
Reserved
PCHx (PPMU current clamp, FV) c coefficient
PCLx (PPMU current clamp, FV) c coefficient
VOHx (differential comparator) c coefficient
VOLx (differential comparator) c coefficient
Reserved
PPMU FI c coefficient
Reserved
POHx (PPMU comparator MI) c coefficient
POLx (PPMU comparator MI) c coefficient
Reserved
Reserved
POHx (PPMU comparator MI Range A) m coefficient
POHx (PPMU comparator MI Range B) m coefficient
POHx (PPMU comparator MI Range C) m coefficient
POHx (PPMU comparator MI Range D) m coefficient
POHx (PPMU comparator MI Range E) m coefficient
POLx (PPMU comparator MI Range A) m coefficient
Rev. B | Page 72 of 82
Reset Value
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
Data Sheet
CH[1:0] 2
CC
CC
CC
CC
XX
Address (ADDR[6:0])
0x67
0x68
0x69
0x6A
0x6B to 0x7F
ADATE320
R/W
R/W
R/W
R/W
R/W
X
DATA[15:0] 3
DDDD
DDDD
DDDD
DDDD
XXXX
Register Description
POLx (PPMU comparator MI Range B) m coefficient
POLx (PPMU comparator MI Range C) m coefficient
POLx (PPMU comparator MI Range D) m coefficient
POLx (PPMU comparator MI Range E) m coefficient
Reserved
Reset Value
0xFFFF
0xFFFF
0xFFFF
0xFFFF
X means don’t care for the respective field.
CC represents two contiguous binary channel bits.
DDDD represents four-digit hexadecimal data.
4
The active load VIOHx and VIOLx voltage offsets are guaranteed to be nonzero and positive. These offsets result in a nonzero current for each IOHx and IOLx level
following valid reset sequence and prior to calibration. Furthermore, the active load is forced into the active on state following a reset, which facilitates a soft connect
of the DUTx pin to VCOMx = 0.0 V following a valid reset sequence (with small but nonzero IOHx and IOLx currents).
1
2
3
Rev. B | Page 73 of 82
ADATE320
Data Sheet
is addressed to only Channel 1 is ignored if no register or
control bit is defined on Channel 1.
REGISTER DETAILS
Reserved bits in any register are undefined. In some cases, a
physical but unused memory bit may be present.
Furthermore, any such write that is addressed to both Channel
0 and Channel 1 (as a multichannel write) proceeds as if the
write is addressed to both Channel 0 and Channel 1. If no
register or control bit is defined at Channel 1, data addressed to the
undefined Channel 1 is ignored. If a register or control bit is
defined at Channel 1, it is filled as part of the multichannel
write.
Any SPI read operation from a reserved bit or register results in
an unknown but deterministic readback value. Any SPI write
operation to a reserved bit or register results in no action.
A write to a control bit or control register defined only on
Channel 0 must be addressed to Channel 0. Any such write that
SPI CLOCK INDEX
DATA-WORD INDEX
15
16
17
18
19
20
21
22
23
24
25
D15 D14 D13 D12 D11 D10
10
11
12
13
14
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESERVED
DAC LOAD CONTROL BIT, SELF RESETTING, CHANNEL 0/CHANNEL 1
[0] = DEFAULT STATE OF THE DAC_LOAD CONTROL BIT
1 = BEGIN DAC LOAD OPERATION (PULSE, SELF CLEAR TO ZERO)
A WRITE TO THIS BIT PARALLEL UPDATES ALL DACs OF CHANNEL x
WITH PREVIOUSLY BUFFERED DATA ASSUMING THAT THE
DAC_LOAD_MODE CONTROL BIT OF CHANNEL x IS NOT SET TO
WRITE DAC IMMEDIATE MODE. THIS BIT AUTOMATICALLY SELF CLEARS.
DAC LOAD MODE, CHANNEL 0/CHANNEL 1
[0] = WRITE DAC IMMEDIATE MODE.
1 = WRITE DAC DEFERRED MODE.
IN WRITE DAC IMMEDIATE MODE, EACH RESPECTIVE DAC IS UPDATED
IMMEDIATELY SUBSEQUENT TO A VALID SPI WRITE INSTRUCTION TO
THAT DAC ADDRESS. IN WRITE DAC DEFERRED MODE, EACH VALID
SPI WRITE TO A DAC ADDRESS IS BUFFERED, AND DACs ARE ONLY
UPDATED FOLLOWING ASSERTION OF THE DAC_LOAD SOFT PIN.
IN THIS MODE, ALL ANALOG DAC DATA FOR EITHER OR BOTH
CHANNELS CAN BE UPDATED IN PARALLEL.
12160-017
DAC CALIBRATION ENGINE ENABLE, CHANNEL 0 ONLY
[0] = CALIBRATION ENGINE IS DISABLED
1 = CALIBRATION ENGINE IS ENABLED
WHEN DAC CALIBRATION IS ENABLED, EACH WRITE TO A VALID DAC
ADDRESS RESULTS IN A SUBSEQUENT MULTIPLY AND ACCUMULATE
(MAC) OPERATION TO THE DATA FOR THE RESPECTIVE DAC USING
CALIBRATION DATA CONTAINED IN THE APPROPRIATE m AND c
COEFFICIENT REGISTERS. WHEN THE CALIBRATION ENGINE IS
DISABLED, DATA WRITTEN TO A VALID DAC ADDRESS IS NOT
MODIFIED BY THE ON-CHIP CALIBRATION COEFFICIENTS.
Figure 146. DAC Control Register (Address 0x11)
SPI CLOCK INDEX
DATA-WORD INDEX
15
16
17
18
19
20
21
22
23
24
25
D15 D14 D13 D12 D11 D10
10
11
12
13
14
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESERVED
SPI SOFTWARE RESET, CHANNEL 0 ONLY
[0] = DEFAULT SETTING, NO ACTION IS TAKEN UNTIL A 1 IS WRITTEN.
1 = RESET (PULSE, SELF CLEAR TO ZERO).
FOLLOWING A WRITE TO SET THIS BIT, A FULL RESET SEQUENCE IS
INITIATED THAT IS SIMILAR TO THE RST PIN ASSERTING ASYNCHRONOUSLY.
FOLLOWING A RESET, THIS BIT SELF CLEARS TO THE DEFAULT 0 CONDITION.
Figure 147. SPI Control Register (Address 0x12)
Rev. B | Page 74 of 82
12160-018
SPI SERIAL DATA OUTPUT PIN, HIGH-Z CONTROL, CHANNEL 0 ONLY
[0] = SDO PIN IS ALWAYS ACTIVE, INDEPENDENT OF THE CS INPUT.
1 = SDO PIN IS ACTIVE ONLY WHEN CS IS ACTIVE, OTHERWISE HIGH-Z.
Data Sheet
ADATE320
SPI CLOCK INDEX
DATA-WORD INDEX
15
16
17
18
19
20
21
22
23
24
25
D15 D14 D13 D12 D11 D10
10
11
12
13
14
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DRIVER DAT INPUT MULTIPLEX SELECT,
CHANNEL 0/CHANNEL 1
[X0] = PRIMARY CHANNEL DATx, NO INVERT
X1 = SECONDARY CHANNEL DATx, INVERTED
DRIVER RCV INPUT MULTIPLEX SELECT,
CHANNEL 0/CHANNEL 1
[X0] = PRIMARY CHANNEL RCVx, NO INVERT
X1 = SECONDARY CHANNEL RCVx, NO INVERT
DRIVER CABLE LOSS COMPENSATION, CHANNEL 0/CHANNEL 1
[000] = DISABLE DRIVER CLC
001 = ENABLE DRIVER MINIMUM CLC
111 = ENABLE DRIVER MAXIMUM CLC
WHEN SET TO 000 THE DRIVER ON CHANNEL x HAS ZERO CABLE LOSS
COMPENSATION (CLC) ADDED TO ITS OUTPUT CHARACTERISTICS. WHEN SET TO
A VALUE OTHER THAN 000, CLC PRE-EMPHASIS IS ADDED AND THE PERCENTAGE
VALUE IS CONTROLLED BY THIS REGISTER VALUE.
RESERVED
DRIVER VT/HIZ MODE SELECT, CHANNEL 0/CHANNEL 1
[0] = DRIVER GOES TO HIGH-Z STATE WHEN RCVx = 1
1 = DRIVER GOES TO VIT STATE WHEN RCVx = 1
WHEN DRIVE_VT_HIZ_x IS ASSERTED, THE DRIVER ON CHANNEL x ASSUMES
THE VIT LEVEL ON ASSERTION OF THE RCVx HIGH SPEED INPUT IN ACCORDANCE WITH
THE DRIVER TRUTH TABLE. THIS CONTROL BIT IS SUBORDINATE TO THE DRIVE_ENABLE_x
AND DRIVE_FORCE_x CONTROL BITS.
DRIVER STATE WHEN DRIVE_FORCE, CHANNEL 0/CHANNEL 1
[00] = FORCE DRIVE VIL STATE
01 = FORCE DRIVE VIH STATE
10 = FORCE DRIVE HIGH-Z STATE
11 = FORCE DRIVE VIT STATE
WHEN THE DRIVE_FORCE_x CONTROL BIT IS ACTIVE, THEN THE DRIVER ON CHANNEL x
ASSUMES THE INDICATED STATE IN ACCORDANCE WITH THE DRIVER TRUTH TABLE.
DRIVER ENABLE, CHANNEL 0/CHANNEL 1
[0] = DRIVER IS DISABLED AND IN LOW LEAKAGE POWER DOWN MODE
1 = DRIVER IS ENABLED AND RESPONDS TO DRIVE_VT_HIZ_x, DATx, AND RCVx
WHEN DRIVE_ENABLE_x IS ASSERTED, THE DRIVER ON CHANNEL X IS
ENABLED RESPONDS TO BOTH THE DRIVE_FORCE_x AND DRIVE_VT_HIZ_x
CONTROL BITS AS WELL AS THE RCVx AND DATx HIGH SPEED INPUTS IN ACCORDANCE
WITH THE DRIVER TRUTH TABLE.
Figure 148. DRV Control Register (Address 0x19)
Rev. B | Page 75 of 82
12160-019
FORCE DRIVER TO DRIVE_FORCE_STATE, CHANNEL 0/CHANNEL 1
[0] = DRIVER RESPONDS TO DATx AND RCVx
1 = FORCE DRIVER STATE TO DRIVE_FORCE_STATE
WHEN DRIVE_FORCE_x IS ASSERTED, THE DRIVER ON CHANNEL x ASSUMES THE
STATE INDICATED BY DRIVE_FORCE_STATE_x IN ACCORDANCE WITH DRIVER TRUTH TABLE.
THIS CONTROL BIT IS SUBORDINATE TO THE DRIVE_ENABLE_x CONTROL BIT, BUT TAKES
PRECEDENCE OVER THE DRIVE_VT_HIZ_x BIT AS WELL AS THE DATx AND RCVx HIGH SPEED
INPUTS. THIS BIT DOES NOT FORCE THE SELECTION OF DRIVER LEVEL CALIBRATION CONSTANTS.
ADATE320
Data Sheet
SPI CLOCK INDEX
DATA-WORD INDEX
15
16
17
18
19
20
21
22
23
24
25
D15 D14 D13 D12 D11 D10
10
11
12
13
14
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NORMAL WINDOW COMPARATOR HYSTERESIS VALUE, CHANNEL 0/CHANNEL 1
0000= DISABLE HYSTERESIS.
0001 = ENABLE MINIMUM HYSTERESIS.
[1111] = ENABLE MAXIMUM HYSTERESIS.
WHEN SET TO 0000, THE NORMAL WINDOW COMPARATOR ON CHANNEL x
HAS NO HYSTERESIS ADDED TO THE INPUT STAGE. WHEN SET TO A VALUE
OTHER THAN 0000, THERE IS HYSTERESIS AND THE AMOUNT IS
CONTROLLED BY THE VALUE IN THIS REGISTER FIELD.
DIFFERENTIAL COMPARATOR HYSTERESIS VALUE, CHANNEL 0 ONLY
0000 = DISABLE HYSTERESIS.
0001 = ENABLE MINIMUM HYSTERESIS.
[1111] = ENABLE MAXIMUM HYSTERESIS.
WHEN SET TO 0000, THE DIFFERENTIAL COMPARATOR ON CHANNEL 0
HAS NO HYSTERESIS ADDED TO THE INPUT STAGE. WHEN SET TO A VALUE
OTHER THAN 0000, HYSTERESIS AND THE AMOUNT ARE CONTROLLED
BY THE VALUE IN THIS REGISTER FIELD.
RESERVED
NORMAL WINDOW COMPRATOR CABLE LOSS COMPENSATION, CHANNEL 0/CHANNEL 1
[000] = DISABLE NWC CLC.
001 = ENABLE NWC MINIMUM CLC.
111 = ENABLE NWC MAXIMUM CLC.
WHEN SET TO 000, THE NORMAL WINDOW COMPARATOR (NWC) ON CHANNEL x HAS NO CLC
ADDED TO THE INPUT WAVEFORM CHARACTERISTIC. WHEN SET TO A VALUE OTHER THAN 000,
THERE IS PRE-EMPHASIS ADDED AND THE PERCENTAGE IS CONTROLLED BY THE VALUE IN
THIS REGISTER.
DIFFERENTIAL MODE COMPARATOR CABLE LOSS COMPENSATION, CHANNEL 0 ONLY
[000] = DISABLE DMC CLC.
001 = ENABLE DMC MINIMUM CLC.
111 = ENABLE DMC MAXIMUM CLC.
WHEN SET TO 000, THE DIFFERENTIAL MODE COMPARATOR (ON CHANNEL 0 ONLY) HAS NO
CLC ADDED TO THE INPUT WAVEFORM CHARACTERISTIC. WHEN SET TO A VALUE OTHER
THAN 000, THERE IS PRE-EMPHASIS ADDED AND THE PERCENTAGE IS CONTROLLED BY THE
VALUE IN THIS REGISTER.
12160-020
DIFFERENTIAL MODE COMPARATOR ENABLE, CHANNEL 0 ONLY
[0] = DISABLE DIFFERENTIAL MODE COMPARATOR.
1 = ENABLE DIFFERENTIAL MODE COMPARATOR.
WHEN DMC_ENABLE IS ASSERTED, THE NWC ON CHANNEL 0 IS DISABLED, THE DMC ON
CHANNEL 0 IS ENABLED, AND ITS OUTPUTS GO TO THE CMPH0 AND CMPL0 HIGH SPEED
OUTPUT PINS. THE OPERATION OF THE NWC ON CHANNEL 1 IS NOT AFFECTED.
Figure 149. CMP Control Register (Address 0x1A)
SPI CLOCK INDEX
DATA-WORD INDEX
15
16
17
18
19
20
21
22
23
24
25
D15 D14 D13 D12 D11 D10
10
11
12
13
14
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESERVED
ACTIVE LOAD POWER ENABLE, CHANNEL 0/CHANNEL 1
0 = ACTIVE LOAD IS DISABLED AND POWERED DOWN.
[1] = ACTIVE LOAD IS ENABLED.
WHEN LOAD_ENABLE_x IS ASSERTED, THEN THE ACTIVE LOAD ON CHANNEL x IS ENABLED CONNECTS TO THE
DUTx PIN ON ASSERTION OF THE LOAD_FORCE_x CONTROL BIT, OR ASSERTION OF THE HIGH SPEED RCVx
INPUT IN ACCORDANCE WITH THE ACTIVE LOAD TRUTH TABLE.
Figure 150. Load Control Register (Address 0x1B)
Rev. B | Page 76 of 82
12160-021
FORCE ACTIVE LOAD TO ACTIVE ON STATE, CHANNEL 0/CHANNEL 1
0 = ACTIVE LOAD RESPONDS TO LOAD_ENABLE_x AND RCVx INPUTS.
[1] = FORCE ACTIVE ON STATE.
WHEN LOAD_FORCE_x IS ASSERTED, THEN THE ACTIVE LOAD ON CHANNEL x ASSUMES THE ACTIVE ON STATE
AND CONNECTS TO THE DUTx PIN IN ACCORDANCE WITH THE ACTIVE LOAD TRUTH TABLE. THIS CONTROL BIT
IS SUBORDINATE TO THE LOAD_ENABLE_x CONTROL BIT, BUT TAKES PRECEDENCE OVER THE RCVx HIGH
SPEED INPUT. THIS BIT DOES NOT FORCE SELECTION OF VCOM CALIBRATION CONSTANTS.
Data Sheet
ADATE320
SPI CLOCK INDEX
DATA-WORD INDEX
15
16
17
18
19
20
21
22
23
24
25
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
10
11
12
13
14
PPMU ANALOG MEASURE OUT PIN SELECT, CHANNEL 0/CHANNEL 1
[X0] = PPMU CHANNEL x TO PPMU_MEASx OUTPUT PIN
X1 = CHANNEL 0: TEMPERATURE SENSOR OUTPUT (VTHERM)
CHANNEL 1: TEMPERATURE SENSOR GROUND REFERENCE
PPMU ANALOG MEASURE OUT PIN ENABLE, CHANNEL 0/CHANNEL 1
[0] = PPMU MEASURE OUT PIN ON CHANNEL x IS HIGH-Z
1 = PPMU MEASURE OUT PIN ON CHANNEL x IS ENABLED
RESERVED
PPMU VOLTAGE CLAMP ENABLE, CHANNEL 0/CHANNEL 1
[0] = PPMU VOLTAGE CLAMPS DISABLED
1 = PPMU VOLTAGE CLAMPS ENABLED
APPLIES ONLY TO VOLTAGE CLAMPS WHEN IN FORCE-I MODE.
PROGRAMMABLE CURRENT CLAMPS CANNOT BE DISABLED.
PPMU SENSE PATH, CHANNEL 0/CHANNEL 1
[0] = PPMU INTERNAL SENSE PATH
1 = PPMU EXTERNAL SENSE PATH
PPMU INPUT SELECT, CHANNEL 0/CHANNEL 1
[00] = PPMU INPUT FROM DUTGND
01 = PPMU INPUT FROM DUTGND + 2.5V
1X = PPMU INPUT FROM DACPPMU LEVEL
PPMU MV OR MI, CHANNEL 0/CHANNEL 1
[0] = PPMU MV MODE
1 = PPMU MI MODE
PPMU FV OR FI, CHANNEL 0/CHANNEL 1
[0] = PPMU FV MODE
1 = PPMU FI MODE
PPMU RANGE, CHANNEL 0/CHANNEL 1
[0XX] = PPMU RANGE E (2µA)
100 = PPMU RANGE D (10µA)
101 = PPMU RANGE C (100µA)
110 = PPMU RANGE B (1mA)
111 = PPMU RANGE A (40mA)
PPMU STANDBY, CHANNEL 0/CHANNEL 1
[0] = PPMU FULL POWER ACTIVE
1 = PPMU FULL POWER STANDBY
12160-022
PPMU POWER ENABLE, CHANNEL 0/CHANNEL 1
[0] = PPMU LOW POWER OFF
1 = PPMU FULL POWER ON
Figure 151. PPMU Control Register (Address 0x1C)
Rev. B | Page 77 of 82
ADATE320
Data Sheet
SPI CLOCK INDEX
DATA-WORD INDEX
15
16
17
18
19
20
21
22
23
24
25
D15 D14 D13 D12 D11 D10
10
11
12
13
14
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESERVED
THERMAL ALARM THRESHOLD, CHANNEL 0 ONLY
000 = 0ºC (FOR TEST USE ONLY).
001 = 25ºC.
010 = 50ºC.
011 = 75ºC.
[100] = 100ºC.
101 = 125ºC.
110 = 150ºC.
111 = 175ºC.
RESERVED
THERMAL ALARM MASK BIT, CHANNEL 0 ONLY
[0] = THERMAL ALARM ENABLED.
1 = THERMAL ALARM DISABLED.
WHEN THERMAL ALARM IS ENABLED, A TEMPERATURE SENSOR READING ABOVE
THE THRESHOLD SPECIFIED BY ALARM_THERM_THRESH ASSERTS AND LATCHES
THE ALARM OPEN-DRAIN OUTPUT PIN.
PPMU CLAMP ALARM MASK, CHANNEL 0/CHANNEL 1
0 = PPMU CLAMP ALARM ENABLED.
[1] = PPMU CLAMP ALARM DISABLED.
WHEN THE PPMU CLAMP ALARM IS ENABLED, A CLAMP CONDITION ON CHANNEL x
PPMU CLAMPS WILL ASSERT AND LATCH THE ALARM OPEN DRAIN OUTPUT PIN.
THE PPMU CLAMP LEVELS ARE DEFINED BY THE PCL AND PCH DAC REGISTERS.
OVERVOLTAGE DETECTOR ALARM MASK, CHANNEL 0/CHANNEL 1
0 = OVERVOLTAGE ALARM ENABLED.
[1] = OVERVOLTAGE ALARM DISABLED.
WHEN THE OVD ALARM IS ENABLED, AN OVERVOLTAGE FAULT CONDITION ON DUTx WILL ASSERT
AND LATCH THE ALARM OPEN DRAIN OUTPUT PIN. THE OVERVOLTAGE THRESHOLDS ARE DEFINED
BY THE OVDH AND OVDL DAC REGISTERS.
Figure 152. Alarm Mask Register (Address 0x1D)
Rev. B | Page 78 of 82
12160-023
RESERVED
Data Sheet
ADATE320
SPI CLOCK INDEX
DATA-WORD INDEX
15
16
17
18
19
20
21
22
23
24
25
D15 D14 D13 D12 D11 D10
10
11
12
13
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
14
RESERVED
THERMAL ALARM FLAG, CHANNEL 0 ONLY
[0] = THERMAL FAULT NOT DETECTED.
1 = THERMAL FAULT DETECTED.
WHEN THE ALARM_THERM_FLAG BIT IS SET, A FAULT WAS DETECTED ON THE DIE ACCORDING TO
THE THERMAL THRESHOLD SET IN THE ALARM_THERM_THRESH BIT. THIS FLAG IS SUBORDINATE
TO THE ALARM_THERM_MASK CONTROL BIT, AND IT AUTOMATICALLY RESETS AFTER ANY READ
FROM THE ALARM STATE REGISTER.
PPMU ALARM FLAG, CHANNEL 0/CHANNEL 1
[0] = PPMU VOLTAGE/CURRENT CLAMP OR STATIC CURRENT LIMIT CONDITION NOT DETECTED.
1 = PPMU VOLTAGE/CURRENT CLAMP OR STATIC CURRENT LIMIT CONDITION DETECTED.
WHEN THE ALARM_PPMU_FLAG_x BIT IS SET, THEN A PPMU VOLTAGE/CURRENT CLAMP OR STATIC
CURRENT LIMIT CONDITION IS DETECTED ON CHANNEL x. THIS FLAG IS SUBORDINATE TO THE
ALARM_PPMU_MASK_x CONTROL BIT, AND AUTOMATICALLY RESETS AFTER ANY READ FROM THE ALARM
STATE REGISTER.
OVERVOLTAGE ALARM FLAG, CHANNEL 0/CHANNEL 1
[0] = OVERVOLTAGE FAULT NOT DETECTED.
1 = OVERVOLTAGE FAULT DETECTED.
WHEN ALARM_OVDH_FLAG IS SET, AN OVERVOLTAGE FAULT CONDITION IS DETECTED ON CHANNEL x
DUTx PIN ACCORDING TO THE THRESHOLD SET IN THE OVDH DAC REGISTER. THIS FLAG IS SUBORDINATE
TO THE ALARM_OVD_MASK_x CONTROL BIT, AND IT AUTOMATICALLY RESETS AFTER ANY READ FROM
THE ALARM STATE REGISTER.
12160-024
UNDERVOLTAGE ALARM FLAG, CHANNEL 0/CHANNEL 1
[0] = UNDERVOLTAGE FAULT NOT DETECTED.
1 = UNDERVOLTAGE FAULT DETECTED.
WHEN ALARM_OVDL_FLAG_x IS SET, AN UNDERVOLTAGE FAULT CONDITION IS DETECTED ON CHANNEL x
DUTx PIN ACCORDING TO THE THRESHOLD SET IN THE OVDL DAC REGISTER. THIS FLAG IS SUBORDINATE
TO THE ALARM_OVD_MASK_x CONTROL BIT, AND AUTOMATICALLY RESETS AFTER ANY READ FROM THE
ALARM STATE REGISTER.
Figure 153. Alarm State Register (Address 0x1E) (Read Only)
SPI CLOCK INDEX
DATA-WORD INDEX
15
16
17
18
19
20
21
22
23
24
25
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
10
11
12
13
14
CHAN 0:
CHAN 1:
PRODUCT SERIALIZATION CODE LOW (LOWER HALF)
PRODUCT SERIALIZATION CODE HIGH (UPPER HALF)
Figure 154. Product Serialization Code Register (Address 0x1F)
Rev. B | Page 79 of 82
12160-025
PRODUCT SERIALIZATION CODE REGISTER, CHANNEL 0/CHANNEL 1
THIS REGISTER CONTAINS UNIQUE NONVOLATILE PRODUCT IDENTIFICATION INFORMATION THAT IS
WRITTEN TO THE DEVICE DURING MANUFACTURE. THIS REGISTER IS INITIALIZED DURING RESET TO
THE DATA TRIMMED INTO NONVOLATILE FUSE MEMORY. WHILE IT IS POSSIBLE TO WRITE SOME
TEMPORARY DATA TO THIS REGISTER, IT HAS NO EFFECT ON OPERATION OF THE DEVICE. THE
CONTENTS OF THE REGISTER ARE REINITIALIZED AT NEXT RESET TO THE FACTORY PROGRAMMED
VALUES. THERE ARE 32 BITS OF IDENTIFICATION DATA CONTAINED IN THIS REGISTER, AS FOLLOWS:
ADATE320
Data Sheet
DEFAULT TEST CONDITIONS
Table 30. Default Test Conditions
Name
VIHx DAC Levels
VITx/VCOMx DAC Levels
VILx DAC Levels
VOHx DAC Levels
VOLx DAC Levels
POHx DAC Levels
POLx DAC Levels
VCHx DAC Levels
VCLx DAC Levels
PCHx DAC Levels
PCLx DAC Levels
VIOHx DAC Levels
VIOLx DAC Levels
PPMUx DAC Levels
OVDH DAC Level
OVDL DAC Level
DAC Control Register
SPI Control Register
DRV Control Registers
SPI Address
Address 0x01[x]
Address 0x02[x]
Address 0x03[x]
Address 0x06[x]
Address 0x07[x]
Address 0x0D[x
Address 0x0E[x]
Address 0x04[x]
Address 0x05[x]
Address 0x0B[x]
Address 0x0C[x]
Address 0x08[x]
Address 0x09[x]
Address 0x0A[x]
Address 0x0F[1]
Address 0x0F[0]
Address 0x11[0]
Address 0x12[1]
Address 0x19[x]
Default Test
Condition
2.0 V
1.0 V
0.0 V
5.0 V
−2.0 V
5.5 V
−2.0 V
5.0 V
−2.0 V
7.0 V
−2.0 V
0.0 mA
0.0 mA
0.0 V
5.0 V
−2.0 V
0x0000
0x0000
0x0000
CMP Control Registers
LOAD Control Registers
PPMU Control Registers
Address 0x1A[x]
Address 0x1B[x]
Address 0x1C[x]
0x0000
0x0000
0x0000
ALARM Mask Registers
Calibration m Coefficients
Calibration c Coefficients
DATx, RCVx Inputs
SCLK Input
DUTx Pins
CMPHx, CMPLx Outputs
VDUTGND
Address 0x1D[x]
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
0x0085
1.0 (0xFFFF)
0.0 (0x8000)
Static low
Static low
Unterminated
Unterminated
0.0 V
Description
DAC calibration disabled, DAC load mode is immediate
SDO pin is always active, independent of CS state
Driver disabled in low leakage mode, DATx/RCVx inputs are multiplexed
to primary channels, CLC is off, driver responds high-Z to RCVx inputs
when enabled
Normal window comparator mode, CLC is off, hysteresis is off
Active load is disabled and in power-down mode
PPMU disabled and in power-down mode, mode set FVMV Range E,
input select VDUTGND internal sense path to VDUTx, PPMU_Mx pins high-Z,
clamps disabled
Disable PPMU and overvoltage detector alarm functions
Rev. B | Page 80 of 82
Data Sheet
ADATE320
EXTERNAL COMPONENTS
In addition to the external components identified in Table 31
and Table 32, see the Power Supply, Grounding, and Typical
Decoupling Strategy section for further information about
recommended power supply decoupling capacitors.
Table 31. PPMU External Compensation Capacitors
External Components Value (pF)
1000 pF
1000 pF
Location
Between the CFFB0 and CFFA0 pins
Between the CFFB1 and CFFA1 pins
Table 32. Other External Components
External Components Value (kΩ)
10 kΩ
1 kΩ
Location
ALARM pull-up resistor to VDD
BUSY pull-up resistor to VDD
Rev. B | Page 81 of 82
ADATE320
Data Sheet
OUTLINE DIMENSIONS
10.10
10.00 SQ
9.90
0.60
0.42
0.24
PIN 1
INDICATOR
EXPOSED PAD
6.85
6.75 SQ
6.65
(SEE NOTE 1)
9.85
9.75 SQ
9.65
0.60
0.42
0.24
0.25
64
63
84 1
43
42
22 21
TOP VIEW
BOTTOM VIEW
8.00 REF
0.70
0.65
0.60
12° MAX
SEATING
PLANE
(SEE NOTE 2)
(SEE NOTE 2)
0.40
BSC
0.60
0.50
0.40
1.00
0.85
0.80
0.97
0.93
0.83
0.73
0.70
0.60
0.50
0.05 MAX
0.01 NOM
COPLANARITY
0.08
0.20 REF
0.30
0.23
0.18
07-02-2012-B
NOTES:
1. FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
2. TIEBARS MAY OR MAY NOT BE SOLDERED TO THE BOARD.
Figure 155. 84-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
10 mm × 10 mm Body, Very Thin Quad
(CP-84-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADATE320KCPZ
ADATE320-1KCPZ
1
Temperature Range
25°C to 75°C
25°C to 75°C
Package Description
84-Lead LFCSP_VQ with Exposed Pad (Tray)
84-Lead LFCSP_VQ with Exposed Pad (Tray)
Package Option
CP-84-2
CP-84-2
Z = RoHS Compliant Part.
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12160-0-9/16(B)
www.analog.com/ADATE320
Rev. B | Page 82 of 82