APW7324 4A,5V, 500KHz Synchronous Buck Converter Features General Description • High Efficiency up to 94% APW7324 is a synchronous buck converters with inte- - Automatic Skip/PWM Mode Operation grated 85mΩ high side and 75mΩ low side power MOSFETs. The APW7324 with a current-mode control • Adjustable Output Voltage from 0.8V to VIN • Operating from 2.9 to 6V Supply • Integrated 85mΩ High Side / 75mΩ Low Side scheme can convert wide input voltage of 2.9V to 6V to the output voltage adjustable from 0.8V to 6V to provide excellent output voltage regulation. The APW7324 is equipped with an automatic Skip/PWM MOSFETs • Low Dropout Operation: 100% Duty Cycle • Stable with Low ESR Ceramic Capacitors • Current up to 4A • Power-On-Reset Detection on VCC and VIN • Integrate Soft-Start and Soft-Stop • Over-Temperature Protection • Over-Voltage Protection • Under-Voltage Protection • High/ Low Side Current Limit • Power Good Indication • Enable/Shutdown Function • Available in SOP-8P and TDFN3x3-10 Packages • Lead Free and Green Devices Available mode operation. At light load , the IC operates in the Skip mode to reduce the switching losses. At heavy load, the IC works in PWM mode. The APW7324 is also equipped with Power-on-reset, soft start, soft-stop, and whole protections (under-voltage, over-voltage, over-temperature and current-limit) into a single package. This device, available in SOP-8P and TDFN3x3-10 packages, provides a very compact system solution external components and PCB area. Simplified Application Circuit VIN VIN (RoHS Compliant) C2 R3 VCC Applications • • Notebook Computer & UMPC • Set-Top Box • DSL, Switch HUBr • Portable Instrument C3 ON LCD Monitor/TV L1 VOUT LX APW7324 FB EN OFF POK GND PGND R1 C4 R2 C1 (optional) Pin Configuration VCC 1 8 VIN POK 2 7 LX GND 3 6 PGND FB 4 5 EN SOP-8P (Top View) EN 1 NC 2 PGND 3 LX 4 LX 5 10 FB 9 GND 8 POK 7 VCC 6 VIN TDFN3x3-10 (Top View) Exposed Pad (connected to GND plane for better heat dissipation ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 1 www.anpec.com.tw APW7324 Ordering and Marking Information Package Code KA: SOP-8P QB : TDFN3x3-10 APW7324 Assembly Material Operating Ambient Temperature Range I : -40 to 85 oC Handling Code Handling Code TR : Tape & Reel Temperature Range Package Code Assembly Material G : Halogen and Lead Free Device APW7324 KA: APW7324 XXXXX APW7324 QB: XXXXX - Date Code APW 7324 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol VIN, VCC VLX Parameter Rating VIN and VCC Input Voltage LX to GND Voltage FB, EN, POK to GND Voltage PD Power Dissipation TJ Junction Temperature -0.3 ~ 7 V -1 ~VCC+0.3 V -0.3 ~ 6.5 V Internally Limited TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature(10 Seconds) Unit W 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Thermal Characteristics Symbol θJA θJC Parameter Typical Value Junction-to-Ambient Resistance in Free Air (Note 2) Junction-to-Case Resistance in Free Air (Note 3) Unit 50 o 10 o C/W C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8P is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P package. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 2 www.anpec.com.tw APW7324 Recommended Operating Conditions (Note 4) Symbol Parameter Range Unit VCC VCC Supply Voltage 2.9~ 6 V VIN VIN Supply Voltage 2.5~6 V VOUT Converter Output Voltage 0.8~6 V IOUT Converter Maximum Output Current TA Ambient Temperature TJ 4 Junction Temperature A -40 ~ 85 o -40 ~ 125 o C C Note 4: Refer to the typical application circuit. Electrical Characteristics Unless otherwise specified, these specifications apply over VCC=VIN=5V, VOUT=3.3V and TA=-40~85oC. Typical values are at TA=25oC. Symbol Parameter APW7324 Test Conditions Unit Min. Typ. Max. SUPPLY CURRENT IVCC IVCC_SD VCC Supply Current VFB=0.7V - 460 - µA VCC Shutdown Supply Current EN=GND - - 20 µA VCC POR Voltage Threshold VCC Rising - 2.7 - V VCC POR Voltage Hysteresis VCC Falling POWER-ON-RESET (POR) VCC Debounce Time - 200 - mV - 10 - µs VIN POR Voltage Threshold VIN Rising - 2.3 - V VIN POR Voltage Hysteresis VIN Falling - 50 - mV - 0.8 - V REFERENCE VOLTAGE VREF Reference Voltage All temperature Output Accuracy IOUT=10mA~3A, VCC=2.9~5V -1 - +1 % -1.5 - +1.5 % 425 500 575 KHz - 100 - % - 70 - ns - 85 115 mΩ - 75 105 mΩ OSCILLATOR and DUTY CYCLE FOSC Oscillator Frequency Maximum Converter’s Duty VFB=0.7V Minimum on Time POWER MOSFET High Side MOSFET Resistance Low Side MOSFET Resistance Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 VCC=VIN=5V, ILX=0.5A, TA=25oC o VCC=VIN=5V, ILX=0.5A, TA=25 C 3 www.anpec.com.tw APW7324 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC=VIN=5V, VOUT=3.3V and TA=-40~85oC. Typical values are at TA=25oC. Symbo Parameter APW7324 Test Conditions Min. Typ. Unit Max. CURRENT -MODE PWM CONVERTER Gm 680 - µA/V - 50 - dB Current Sense Resistance - 400 - mΩ Dead Time - 20 - ns 5 6 7 A - 160 - °C Error Amplifier DC Gain TD - Error Amplifier Transconductance COMP=NC PROTECEIONS ILIM High Side MOSFET current-limit TOTP Over-temperature Trip Point Peak Current Over-temperature Hysteresis - 50 - °C 120 125 130 %VREF - 3 - µs 45 50 55 %VREF - 3 - µs -1.6 -1.9 -2.2 A - 2.5 - ms 0.8 - 1.3 V EN Threshold Hysteresis - 0.15 - V EN Pull High Resistance - 300 - KΩ POK in from lower (POK goes high) 85 87.5 90 %VOUT POK low hysteresis - 5 - %VOUT POK in from higher (POK goes high) 110 112.5 115 %VOUT POK high hysteresis - 5 - %VOUT POK Pull Low Resistance - 1 - ΚΩ POK Low-to-High Debounce Time - 0.5 - ms Over- Voltage Protection Threshold OVP Debounce Time Under-Voltage Protection Threshold UVP Debounce Time Low Side Switch Current-Limit From Drain to Source SOFT-START, ENABLE and INPUT CURRENTS Soft Start Time EN Enable Threshold Voltage VEN Rising POWER GOOD POK Threshold Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 4 www.anpec.com.tw APW7324 Typical Operating Characteristics VCC Supply Current vs. VCC Supply Voltage Efficiency vs. Output Current 600 100 VCC Supply Current, IVCC (µA) 95 Efficiency(%) 90 85 VOUT =3.3V 80 VOUT =1.2V 75 70 65 VIN =5V 500 400 300 200 100 0 60 0.001 0.01 0.1 10 1 VCC =5V, VIN =5V, VOUT =3.3V, No Load, TA=25oC 2.5 3 4 4.5 5 5.5 6 VCC Supply Voltage (V) Output Current, IOUT(A) High Side MOSFET Current Limit Threshold vs. VIN Voltage On-Resistance vs. VIN Voltage 4.5 120 4.0 115 On- Resistance, RDS(ON) (mΩ) High Side MOSFET Current Limit Threshold, ILIM (Α) 3.5 3.5 3.0 2.5 2.0 1.5 1.0 0.5 TA=25oC 110 P-MOSFET 105 N-MOSFET 100 95 90 85 80 75 70 0.0 2.5 3 3.5 4.5 4 5 5.5 6 2.5 VIN Voltage,VVIN(V) 3 3.5 4 4.5 5 5.5 6 VIN Voltage, VVIN (V) Reference Voltage vs. Output Current 0.85 Reference Voltage, VREF (V) 0.84 0.83 0.82 0.81 0.80 0.79 0.78 0.77 0.76 0.75 0 0.5 1 1.5 2 2.5 3 3.5 4 Output Current, IOUT(A) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 5 www.anpec.com.tw APW7324 Operating Waveforms The test condition is APW7324, VIN=VCC=5V, VOUT=1.8V, COUT =22µFx2, L=2.2µH, TA= 25oC unless otherwise specified. Shutdown without Loading Enable without Loading VEN VEN 1 1 VOUT V OUT 2 2 V POK V POK 3 3 IL 4 IL 4 No load , EN Power Off No load, EN Power On CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IL, 2A/Div, DC TIME: 1ms/Div CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IL, 2A/Div, DC TIME: 100µs/Div Enable with 2A Loading Shutdown with 2A Loading VEN VEN 1 1 V OUT VOUT 2 2 VPOK 3 VPOK 3 IL 4 IL 4 IOUT=2A, EN Power On IOUT=2A, EN Power Off CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IL, 2A/Div, DC TIME: 1ms/Div CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IL, 2A/Div, DC TIME: 100µs/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 6 www.anpec.com.tw APW7324 Operating Waveforms The test condition is APW7324, VIN=VCC=5V, VOUT=1.8V, COUT =22µFx2, L=2.2µH, TA= 25oC unless otherwise specified. Load Transient Load Transient VOUT V OUT 1 1 I OUT I OUT 2 2 IOUT=100mA-4A-100mA, Slew Rate=1A/µs IOUT=1A-4A-1A, Slew Rate=1A/µs CH1: VOUT, 200mV/Div, offset=1.8V CH2: IOUT, 2A/Div, DC CH1: VOUT, 200mV/Div, offset=1.8V TIME: 50µs/Div TIME: 50µs/Div CH2: IOUT, 2A/Div, DC Current Limit Over Voltage Protection V OUT VOUT 1 V POK VPOK 1 2 2 I OUT IL 3 3 No Load, a 2.5V power source is externally attached to VOUT CH1: VOUT, 1V/Div, DC CH2: VPOK, 5V/Div, DC CH3: IL, 2A/Div, DC TIME: 50µs/Div CH1: VOUT ,1V/Div, DC CH2: VPOK, 5V/Div, DC CH3: IOUT, 5A/Div, DC TIME: 200µs/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 7 www.anpec.com.tw APW7324 Operating Waveforms The test condition is APW7324, VIN=VCC=5V, VOUT=1.8V, COUT =22µFx2, L=2.2µH, TA= 25oC unless otherwise specified. Normal Operation in Heavy Load Normal Operation in Ligh Load VOUT VOUT 1 1 VLX VLX 2 2 IL IL 3 3 IOUT=200mA IOUT=4A CH1: VOUT, 50mV/Div, offset=1.8V CH2: VLX, 5V/Div, DC CH3: ILX, 2A/Div, DC TIME: 2µs/Div CH1: VOUT, 50mV/Div, offset=1.8V CH2: VLX, 5V/Div, DC CH3: ILX, 5A/Div, DC TIME: 2µs/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 8 www.anpec.com.tw APW7324 Pin Description Pin NO. Function Name SOP-8P TDFN3x3-10 1 7 VCC 2 8 POK 3 9 GND 4 10 FB Output Feedback Input. The APW7324 senses the feedback voltage via FB and regulates the voltage at 0.8V. Connecting FB with a resistor-divider from the converter’s output sets the output voltage. 5 1 EN Enable Input. EN is a digital input that turns the regulator on or off. Driving the EN high turns on the regulator, otherwise, driving it low turns it off. The EN pin is internally pulled high via a 300kΩ resistor. 6 3 PGND 7 4, 5 LX Power Switching Output. LX is the Junction of the high-side and low-side Power MOSFETs to supply power to the output LC filter. 8 6 VIN Power Input. VIN supplies the step-down converter switches. 9 11 Signal Input. VCC supplies the control circuitry, gate drivers. Connecting a ceramic bypass capacitor from VCC to GND to eliminate switching noise and voltage ripple on the input to the IC. Power Good Output. This pin is open-drain logic output that is pulled to ground when the output voltage is not within ±12.5% of regulation point. The POK pin, if used, needs an external pull high resistor in the range of 30kΩ~100kΩ Ground. Power and signal ground. Power Ground. Exposed Exposed pad. Connect the exposed pad to the system ground plane with large copper Pad area for dissipating heat into the ambient air. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 9 www.anpec.com.tw APW7324 Block Diagram VIN VCC Current Sense Amplifier LOC Over Temperature Protection Power-OnReset Current Limit Zero Crossing Comparator POR OTP OVP 125 %V RE F Fault Logics 50%VR E F UVP Inhibit 112.5%VR E F 87.5%V RE Current Comparator Error Amplifie r Gm F FB Soft start VR E F 0.8V Gate Control Slope Compensation Oscillator Shutdown LX Gate Driver Gat e LOC Current Sense Amplifier GND 300kΩ VIN EN POK Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 10 www.anpec.com.tw APW7324 Typical Application Circuit VIN 5V VOUT 1.8V VIN LX R4 2.2Ω CIN 22µF VCC 100kΩ FB C2 1µF Off R5 C3 Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 C1 22pF R1 25kΩ COUT 22 µ Fx2 APW7324 R2 20kΩ POK On L1 2.2 µH EN GND PGND Exposed pad 11 www.anpec.com.tw APW7324 Function Description VCC and VIN Power-On-Reset (POR) The thermal sensor allows the converters to start a start- TThe APW7324 keeps monitoring the voltage on VIN and VCC pins to prevent wrong logic operations which may up process and to regulate the output voltage again after the junction temperature cools by 50oC. The OTP is de- occur when VIN or VCC voltage is not high enough for internal control circuitry to operate. The VCC POR rising signed with a 50 oC hysteresis to lower the average TJ during continuous thermal overload conditions, increas- threshold is 2.7V (typical) with 0.2V hysteresis and VIN POR rising threshold is 2.3V with 0.05V hysteresis. ing lifetime of the APW7324. Current-Limit Protection During startup, the VCC and VIN voltage must exceed the POR threshold. Then the IC starts a starts-up process The APW7324 monitors the output current, flows through the high-side and low-side power MOSFETs, and limits the current peak at current-limit level to prevent the IC and ramps up the output voltage to the voltage target. Output Under-Voltage Protection (UVP) from damaging during overload, short-circuit and overvoltage conditions. Typical high side power MOSFET cur- In the operational process, if a short-circuit occurs, the rent limit is 6A, and low side MOSFET current limit is 1.9A. output voltage will drop quickly. Before the current-limit circuit responds, the output voltage will fall out of the re- Soft-Start quired regulation range. The under-voltage continually monitors the FB voltage after soft-start is completed. If a The APW7324 has a built-in soft-start to control the rise rate of the output voltage and limit the input current surge during start-up. During soft-start, an internal voltage ramp load step is strong enough to pull the output voltage lower than the under-voltage threshold, the IC shuts down connected to one of the positive inputs of the error converter’s output. amplifier, rises up from 0V to 0.95V to replace the reference voltage (0.8V) until the voltage ramp reaches the The under-voltage threshold is 50% of the nominal output voltage. The under-voltage comparator has a built-in reference voltage. During soft-start without output overvoltage, the APW7324 converter’s sinking capability is dis- 3µs noise filter to prevent the chips from wrong UVP shutdown being caused by noise. The APW7324 will be latched abled until the output voltage reaches the voltage target. after under-voltage protection. Soft-Stop Over-Voltage Protection (OVP) At the moment of shutdown controlled by EN signal, un- The over-voltage function monitors the output voltage by der-voltage event or over-temperature protection, the APW7324 initiates a soft-stop process to discharge the FB pin. When the FB voltage increases over 125% of the reference voltage due to the high-side MOSFET failure or output voltage in the output capacitors. Certainly, the load current also discharges the output voltage. During soft- for other reasons, the over-voltage protection comparator will force the low-side MOSFET gate driver high. This ac- stop, the internal voltage ramp (VRAMP) falls down from 0. 95V to 0V to replace the reference voltage. Therefore, the tion actively pulls down the output voltage and eventually attempts to blow the internal bonding wires. As soon as output voltage falls down slowly at the light load. After the soft-stop interval elapses, the soft-stop process ends and the output voltage is within regulation, the OVP comparator is disengaged. The chip will restore its normal the IC turns on the low-side power MOSFET. operation. Enable and Shutdown Over-Temperature Protection (OTP) Driving EN to ground places the APW7324 in shutdown. The over-temperature circuit limits the junction tempera- In shutdown mode, the internal power MOSFETs turns off, all internal circuitry shuts down and the quiescent ture of the APW7324. When the junction temperature exceeds TJ = 160 oC, a thermal sensor turns off the both supply current reduces to less than 20µA. power MOSFETs, allowing the devices to cool. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 12 www.anpec.com.tw APW7324 Function Description (Cont.) Power Good Indicator POK is actively held low in shutdown and soft-start status. In the soft-start process, the POK is an open-drain. When the soft-start is finished, the POK is released. In normal operation, the POK window is from 87.5% to 112.5% of the converter reference voltage. When the output voltage has to stay within this window, POK signal will become high after 0.5ms internal delay. When the output voltage outruns 82.55% or 117.5% of the target voltage, POK signal will be pulled low immediately. In order to prevent false POK drop, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 13 www.anpec.com.tw APW7324 Application Information Input Capacitor Selection shown in “Typical Application Circuits”. A suggestion of Because buck converters have a pulsating input current, maximum value of R2 is 300kΩ to keep the minimum current that provides enough noise rejection ability through a low ESR input capacitor is required. This results in the best input voltage filtering, minimizing the interference with other circuits caused by high input voltage spikes. Also, the input capacitor must be sufficiently large to sta- the resistor divider. The output voltage can be calculated as below: R1 VOUT = VREF ⋅ 1 + R 2 bilize the input voltage during heavy load transients. For good input voltage filtering, usually a 22µF input capaci- VOUT tor is sufficient. It can be increased without any limit for better input voltage filtering. Ceramic capacitors show R1≤1MΩ better performance because of the low ESR value, and they are less sensitive against voltage transients and FB R2 ≤ 300KΩ APW7324 spikes compared to tantalum capacitors. Place the input capacitor as close as possible to the input and GND pin GND of the device for better performance. Output Capacitor Selection Inductor Selection For high efficiencies, the inductor should have a low dc The current-mode control scheme of the APW7324 allows the use of tiny ceramic capacitors. The higher ca- resistance to minimize conduction losses. Especially at high-switching frequencies the core material has a higher pacitor value provides the good load transients response. Ceramic capacitors with low ESR values have the lowest impact on efficiency. When using small chip inductors, the efficiency is reduced mainly due to higher inductor output voltage ripple and are recommended. If required, tantalum capacitors may be used as well. The output core losses. This needs to be considered when selecting the appropriate inductor. The inductor value deter- ripple is the sum of the voltages across the ESR and the ideal output capacitor. mines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the lower ∆VOUT the conduction losses of the converter. Conversely, larger inductor values cause a slower load transient response. A reasonable starting point for setting ripple current, ∆IL, is 40% of maximum output current. The recommended inductor value can be calculated as below: V VOUT 1 − OUT VIN L≥ FSW ⋅ ∆IL V VOUT ⋅ 1 − OUT VIN ≅ FSW ⋅ L 1 ⋅ ESR + ⋅ 8 F SW ⋅ COUT When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. VIN IIN IP-FET IL(MAX) = IOUT(MAX) + 1/2 x ∆IL To avoid saturation of the inductor, the inductor should be rated at least for the maximum output current of the converter plus the inductor ripple current. IL CIN P-FET VOUT LX N-FET Output Voltage Setting IOUT ESR COUT In the adjustable version, the output voltage is set by a resistive divider. The external resistive divider is connected to the output, allowing remote voltage sensing as Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 14 www.anpec.com.tw APW7324 Application Information (Cont.) Recommended Minimum Footprint Output Capacitor Selection (Cont.) 0.024 ILIM 8 7 6 5 0.072 IL IPEAK ∆IL 0.118 0.212 0.138 IOUT IP-FET 1 2 0.050 3 4 Unit : Inch SOP-8P Layout Considerations For all switching power supplies, the layout is an important step in the design; especially at high peak currents and switching frequencies. If the layout is not carefully done, the regulator might show noise problems and duty ThermalVia diameter 12mil X 5 Ground plane for ThermalPAD 0. 275mm 0.75mm 0.30mm cycle jitter. 1. The input capacitor should be placed close to the VIN 2.70mm and GND. Connect the capacitor and VIN/GND with short and wide trace without any via holes for good input voltage filtering. The distance between VIN/GND to capacitor less than 2mm respectively is recommended. 2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed as 0.50mm close as possible to the LX pin to minimize the noise coupling into other circuits. 1.75mm TDFN3X3-10 3. The output capacitor should be place closed to VOUT and GND. 4. Keep the sensitive small signal nodes (FB) away from switching nodes (LX) on the PCB. Therefore place the feedback divider and the feedback compensation network close to the IC to avoid switching noise. Connect the ground of feedback divider directly to the GND pin of the IC using a dedicated ground trace. 5. A star ground connection or ground plane minimizes ground shifts and noise is recommended. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 15 www.anpec.com.tw APW7324 Package Information SOP-8P D SEE VIEW A h X 45o E THERMAL PAD E1 E2 D1 c A1 0.25 A2 A b e GAUGE PLANE SEATING PLANE θ L VIEW A S Y M B O L SOP-8P INCHES MILLIMETERS MAX. MIN. A MIN. MAX. 1.60 A1 0.00 A2 1.25 b 0.31 0.063 0.000 0.15 0.006 0.049 0.51 0.012 0.020 0.010 c 0.17 0.25 0.007 D 4.80 5.00 0.189 0.197 D1 2.50 3.50 0.098 0.138 0.244 E 5.80 6.20 0.228 E1 3.80 4.00 0.150 0.157 E2 2.00 3.00 0.079 0.118 e 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0o C 8o C 0 0oC 8oC Note : 1. Followed from JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 16 www.anpec.com.tw APW7324 Package Information TDFN3x3-10 D E A b Pin 1 A1 D2 A3 L K E2 Pin 1 Corner e TDFN3x3-10 S Y M B O L A MIN. MAX. MIN. MAX. 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 0.30 0.007 0.012 3.10 0.114 0.122 A3 b INCHES MILLIMETERS 0.20 REF 0.18 0.008 REF D 2.90 D2 2.20 2.70 0.087 0.106 E 2.90 3.10 0.114 0.122 1.75 0.055 0.069 0.50 0.012 E2 1.40 e L K 0.50 BSC 0.30 0.020 BSC 0.020 0.008 0.20 Note : 1. Followed from JEDEC MO-229 VEED-5. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 17 www.anpec.com.tw APW7324 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-8P Application TDFN3x3-10 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.40±0.20 5.20±0.20 2.10±0.20 4.0±0.10 8.0±0.10 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 (mm) Devices Per Unit Unit Package Type Quantity SOP- 8P Tape & Reel 2500 TDFN-3x3-10 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 18 www.anpec.com.tw APW7324 Taping Direction Information SOP-8P USER DIRECTION OF FEED TDFN3x3-10 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 19 www.anpec.com.tw APW7324 Classification Profile Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 20 www.anpec.com.tw APW7324 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Volume mm Thickness <350 <2.5 mm 235 °C ≥2.5 mm 220 °C Table 2. Pb-free Process – Classification Temperatures (Tc) 3 3 Volume mm ≥350 220 °C 220 °C Volume mm 350-2000 260 °C 3 3 Package Thickness <1.6 mm Volume mm <350 260 °C Volume mm >2000 260 °C 1.6 mm – 2.5 mm 260 °C 250 °C 245 °C ≥2.5 mm 250 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 21 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7324 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 22 www.anpec.com.tw