a Complete Dual 18-Bit 16 ⴛ FS Audio DAC AD1865 FUNCTIONAL BLOCK DIAGRAM (DIP Package) FEATURES Dual Serial Input, Voltage Output DACs No External Components Required 110 dB SNR 0.003% THD+N Operates at 16 ⴛ Oversampling per Channel ⴞ5 Volt Operation Cophased Outputs 116 dB Channel Separation Pin Compatible with AD1864 DIP or SOIC Packaging APPLICATIONS Multichannel Audio Applications Compact Disc Players Multivoice Keyboard Instruments DAT Players and Recorders Digital Mixing Consoles Multimedia Workstations 1 TRIM 2 23 TRIM REFERENCE MSB REFERENCE 3 22 MSB IOUT IOUT 4 21 AGND 5 20 AGND 19 SJ RF 7 18 RF VOUT 8 17 VOUT +VL 9 16 NC DR 10 15 DL LR 11 14 LL 13 DGND TE SJ 6 CLK 18-BIT LATCH 18-BIT D/A 18-BIT D/A 12 18-BIT LATCH NC = NO CONNECT A versatile digital interface allows the AD1865 to be directly connected to standard digital filter chips. This interface employs five signals: Data Left (DL), Data Right (DR), Latch Left (LL), Latch Right (LR) and Clock (CLK). DL and DR are the serial input pins for the left and right DAC input registers. Input data bits are clocked into the input register on the rising edge of CLK. A low-going latch edge updates the respective DAC output. For systems using only a single latch signal, LL and LR may be connected together. For systems using only one DATA signal, DR and DL may be connected together. O B SO The AD1865 is a complete, dual 18-bit DAC offering excellent THD+N and SNR while requiring no external components. Two complete signal channels are included. This results in cophased voltage or current output signals and eliminates the need for output demultiplexing circuitry. The monolithic AD1865 chip includes CMOS logic elements, bipolar and MOS linear elements and laser-trimmed thin-film resistor elements, all fabricated on Analog Devices’ ABCMOS process. The DACs on the AD1865 chip employ a partially segmented architecture. The first four MSBs of each DAC are segmented into 15 elements. The 14 LSBs are produced using standard R-2R techniques. Segment and R-2R resistors are laser trimmed to provide extremely low total harmonic distortion. This architecture minimizes errors at major code transitions resulting in low output glitch and eliminating the need for an external deglitcher. When used in the current output mode, the AD1865 provides two ± 1 mA output signals. Each channel is equipped with a high performance output amplifier. These amplifiers achieve fast settling and high slew rate, producing ± 3 V signals at load currents up to 8 mA. Each output amplifier is short-circuit protected and can withstand indefinite short circuits to ground. The AD1865 was designed to balance two sets of opposing requirements, channel separation and DAC matching. High channel separation is the result of careful layout. At the same time, both channels of the AD1865 have been designed to ensure matched gain and linearity as well as tracking over time and temperature. This assures optimum performance when used in stereo and multi-DAC per channel applications. 24 +V S AD1865 LE PRODUCT DESCRIPTION –V S The AD1865 operates with ± 5 V power supplies. The digital supply, VL, can be separated from the analog supplies, VS and –VS, for reduced digital feedthrough. Separate analog and digital ground pins are also provided. The AD1865 typically dissipates only 225 mW, with a maximum power dissipation of 260 mW. The AD1865 is packaged in both a 24-pin plastic DIP and a 28-pin SOIC package. Operation is guaranteed over the temperature range of –25°C to +70°C and over the voltage supply range of ± 4.75 V to ± 5.25 V. PRODUCT HIGHLIGHTS REV. 0 11. 12. 13. 14. 15. 16. 17. 18. 19. 10. The AD1865 is a complete dual 18-bit audio DAC. 110 dB signal-to-noise ratio for low noise operation. THD+N is typically 0.003%. Interchannel gain and midscale matching. Output voltages and currents are cophased. Low glitch for improved sound quality. Both channels are 100% tested at 16 × FS. Low Power—only 225 mW typ, 260 mW max. Five-wire interface for individual DAC control. 24-pin DIP or 28-pin SOIC packages available. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 = +25ⴗC, +V = +V = +5 V and –V = –5 V, F = 705.6 kHz, no MSB adjustment AD1865–SPECIFICATIONS or(T deglitcher) A L Parameter S S Min RESOLUTION S Typ Max 18 DIGITAL INPUTS VIH VIL IIH, VIH = +VL IIL, VIL = 0.4 V Clock Input Frequency 2.0 0.004 0.003 0.010 0.010 1.0 1.0 1.0 0.8 % of FSR % of FSR mV mV dB D-RANGE* (With A-Weight Filter) –60 dB, 990.5 Hz AD1865N, R AD1865N-J, R-J OUTPUT Voltage Output Configuration Output Range (± 1%) Output Impedance Load Current Short Circuit Duration Current Output Configuration Bipolar Output Range (± 30%) Output Impedance (± 30%) O 0.006 0.004 0.040 0.020 4.0 2.0 % % % % % % 116 dB 107 110 dB 88 94 100 100 dB dB ⴞ2.94 ± 3.0 0.1 ±8 POWER SUPPLY +VL and +VS –VS +I, +VL and +VS = +5 V –I, –VS = –5 V ppm of FSR/°C ppm of FSR/°C 110 B SO SIGNAL-TO-NOISE RATIO* (20 Hz to 30 kHz) V V µA µA MHz ± 25 ±4 LE CHANNEL SEPARATION* 0 dB, 990.5 Hz +VL 0.8 1.0 –10 TE 0.2 0.3 4 5 <2 DRIFT (0°C to +70°C) Gain Drift Midscale Drift TOTAL HARMONIC DISTORTION + NOISE* 0 dB, 990.5 Hz AD1865N, R AD1865N-J, R-J 20 dB, 990.5 Hz AD1865N, R AD1865N-J, R-J –60 dB, 990.5 Hz AD1865N, R AD1865N-J, R-J Bits 13.5 ACCURACY Gain Error Interchannel Gain Matching Midscale Error Interchannel Midscale Matching Gain Linearity (0 dB to –90 dB) Unit POWER DISSIPATION, +VL = +VS = +5 V, –VS = –5 V 0 –25 –60 WARMUP TIME 1 V Ω mA Indefinite to Common 4.75 –5.25 TEMPERATURE RANGE Specification Operation Storage ⴞ3.06 ±1 1.7 mA kΩ 5.0 –5.0 22 –23 5.25 –4.75 26 –26 V V mA mA 225 260 mW +25 +70 +70 +100 °C °C °C min Specifications shown in boldface are tested on production units at final test without optional MSB adjustment. *Tested in accordance with EIAJ Test Standard CP-307 with 18-bit data. Specifications subject to change without notice. –2– REV. 0 AD1865 ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.0 V VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.0 V –VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –6.0 V to 0 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 to VL Short Circuit Protection . . . . . . . . Indefinite Short to Ground Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1865 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. TE Temperature Range THD+N @ FS Package Option* AD1865N AD1865N-J AD1865R AD1865R-J –25°C to +70°C –25°C to +70°C –25°C to +70°C –25°C to +70°C 0.006% 0.004% 0.006% 0.004% N-24A N-24A R-28 R-28 –V S 1 24 +VS TRIM 2 23 TRIM MSB 3 22 MSB IOUT 4 21 IOUT AGND 5 20 AGND 19 SJ 18 RF LE Model RIGHT CHANNEL 11 12 13 –VS TRIM MSB Negative Analog Supply Right Channel Trim Network Connection Right Channel Trim Potentiometer Wiper Connection 26 IOUT Right Channel Output Current 28 AGND Analog Common Pin 11 SJ Right Channel Amplifier Summing Junction 12 RF Right Channel Feedback Resistor 13 VOUT Right Channel Output Voltage 14 +VL Positive Digital Supply 15 DR Right Channel Data Input Pin 16 LR Right Channel Latch Pin 17 CLK Clock Input Pin 18 DGND Digital Common Pin 19 LL Left Channel Latch Pin 10 DL Left Channel Data Input Pin 11, 16, 18 NC No Internal Connection* 25, 27 12 VOUT Left Channel Output Voltage Left Channel Feedback Resistor 13 RF 14 SJ Left Channel Amplifier Summing Junction 15 AGND Analog Common Pin 17 IOUT Left Channel Output Current 19 MSB Left Channel Trim Potentiometer Wiper Connection 20 TRIM Left Channel Trim Network Connection 21 +VS Positive Analog Supply O 14 15 16 17 18 19 10 11 12 13 14 15 16 22 23 24 B SO DIP SOIC 17 18 19 20 21 22 23 24 6 REV. 0 TOP VIEW RF 7 VOUT 8 17 VOUT +VL 9 16 NC DR 10 15 DL LR 11 14 LL CLK 12 13 DGND (Not to Scale) NC = NO CONNECT (28-Pin SOIC Package) SJ 1 RF 2 27 NC VOUT 3 26 IOUT +VL 4 25 NC 5 24 MSB DR LR 6 CLK 7 DGND 8 LL V 28 AGND AD1865 TOP VIEW (Not to Scale) 21 +VS 9 20 TRIM 19 MSB NC 11 18 NC 17 IOUT 12 RF 13 16 NC SJ 14 15 AGND NC = NO CONNECT –3– 23 TRIM 22 –VS DL 10 OUT *Pin 16 has no internal connection; –V L from AD1864 DIP socket can be safely applied. LEFT CHANNEL AD1865 SJ PIN DESIGNATIONS ESD SENSITIVE DEVICE PINOUT (24-Pin DIP Package) ORDERING GUIDE *N = Plastic DIP, R = Small Outline IC Package. WARNING! AD1865 TOTAL HARMONIC DISTORTION + NOISE INTERCHANNEL MIDSCALE MATCHING Total harmonic distortion plus noise (THD+N) is defined as the ratio of the square root of the sum of the squares of the amplitudes of the harmonics and noise to the value of the fundamental input frequency. It is usually expressed in percent. The midscale matching specification indicates how closely the amplitudes of the output signals of the two channels match when the twos complement input code representing half scale is loaded into the input register of both channels. It is expressed in mV and is measured with half-scale output signals. SIGNAL-TO-NOISE RATIO The signal-to-noise ratio is defined as the ratio of the amplitude of the output when a full-scale code is entered to the amplitude of the output when a midscale code is entered. It is measured using a standard A-Weight filter. SNR for the AD1865 is measured for noise components out to 30 kHz. CHANNEL SEPARATION D-Range distortion is equal to the value of the total harmonic distortion + noise (THD+N) plus 60 dB when a signal level of –60 dB below full scale is reproduced. D-Range is tested with a 1 kHz input sine wave. This is measured with a standard A-Weight filter as specified by EIAJ Standard CP-307. GAIN ERROR The voltage reference section provides a reference voltage for each DAC circuit. These voltages are produced by low-noise bandgap circuits. Buffer amplifiers are also included. This combination of elements produces reference voltages that are unaffected by changes in temperature and age. The output amplifiers use both MOS and bipolar devices and incorporate an all NPN output stage. This design technique produces higher slew rate and lower distortion than previous techniques. Frequency response is also improved. When combined with the appropriate on-chip feedback resistor, the output op amps convert the output current to output voltages. The 18-bit D/A converters use a combination of segmented decoder and R-2R architecture to achieve consistent linearity and differential linearity. The resistors which form the ladder structure are fabricated with silicon chromium thin film. Laser trimming of these resistors further reduces linearity errors resulting in low output distortion. B SO D-RANGE DISTORTION The AD1865 is a complete, monolithic, dual 18-bit audio DAC. No external components are required for operation. As shown in the block diagram, each chip contains two voltage references, two output amplifiers, two 18-bit serial input registers and two 18-bit DACs. LE Channel separation is defined as the ratio of the amplitude of a full-scale signal appearing on one channel to the amplitude of that same signal which couples onto the adjacent channel. It is usually expressed in dB. For the AD1865 channel separation is measured in accordance with EIAJ Standard CP-307, Section 5.5. FUNCTIONAL DESCRIPTION TE THD+N is a measure of the magnitude and distribution of linearity error, differential linearity error, quantization error and noise. The distribution of these errors may be different, depending on the amplitude of the output signal. Therefore, to be most useful, THD+N should be specified for both large (0 dB) and small (–20 dB, –60 dB) signal amplitudes. THD+N measurements for the AD1865 are made using the first 19 harmonics and noise out to 30 kHz. The input registers are fabricated with CMOS logic gates. These gates allow the achievement of fast switching speeds and low power consumption, contributing to the low glitch and low power dissipation of the AD1865. The gain error specification indicates how closely the output of a given channel matches the ideal output for given input data. It is expressed in % of FSR and is measured with a full-scale output signal. O INTERCHANNEL GAIN MATCHING The gain matching specification indicates how closely the amplitudes of the output signals match when producing identical input data. It is expressed in % of FSR (Full-Scale Range = 6 V for the AD1865) and is measured with full-scale output signals. MIDSCALE ERROR Midscale error is the deviation of the actual analog output of a given channel from the ideal output (0 V) when the twos complement input code representing half scale is loaded into the input register of the DAC. It is expressed in mV and is measured with half-scale output signals. –V S 1 TRIM 2 24 +V S AD1865 23 TRIM REFERENCE REFERENCE 22 MSB 4 21 IOUT 5 20 AGND MSB 3 IOUT AGND SJ 6 19 SJ RF 7 18 RF VOUT 8 17 VOUT +VL 9 DR 10 LR 11 CLK 12 18-BIT LATCH 18-BIT D/A 18-BIT D/A 18-BIT LATCH 16 NC 15 DL 14 LL 13 DGND NC = NO CONNECT AD1865 Block Diagram (DIP Package) –4– REV. 0 Typical Performance Data–AD1865 100 CHANNEL SEPARATION – dB 120 0dB THD+N – dB 90 80 110 100 90 80 70 4 4 0 16 12 8 12 8 16 TE 0 FREQUENCY – kHz FREQUENCY – kHz Figure 1. THD+N (dB) vs. Frequency (kHz) Figure 2. Channel Separation (dB) vs. Frequency (kHz) 10 LE THD+N – % 1 –60dB .1 .01 B SO –20dB .001 –30 –20 –10 0 10 20 30 0dB 40 50 60 70 80 90 TEMPERATURE – °C Figure 3. THD+N (%) vs. Temperature (°C) 90 O THD+N – dB 80 70 60 10 8 6 4 THD+N – dB 100 2 0 –2 –4 –6 50 –8 40 –10 0 500 1000 1500 2000 2500 3000 –100 –90 LOAD RESISTANCE – Ω –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE – dB Figure 4. THD+N (dB) vs. Load Resistance (Ω) REV. 0 –80 Figure 5. Gain Linearity (dB) vs. Input Amplitude (dB) –5– AD1865–Analog Circuit Consideration GROUNDING RECOMMENDATIONS The AD1865 has three ground pins, two labeled AGND and one labeled DGND. AGND, the analog ground pins, are the “high quality” ground references for the device. To minimize distortion and reduce crosstalk between channels, the analog ground pins should be connected together only at the analog common point in the system. As shown in Figure 6, the AGND pins should not be connected at the chip. –ANALOG SUPPLY AD1865 1 –VS +VS 24 2 TRIM TRIM 23 3 MSB MSB 22 4 IOUT IOUT 21 ANALOG SUPPLY As with most linear circuits, changes in the power supplies will affect the output of the DAC. Analog Devices recommends that well regulated power supplies with less than 1% ripple be incorporated into the design of an audio system. DISTORTION PERFORMANCE AND TESTING The THD+N figure of an audio DAC represents the amount of undesirable signal produced during reconstruction and playback of an audio waveform. The THD+N specification, therefore, provides a direct method to classify and choose an audio DAC for a desired level of performance. Figure 1 illustrates the typical THD+N performance of the AD1865 versus frequency. A load impedance of at least 1.5 kΩ is recommended for best THD+N performance. 5 AGND AGND 20 RF 18 8 VOUT VOUT 17 9 +VL NC 16 10 DR DL 15 11 LR 12 CLK VOUT LL 14 DGND 13 NC = NO CONNECT DIGITAL COMMON Analog Devices tests and grades all AD1865s on the basis of THD+N performance. During the distortion test, a high-speed digital pattern generator transmits digital data to each channel of the device under test. Eighteen-bit data is transmitted at 705.6 kHz (16 × FS). The test waveform is a 990.5 Hz sine wave with 0 dB, –20 dB and –60 dB amplitudes. A 4096 point FFT calculates total harmonic distortion + noise, signal-to-noise ratio, D-Range and channel separation. No deglitchers or MSB trims are used in the testing of the AD1865. TE SJ 19 7 RF LE VOUT DIGITAL SUPPLY 6 SJ OPTIONAL MSB ADJUSTMENT Figure 6. Recommended Circuit Schematic B SO The digital ground pin returns ground current from the digital logic portions of the AD1865 circuitry. This pin should be connected to the digital common pin in the system. Other digital logic chips should also be referred to that point. The analog and digital grounds should be connected together at one point in the system, preferably at the power supply. Use of optional adjust circuitry allows residual distortion error to be eliminated. This distortion is especially important when low amplitude signals are being reproduced. The MSB adjust circuitry is shown in Figure 7. The trim potentiometer should be adjusted to produce the lowest distortion using an input signal with a –60 dB amplitude. POWER SUPPLIES AND DECOUPLING O The AD1865 has three power supply input pins. ± VS provides the supply voltages which operate the analog portions of the DAC including the voltage references, output amplifiers and control amplifiers. The ± VS supplies are designed to operate from ± 5 V supplies. Each supply should be decoupled to analog common using a 0.1 µF capacitor in parallel with a 10 µF capacitor. Good engineering practice suggests that the bypass capacitors be placed as close as possible to the package pins. This minimizes the parasitic inductive effects of printed circuit board traces. AD1865 200kΩ 100kΩ 470kΩ 1 –VS TRIM 23 3 MSB MSB 22 4 IOUT IOUT 21 470kΩ 100kΩ 200kΩ 5 AGND AGND 20 6 SJ 7 RF 8 VOUT SJ 19 RF 18 VOUT 17 9 +VL NC 16 10 DR DL 15 11 LR 12 CLK The +VL supply operates the digital portions of the chip including the input shift registers and the input latching circuitry. This supply should be bypassed to digital common using a 0.1 µF capacitor in parallel with a 10 µF capacitor. +VL operates with a +5 V supply. In order to assure proper operation of the AD1865, –VS must be the most negative power supply voltage at all times. +VS 24 2 TRIM LL 14 DGND 13 NC = NO CONNECT Figure 7. Optional THD+N Adjust Circuitry Though separate positive power supply pins are provided for the analog and digital portions of the AD1865, it is also possible to use the AD1865 in systems featuring a single +5 V power supply. In this case, both the +VS and +VL input pins should be connected to the single +5 V power supply. This feature allows reduction of the cost and complexity of the system power supply. –6– REV. 0 Digital Circuit Considerations–AD1865 CURRENT OUTPUT MODE VOLTAGE OUTPUT MODES One or both channels of the AD1865 can be operated in current output mode. IOUT can be used to directly drive an external current-to-voltage (I-V) converter. The internal feedback resistor, RF, can still be used in the feedback path of the external I-V converter, thus assuring that RF tracks the DAC over time and temperature. As shown on the block diagram, each channel of the AD1865 is complete with an I-V converter and a feedback resistor. These can be connected externally to provide direct voltage output from one or both AD1865 channels. Figure 6 shows these connections. IOUT is connected to the Summing Junction, SJ. VOUT is connected to the feedback resistor, RF. This implementation results in the lowest possible component count and achieves the specifications shown on the Specifications page while operating at 16 × FS. Of course, the AD1865 can also be used in voltage output mode in order to utilize the onboard I-V converter. DL M S B DR M S B TE CLK L S B L S B LE LL LR B SO Figure 8. AD1865 Control Signals INPUT DATA TIMING Data is transmitted to the AD1865 in a bit stream composed of 18-bit words with a serial, twos complement, MSB first format. Data Left (DL) and Data Right (DR) are the serial inputs for the left and right DACs, respectively. Similarly, Latch Left (LL) and Latch Right (LR) update the left and right DACs. The falling edge of LL and LR cause the last 18 bits which were clocked into the Serial Registers to be shifted into the DACs, thereby updating the DAC outputs. Left and Right channels share the Clock (CLK) signal. Data is clocked into the input registers on the rising edge of CLK. Figure 9 illustrates the specific timing requirements that must be met in order for the data transfer to be accomplished properly. The input pins of the AD1865 are both TTL and 5 V CMOS compatible. The minimum clock rate of the AD1865 is at least 13.5 MHz. This clock rate allows data transfer rates of 2×, 4×, 8× and 16 × FS (where FS equals 44.1 kHz). O Figure 8 illustrates the general signal requirements for data transfer for the AD1865. >74.1ns >30ns >30ns CLK >40ns >40ns >15ns >40ns LL/LR >15ns >15ns DL/DR >30ns MSB 1st BIT INTERNAL DAC INPUT REGISTER UPDATED WITH 18 MOST RECENT BITS 2nd BIT LSB 18th BIT NEXT WORD BITS CLOCKED TO SHIFT REGISTER Figure 9. AD1865 Timing Diagram REV. 0 –7– AD1865 –5V ANALOG SUPPLY AD1865 28 1 –VS +VS 24 2 27 2 TRIM TRIM 23 3 BCKO 26 3 MSB MSB 22 4 WCKO 25 4 IOUT IOUT 21 5 DOL 24 5 AGND 6 DOR 23 6 SJ SJ 19 7 VDD 22 7 RF VSS2 21 8 VOUT 8 9 VSS1 DG 10 11 12 OW18 13 OW20 14 C1 AGND 20 1 +VS 8 RF 18 2 7 VOUT 17 3 6 NC 16 4 20 9 19 10 DR DL 15 18 11 LR LL 14 17 12 CLK +VL RIGHT CHANNEL OUTPUT 5 –VS NE5532 DGND 13 16 15 +5V DIGITAL SUPPLY LEFT CHANNEL OUTPUT C2 LE 1 TE SM5813AP/ APT +5V ANALOG SUPPLY Figure 10. Complete 8 × FS 18-Bit CD Player 18-BIT CD PLAYER DESIGN An NE5532 dual op amp is used to provide the output antialias filters required for adequate image rejection. One 2-pole filter section is provided for each channel. An additional pole is created from the combination of the internal feedback resistors (RF) and the external capacitors C1 and C2. For example, the nominal 3 kΩ RF with a 360 pF capacitor for C1 and C2 will place a pole at approximately 147 kHz, effectively eliminating all high frequency noise components. B SO Figure 10 illustrates an 18-bit CD player design incorporating an AD1865 D/A converter, an NE5532 dual op amp and the SM5813 digital filter chip manufactured by NPC. In this design, the SM5813 filter transmits left and right digital data to both channels of the AD1865. The left and right latch signals, LL and LR, are both provided by the word clock signal (WCKO) of the digital filter. The digital filter supplies data at an 8 × FS oversample rate to each channel. Low distortion, superior channel separation, low power consumption and a low parts count are all realized by this simple design. O The digital data is converted to analog output voltages by the output amplifiers on the AD1865. Note that no external components are required by the AD1865. Also, no deglitching circuitry is required. –8– REV. 0 AD1865 Figure 11 illustrates how to cascade AD1865’s to add multiple voices to an electronic musical instrument. In this example, the data and clock signals are shared between all six DACs. As the data representing an output for a specific voice is loaded, the appropriate DAC is updated. For example, after the 18-bits representing the next output value for Voice 4 is clocked out on the data line, then “Voice 4 Load” is pulled low. This produces a new output for Voice 4. Furthermore, all voices can be returned to the same output by pulling all six load signals low. VOICE 2 OUTPUT VOICE 1 OUTPUT VOICE 3 OUTPUT VOICE 4 OUTPUT +5V ANALOG SUPPLY –5V ANALOG SUPPLY AD1865 AD1865 2 ANALOG COMMON TRIM MSB 22 IOUT 21 5 AGND AGND 20 6 SJ 19 RF 18 –V S 2 TRIM VOUT VOUT NC 24 1 TRIM 23 3 MSB MSB 22 21 4 IOUT IOUT AGND 20 5 AGND SJ 19 6 SJ RF 18 7 RF MSB IOUT IOUT 5 AGND RF 24 TRIM 4 7 +V S 2 3 SJ –VS 23 TRIM MSB 22 6 AGND 20 SJ 19 RF 18 8 VOUT +VL NC 16 9 +VL NC 16 17 VOUT 16 9 VOUT 17 10 DR DL 15 10 DR DL 15 10 DR DL 15 11 LR LL 14 11 LR LL 14 11 LR LL 14 DGND 13 12 CLK DGND 13 12 CLK DGND VOICE 6 LOAD 13 VOICE 5 LOAD VOICE 4 LOAD DIGITAL COMMON +5V DIGITAL SUPPLY Figure 11. Cascaded AD1865s in a Multichannel Keyboard Instrument REV. 0 21 VOUT 17 8 VOICE 6 OUTPUT AD1865 +V S O CLOCK SJ 1 B SO RF 12 CLK DATA 23 IOUT 9 +VL VOICE 2 LOAD TRIM 4 8 VOICE 3 LOAD 24 3 MSB 7 VOICE 1 LOAD +VS VOICE 5 OUTPUT LE 1 –V S TE In this application, the advantages of choosing the AD1865 are clear. Its flexible digital interface allows the clock and data to be shared among all DACs. This reduces PC board area requirements and also simplifies the actual layout of the board. The low power requirements of the AD1865 (approximately 225 mW) is an advantage in a multiple DAC system where any power advantage is multiplied by the number of DACs used. The AD1865 requires no external components, simplifying the design, reducing the total number of components required and enhancing reliability. MULTICHANNEL DIGITAL KEYBOARD DESIGN –9– AD1865 ADDITIONAL APPLICATIONS –5V ANALOG SUPPLY Figures 12 through 14 show connection diagrams for the AD1865 and standard digital filter chips from Yamaha, NPC and Sony. Each figure is an example of cophase operation operating at 8 × FS for each channel. The 2-pole Rauch low-pass filters shown in Figure 10 can be used with all of the applications shown in this data sheet. +5V ANALOG SUPPLY AD1865 1 +VS 24 –V S 2 TRIM 3 MSB 2 3 4 V DD2 TEST 39 3 TEST 38 4 TEST 37 5 36 1 –V S 24 35 2 TRIM TRIM 23 34 3 MSB MSB 22 8 BCKO 33 4 IOUT 9 XIN DATAL 32 10 V DD 11 VDD GND 31 6 SJ SJ 19 GND 30 7 R RF 18 12 28 8 V OUT 9 +VL 14 LE/WS 27 10 DR 15 OUT 16/18 26 11 LR 16 25 17 LFS IOUT 21 AGND 20 F V DL 15 6 WCO 11 11 LR 12 CLK LL 14 DLO DGND 13 12 CLK DRO 10 9 OUT 17 RIGHT CHANNEL OUTPUT LPF LEFT CHANNEL OUTPUT B SO DATAR 29 13 5 AGND LPF NC 16 DL 15 LL 14 DGND 13 DPOL 24 18 SONY/12S 23 19 TEST 22 20 TEST TEST 21 –5V ANALOG SUPPLY +5V ANALOG SUPPLY AD1865 1 –V S +5V DIGITAL SUPPLY 2 TRIM Figure 13. AD1865 with Sony CXD1244s Digital Filter O 16.9344 MHz CXD1244S NC 16 L Figure 12. AD1865 with Yamaha YM3434 Digital Filter S 7 6 +V +5V DIGITAL SUPPLY AD1865 +V VOUT 9 10 DR +5V ANALOG SUPPLY –5V ANALOG SUPPLY 8 13 SS LEFT CHANNEL OUTPUT VOUT 17 ST 14 V LPF TE TEST 40 TEST RF 18 LE GND 2 SJ 19 BCO 12 8 V DD1 1 SJ 5 7 OUT AGND 20 7 R F 6 SHR 16 16/18 15 21 I 5 AGND YM3434 SHL RIGHT CHANNEL OUTPUT MSB 22 4 IOUT 1 LPF 23 TRIM 3 MSB SM5818 4 IOUT 5 AGND 1 VDD 16 6 SJ 2 BCKO 15 7 RF 8 VOUT +VS 24 TRIM 23 RIGHT CHANNEL OUTPUT LPF LEFT CHANNEL OUTPUT MSB 22 IOUT 21 AGND 20 SJ 19 RF 18 VOUT 17 3 WDCO 14 4 OMOD2 13 9 +VL NC 16 5 DOR 12 10 DR DL 15 6 DOL 11 11 LR 7 10 12 CLK LPF LL 14 DGND 13 8 VSS OMOD1 9 +5V DIGITAL SUPPLY Figure 14. AD1865 with NPC SM5818AP Digital Filter –10– REV. 0 AD1865 OTHER DIGITAL AUDIO COMPONENTS AVAILABLE FROM ANALOG DEVICES 1 DGND 2 +VL 3 NC 4 CLK 5 LE 6 DATA 7 –VL 8 16-BIT LATCH 16-BIT DAC AD1856 16-BIT AUDIO DAC 16 +VS 15 TRIM SERIAL INPUT REGISTER 14 MSB ADJ IOUT REF CONTROL LOGIC 13 IOUT Complete, No External Components Required 0.0025% THD Low Cost 16-Pin DIP or SOIC Package Standard Pinout 12 AGND 11 SJ 10 RF AD1856 9 VOUT TE –VS NC = NO CONNECT 1 DGND 2 +VL 3 NC 4 CLK 5 LE 6 DATA 7 8 18-BIT DAC AD1860 18-BIT AUDIO DAC 16 +VS 15 TRIM SERIAL INPUT REGISTER 14 MSB ADJ IOUT REF CONTROL LOGIC Complete, No External Components Required 0.0025% THD+N 108 dB Signal-to-Noise Ratio 16-Pin DIP or SOIC Package Standard Pinout 13 IOUT 12 AGND 11 SJ 10 RF AD1860 9 VOUT B SO –VL 18-BIT LATCH LE –VS NC = NO CONNECT AD1862 20-BIT AUDIO DAC –VS 1 –VS 2 15 NR2 TRIM 3 14 ADJ +VL 4 13 NR1 CLK 5 6 REV. 0 DATA 7 –VL 8 VL 1 LL 2 DL 3 CLK 4 DR 5 LR 6 DGND 7 VBIAS R 8 16 +VS 119 dB Signal-to-Noise Ratio 0.0016% THD+N 102 dB D-Range Performance ± 1 dB Gain Linearity 16-Pin DIP Package 12 AGND INPUT & DIGITAL OFFSET 20-BIT DAC O LE VOLTAGE REFERENCE 10 RF AD1862 18-BIT DAC 9 VREF 18-BIT DAC DGND AD1868 18-BIT SERIAL REGISTER 18-BIT SERIAL REGISTER 11 IOUT VREF 16 VBIAS L 15 VS 14 VOUT L 13 NRL 12 AGND 11 NRR 10 VOUT R 9 AD1868 +5 V SINGLE SUPPLY DUAL 18-BIT AUDIO DAC No External Components Required 0.004% THD+N 92 dB D-Range Performance ± 3 dB Gain Linearity 16-Pin DIP or SOIC Package VS –11– AD1865 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24 C1468–8–8/91 24-Pin Plastic DIP (N-24A) Package 13 0.580 (14.73) 0.485 (12.32) PIN 1 1 12 1.290 (32.70) 1.150 (29.30) 0.200 (5.05) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.015 (0.381) 0.008 (0.204) 0.150 (3.81) 0.070 (1.77) 0.030 (0.77) 0.100 (2.54) BSC LE 0.022 (0.558) 0.014 (0.356) TE 0.250 (6.35) SEATING PLANE 0.625 (15.87) 0.600 (15.24) 0.060 (1.52) 0.015 (0.38) 28-Pin SOIC (R-28) Package 0.708 (18.02) 0.696 (17.67) 15 28 B SO 0.299 (7.6) 0.291 (7.39) 0.414 (10.52) 0.398 (10.10) 14 1 0.003 (0.76) 0.02 (0.51) 0.096 (2.44) 0.089 (2.26) 0.019 (0.49) 0.014 (0.35) 0.01 (0.254) 0.006 (0.15) 0.013 (0.32) 0.009 (0.23) 0.042 (0.32) 0.009 (0.23) 6° 0° PRINTED IN U.S.A. O 0.050 (1.27) BSC –12– REV. 0