PROCESS CP555 Small Signal Transistor PNP - Saturated Switch Transistor Chip PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 15 x 10 MILS Die Thickness 8.0 MILS Base Bonding Pad Area 3.6 x 2.4 MILS Emitter Bonding Pad Area 3.6 x 2.4 MILS Top Side Metalization Al - 20,000Å Back Side Metalization Au - 15,000Å GEOMETRY GROSS DIE PER 4 INCH WAFER 76,000 PRINCIPAL DEVICE TYPES CMPT3640 CMPT4209 2N4209 BACKSIDE COLLECTOR R4 (22-March 2010) w w w. c e n t r a l s e m i . c o m PROCESS CP555 Typical Electrical Characteristics R4 (22-March 2010) w w w. c e n t r a l s e m i . c o m