CAT93C86B 16-Kb Microwire Serial EEPROM Description The CAT93C86B is a 16−Kb Serial EEPROM memory device which is configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C86B features a self−timed internal write with auto−clear. On−chip Power−On Reset circuit protects the internal logic against powering up in the wrong state. Features • • • • • • • • • • • • • • High Speed Operation: 4 MHz (5 V), 2 MHz (1.8 V) 1.8 V (1.65 V*) to 5.5 V Supply Voltage Range Selectable x8 or x16 Memory Organization Self−timed Write Cycle with Auto−clear Sequential Read Hardware and Software Write Protection Power−up Inadvertent Write Protection Low Power CMOS Technology Program Enable (PE) Pin 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial and Extended Temperature Ranges 8−pin PDIP, SOIC, MSOP, TSSOP, 8−pad UDFN, and WLCSP 6−ball Packages This Device is Pb−Free, Halogen Free/BFR Free, and RoHS Compliant† http://onsemi.com MSOP−8 Z SUFFIX CASE 846AD SOIC−8 X SUFFIX CASE 751BE WLCSP−6 C6A SUFFIX PRELIMINARY PDIP−8 L SUFFIX CASE 646AA TSSOP−8 Y SUFFIX CASE 948AL CS 1 SK DI DO Pin 1 1 A VCC VCC PE ORG GND PDIP (L), SOIC (V, X), TSSOP (Y), UDFN (HU4), MSOP (Z) B SK DI C GND DO PIN FUNCTION Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC Power Supply GND GND Ground Figure 1. Functional Symbol ORG Memory Organization ORG DI CAT93C86B 2 CS WLCSP*, ** (C6A) *ORG internally connected to GND **PE float Pin Name SK SOIC−8 V SUFFIX CASE 751BD PIN CONFIGURATION VCC CS UDFN−8 HU4 SUFFIX CASE 517AZ DO PE PE *CAT93C86Bxx−xxL (TA = −205C to +855C) †For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Program Enable Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pull−up device will select the x16 organization. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. © Semiconductor Components Industries, LLC, 2013 September, 2013 − Rev. 3 1 Publication Order Number: CAT93C86B/D CAT93C86B Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature −65 to +150 °C Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter NEND (Note 3) TDR Endurance Min Units 1,000,000 Program / Erase Cycles 100 Years Data Retention 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Block Mode, VCC = 5 V, 25°C. Table 3. D.C. OPERATING CHARACTERISTICS (VCC = +1.8 V to +5.5 V, TA = −40°C to +125°C, VCC = +1.65 V to +5.5 V, TA = −20°C to +85°C unless otherwise specified.) Symbol Parameter ICC1 Supply Current (Write) Write, VCC = 5.0 V ICC2 Supply Current (Read) Read, DO open, fSK = 2 MHz, VCC = 5.0 V ISB1 Standby Current (x8 Mode) VIN = GND or VCC CS = GND, ORG = GND TA = −40°C to +85°C TA = −40°C to +125°C 5 Standby Current (x16 Mode) VIN = GND or VCC CS = GND, ORG = Float or VCC TA = −40°C to +85°C 1 TA = −40°C to +125°C 3 VIN = GND to VCC TA = −40°C to +85°C 1 TA = −40°C to +125°C 2 TA = −40°C to +85°C 1 TA = −40°C to +125°C 2 ISB2 ILI ILO Input Leakage Current Test Conditions Min Output Leakage Current VOUT = GND to VCC CS = GND VIL1 Input Low Voltage 4.5 V ≤ VCC < 5.5 V −0.1 VIH1 Input High Voltage 4.5 V ≤ VCC < 5.5 V VIL2 Input Low Voltage 1.65 V ≤ VCC < 4.5 V VIH2 Input High Voltage 1.65 V ≤ VCC < 4.5 V VOL1 Output Low Voltage 4.5 V ≤ VCC < 5.5 V, IOL = 3 mA VOH1 Output High Voltage 4.5 V ≤ VCC < 5.5 V, IOH = −400 mA VOL2 Output Low Voltage 1.65 V ≤ VCC < 4.5 V, IOL = 1 mA VOH2 Output High Voltage 1.65 V ≤ VCC < 4.5 V, IOH = −100 mA Max Units 2 mA 500 mA 2 mA mA mA mA 0.8 V 2 VCC + 1 V 0 VCC x 0.2 V VCC x 0.7 VCC + 1 V 0.4 V 2.4 V 0.2 VCC − 0.2 V V Table 4. PIN CAPACITANCE (Note 4) Symbol COUT CIN Test Conditions Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG) Min Typ Max Units VOUT = 0 V 5 pF VIN = 0 V 5 pF Table 5. POWER−UP TIMING (Notes 4, 5) Symbol Parameter Max Units tPUR Power−up to Read Operation 1 ms tPUW Power−up to Write Operation 1 ms http://onsemi.com 2 CAT93C86B Table 6. A.C. TEST CONDITIONS Input Rise and Fall Times ≤ 50 ns Input Pulse Voltages 0.4 V to 2.4 V 4.5 V ≤ VCC ≤ 5.5 V Timing Reference Voltages 0.8 V, 2.0 V 4.5 V ≤ VCC ≤ 5.5 V Input Pulse Voltages 0.2 VCC to 0.7 VCC 1.65 V ≤ VCC ≤ 4.5 V Timing Reference Voltages 0.5 VCC 1.65 V ≤ VCC ≤ 4.5 V Output Load Current Source IOLmax/IOHmax; CL = 100 pF 4. These parameters are tested initially and after a design or process change that affects the parameter. 5. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Table 7. A.C. CHARACTERISTICS (VCC = +1.8 V to +5.5 V, TA = −40°C to +125°C, VCC = +1.65 V to +5.5 V, TA = −20°C to +85°C unless otherwise specified.) VCC < 4.5 V Symbol Min Parameter VCC > 4.5 V Max Min Max Units tCSS CS Setup Time 50 50 ns tCSH CS Hold Time 0 0 ns tDIS DI Setup Time 100 50 ns tDIH DI Hold Time 100 50 ns tPD1 Output Delay to 1 0.25 0.1 ms tPD0 Output Delay to 0 0.25 0.1 ms Output Delay to High−Z 100 100 ns 5 5 ms tHZ (Note 6) tEW Program/Erase Pulse Width tCSMIN Minimum CS Low Time 0.25 0.1 ms tSKHI Minimum SK High Time 0.25 0.1 ms tSKLOW Minimum SK Low Time 0.25 0.1 ms tSV Output Delay to Status Valid SKMAX Maximum Clock Frequency 0.25 DC 2000 DC 0.1 ms 4000 kHz 6. This parameter is tested initially and after a design or process change that affects the parameter. Table 8. INSTRUCTION SET Address Data Instruction Start Bit Opcode x8 x16 READ 1 10 A10−A0 A9−A0 ERASE 1 11 A10−A0 A9−A0 WRITE 1 01 A10−A0 A9−A0 EWEN 1 00 11XXXXXXXXX 11XXXXXXXX Write Enable EWDS 1 00 00XXXXXXXXX 00XXXXXXXX Write Disable ERAL* 1 00 10XXXXXXXXX 10XXXXXXXX Clear All Addresses WRAL* 1 00 01XXXXXXXXX 01XXXXXXXX *Not available at VCC < 1.8 V http://onsemi.com 3 x8 x16 Comments Read Address AN– A0 Clear Address AN– A0 D7−D0 D7−D0 D15−D0 D15−D0 Write Address AN– A0 Write All Addresses CAT93C86B Device Operation The CAT93C86B is a 16,384−bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C86B can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 13−bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 14−bit instructions control the reading, writing and erase operations of the device. The CAT93C86B operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical “1” start bit, a 2−bit (or 4−bit) opcode, 10−bit address (an additional bit when organized X8) and for write operations a 16−bit data field (8−bit for X8 organizations). Note: The Write, Erase, Write all and Erase all instructions require PE = 1. If PE is left floating, 93C86B is in Program Enabled mode. For Write Enable and Write Disable instruction PE = don’t care. Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C86B will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). After the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86B can be determined by selecting the device and polling the DO pin. Since this device features Auto−Clear before write, it is NOT necessary to erase a memory location before it is written into. http://onsemi.com 4 CAT93C86B tSKHI tSKLOW tCSH SK tDIS tDIH VALID DI VALID tCSS CS tPD0, tPD1 tDIS DO tCSMIN DATA VALID Figure 2. Synchronous Data Timing SK 1 1 1 1 1 AN AN−1 1 1 1 1 1 1 1 1 1 1 CS DI 1 1 Don’t Care A0 0 HIGH−Z DO Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D7 . . . D0 Address + 2 D15 . . . D0 or D7 . . . D0 Address + n D15 . . . or D7 . . . Figure 3. Read Instruction Timing SK tCSMIN CS AN AN−1 DI DO 1 0 A0 DN STATUS VERIFY D0 STANDBY 1 tSV HIGH−Z BUSY READY tEW Figure 4. Write Instruction Timing http://onsemi.com 5 tHZ HIGH−Z CAT93C86B Erase Erase All Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86B can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86B can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Erase/Write Enable and Disable Write All The CAT93C86B powers up in the write disable state. Any writing after power−up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C86B write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86B can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. SK CS AN DI DO 1 1 AN−1 A0 tCS STATUS VERIFY STANDBY 1 tSV HIGH−Z BUSY tEW Figure 5. Erase Instruction Timing http://onsemi.com 6 tHZ READY HIGH−Z CAT93C86B PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL MIN NOM A E1 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.25 E1 6.10 6.35 7.11 e PIN # 1 IDENTIFICATION MAX 2.54 BSC eB 7.87 L 2.92 10.92 3.30 3.80 D TOP VIEW E A2 A A1 c b2 L e eB b SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. http://onsemi.com 7 CAT93C86B PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 MAX 4.00 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 8 CAT93C86B PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL MIN NOM 2.03 A E1 E MAX A1 0.05 0.25 b 0.36 0.48 c 0.19 0.25 D 5.13 5.33 E 7.75 8.26 E1 5.13 5.38 1.27 BSC e L 0.51 0.76 θ 0º 8º PIN#1 IDENTIFICATION TOP VIEW D A e b q L A1 SIDE VIEW c END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. http://onsemi.com 9 CAT93C86B PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O b SYMBOL MIN NOM E1 E MAX 1.20 A A1 0.05 A2 0.80 b 0.19 0.30 c 0.09 0.20 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 0.15 0.90 e 0.65 BSC L 1.00 REF L1 0.50 θ 0º 0.60 1.05 0.75 8º e TOP VIEW D A2 c q1 A A1 L1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. http://onsemi.com 10 CAT93C86B PACKAGE DIMENSIONS UDFN8, 2x3 EXTENDED PAD CASE 517AZ−01 ISSUE O D b A e L DAP SIZE 1.8 x 1.8 E2 E PIN #1 IDENTIFICATION A1 PIN #1 INDEX AREA D2 TOP VIEW SIDE VIEW SYMBOL MIN NOM MAX A 0.45 0.50 0.55 A1 0.00 0.02 0.05 A3 0.127 REF b 0.20 0.25 0.30 D 1.95 2.00 2.05 D2 1.35 1.40 1.45 E 2.95 3.00 3.05 E2 1.25 1.30 1.35 e L BOTTOM VIEW DETAIL A 0.065 REF A3 A FRONT VIEW 0.50 REF 0.25 0.30 0.35 A3 Notes: (1) All dimensions are in millimeters. (2) Refer JEDEC MO-236/MO-252. 0.0 - 0.05 DETAIL A http://onsemi.com 11 0.065 REF Copper Exposed CAT93C86B PACKAGE DIMENSIONS MSOP 8, 3x3 CASE 846AD−01 ISSUE O MIN NOM A1 0.05 0.10 0.15 A2 0.75 0.85 0.95 b 0.22 0.38 c 0.13 0.23 D 2.90 3.00 3.10 E 4.80 4.90 5.00 E1 2.90 3.00 3.10 SYMBOL MAX 1.10 A E E1 0.65 BSC e L 0.60 0.40 0.80 L1 0.95 REF L2 0.25 BSC θ 0º 6º TOP VIEW D A A2 A1 DETAIL A e b c SIDE VIEW END VIEW q L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. L L1 DETAIL A http://onsemi.com 12 CAT93C86B PACKAGE DIMENSIONS WLCSP 6, 0.96 x 1.17 CASE TBD ISSUE O http://onsemi.com 13 CAT93C86B ORDERING INFORMATION Specific Device Marking Package Type Temperature Range Lead Finish Shipping CAT93C86BLI−G 93C86D PDIP−8 I = Industrial (−40°C to +85°C) NiPdAu Tube, 50 Units / Tube CAT93C86BLE−G 93C86D PDIP−8 E = Extended (−40°C to +125°C) NiPdAu Tube, 50 Units / Tube CAT93C86BVI−GT3 93C86D SOIC−8, JEDEC I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C86BVI−GT3L 93C86D SOIC−8, JEDEC I = Industrial −20°C to +85°C NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C86BVE−GT3 93C86D SOIC−8, JEDEC E = Extended (−40°C to +125°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C86BYI−GT3 M86D TSSOP−8 I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C86BYI−GT3L M86D TSSOP−8 I = Industrial (−20°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C86BYE−GT3 M86D TSSOP−8 E = Extended (−40°C to +125°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C86BHU4I−GT3 M4U UDFN−8 I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C86BHU4E−GT3 M4U UDFN−8 E = Extended (−40°C to +125°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C86BC6ATR (Note 9) M4 WLCSP−6 I = Industrial (−40°C to +85°C) SnAgCu Tape & Reel, 5,000 Units / Reel CAT93C86BZI−GT3 M4 MSOP−8 I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C86BZE−GT3 M4 MSOP−8 E = Extended (−40°C to +125°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT93C86BXI−T2 93C86D SOIC−8, EIAJ I = Industrial (−40°C to +85°C) Matte−Tin Tape & Reel, 2,000 Units / Reel CAT93C86BXE−T2 93C86D SOIC−8, EIAJ E = Extended (−40°C to +125°C) Matte−Tin Tape & Reel, 2,000 Units / Reel Order Number 7. All packages are RoHS−compliant (Lead−free, Halogen−free). 8. The standard lead finish is NiPdAu. 9. Preliminary. Please contact factory for availability. 10. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 11. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 12. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 14 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CAT93C86B/D