PSoC® 4: PSoC 4200D Family
Datasheet
®
Programmable System-on-Chip (PSoC )
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The
PSoC 4200D product family, based on this platform architecture, is a combination of a microcontroller with digital programmable logic,
programmable interconnect, and standard communication and timing peripherals. The PSoC 4200D products will be fully compatible
with members of the PSoC 4 platform for new applications and design needs. The programmable digital subsystem allows flexibility
and in-field tuning of the design.
Features
32-bit MCU Subsystem
Packages
■
48 MHz ARM Cortex-M0 CPU with single-cycle multiply
■
Up to 64 kB of flash with Read Accelerator
■
Up to 8 kB of SRAM
■
DMA engine
Programmable Digital
25-ball CSP package 2.07 mm × 2.11 mm, 28-SSOP package.
■
Up to 21 programmable GPIOs
■
GPIO drive modes, strengths, and slew rates are programmable
PSoC Creator Design Environment
■
Four programmable logic blocks, each with 8 Macrocells and
an 8-bit data path (called universal digital blocks or UDBs)
■
Programmable I/O block (PRGIO) provides the ability to
perform Boolean functions in the I/O signal path
■
Cypress-provided peripheral component library, user-defined
state machines, and Verilog input
Low Power 1.71 to 5.5 V Operation
■
■
Low-power Deep Sleep Mode with GPIO pin wakeup
■
Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
■
Applications Programming Interface (API component) for all
fixed-function and programmable peripherals
Industry-Standard Tool Compatibility
■
After schematic entry, development can be done with
ARM-based industry-standard development tools
Serial Communication
■
Three independent run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, or UART
functionality
Timing and Pulse-Width Modulation
■
Four 16-bit timer/counter pulse-width modulator (TCPWM)
blocks
■
Center-aligned, Edge, and Pseudo-random modes
■
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Cypress Semiconductor Corporation
Document Number: 001-98044 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 1, 2017
PSoC® 4: PSoC 4200D Family
Datasheet
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4:
■
■
■
Overview: PSoC Portfolio, PSoC Roadmap
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 4 are:
❐ AN79953: Getting Started With PSoC 4
❐ AN88619: PSoC 4 Hardware Design Considerations
❐ AN86439: Using PSoC 4 GPIO Pins
❐ AN57821: Mixed Signal Circuit Board Layout
❐ AN81623: Digital Design Best Practices
❐ AN73854: Introduction To Bootloaders
❐ AN89610: ARM Cortex Code Optimization
■
Technical Reference Manual (TRM) is in two documents:
❐ Architecture TRM details each PSoC 4 functional block.
❐ Registers TRM describes each of the PSoC 4 registers.
Development Kits:
❐ CY8CKIT-042, PSoC 4 Pioneer Kit, is an easy-to-use and
inexpensive development platform. This kit includes
connectors for Arduino™ compatible shields and Digilent®
Pmod™ daughter cards.
❐ CY8CKIT-049 is a very low-cost prototyping platform. It is a
low-cost alternative to sampling PSoC 4 devices.
❐ CY8CKIT-001 is a common development platform for any
one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP families
of devices.
The MiniProg3 device provides an interface for flash
programming and debug.
■
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
3. Configure components using the configuration tools
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator
1
2
3
4
5
Document Number: 001-98044 Rev. *C
Page 2 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Contents
PSoC 4200D Block Diagram ............................................ 4
Functional Definition........................................................ 5
CPU and Memory Subsystem ..................................... 5
System Resources ...................................................... 5
Analog Block ............................................................... 6
Programmable Digital.................................................. 6
Fixed Function Digital.................................................. 7
GPIO ........................................................................... 7
Pinouts .............................................................................. 8
Power................................................................................. 9
Unregulated External Supply....................................... 9
Regulated External Supply.......................................... 9
Development Support ...................................................... 9
Documentation ............................................................ 9
Online .......................................................................... 9
Tools............................................................................ 9
Electrical Specifications ................................................ 10
Absolute Maximum Ratings ...................................... 10
Device Level Specifications....................................... 10
Document Number: 001-98044 Rev. *C
Analog Peripherals ....................................................
Digital Peripherals .....................................................
Memory .....................................................................
System Resources ....................................................
Ordering Information......................................................
Part Numbering Conventions ....................................
Packaging........................................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Revision History .............................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support.............................................................
13
14
16
16
19
20
21
23
25
25
26
27
27
27
27
27
27
Page 3 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
PSoC 4200D Block Diagram
CPU Subsystem
SW D/ TC
SPCIF
Cortex
M0
32-bit
FLASH
64 KB
48 MHz
FAST MUL
NVIC, IRQM UX
AHB - Lite
System Resources
Lite
Test
TestM ode Entry
Digital DFT
Analog DFT
ROM Controller
Initiator / MM IO
Peripheral Interconnect (MMIO)
PCLK
Programmable
Digital
UDB
...
UDB
x4
2x LP Comparator
Reset
Reset Control
XRES
DataW ire /
DMA
Peripherals
3x SCB-I2C/SPI/UART
Clock
Clock Control
W DT
ILO
IMO
SRAM Controller
ROM
8 KB
System Interconnect (Single Layer AHB)
IOSS GPIO (4x ports)
Power
Sleep Control
W IC
POR
REF
PW RSYS
SRAM
8 KB
Read Accelerator
4x TCPWM
PSoC 4200D
M0S8
Architecture
Port Interface & Digital System Interconnect ( DSI)
High Speed I / O M atrix & 1x Programm able I/O
Power M odes
Active/ Sleep
DeepSleep
21 x GPIOs
I/O Subsystem
The PSoC 4200D devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial_Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator Integrated Development Environment (IDE)
provides fully integrated programming and debug support for
PSoC 4200D devices. The SWD interface is fully compatible with
industry-standard third-party tools. The PSoC 4200D family
provides a level of security not possible with multi-chip application solutions or with microcontrollers. This is due to its ability
to disable debug features, robust flash protection, and because
Document Number: 001-98044 Rev. *C
it allows customer-proprietary functionality to be implemented in
on-chip programmable blocks.
The debug circuits are enabled by default and can only be
disabled in firmware. If not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. Because all programming, debug, and test interfaces are disabled when maximum device security is enabled,
PSoC 4200D with device security enabled may not be returned
for failure analysis. This is a trade-off the PSoC 4200D allows the
customer to make.
Page 4 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in the PSoC 4200D is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. Most instructions are 16 bits in length and
execute a subset of the Thumb-2 instruction set. The Cypress
implementation includes a hardware multiplier that provides a
32-bit result in one cycle. It includes a nested vectored interrupt
controller (NVIC) block with 32 interrupt inputs and also includes
a Wakeup Interrupt Controller (WIC), which can wake the
processor up from the Deep Sleep mode allowing power to be
switched off to the main processor when the chip is in the Deep
Sleep mode. The Cortex-M0 CPU provides a Non-Maskable
Interrupt (NMI) input, which is made available to the user when
it is not in use for system functions requested by the user.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a 2-wire form of JTAG; the debug
configuration used for PSoC 4200D has four break-point
(address) comparators and two watchpoint (data) comparators.
Clock System
The PSoC 4200D clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that no meta-stable conditions occur.
The clock system for the PSoC 4200D consists of the IMO (3 to
48 MHz) and the ILO (40-kHz nominal) internal oscillators, and
provision for an external clock.
Figure 2. PSoC 4200D MCU Clocking Architecture
IMO
clk_hf
clk_ext
dsi_in[0]
dsi_in[1]
dsi_in[2]
dsi_in[3]
dsi_out[3:0]
Flash
The PSoC 4200D has a flash module with a flash accelerator,
tightly coupled to the CPU to improve average access times from
the flash block. The flash accelerator delivers 85% of
single-cycle SRAM access performance on average. Part of the
flash module can be used to emulate EEPROM operation if
required.
ILO
clk_lf
SROM
The clk_hf signal can be divided down to generate synchronous
clocks for the UDBs, and the analog and digital peripherals.
There are a total of six clock dividers for the PSoC 4200D, each
with 16-bit divide capability, two of which support fractional
baud-rate generation. The 16-bit capability allows a lot of flexibility in generating fine-grained frequency values and is fully
supported in PSoC Creator.
A supervisory ROM that contains boot and configuration routines
is provided.
IMO Clock Source
SRAM
8K of SRAM memory is provided.
DMA
A DMA engine, with eight channels, is provided that can do 32-bit
transfers and has chainable ping-pong descriptors.
System Resources
Power System
The power system is described in detail in the section Power on
page 10. It provides assurance that voltage levels are as
required for each respective mode and either delay mode entry
(on power-on reset (POR), for example) until voltage levels are
as required for proper function or generate resets (brown-out
detect (BOD)) or interrupts (low-voltage detect (LVD)). The
PSoC 4200D operates with a single external supply over the
range of 1.71 V to 5.5 V and has three different power modes,
transitions between which are managed by the power system.
The PSoC 4200D provides Active, Sleep, and Deep Sleep
modes.
Document Number: 001-98044 Rev. *C
The IMO is the primary source of internal clocking in the
PSoC 4200D. It is trimmed during testing to achieve the
specified accuracy. Trim values are stored in nonvolatile
memory. Trimming can also be done on the fly to allow in-field
calibration. The IMO default frequency is 24 MHz and it can be
adjusted between the range of 24 to 48 MHz. IMO tolerance with
Cypress-provided calibration settings is ±2%. An IMO
post-divider with possible divide values of 2, 4, or 8 can be used
to divide the clock down to 3 MHz if required.
ILO Clock Source
The ILO is a very low power oscillator, nominally 40 kHz, which
is primarily used to generate clocks for peripheral operation in
Deep Sleep mode. ILO-driven counters can be calibrated to the
IMO to improve accuracy. Cypress provides a software
component, which does the calibration.
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the low-frequency clock; this allows watchdog operation during
Deep Sleep and generates a watchdog reset or an interrupt if not
serviced before the timeout occurs. The watchdog reset is
recorded in the Reset Cause register.
Page 5 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Figure 3. UDB Array
Reset
AHB Bridge CPUSS
Dig CLKS
4 to 8
8 to 32
High -Speed I/O Matrix
The PSoC 4200D can be reset from a variety of sources
including a software reset. Reset events are asynchronous and
guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through reset and allows
software to determine the cause of the reset. An XRES pin is
reserved for external reset to avoid complications with configuration and multiple pin functions during power-on or reconfiguration.
UDBIF
BUS IF
Other Digital
Signals in Chip
Analog Block
Low-power Comparators
The PSoC 4200D has a pair of low-power comparators, with two
different power modes allowing trade-off of power versus
response time.
IRQ IF CLK IF
Port
IF IF
Port
Port
IF
DSI
DSI
UDB
UDB
UDB
UDB
Scalable array of
UDBs (max=16)
Routing
Channels
Programmable Digital
Universal Digital Blocks (UDBs) and Port Interfaces
The PSoC 4200D has four UDBs; the UDB array also provides
a switched Digital System Interconnect (DSI) fabric that allows
signals from peripherals and ports to be routed to and through
the UDBs for communication and control. The UDB array is
shown in the following figure.
DSI
DSI
Programmable Digital Subsystem
UDBs can be clocked from a clock divider block, from a port
interface (required for peripherals such as SPI), and from the DSI
network directly or after synchronization.
A port interface is defined, which acts as a register that can be
clocked with the same source as the PLDs inside the UDB array.
This allows faster operation because the inputs and outputs can
be registered at the port interface close to the I/O pins and at the
edge of the array. The port interface registers can be clocked by
one of the I/Os from the same port. This allows interfaces such
as SPI to operate at higher clock speeds by eliminating the delay
for the port input to be routed over DSI and used to register other
inputs. The port interface is shown in Figure 4.
The UDBs can generate interrupts (one UDB at a time) to the
interrupt controller. The UDBs retain the ability to connect to any
pin on the chip through the DSI.
Figure 4. Port Interface
High Speed I/O Matrix
To Clock
Tree
8
Input Registers
7
Digital
GlobalClocks
3 DSI Signals ,
1 I/O Signal
6
Clock Selector
Block from
UDB
0
...
2
0
3
2
1
0
[1]
4
8
[1]
[0]
To DSI
Document Number: 001-98044 Rev. *C
6
Enables
[1]
8
Reset Selector
Block from
UDB
7
[0]
2
4
Output Registers
...
9
4
8
8
From DSI
[1]
From DSI
Page 6 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Fixed Function Digital
Timer/Counter/PWM (TCPWM) Block
The TCPWM block uses a16-bit counter with user-programmable period length. There is a Capture register to record the
count value at the time of an event (which may be an I/O event),
a period register which is used to either stop or auto-reload the
counter when its count is equal to the period register, and
compare registers to generate compare value signals, which are
used as PWM duty cycle outputs. The block also provides true
and complementary outputs with programmable offset between
them to allow use as deadband programmable complementary
PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems
when an overcurrent state is indicated and the PWMs driving the
FETs need to be shut off immediately with no time for software
intervention. The PSoC 4200D has four TCPWM blocks.
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated. Note that
hardware handshaking is not supported. This is not commonly
used and can be implemented with a UDB-based UART in the
system, if required.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(essentially adds a start pulse used to synchronize SPI Codecs),
and National Microwire (half-duplex form of SPI). The SPI block
can use the FIFO to buffer transfers.
GPIO
The PSoC 4200D has 21 GPIOs in the 25-ball CSP package.
The GPIO block implements the following:
■
Eight drive strength modes including strong push-pull, resistive
pull-up and pull-down, weak (resistive) pull-up and pull-down,
open drain and open source, input only, and disabled
■
Input threshold select (CMOS or LVTTL)
■
Individual control of input and output disables
■
Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode)
■
Selectable slew rates for dV/dt related noise control to improve
EMI
Serial Communication Blocks (SCB)
The PSoC 4200D has three SCBs, which can each implement
an I2C, UART, or SPI interface.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multimaster
arbitration). This block is capable of operating at speeds of up to
1 Mbps (Fast Mode Plus) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
supports EzI2C that creates a mailbox address range in the
memory of the PSoC 4200D and effectively reduces I2C communication to reading from and writing to an array in memory. In
addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read
data, greatly reduces the need for clock stretching caused by the
CPU not having read data on time. The FIFO mode is available
in all channels and is very useful in the absence of DMA.
The I2C peripheral is compatible with the I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/O is implemented with GPIO in open-drain modes.
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
Document Number: 001-98044 Rev. *C
The pins are organized in logical entities called ports, which are
8-bit in width. During power-on and reset, the blocks are forced
to the disable state so as not to crowbar any inputs and/or cause
excess turn-on current. A multiplexing network known as a
high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin. Pin locations for
fixed-function peripherals are also fixed to reduce internal multiplexing complexity (these signals do not go through the DSI
network). DSI signals are not affected by this and any pin may
be routed to any UDB through the DSI network.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (4 for the PSoC 4200D).
Page 7 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Pinouts
The following is the pin list for the PSoC 4200D. Pins 16, 17, and 18 are No-Connects in the 28-SSOP package.
Table 1. PSoC 4200D Pin Description
28-Pin SSOP
25-Ball CSP
Alternate Functions for Pins
Name
Pin
Name
Analog
19
P0.0
E4
P0.0
lpcomp.in_p[0]
tcpwm.line[2]
scb[0].spi_select P0.0, LPC0, TCPWM2, SCB0
1
20
P0.1
E3
P0.1
lpcomp.in_n[0]
tcpwm.line_compl[
2]
scb[0].spi_select P0.1, LPC0, TCPWM2, SCB0
2
21
P0.2
D3
P0.2
22
P0.4
E2
P0.4
scb[1].uart_rx
scb[1].i2c_sc scb[1].spi_mosi
l
P0.4, SCB1
23
P0.5
C4
P0.5
scb[1].uart_tx
scb[1].i2c_sd scb[1].spi_miso
a
P0.5, SCB1
24
P0.6
C3
P0.6
25
XRES
D2
XRES
XRES
26
VCCD
E1
VCCD
Regulator Output
28
VSSD
D1
VSSD
Power Supply
27
VDDD
C1
VDDD
Ground
1
P1.0
C2
P1.0
tcpwm.line[2]
scb[0].uart_rx
scb[0].i2c_sc scb[0].spi_mosi
l
P1.0, TCPWM2, SCB0
2
P1.1
B2
P1.1
tcpwm.line_compl[
2]
scb[0].uart_tx
scb[0].i2c_sd scb[0].spi_miso
a
P1.1, TCPWM2, SCB0
3
P1.2
B1
P1.2
tcpwm.line[3]
scb[0].uart_cts
scb[0].spi_clk
P1.2, TCPWM3, SCB0
4
P1.3
A1
P1.3
tcpwm.line_compl[
3]
scb[0].uart_rts
scb[0].spi_select
0
P1.3, TCPWM3, SCB0
5
P2.2
B3
P2.2
prgio[0].io[2]
scb[2].uart_rx
scb[2].i2c_sc scb[2].spi_mosi
l
P2.2, PRG, SCB2
6
P2.3
A2
P2.3
prgio[0].io[3]
scb[2].uart_tx
scb[2].i2c_sd scb[2].spi_miso
a
P2.3, PRG. SCB2
7
P2.4
B4
P2.4
prgio[0].io[4]
tcpwm.line[0]
8
P2.5
A4
P2.5
prgio[0].io[5]
tcpwm.line_compl[
0]
9
P2.6
A3
P2.6
prgio[0].io[6]
tcpwm.line[1]
scb[2].spi_select P2.6, PRG, TCPWM1, SCB2
1
10
P2.7
A5
P2.7
prgio[0].io[7]
tcpwm.line_compl[
1]
scb[2].spi_select P2.7, PRG, TCPWM1, SCB2
2
Document Number: 001-98044 Rev. *C
PRGIO
Alt 1
Alt 2
Alt 3
tcpwm.line[3]
ext_clk
Alt 4
Pin Description
Pin
scb[0].spi_select
3
scb[1].uart_cts
scb[1].spi_clk
scb[2].uart_cts lpcomp.comp
[0]
scb[2].uart_rts
scb[2].spi_clk
P0.2, TCPWM3, SCB0
P0.6, Ext Clock, SCB1
P2.4, PRG, TCPWM0, SCB2,
LPC0
scb[2].spi_select P2.5, PRG, TCPWM0, SCB2
0
Page 8 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Table 1. PSoC 4200D Pin Description (continued)
28-Pin SSOP
25-Ball CSP
Pin
Name
Pin
Name
11
P3.0
D5
12
P3.1
13
Alternate Functions for Pins
Analog
PRGIO
Alt 3
Alt 4
Pin Description
Alt 1
Alt 2
P3.0
tcpwm.line[0]
scb[1].uart_rx
scb[1].i2c_sc scb[1].spi_mosi
l
P3.0, TCPWM0, SCB1
C5
P3.1
tcpwm.line_compl[
0]
scb[1].uart_tx
scb[1].i2c_sd scb[1].spi_miso
a
P3.1, TCPWM0, SCB1
P3.2
E5
P3.2
tcpwm.line[1]
scb[1].uart_cts
swd_data
scb[1].spi_clk
P3.2, TCPWM1, SCB1,
SWD_IO
14
P3.3
B5
P3.3
tcpwm.line_compl[
1]
scb[1].uart_rts
swd_clk
scb[1].spi_select
0
P3.3, TCPWM1, SCB1,
SWD_CLK
15
P3.4
D4
P3.4
scb[1].spi_select
1
P3.4, SCB1
Descriptions of the power pin functions are as follows:
VDDD: Power supply for the chip.
VSSD: Ground pin.
VCCD: Regulated digital supply (1.8 V ±5% if supplied externally).
Document Number: 001-98044 Rev. *C
Page 9 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Power
Development Support
The supply voltage range is 1.71 to 5.5 V with all functions and
circuits operating over that range.
The PSoC 4200D family has a rich set of documentation, development tools, and online resources to assist you during your
development process. Visit www.cypress.com/go/psoc4 to find
out more.
The PSoC 4200D family allows two distinct modes of power
supply operation: Unregulated External Supply and Regulated
External Supply modes.
Unregulated External Supply
In this mode, the PSoC 4200D is powered by an External Power
Supply that can be anywhere in the range of 1.8 to 5.5 V. This
range is also designed for battery-powered operation, for
instance, the chip can be powered from a battery system that
starts at 3.5V and works down to 1.8 V. In this mode, the internal
regulator of the PSoC 4200D supplies the internal logic and the
VCCD output of the PSoC 4200D must be bypassed to ground
via an external capacitor.
Bypass capacitors must be used from VDDD to ground, typical
practice for systems in this frequency range is to use a capacitor
in the 1 µF range in parallel with a smaller capacitor (0.1 µF, for
example). Note that these are simply rules of thumb and that, for
critical applications, the PCB layout, lead inductance, and the
Bypass capacitor parasitic should be simulated to design and
obtain optimal bypassing.
Power Supply
VDDD–VSS
VCCD–VSS
Typical Bypass Capacitors
0.1-µF ceramic at each pin plus bulk
capacitor 1 to 10 µF.
0.1-µF ceramic capacitor at the VCCD pin
Documentation
A suite of documentation supports the PSoC 4200D family to
ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using
PSoC Creator. The software user guide shows you how the
PSoC Creator build process works in detail, how to use source
control with PSoC Creator, and much more.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component data sheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Technical Reference Manual: The Technical Reference Manual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
Online
Regulated External Supply
In this mode, the PSoC 4200D is powered by an external power
supply that must be within the range of 1.71 to 1.89 V (1.8 ±5%);
note that this range needs to include power supply ripple. In this
mode, VCCD and VDDD pins are shorted together and
bypassed. The internal regulator should be disabled in firmware.
Document Number: 001-98044 Rev. *C
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
Tools
With industry standard cores, programming, and debugging
interfaces, the PSoC 4200D family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Page 10 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings[1]
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID1
VDD_ABS
Analog or digital supply relative to VSS
(VSSD = VSSA)
–0.5
–
6
V
Absolute maximum
SID2
VCCD_ABS
Direct digital core voltage input relative
to VSSD
–0.5
–
1.95
V
Absolute maximum
SID3
VGPIO_ABS
GPIO voltage; VDDD or VDDA
–0.5
–
VDD+0.
5
V
Absolute maximum
SID4
IGPIO_ABS
Current per GPIO
–25
–
25
mA
Absolute maximum
SID5
IG-PIO_injection
GPIO injection current per pin
–0.5
–
0.5
mA
Absolute maximum
BID44
ESD_HBM
Electrostatic discharge human body
model
2200
–
–
V
BID45
ESD_CDM
Electrostatic discharge charged device
model
500
–
–
V
BID46
LU
Pin current for latch-up
–140
–
140
mA
Device Level Specifications
All specifications are valid for -40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
Table 3. DC Specifications
Description
Min
Typ
Max
Units
Details / Conditions
SID53
Spec Id#
VDDD
Parameter
Power supply input voltage unregulated
1.8
–
5.5
V
With on-chip internal
regulator enabled
SID255
VDDD
Power supply input voltage externally
regulated
1.71
1.8
1.89
V
Externally regulated
within this range
SID54
VCCD
Output voltage (for core logic)
–
1.8
–
V
SID55
CEFC
External regulator voltage bypass
–
0.1
–
µF
X5R ceramic or
better
SID56
CEXC
Power supply decoupling capacitor
–
1
–
µF
X5R ceramic or
better
Active Mode
SID6
IDD1
Execute from flash; CPU at 6 MHz
–
2.1
2.85
mA
SID7
IDD2
Execute from flash; CPU at 12 MHz
–
3.6
4
mA
SID8
IDD3
Execute from flash; CPU at 24 MHz
–
5.3
6
mA
SID9
IDD4
Execute from flash; CPU at 48 MHz
–
9.8
13
mA
SID21
IDD16
I2C wakeup, WDT, and comparators on.
Regulator off.
–
1.45
1.65
mA
VDD = 1.71 to 1.89,
6 MHz
SID22
IDD17
I2C wakeup, WDT, and comparators on.
–
1.8
2.45
mA
VDD = 1.8 to 5.5,
6 MHz
SID23
IDD18
I2C wakeup, WDT, and comparators on.
Regulator off.
–
1.6
1.9
mA
VDD = 1.71 to 1.89,
12 MHz
Sleep Mode
Note
1. Usage above the absolute maximum conditions listed in Table 2 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 001-98044 Rev. *C
Page 11 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Table 3. DC Specifications (continued)
Spec Id#
SID24
Parameter
IDD19
Description
Min
Typ
Max
Units
I C wakeup, WDT, and comparators on.
–
2
2.7
mA
2
Details / Conditions
VDD = 1.8 to 5.5,
12 MHz
Deep Sleep Mode, -40 °C to + 60 °C (Guaranteed by characterization)
SID30
IDD25
I2C wakeup and WDT on. Regulator off.
–
2
15
µA
VDD = 1.71 to 1.89
SID31
IDD26
I2C wakeup and WDT on.
–
2
15
µA
VDD = 1.8 to 3.6
SID32
IDD27
I2C wakeup and WDT on.
–
2
15
µA
VDD = 3.6 to 5.5
Deep Sleep Mode, +85 °C (Guaranteed by characterization)
IDD28
I2C wakeup and WDT on. Regulator off.
–
4
45
µA
VDD = 1.71 to 1.89
SID34
IDD29
I2C
wakeup and WDT on.
–
4
45
µA
VDD = 1.8 to 3.6
SID35
IDD30
I2C wakeup and WDT on.
–
4
45
µA
VDD = 3.6 to 5.5
Supply current while XRES (Active Low)
asserted
–
2
5
mA
Min
Typ
Max
Units
SID33
XRES current
SID307
IDD_XR
Table 4. AC Specifications
Spec ID#
Parameter
Description
Details/
Conditions
SID48
FCPU
CPU frequency
DC
–
48
MHz
1.71 VDD 5.5
SID49
TSLEEP
Wakeup from sleep mode
–
0
–
µs
Guaranteed by
characterization
SID50
TDEEPSLEEP
Wakeup from Deep Sleep mode
–
–
35
µs
Guaranteed by
characterization
SID52
TRESETWIDTH
External reset pulse width
1
–
–
µs
Guaranteed by
characterization
GPIO
Table 5. GPIO DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
0.7 ×
VDDD
–
–
–
V
Details/
Conditions
CMOS Input
–
0.3 ×
VDDD
–
V
CMOS Input
SID57
VIH[2]
Input voltage high threshold
SID58
VIL
Input voltage low threshold
SID241
VIH[2]
LVTTL input, VDDD < 2.7 V
SID242
VIL
LVTTL input, VDDD < 2.7 V
0.7×
VDDD
–
SID243
VIH[2]
LVTTL input, VDDD 2.7 V
2.0
SID244
VIL
LVTTL input, VDDD 2.7 V
–
SID59
VOH
Output voltage high level
SID60
VOH
Output voltage high level
SID61
VOL
Output voltage low level
VDDD
–0.6
VDDD
–0.5
–
–
–
V
V
–
0.3 ×
VDDD
–
–
0.8
V
–
–
V
–
–
V
–
0.6
V
V
IOH = 4 mA at 3 V
VDDD
IOH = 1 mA at
1.8 V VDDD
IOL = 4 mA at
1.8 V VDDD
Note
2. VIH must not exceed VDDD + 0.2 V.
Document Number: 001-98044 Rev. *C
Page 12 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Table 5. GPIO DC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
SID62
VOL
Output voltage low level
–
–
0.6
V
SID62A
VOL
Output voltage low level
–
–
0.4
V
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
SID65
IIL
Input leakage current (absolute value)
–
–
2
nA
SID66
CIN
Input capacitance
–
–
7
pF
SID67
VHYSTTL
Input hysteresis LVTTL
25
40
–
mV
SID68
VHYSCMOS
Input hysteresis CMOS
–
–
mV
SID69
IDIODE
–
100
µA
SID69A
ITOT_GPIO
Current through protection diode to
VDD/Vss
Maximum Total Source or Sink Chip
Current
0.05 ×
VDDD
–
–
–
200
mA
Min
2
Typ
–
Max
12
Units
ns
Details/
Conditions
IOL = 8 mA at 3 V
VDDD
IOL = 3 mA at 3 V
VDDD
25 °C, VDDD =
3.0 V
VDDD 2.7 V
Guaranteed by
characterization
Guaranteed by
characterization
Table 6. GPIO AC Specifications
(Guaranteed by Characterization)[3]
Spec ID#
SID70
Parameter
TRISEF
Description
Rise time in fast strong mode
SID71
TFALLF
Fall time in fast strong mode
2
–
12
ns
SID72
TRISES
Rise time in slow strong mode
10
–
60
ns
SID73
TFALLS
Fall time in slow strong mode
10
–
60
ns
SID74
FGPIOUT1
GPIO Fout;3.3 V VDDD 5.5 V. Fast
strong mode.
–
–
33
MHz
SID75
FGPIOUT2
GPIO Fout;1.7 VVDDD3.3 V. Fast
strong mode.
–
–
16.7
MHz
SID76
FGPIOUT3
GPIO Fout;3.3 V VDDD 5.5 V. Slow
strong mode.
–
–
7
MHz
SID245
FGPIOUT4
GPIO Fout;1.7 V VDDD 3.3 V. Slow
strong mode.
–
–
3.5
MHz
SID246
FGPIOIN
GPIO input operating frequency;
1.71 V VDDD 5.5 V
–
–
48
MHz
Details/
Conditions
3.3 V VDDD,
Cload = 25 pF
3.3 V VDDD,
Cload = 25 pF
3.3 V VDDD,
Cload = 25 pF
3.3 V VDDD,
Cload = 25 pF
90/10%, 25 pF
load, 60/40 duty
cycle
90/10%, 25 pF
load, 60/40 duty
cycle
90/10%, 25 pF
load, 60/40 duty
cycle
90/10%, 25 pF
load, 60/40 duty
cycle
90/10% VIO
Note
3. Simultaneous switching transitions on many fully-loaded GPIO pins may cause ground perturbations depending on several factors including PCB and decoupling
capacitor design. For applications that are very sensitive to ground perturbations, the slower GPIO slew rate setting may be used.
Document Number: 001-98044 Rev. *C
Page 13 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
XRES
Table 7. XRES DC Specifications
Spec ID#
SID77
Parameter
VIH
Description
Input voltage high threshold
Min
0.7 ×
VDDD
–
Typ
–
Max
–
Units
V
SID78
VIL
Input voltage low threshold
–
V
3.5
5.6
0.3 ×
VDDD
8.5
SID79
RPULLUP
Pull-up resistor
SID80
CIN
Input capacitance
kΩ
–
3
–
pF
SID81
VHYSXRES
Input voltage hysteresis
–
100
–
mV
SID82
IDIODE
Current through protection diode to
VDDD/VSS
–
–
100
µA
Min
1
Typ
–
Max
–
Units
µs
Details/
Conditions
CMOS Input
CMOS Input
Guaranteed by
characterization
Guaranteed by
characterization
Table 8. XRES AC Specifications
Spec ID#
SID83
Parameter
TRESETWIDTH
Description
Reset pulse width
Details/
Conditions
Guaranteed by
characterization
Analog Peripherals
Comparator
Table 9. Comparator DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID85
VOFFSET2
Input offset voltage, Common Mode
voltage range from 0 to VDD-1
–
–
±4
mV
SID86
VHYST
Hysteresis when enabled, Common
Mode voltage range from 0 to VDD -1.
–
10
35
mV
Guaranteed by
characterization
SID87
VICM1
Input common mode voltage in normal
mode
0
–
VDDD – 0.1
V
Modes 1 and 2.
SID247
VICM2
Input common mode voltage in
low-power mode
0
–
VDDD
V
SID88
CMRR
Common mode rejection ratio
50
–
–
dB
VDDD 2.7 V.
Guaranteed by
characterization
SID88A
CMRR
Common mode rejection ratio
42
–
–
dB
VDDD 2.7 V.
Guaranteed by
characterization
SID89
ICMP1
Block current, normal mode
–
–
400
µA
Guaranteed by
characterization
SID248
ICMP2
Block current, low power mode
–
–
100
µA
Guaranteed by
characterization
SID90
ZCMP
DC input impedance of comparator
35
–
–
MΩ
Guaranteed by
characterization
Table 10. Comparator AC Specifications
(Guaranteed by Characterization)
Min
Typ
Max
Units
SID91
Spec ID#
TRESP1
Parameter
Response time, normal mode
Description
–
–
110
ns
50-mV overdrive
SID258
TRESP2
Response time, low power mode
–
–
200
ns
50-mV overdrive
Document Number: 001-98044 Rev. *C
Details/Conditions
Page 14 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripheral in timer mode.
Timer/Counter/PWM
Table 11. TCPWM Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
SID.TCPWM.1
ITCPWM1
Block current consumption at 3 MHz
–
–
45
µA
SID.TCPWM.2
ITCPWM2
Block current consumption at 12 MHz
–
–
155
µA
SID.TCPWM.2A ITCPWM3
Block current consumption at 48 MHz
–
–
650
µA
–
–
Fc
MHz
SID.TCPWM.3
TCPWMFREQ Operating frequency
SID.TCPWM.4
TPWMENEXT
Input Trigger Pulse Width for all
Trigger Events
2/Fc
–
–
ns
SID.TCPWM.5
TPWMEXT
Output Trigger Pulse widths
2/Fc
–
–
ns
SID.TCPWM.5A TCRES
Resolution of Counter
1/Fc
–
–
ns
SID.TCPWM.5B PWMRES
PWM Resolution
1/Fc
–
–
ns
SID.TCPWM.5C QRES
Quadrature inputs resolution
1/Fc
–
–
ns
Details/Conditions
All modes
(Timer/Counter/PWM)
All modes
(Timer/Counter/PWM)
All modes
(Timer/Counter/PWM)
Fc max = Fcpu.
Maximum = 48 MHz
Trigger Events can be
Stop, Start, Reload,
Count, Capture, or Kill
depending on which
mode of operation is
selected.
Minimum possible
width of Overflow,
Underflow, and CC
(Counter equals
Compare value)
trigger outputs
Minimum time
between successive
counts
Minimum pulse width
of PWM Output
Minimum pulse width
between Quadrature
phase inputs.
I2C
Table 12. Fixed I2C DC Specifications
(Guaranteed by Characterization)
Spec ID
SID149
Parameter
II2C1
Description
Block current consumption at 100 kHz
Min
–
Typ
–
Max
50
Units
µA
SID150
II2C2
Block current consumption at 400 kHz
–
–
135
µA
SID151
II2C3
Block current consumption at 1 Mbps
–
–
310
µA
II2C4
I2C
–
–
1.4
µA
Min
–
Typ
–
Max
1
Units
Mbps
SID152
enabled in Deep Sleep mode
Details/Conditions
Table 13. Fixed I2C AC Specifications
(Guaranteed by Characterization)
Spec ID
SID153
Parameter
FI2C1
Description
Bit rate
Document Number: 001-98044 Rev. *C
Details/Conditions
Page 15 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Table 14. Fixed UART DC Specifications
(Guaranteed by Characterization)
Min
Typ
Max
Units
SID160
Spec ID
IUART1
Parameter
Block current consumption at
100 Kbits/sec
Description
–
–
55
µA
SID161
IUART2
Block current consumption at
1000 Kbits/sec
–
–
312
µA
Min
Typ
Max
Units
–
–
1
Mbps
Description
Min
Typ
Max
Units
Details/Conditions
Table 15. Fixed UART AC Specifications
(Guaranteed by Characterization)
Spec ID
SID162
Parameter
FUART
Description
Bit rate
Details/Conditions
SPI Specifications
Table 16. Fixed SPI DC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
SID163
ISPI1
Block current consumption at 1 Mbits/sec
–
–
360
µA
SID164
ISPI2
Block current consumption at 4 Mbits/sec
–
–
560
µA
SID165
ISPI3
Block current consumption at 8 Mbits/sec
–
–
600
µA
Min
Typ
Max
Units
–
–
8
MHz
Details/Conditions
Table 17. Fixed SPI AC Specifications
(Guaranteed by Characterization)
Spec ID
SID166
Parameter
FSPI
Description
SPI operating frequency (master; 6X
oversampling)
Details/Conditions
Table 18. Fixed SPI Master mode AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
SID167
TDMO
MOSI valid after Sclock driving edge
–
–
15
ns
SID168
TDSI
MISO valid before Sclock capturing edge.
Full clock, late MISO Sampling used
20
–
–
ns
SID169
THMO
Previous MOSI data hold time with
respect to capturing edge at Slave
0
–
–
ns
Document Number: 001-98044 Rev. *C
Page 16 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Table 19. Fixed SPI Slave mode AC Specifications
(Guaranteed by Characterization)
Description
Min
Typ
Max
Units
SID170
Spec ID
TDMI
Parameter
MOSI valid before Sclock capturing edge
40
–
–
ns
SID171
TDSO
MISO valid after Sclock driving edge
–
–
42 + 3 ×
(1/FCPU)
ns
SID171A
TDSO_ext
MISO valid after Sclock driving edge in Ext.
Clock mode
–
–
48
ns
SID172
THSO
Previous MISO data hold time
SID172A
TSSELSCK
SSEL Valid to first SCK Valid edge
0
–
–
ns
100
–
–
ns
Memory
Table 20. Flash DC Specifications
Spec ID
SID173
Parameter
VPE
Description
Erase and program voltage
Min
Typ
Max
Units
1.71
–
5.5
V
Details/Conditions
Table 21. Flash AC Specifications
Description
Min
Typ
Max
Units
Details/Conditions
SID174
Spec ID
TROWWRITE
Parameter
Row (block) write time (erase and
program)
–
–
20
ms
Row (block) = 256 bytes
SID175
TROWERASE
Row erase time
–
–
13
ms
SID176
TROWPROGRAM
Row program time after erase
–
–
7
ms
SID178
TBULKERASE
Bulk erase time (64 KB)
–
–
35
ms
SID180
TDEVPROG
Total device program time
–
–
15
SID181
FEND
Flash endurance
100 K
–
–
cycles
Guaranteed by characterization
SID182
FRET
Flash retention. TA 55 °C, 100 K
P/E cycles
20
–
–
years
Guaranteed by characterization
Flash retention. TA 85 °C, 10 K
P/E cycles
10
–
–
years
Guaranteed by characterization
Min
Typ
Max
Units
1
–
67
V/ms
SID182A
seconds Guaranteed by characterization
System Resources
Power-on-Reset and Brown-out Detect (BOD) Specifications
Table 22. Power On Reset
Spec ID
Parameter
Description
SID.CLK#6 SR_POWER_UP Power supply slew rate
Details/Conditions
At power-up
SID185
VRISEIPOR
Rising trip voltage
0.80
–
1.45
V
Guaranteed by characterization
SID186
VFALLIPOR
Falling trip voltage
0.75
–
1.4
V
Guaranteed by characterization
BID51
Twupo
Initialization after Power-On
–
–
3
ms
Document Number: 001-98044 Rev. *C
Page 17 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Table 23. Brown-out Detect (BOD) for VCCD
Spec ID
Parameter
Description
SID190
VFALLPPOR
BOD trip voltage in active and
sleep modes
SID192
VFALLDPSLP
BOD trip voltage in Deep Sleep
Min
Typ
Max
1.48
-
1.62
1.11
-
1.5
Units
Details/Conditions
V
Guaranteed by
characterization
V
Guaranteed by
characterization
SWD Interface
Table 24. SWD Interface Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID213
F_SWDCLK1
3.3 V VDD 5.5 V
–
–
14
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
–
–
7
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID215
T_SWDI_SETUP T = 1/f SWDCLK
0.25*T
–
–
ns
Guaranteed by
characterization
SID216
T_SWDI_HOLD
0.25*T
–
–
ns
Guaranteed by
characterization
SID217
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5*T
ns
Guaranteed by
characterization
SID217A
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
ns
Guaranteed by
characterization
Min
Typ
Max
Units
T = 1/f SWDCLK
Internal Main Oscillator
Table 25. IMO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
SID218
IIMO1
IMO operating current at 48 MHz
–
–
250
µA
SID219
IIMO2
IMO operating current at 24 MHz
–
–
180
µA
Min
Typ
Max
Units
Details/Conditions
Table 26. IMO AC Specifications
Spec ID
Parameter
Description
SID223
FIMOTOL1
Frequency variation
–
–
±2
%
SID226
TSTARTIMO
IMO startup time
–
–
7
µs
SID228
TJITRMSIMO2
RMS Jitter at 24 MHz
–
145
–
ps
Min
Typ
Max
Units
–
0.3
1.05
µA
Details/Conditions
Internal Low-Speed Oscillator
Table 27. ILO DC Specifications
(Guaranteed by Design)
Spec ID
SID231
Parameter
IILO1
Description
ILO operating current
Document Number: 001-98044 Rev. *C
Details/Conditions
Guaranteed by
Characterization
Page 18 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Table 28. ILO AC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID234
TSTARTILO1
ILO startup time
–
–
2
ms
Guaranteed by characterization
SID236
TILODUTY
ILO duty cycle
40
50
60
%
Guaranteed by characterization
SID237
FILOTRIM1
Operating frequency
20
40
80
kHz
Table 29. External Clock Specifications
Min
Typ
Max
Units
SID305
Spec ID
ExtClkFreq
Parameter
External clock input frequency
Description
0
–
48
MHz
Guaranteed by
characterization
Details/Conditions
SID306
ExtClkDuty
Duty cycle; Measured at VDD/2
45
–
55
%
Guaranteed by
characterization
Table 30. UDB AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Datapath performance
SID249
FMAX-TIMER
Max frequency of 16-bit timer in a
UDB pair
–
–
48
MHz
SID250
FMAX-ADDER
Max frequency of 16-bit adder in a
UDB pair
–
–
48
MHz
SID251
FMAX_CRC
Max frequency of 16-bit CRC/PRS in
a UDB pair
–
–
48
MHz
Max frequency of 2-pass PLD
function in a UDB pair
–
–
48
MHz
PLD Performance in UDB
SID252
FMAX_PLD
Clock to Output Performance
SID253
TCLK_OUT_UDB1
Prop. delay for clock in to data out at
25 °C, Typ.
–
15
–
ns
SID254
TCLK_OUT_UDB2
Prop. delay for clock in to data out,
Worst case.
–
25
–
ns
Table 31. Block Specs
Spec ID
SID256*
Parameter
TWS48*
Description
Number of wait states at 48 MHz
Min
2
Typ
–
Max
–
SID257
TWS24*
Number of wait states at 24 MHz
1
–
–
Units
Details/Conditions
CPU execution from
Flash
CPU execution from
Flash
* Tws48 and Tws24 are guaranteed by Design
Document Number: 001-98044 Rev. *C
Page 19 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Ordering Information
The PSoC 4200D family part numbers and features are listed in the following table.
Flash (KB)
SRAM (KB)
Low-power
Comparators
No. of Universal
Digital Blocks (UDB)
Timer/Counter/PWM
Blocks (TCPWM)
No. of Serial
Communication
Blocks (SCB)
PRGIO
No. of GPIOs
Package Type
4246
No. of DMA Channels
4245
MAX. CPU Speed
(MHz)
4045
Marketing Part
Number (MPN)
Category
Table 32. PSoC 4200D Ordering Information
CY8C4045PVI-DS402
48
8
32
4
2
-
4
3
1
21
28-pin SSOP
CY8C4045FNI-DS402
48
8
32
4
2
-
4
3
1
21
25-ball WLCSP
CY8C4245PVI-DS402
48
8
32
4
2
4
4
3
1
21
28-pin SSOP
CY8C4245FNI-DS402
48
8
32
4
2
4
4
3
1
21
25-ball WLCSP
CY8C4246PVI-DS402
48
8
64
8
2
4
4
3
1
21
28-pin SSOP
CY8C4246FNI-DS402
48
8
64
8
2
4
4
3
1
21
25-ball WLCSP
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
Description
CY8C
4
A
B
C
Cypress Prefix
Architecture
Family
CPU Speed
Flash Capacity
DE
Package Code
F
S
XYZ
Temperature Range
Silicon Family
Attributes Code
Values
Meaning
4
2
4
5
6
PV
FN
I
D
000-999
PSoC 4
4200 Family
48 MHz
32 KB
64 KB
SSOP
CSP
Industrial
PSoC 4D
Code of feature set in the specific family
Document Number: 001-98044 Rev. *C
Page 20 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Part Numbering Conventions
The part number fields are defined as follows.
CY8C
4 A B C D E F -
S
XYZ
Cypress Prefix
Architecture
Family Group within Architecture
Speed Grade
Flash Capacity
Package Code
Temperature Range
Silicon Family
Attributes Code
Document Number: 001-98044 Rev. *C
Page 21 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Packaging
The description of the PSoC 4200D package dimensions follows.
Spec Id#
Package
Description
Package Dwg #
PKG_1
28-pin SSOP
28-pin SSOP, 8 mm × 10 mm × 2.0 mm
height with 0.65-mm pitch
51-85079
PKG_2
25-ball CSP
25-ball CSP, 2.07 mm × 2.11 mm ×
0.55 mm height with 0.4-mm pitch
001-97945
Table 33. Package Characteristics
Min
Typ
Max
Units
TA
Parameter
Operating ambient temperature
Description
Conditions
–40
25
85
°C
TJ
Operating junction temperature
–40
100
°C
TJA
Package θJA (28-pin SSOP)
–
67
–
°C/Watt
TJC
Package θJC (28-pin SSOP)
–
26
–
°C/Watt
TJA
Package θJA (25-ball CSP)
–
48
–
°C/Watt
TJC
Package θJC (25-ball CSP)
–
0.47
–
°C/Watt
Table 34. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
All packages
260 °C
30 seconds
Table 35. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
28-SSOP
MSL 3
25-ball CSP
MSL 1
Document Number: 001-98044 Rev. *C
MSL
Page 22 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Figure 5. 28-Pin SSOP Package Outline
51-85079 *F
Figure 6. 25-ball CSP 2.07 × 2.11 × 0.55 mm
001-97945 **
Document Number: 001-98044 Rev. *C
Page 23 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Acronyms
Table 36. Acronyms Used in this Document (continued)
Table 36. Acronyms Used in this Document
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
flash patch and breakpoint
Acronym
Acronym
Description
Description
abus
analog local bus
FPB
ADC
analog-to-digital converter
FS
full-speed
AG
analog global
GPIO
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
general-purpose input/output, applies to a PSoC
pin
HVI
high-voltage interrupt, see also LVI, LVD
IC
integrated circuit
IDAC
current DAC, see also DAC, VDAC
IDE
integrated development environment
ALU
arithmetic logic unit
AMUXBUS
analog multiplexer bus
API
application programming interface
APSR
application program status register
ARM®
advanced RISC machine, a CPU architecture
IIR
ATM
automatic thump mode
ILO
internal low-speed oscillator, see also IMO
BW
bandwidth
IMO
internal main oscillator, see also ILO
CAN
Controller Area Network, a communications
protocol
INL
integral nonlinearity, see also DNL
CMRR
common-mode rejection ratio
I/O
input/output, see also GPIO, DIO, SIO, USBIO
CPU
central processing unit
IPOR
initial power-on reset
CRC
cyclic redundancy check, an error-checking
protocol
IPSR
interrupt program status register
IRQ
interrupt request
DAC
digital-to-analog converter, see also IDAC, VDAC
ITM
instrumentation trace macrocell
DFB
digital filter block
LCD
liquid crystal display
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
LIN
Local Interconnect Network, a communications
protocol.
DMIPS
Dhrystone million instructions per second
LR
link register
DMA
direct memory access, see also TD
LUT
lookup table
DNL
differential nonlinearity, see also INL
LVD
low-voltage detect, see also LVI
DNU
do not use
LVI
low-voltage interrupt, see also HVI
DR
port write data registers
LVTTL
low-voltage transistor-transistor logic
DSI
digital system interconnect
MAC
multiply-accumulate
DWT
data watchpoint and trace
MCU
microcontroller unit
ECC
error correcting code
MISO
master-in slave-out
ECO
external crystal oscillator
NC
no connect
electrically erasable programmable read-only
memory
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
EMI
electromagnetic interference
NVIC
nested vectored interrupt controller
EMIF
external memory interface
NVL
nonvolatile latch, see also WOL
EOC
end of conversion
opamp
operational amplifier
EOF
end of frame
PAL
programmable array logic, see also PLD
EPSR
execution program status register
PC
program counter
ESD
electrostatic discharge
PCB
printed circuit board
EEPROM
Document Number: 001-98044 Rev. *C
2C,
I
or IIC
Inter-Integrated Circuit, a communications
protocol
infinite impulse response, see also FIR
Page 24 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Table 36. Acronyms Used in this Document (continued)
Acronym
Description
Table 36. Acronyms Used in this Document (continued)
Acronym
Description
PGA
programmable gain amplifier
THD
total harmonic distortion
PHUB
peripheral hub
TIA
transimpedance amplifier
PHY
physical layer
TRM
technical reference manual
PICU
port interrupt control unit
TTL
transistor-transistor logic
PLA
programmable logic array
TX
transmit
PLD
programmable logic device, see also PAL
UART
PLL
phase-locked loop
Universal Asynchronous Transmitter Receiver, a
communications protocol
PMDD
package material declaration data sheet
UDB
universal digital block
POR
power-on reset
USB
Universal Serial Bus
PRES
precise power-on reset
USBIO
PRS
pseudo random sequence
USB input/output, PSoC pins used to connect to
a USB port
PS
port read data register
VDAC
voltage DAC, see also DAC, IDAC
PSoC®
Programmable System-on-Chip™
WDT
watchdog timer
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
SWD
serial wire debug, a test protocol
SWV
single-wire viewer
TD
transaction descriptor, see also DMA
Document Number: 001-98044 Rev. *C
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Page 25 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Document Conventions
Units of Measure
Table 37. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Document Number: 001-98044 Rev. *C
Page 26 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Revision History
Description Title: PSoC® 4: PSoC 4200D Family Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 001-98044
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
**
4795389
WKA
06/23/2015 New datasheet
*A
4931127
WKA
09/23/2015 Removed 28-pin SSOP package.
Updated Pinouts.
Updated DC Specifications.
Removed SID85A, SID247A, SID259, and SID92.
Added BID51.
*B
4958966
WKA
10/12/2015 Updated package dimensions.
Updated bulk erase time to 64 KB.
Changed SID226 max to 7.
Updated TJA typ to 48 and TJC typ to 0.47.
*C
5759255
WKA
05/31/2017 Added 28-pin SSOP package.
Updated Cypress logo, copyright notice, and Sales, Solutions, and Legal Information based on the template.
Document Number: 001-98044 Rev. *C
Page 27 of 28
PSoC® 4: PSoC 4200D Family
Datasheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
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cypress.com/iot
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Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
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cypress.com/usb
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Document Number: 001-98044 Rev. *C
Revised June 1, 2017
Page 28 of 28