HDMI Transceiver with Fast Port Switching ADV7623 Data Sheet FEATURES APPLICATIONS 4-input, 1-output multiplexed HDMI transceiver Xpressview fast switching on all HDMI input ports Character- and icon-based on-screen display (OSD) High-Bandwidth Digital Content Protection (HDCP 1.4) HDCP repeater support 225 MHz HDMI Rx and Tx support 36-/30-/24-bit Deep Color Supports DVI RGB graphics up to 1600 × 1200 at 60 Hz Ultralow jitter digital PLL (100% deskew) Quad HDMI Rx input Format details available on all unselected ports Adaptive equalizer for cable lengths up to 30 meters Internal extended display identification data (EDID) RAM EDID replication (512 bytes per port) EDID with HDMI cable 5 V power support 5 V detect inputs Hot plug assertion control pins Single HDMI Tx output EDID data extraction Hot plug detect (HPD) input Audio support HDMI-compatible audio interface Dedicated flexible audio input/output port S/PDIF (IEC 60958-compatible) digital audio input/output Super audio CD (SACD) with DSD input/output interface High bit rate (HBR) audio Dolby® TrueHD DTS-HD Master Audio™ Full audio input and output support General Interrupt controller with 3 interrupt outputs STDI (standard identification circuit) Software libraries, driver, and application available 2-layer PCB design supported AVRs HTiB Sound bar with HDMI repeater support HBR enabled TVs Other repeater applications GENERAL DESCRIPTION The ADV7623 is a high performance, four-input, one-output, High-Definition Multimedia Interface (HDMI®) transceiver that integrates HDMI receiver and transmitter functions with digital audio I/Os onto one chip. It supports all HDCP repeater functions through fully tested Analog Devices, Inc., repeater software libraries and drivers. The ADV7623 incorporates Xpressview™ fast switching on all input HDMI ports. Using an Analog Devices hardware-based HDCP engine that minimizes software overhead, Xpressview technology allows fast switching between any HDMI input ports in less than 1 second. The ADV7623 supports all mandatory HDMI 3D TV formats in addition to all HDTV formats up to 1080p 36-bit Deep Color. The ADV7623 also features an integrated HDMI CEC controller that supports capability, discovery, and control (CDC). The ADV7623 has an integrated on-screen display (OSD) feature that allows generation and control of high quality character- and icon-based system status and control displays. Customers interested in using OSD are provided with Analog Devices OSD SDK. The ADV7623 offers a dedicated flexible audio output port and a dedicated audio input port to allow for easy extraction and insertion of audio data into and out of the HDMI stream. HDMI audio formats, including SACD via DSD and compressed high bit rate audio via HBR, are supported. The ADV7623 also features an audio return channel (ARC) receiver. ARC simplifies cabling by combining upstream audio capability in a conventional HDMI cable. Fabricated in an advanced CMOS process, the ADV7623 is provided in a 144-lead, 20 mm × 20 mm, Pb-free LQFP and is specified over the 0°C to 70°C temperature range. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADV7623 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Package Thermal Performance....................................................8 Applications ....................................................................................... 1 ESD Caution...................................................................................8 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................9 Revision History ............................................................................... 2 Functional Overview...................................................................... 13 Functional Block Diagram .............................................................. 3 HDMI Receiver........................................................................... 13 Specifications..................................................................................... 4 HDMI Transmitter ..................................................................... 13 Digital, HDMI, and AC Specifications ...................................... 4 I2C Interface ................................................................................ 13 Data and I2C Timing Characteristics ......................................... 5 Other Features ............................................................................ 13 Power Specifications .................................................................... 7 Outline Dimensions ....................................................................... 14 Absolute Maximum Ratings ............................................................ 8 Ordering Guide .......................................................................... 14 REVISION HISTORY 3/13—Revision D: Initial Version Rev. D | Page 2 of 16 Data Sheet ADV7623 FUNCTIONAL BLOCK DIAGRAM TX PLL XTAL RXD_0 RXD_1 RXD_2 EQUALIZER SAMPLER 5V DETECT HP_CTRLA HP_CTRLB HP_CTRLC HP_CTRLD RX HPD CONTROLLER EP_MISO EP_MOSI EP_CS EP_SCK SPI MASTER/ SLAVE PWRDN RESET SCL SDATA ALSB CS AUDIO CAPTURE INFOFRAME PACKET MEMORY TXDDC_SDA TXDDC_SCL INT1 INT2 INT_TX AP0_IN AP1_IN AP2_IN AP3_IN AP4_IN AP5_IN SCLK_IN MCLK_IN AP0_OUT AP1_OUT AP2_OUT AP3_OUT AP4_OUT AP5_OUT SCLK_OUT MCLK_OUT EDID RAM RX EDID/ REPEATER CONTROLLER GLOBAL CONTROLS ADV7623 TXC TX0 TX1 TX2 ARC RECEIVER HPD_ARC– ARC+ I2 C CONTROLLER 08302-001 DDCA_SDA DDCA_SCL DDCB_SDA DDCB_SCL DDCC_SDA DDCC_SCL DDCD_SDA DDCD_SCL PACKET PROCESSOR CH2 TX HPD CONTROLLER 5V_DETA 5V_DETB 5V_DETC 5V_DETD CEC CONTROLLER AUDIO PROCESSOR SYNC MEASUREMENT CH1 SERIALIZER TMDS DRIVERS SAMPLER CH0 TX EDID/HDCP CONTROLLER EQUALIZER VIDEO DATA DE VS HS AUDIO DATA INTERRUPT CONTROLLER RXC_0 RXC_1 RXC_2 VIDEO DATA DE VS HS AUDIO DATA EDID/HDCP BUFFER SAMPLER TRANSMITTER PACKET BUILDER EQUALIZER COMPONENT PROCESSOR RXB_0 RXB_1 RXB_2 OSD VIDEO DATA DE VS HS AUDIO DATA HDMI ENCODER VIDEO/AUDIO CLOCK GENERATION SAMPLER HDMI RECEIVER PROCESSOR EQUALIZER HDCP DECRYPTION ENGINE RX PLL RXA_0 RXA_1 RXA_2 CEC VIDEO DATA DE VS HS AUDIO DATA HDCP KEYS RXA_C RXB_C RXC_C RXD_C HDCP ENCRYPTION ENGINE XTAL1 Figure 1. Rev. D | Page 3 of 16 ADV7623 Data Sheet SPECIFICATIONS CVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%, DVDDIO = 3.3 V ± 5%, PVDD = 1.8 V ± 5%, TVDD = 3.3 V ± 5%, TXAVDD = 1.8 V ± 5%, TXPVDD = 1.8 V ± 5%, TXPLVDD = 1.8 V ± 5%, TMIN to TMAX = 0°C to 70°C. DIGITAL, HDMI, AND AC SPECIFICATIONS Table 1. Parameter DIGITAL INPUTS Input High Voltage (VIH) Input Low Voltage (VIL) Input Current (IIN) Test Conditions/Comments Typ Max Unit 0.8 +60 +10 10 V V µA µA pF 0.8 +82 V V µA 2 RESET, EP_MISO, ALSB and CS pins Other digital inputs Input Capacitance (CIN) DIGITAL INPUTS (5 V TOLERANT) 1 Input High Voltage (VIH) Input Low Voltage (VIL) Input Current (IIN) DIGITAL OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) High Impedance Leakage Current (ILEAK) Output Capacitance (COUT) HDMI TMDS Differential Pin Capacitance AC SPECIFICATIONS Input Specifications Intrapair (+ to −) Differential Input Skew for TMDS Clock Rates up to 222.75 MHz Intrapair (+ to −) Differential Input Skew for TMDS Clock Rates Above 222.75 MHz Channel-to-Channel Differential Input Skew TMDS Input Clock Range TMDS Input Clock Jitter Tolerance Output Specifications TMDS Output Clock Frequency TMDS Output Clock Duty Cycle TMDS Output Differential Swing Differential Output Timing Low-to-High Transition Time High-to-Low Transition Time 1 Min −60 −10 2.6 −82 2.4 0.4 10 20 0.3 pF 0.4 tBIT ps 0.15 tBIT + 112 ps 0.5 0.2 tPIXEL + 1.78 225 0.25 ns MHz tBIT 20 48 900 1100 225 52 1200 MHz % mV 75 75 175 175 25 The following pins are 5 V tolerant: DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA, TXDDC_SDA, TXDDC_SCL, HP_CTRLA, HP_CTRLB, HP_CTRLC, HP_CTRLD, HPD_ARC−, 5V_DETA, 5V_DETB, 5V_DETC, 5V_DETD, PWRDN, CEC, ARC+. Rev. D | Page 4 of 16 V V µA pF ps ps Data Sheet ADV7623 DATA AND I2C TIMING CHARACTERISTICS Table 2. Parameter VIDEO SYSTEM CLOCK AND XTAL Crystal Nominal Frequency Crystal Frequency Stability External Clock Source 1 Input High Voltage Input Low Voltage RESET FEATURE Reset Pulse Width 2 I C PORTS (FAST MODE) xCL Frequency 2 xCL Minimum Pulse Width High2 xCL Minimum Pulse Width Low2 Hold Time (Start Condition) Setup Time (Start Condition) xDA Setup Time2 xCL and xDA Rise Time2 xCL and xDA Fall Time2 Setup Time (Stop Condition) I2C PORTS (NORMAL MODE) xCL Frequency2 xCL Minimum Pulse Width High2 xCL Minimum Pulse Width Low2 Hold Time (Start Condition) Setup Time (Start Condition) xDA Setup Time2 xCL and xDA Rise Time2 xCL and xDA Fall Time2 Setup Time (Stop Condition) AUDIO OUTPUT PORT (MASTER MODE) SCLK Mark Space Ratio APx_OUT Data Transition Time (LRCLK) 3 APx_OUT Data Transition Time (LRCLK)3 APx_OUT Data Transition Time (I2S Data)3 APx_OUT Data Transition Time (I2S Data)3 AUDIO INPUT PORT APx_IN Setup Time (I2S Data)3 APx_IN Hold Time (I2S Data)3 APx_IN Setup Time (LRCLK)3 APx_IN Hold Time (LRCLK)3 1 2 3 Symbol Test Conditions/Comments Min Typ Max Unit ±50 MHz ppm 0.4 V V 28.63636 VIH VIL External crystal must operate at 1.8 V XTAL driven with external clock source XTAL driven with external clock source 1.2 5 ms 400 t1 t2 t3 t4 t5 t6 t7 t8 600 1.3 600 600 100 t1 t2 t3 t4 t5 t6 t7 t8 4.0 4.7 4.0 4.7 250 t13:t14 45:55 300 300 0.6 100 t15 t16 t17 t18 1000 300 4.0 End of valid data to negative SCLK edge Negative SCLK edge to start of valid data End of valid data to negative SCLK edge Negative SCLK edge to start of valid data t19 t20 t19 t20 10 10 5 5 2 2 2 2 This part must be configured for external oscillator operation. A 1.8 V oscillator must be used. The prefix x refers to S, DDCA_S, DDCB_S, DDCC_S, and DDCD_S. The suffix x refers to 0, 1, 2, 3, 4, and 5. Rev. D | Page 5 of 16 55:45 kHz ns µs ns ns ns ns ns µs kHz µs µs µs µs ns ns ns µs % duty cycle ns ns ns ns ns ns ns ns ADV7623 Data Sheet Timing Diagrams t3 t5 t3 xDA t6 t1 xCL t7 t4 t8 08302-002 t2 NOTES 1. x REFERS TO S, DDCA_S, DDCB_S, DDCC_S, DDCD_S. Figure 2. I2C Timing t13 SCLK t14 t15 LRCLK t16 t17 MSB – 1 t18 I2S[3:0] I2S MODE t17 MSB MSB – 1 t18 I2S[3:0] RIGHT-JUSTIFIED MODE t17 MSB LSB t18 Figure 3. I2S Output Timing t19 SCLK RISING EDGE R0x0B[6] = 0 I2S[3:0], LRCLK t20 VALID DATA t19 SCLK FALLING EDGE R0x0B[6] = 1 I2S[3:0] LRCLK t20 VALID DATA Figure 4. I2S Input Timing Rev. D | Page 6 of 16 08302-004 MSB 08302-007 I2S[3:0] LEFT-JUSTIFIED MODE Data Sheet ADV7623 POWER SPECIFICATIONS Table 3. Parameter POWER SUPPLIES Comparator Power Supply (CVDD) Digital Core Power Supply (DVDD) Digital I/O Power Supply (DVDDIO) PLL Power Supply (PVDD) Termination Power Supply (TVDD) TX TMDS Output Power Supply (TXAVDD) TX Power Supply (TXPVDD) TX PLL Power Supply (TXPLVDD) CURRENT CONSUMPTION 1, 2, 3, 4 Comparator Power Supply (ICVDD) Min Typ Max Unit 1.71 1.71 3.14 1.71 3.14 1.71 1.71 1.71 1.8 1.8 3.3 1.8 3.3 1.8 1.8 1.8 1.89 1.89 3.46 1.89 3.46 1.89 1.89 1.89 V V V V V V V V 481 545 1.0 1.0 350 9.0 6.7 2.0 3.4 3.3 39.6 1.7 1.6 312 0.4 0.4 14.3 0.5 0.3 6.6 2.8 2.8 26.4 1.6 1.6 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Digital Core Power Supply (IDVDD) 301 Digital I/O Power Supply (IDVDDIO) 1.0 PLL Power Supply (IPVDD) 34.0 Termination Power Supply (ITVDD) 283 TX TMDS Output Power Supply (ITXAVDD) 13.0 TX Power Supply (ITXPVDD) 5.0 TX PLL Power Supply (ITXPLVDD) 23.0 Test Conditions/Comments Four ports with 1080p 12-bit, Xpressview and OSD enabled Power-Down Mode 1 Power-Down Mode 0 Four ports with 1080p 12-bit, Xpressview and OSD enabled Power-Down Mode 1 Power-Down Mode 0 Four ports with 1080p 12-bit, Xpressview and OSD enabled Power-Down Mode 1 Power-Down Mode 0 Four ports with 1080p 12-bit, Xpressview and OSD enabled Power-Down Mode 1 Power-Down Mode 0 Four ports with 1080p 12-bit, Xpressview and OSD enabled Power-Down Mode 1 Power-Down Mode 0 Four ports with 1080p 12-bit, Xpressview and OSD enabled Power-Down Mode 1 Power-Down Mode 0 Four ports with 1080p 12-bit, Xpressview and OSD enabled Power-Down Mode 1 Power-Down Mode 0 Four ports with 1080p 12-bit, Xpressview and OSD enabled Power-Down Mode 1 Power-Down Mode 0 All maximum current values are guaranteed by characterization to assist in power supply design. Typical current consumption values are recorded with nominal voltage supply levels and at room temperature. 3 Maximum current consumption values are recorded with maximum rated voltage supply levels and at room temperature. 4 Termination power supply includes TVDD current consumed off chip. 1 2 Rev. D | Page 7 of 16 ADV7623 Data Sheet ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL PERFORMANCE Table 4. Parameter CVDD to GND DVDD to GND PVDD to GND DVDDIO to GND TVDD to GND TXAVDD to GND TXPVDD to GND TXPLVDD to GND Digital Inputs Voltage to GND 5 V Tolerant Digital Inputs to GND1 Digital Output Voltage to GND XTAL, XTAL1 Pins Maximum Junction Temperature (TJ MAX) Storage Temperature Infrared Reflow, Soldering (20 sec) 1 Rating 2.2 V 2.2 V 2.2 V 4.0 V 4.0 V 2.2 V 2.2 V 2.2 V GND − 0.3 V to DVDDIO + 0.3 V up to a maximum of 4.0 V 5.5 V GND − 0.3 V to DVDDIO + 0.3 V up to a maximum of 4.0 V −0.3 V to PVDD to +0.3 V 125°C 150°C 260°C The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA, TXDDC_SDA, TXDDC_SCL, HP_CTRLA, HP_CTRLB, HP_CTRLC, HP_CTRLD, HPD_ARC−, 5V_DETA, 5V_DETB, 5V_DETC, 5V_DETD, PWRDN, CEC, ARC+. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. To reduce power consumption when using the ADV7623, turn off the unused sections of the part. Due to printed circuit board (PCB) metal variation and, thus, variation in PCB heat conductivity, the value of θJA may differ for various PCBs. The most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this eliminates the variance associated with the θJA value. The maximum junction temperature (TJ MAX) of 125°C must not be exceeded. The following equation calculates the junction temperature using the measured package surface temperature and applies only when no heat sink is used on the DUT: TJ = TS + (ΨJT × WTOTAL) where: TS = the package surface temperature (°C). ΨJT = 0.6°C/W for a 144-lead LQFP. WTOTAL = ((CVDD × ICVDD) + (DVDD × IDVDD) + (PVDD × IPVDD) + (DVDDIO × IDVDDIO) + (0.7 × TVDD × ITVDD) + (TXAVDD × ITXAVDD) + (TXPVDD × ITXPVDD) + (TXPLVDD × ITXPLVDD)) Note that for WTOTAL, 5% of TVDD power is dissipated on the part itself. ESD CAUTION Rev. D | Page 8 of 16 Data Sheet ADV7623 109 108 PIN 1 2 107 3 106 4 105 5 104 6 103 7 102 8 101 9 100 10 99 11 98 12 97 13 96 14 95 15 94 16 93 17 18 19 20 ADV7623 92 TOP VIEW (Not to Scale) 90 91 89 21 88 22 87 23 86 24 85 25 84 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 TXPLVDD TXGND TXPGND EXT_SWING HPD_ARC– ARC+ TXDDC_SDA TXDDC_SCL TXAVDD TXGND TXC– TXC+ TXGND TX0– TX0+ TXGND TX1– TX1+ TXAVDD TX2– TX2+ TXGND CEC DGND DVDD ALSB CS EP_SCK EP_CS EP_MOSI EP_MISO MCLK_IN SCLK_IN AP5_IN AP4_IN DGNDIO 49 73 48 74 36 47 75 35 46 76 34 45 77 33 44 78 32 43 79 31 42 80 30 41 81 29 40 82 39 83 28 38 26 27 DDCA_SDA RTERM 5V_DETA HP_CTRLA PGND PVDD XTAL1 XTAL PVDD PGND PWRDN RESET MCLK_OUT SCLK_OUT AP5_OUT DVDD DGND AP4_OUT AP3_OUT AP2_OUT AP1_OUT AP0_OUT DVDDIO DGNDIO INT_TX INT2 INT1 DVDD DGND SCL SDATA AP0_IN AP1_IN AP2_IN AP3_IN DVDDIO 08302-005 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 1 37 DDCC_SCL CVDD CGND RXC_C– RXC_C+ TVDD RXC_0– RXC_0+ CGND RXC_1– RXC_1+ TVDD RXC_2– RXC_2+ HP_CTRLD 5V_DETD DGND DVDD DDCD_SDA DDCD_SCL CVDD CGND RXD_C– RXD_C+ TVDD RXD_0– RXD_0+ CGND RXD_1– RXD_1+ TVDD RXD_2– RXD_2+ CVDD CGND TXPVDD 143 144 DDCC_SDA 5V_DETC HP_CTRLC RXB_2+ RXB_2– TVDD RXB_1+ RXB_1– CGND RXB_0+ RXB_0– TVDD RXB_C+ RXB_C– CGND CVDD DDCB_SCL DDCB_SDA DVDD DGND 5V_DETB HP_CTRLB RXA_2+ RXA_2– TVDD RXA_1+ RXA_1– CGND RXA_0+ RXA_0– TVDD RXA_C+ RXA_C– CGND CVDD DDCA_SCL PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Mnemonic DDCC_SCL CVDD CGND RXC_C− RXC_C+ TVDD RXC_0− RXC_0+ CGND RXC_1− RXC_1+ TVDD Type Digital input Power Ground HDMI input HDMI input Power HDMI input HDMI input Ground HDMI input HDMI input Power Description HDCP Slave Serial Clock Port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant. Receiver Comparator Supply Voltage (1.8 V). TVDD and CVDD Ground. Digital Input Clock Complement of Port C in the HDMI Interface. Digital Input Clock True of Port C in the HDMI Interface. Receiver Terminator Supply Voltage (3.3 V). Digital Input Channel 0 Complement of Port C in the HDMI Interface. Digital Input Channel 0 True of Port C in the HDMI Interface. TVDD and CVDD Ground. Digital Input Channel 1 Complement of Port C in the HDMI Interface. Digital Input Channel 1 True of Port C in the HDMI Interface. Receiver Terminator Supply Voltage (3.3 V). Rev. D | Page 9 of 16 ADV7623 Data Sheet Pin No. 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Mnemonic RXC_2− RXC_2+ HP_CTRLD 5V_DETD DGND DVDD DDCD_SDA DDCD_SCL CVDD CGND RXD_C− RXD_C+ TVDD RXD_0− RXD_0+ CGND RXD_1− RXD_1+ TVDD RXD_2− RXD_2+ CVDD CGND TXPVDD Type HDMI input HDMI input Digital output Digital input Ground Power Digital I/O Digital input Power Ground HDMI input HDMI input Power HDMI input HDMI input Ground HDMI input HDMI input Power HDMI input HDMI input Power Ground Power 37 38 39 40 TXPLVDD TXGND TXPGND EXT_SWING Power Ground Ground Analog input 41 HPD_ARC− Analog input 42 43 ARC+ TXDDC_SDA Analog input Digital I/O 44 TXDDC_SCL Digital output 45 46 47 TXAVDD TXGND TXC− Power Ground HDMI output 48 TXC+ HDMI output 49 50 TXGND TX0− Ground HDMI output 51 TX0+ HDMI output 52 53 TXGND TX1− Ground HDMI output 54 TX1+ HDMI output 55 TXAVDD Power Description Digital Input Channel 2 Complement of Port C in the HDMI Interface. Digital Input Channel 2 True of Port C in the HDMI Interface. Hot Plug Detect for Port D. 5 V Detect Pin for Port D in the HDMI Interface. DVDD Ground. Digital Supply Voltage (1.8 V). HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant. HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant. Receiver Comparator Supply Voltage (1.8 V). TVDD and CVDD Ground. Digital Input Clock Complement of Port D in the HDMI Interface. Digital Input Clock True of Port D in the HDMI Interface. Receiver Terminator Supply Voltage (3.3 V). Digital Input Channel 0 Complement of Port D in the HDMI Interface. Digital Input Channel 0 True of Port D in the HDMI Interface. TVDD and CVDD Ground. Digital Input Channel 1 Complement of Port D in the HDMI Interface. Digital Input Channel 1 True of Port D in the HDMI Interface. Receiver Terminator Supply Voltage (3.3 V). Digital Input Channel 2 Complement of Port D in the HDMI Interface. Digital Input Channel 2 True of Port D in the HDMI Interface. Receiver Comparator Supply Voltage (1.8 V). TVDD and CVDD Ground. 1.8 V Power Supply for Digital and I/O Power Supply. This pin supplies power to the digital logic and I/Os. It should be filtered and as quiet as possible. 1.8 V Power Supply. TXPVDD Ground. TXPLVDD Ground. This pin sets the internal reference currents. Place an 887 Ω resistor (1% tolerance) between this pin and ground. Hot Plug Detect Signal and Audio Return Channel Inverted Input. This pin indicates to the interface whether the receiver is connected. Audio Return Channel (ARC) Input (5 V Tolerant). Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. It supports a 5 V CMOS logic level. Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. It supports a 5 V CMOS logic level. 1.8 V Power Supply for TMDS Outputs. TXAVDD Ground. Differential Clock Output. Differential clock output at the TMDS clock rate; supports TMDS logic level. Differential Clock Output. Differential clock output at the TMDS clock rate; supports TMDS logic level. TXAVDD Ground. Differential Output Channel 0 Complement. Differential output of the red data at 10× the pixel clock rate; supports TMDS logic level. Differential Output Channel 0 True. Differential output of the red data at 10× the pixel clock rate; supports TMDS logic level. TXAVDD Ground. Differential Output Channel 1 Complement. Differential output of the red data at 10× the pixel clock rate; supports TMDS logic level. Differential Output Channel 1 True. Differential output of the red data at 10× the pixel clock rate; supports TMDS logic level. 1.8 V Power Supply for TMDS Outputs. Rev. D | Page 10 of 16 Data Sheet ADV7623 Pin No. 56 Mnemonic TX2− Type HDMI output 57 TX2+ HDMI output 58 59 60 61 62 63 TXGND CEC DGND DVDD ALSB CS Ground Digital I/O Ground Power Digital input Digital input 64 65 66 67 68 EP_SCK EP_CS EP_MOSI EP_MISO MCLK_IN Digital output Digital output Digital output Digital input Digital input 69 70 71 72 73 74 75 76 77 78 79 80 81 82 SCLK_IN AP5_IN AP4_IN DGNDIO DVDDIO AP3_IN AP2_IN AP1_IN AP0_IN SDATA SCL DGND DVDD INT1 (AMUTE1) Digital input Digital input Digital input Ground Power Digital input Digital input Digital input Digital input Digital I/O Digital input Ground Power Digital output 83 INT2 (AMUTE2) Digital output 84 85 86 87 88 89 90 91 92 93 94 95 96 97 INT_TX DGNDIO DVDDIO AP0_OUT AP1_OUT AP2_OUT AP3_OUT AP4_OUT DGND DVDD AP5_OUT SCLK_OUT MCLK_OUT RESET Digital output Ground Power Digital output Digital output Digital output Digital output Digital output Ground Power Digital output Digital output Digital output Digital input 98 PWRDN Digital input Description Differential Output Channel 2 Complement. Differential output of the red data at 10× the pixel clock rate; supports TMDS logic level. Differential Output Channel 2 True. Differential output of the red data at 10× the pixel clock rate; supports TMDS logic level. TXAVDD Ground. Consumer Electronics Control Channel (5 V Tolerant). DVDD Ground. Digital Supply Voltage (1.8 V). This pin is used to set the I2C address of the Rx IO and the Tx main map. Chip Select Pin. This pin must be set low or left floating for the chip to process I2C messages that are destined for the ADV7623. The ADV7623 ignores I2C messages that it receives if this pin is high. SPI Clock Interface for the EDID/OSD. SPI Chip Selected Interface for the EDID/OSD. SPI Master Out/Slave In for the EDID/OSD. SPI Master In/Slave Out for the EDID/OSD. Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (fS), 256 × fS, 384 × fS, or 512 × fS. It supports CMOS logic levels from 1.8 V to 3.3 V. I2S Audio Clock. It supports CMOS logic levels from 1.8 V to 3.3 V. Audio Input Port 5. It supports CMOS logic levels from 1.8 V to 3.3 V. Audio Input Port 4. It supports CMOS logic levels from 1.8 V to 3.3 V. DVDDIO Ground. Digital I/O Supply Voltage (3.3 V). Audio Input Port 3. It supports CMOS logic levels from 1.8 V to 3.3 V. Audio Input Port 2. It supports CMOS logic levels from 1.8 V to 3.3 V. Audio Input Port 1. It supports CMOS logic levels from 1.8 V to 3.3 V. Audio Input Port 0. It supports CMOS logic levels from 1.8 V to 3.3 V. I2C Port Serial Data Input/Output Pin. SDATA is the data line for the control port. I2C Port Serial Clock Input. SCL is the clock line for the control port. DVDD Ground. Digital Supply Voltage (1.8 V). Interrupt Pin. This pin can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user control. This pin can also output an audio mute signal. Interrupt Pin. This pin can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user control. This pin can also output an audio mute signal. Interrupt; Open Drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply is recommended. DVDDIO Ground. Digital I/O Supply Voltage (3.3 V). Audio Output Port 0. Audio Output Port 1. Audio Output Port 2. Audio Output Port 3. Audio Output Port 4. DVDD Ground. Digital Supply Voltage (1.8 V). Audio Output Port 5. Audio Serial Clock Output. Audio Master Clock Output. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7623 circuitry. Active Low Power-Down Pin. If used, this pin should be pulled high to power up the ADV7623. This pin can also be used as an in system power detect where internal EDID can be powered from a 5 V signal of the HDMI port when it is connected to active equipment. Rev. D | Page 11 of 16 ADV7623 Pin No. 99 100 101 Mnemonic PGND PVDD XTAL 102 XTAL1 103 104 105 106 107 PVDD PGND HP_CTRLA 5V_DETA RTERM 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 DDCA_SDA DDCA_SCL CVDD CGND RXA_C− RXA_C+ TVDD RXA_0− RXA_0+ CGND RXA_1− RXA_1+ TVDD RXA_2− RXA_2+ HP_CTRLB 5V_DETB DGND DVDD DDCB_SDA DDCB_SCL CVDD CGND RXB_C− RXB_C+ TVDD RXB_0− RXB_0+ CGND RXB_1− RXB_1+ TVDD RXB_2− RXB_2+ HP_CTRLC 5V_DETC DDCC_SDA Data Sheet Type Ground Power Miscellaneous analog Miscellaneous analog Power Ground Digital output Digital input Miscellaneous analog Digital I/O Digital input Power Ground HDMI input HDMI input Power HDMI input HDMI input Ground HDMI input HDMI input Power HDMI input HDMI input Digital output Digital input Ground Power Digital I/O Digital input Power Ground HDMI input HDMI input Power HDMI input HDMI input Ground HDMI input HDMI input Power HDMI input HDMI input Digital output Digital input Digital I/O Description PVDD Ground. PLL Supply Voltage (1.8 V). Input pin for 28.63636 MHz crystal or an external 1.8 V 28.63636 MHz clock oscillator source to clock the ADV7623. Crystal Output Pin. This pin should be left floating if a clock oscillator is used. PLL Supply Voltage (1.8 V). PVDD Ground. Hot Plug Detect for Port A. 5 V Detect Pin for Port A in the HDMI Interface. This pin sets the internal termination resistance. A 500 Ω resistor between this pin and ground should be used. HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input/output that is 5 V tolerant. HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. Receiver Comparator Supply Voltage (1.8 V). TVDD and CVDD Ground. Digital Input Clock Complement of Port A in the HDMI Interface. Digital Input Clock True of Port A in the HDMI Interface. Receiver Terminator Supply Voltage (3.3 V). Digital Input Channel 0 Complement of Port A in the HDMI Interface. Digital Input Channel 0 True of Port A in the HDMI Interface. TVDD and CVDD Ground. Digital Input Channel 1 Complement of Port A in the HDMI Interface. Digital Input Channel 1 True of Port A in the HDMI Interface. Receiver Terminator Supply Voltage (3.3 V). Digital Input Channel 2 Complement of Port A in the HDMI Interface. Digital Input Channel 2 True of Port A in the HDMI Interface. Hot Plug Detect for Port B. 5 V Detect Pin for Port B in the HDMI Interface. DVDD Ground. Digital Supply Voltage (1.8 V). HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant. HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. Receiver Comparator Supply Voltage (1.8 V). TVDD and CVDD Ground. Digital Input Clock Complement of Port B in the HDMI Interface. Digital Input Clock True of Port B in the HDMI Interface. Receiver Terminator Supply Voltage (3.3 V). Digital Input Channel 0 Complement of Port B in the HDMI Interface. Digital Input Channel 0 True of Port B in the HDMI Interface. TVDD and CVDD Ground. Digital Input Channel 1 Complement of Port B in the HDMI Interface. Digital Input Channel 1 True of Port B in the HDMI Interface. Receiver Terminator Supply Voltage (3.3 V). Digital Input Channel 2 Complement of Port B in the HDMI Interface. Digital Input Channel 2 True of Port B in the HDMI Interface. Hot Plug Detect for Port C. 5 V Detect Pin for Port C in the HDMI Interface. HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input/output that is 5 V tolerant. Rev. D | Page 12 of 16 Data Sheet ADV7623 FUNCTIONAL OVERVIEW HDMI RECEIVER The ADV7623 front end incorporates a 4:1 multiplexed HDMI receiver boasting Xpressview fast switching technology and support for HDMI features including 3D TV, content type bits, and advanced features, such as capability discovery and control. Building on the feature set of existing Analog Devices HDMI devices, the ADV7623 also offers support for all HDTV formats up to 36-bit, 1080p Deep Color and all display resolutions up to UXGA (1600 × 1200 at 60 Hz). Xpressview fast switching technology, using Analog Devices hardware-based HDCP engine that minimizes software overhead, allows switching between any two input ports in less than 1 second. A key feature of the ADV7623 is the on-chip character-based OSD generator. The OSD generated can be converted to match the input format 4:2:2 or 4:4:4 in RGB or YCrCb color space. The OSD is overlaid at the output resolution for best performance. The OSD portion of the image is optionally semitransparent using a 5-bit alpha blend between the input video and the OSD. The OSD font characters are stored in either an external SPI flash or read directly into the RAM when instructed or can be loaded in to the on-chip RAM via the SPI or I2C. With the inclusion of HDCP 1.4, displays can receive encrypted video content. The HDMI interface of the ADV7623 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP 1.4 protocol. Repeater support is also offered by the ADV7623. The HDMI receiver offers advanced audio functionality. It supports multichannel I2S audio for up to eight channels. It also supports a 6-DSD channel interface with each channel carrying an oversampled 1-bit representation of the audio signal as delivered on SACD. The ADV7623 can also receive HBR audio packet streams and output them through the HBR interface in an S/PDIF format conforming to the IEC 60958 standard. S/PDIF is supported via the HPD back channel. The receiver also contains an audio mute controller that can detect a variety of conditions that may result in audible extraneous noise in the audio output. On detection of these conditions, the audio data can be ramped to prevent audio clicks or pops. high frequency losses inherent in HDMI and DVI cabling, especially at longer lengths and higher frequencies. The receiver also contains a programmable data island packet interrupt generator. HDMI TRANSMITTER The ADV7623 features a single HDMI transmitter supporting ARC, 3D TV formats as well as all HDTV formats up to 1080p, 36-bit Deep Color. Supporting both single-ended and differential modes, the ARC feature simplifies cabling by combining an upstream audio capability in a conventional HDMI cable. The transmitter features an on-chip MPU with an I2C master to perform HDCP operations and EDID reading operations. I2C INTERFACE The ADV7623 supports a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. The ADV7623 is controlled by an external I2C master device, such as a microcontroller. OTHER FEATURES Other features include the following: • • • • • • • • Fully qualified software low level libraries, driver, and application Complete input and output audio support Programmable interrupt request output pins: INT1, INT2, and INT_TX Chip select Non-HDCP professional variant available (ADV7623BSTZ-P). No evaluation board is available for this variant. Low power consumption: 1.8 V digital core, 1.8 V analog, and 3.3 V digital input/output, low power power-down mode, and green PC mode Temperature range: 0°C to 70°C 20 mm × 20 mm, Pb-free, 144-lead LQFP For more detailed product information about the ADV7623, contact your local Analog Devices sales office. The ADV7623HDMI receiver incorporates active, programmable equalization of the HDMI data signals that compensates for the Rev. D | Page 13 of 16 ADV7623 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 22.20 22.00 SQ 21.80 1.60 MAX 109 144 108 1 PIN 1 20.20 20.00 SQ 19.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 73 36 0.08 COPLANARITY 72 37 VIEW A VIEW A ROTATED 90° CCW 0.50 BSC LEAD PITCH 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BFB 051706-A 1.45 1.40 1.35 Figure 6. 144-Lead Low Profile Quad Flat Package [LQFP] (ST-144) Dimensions shown in millimeters ORDERING GUIDE Model1 ADV7623BSTZ ADV7623BSTZ-RL ADV7623BSTZ-P ADV7623BSTZ-P-RL EVAL-ADV7623EB1Z 1 Model Description HDCP Transceiver HDCP Transceiver (Reel) Non-HDCP Transceiver Non-HDCP Transceiver (Reel) HDCP Transceiver Evaluation Board Temperature Range 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C Z = RoHS Compliant Part. Rev. D | Page 14 of 16 Package Description 144-Lead Low Profile Quad Flat Package [LQFP] 144-Lead Low Profile Quad Flat Package [LQFP] 144-Lead Low Profile Quad Flat Package [LQFP] 144-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Package Option ST-144 ST-144 ST-144 ST-144 Data Sheet ADV7623 NOTES Rev. D | Page 15 of 16 ADV7623 Data Sheet NOTES I2C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors). HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08302-0-3/13(D) Rev. D | Page 16 of 16