CXR702F080
CMOS 32-bit Single Chip Microcomputer
Description
The CXR702F080 is a CMOS 32-bit microcomputer
integrating on a single chip an A/D converter, serial
interface, timer, bus interface unit, DMA controller,
memory stick interface, and as well as basic
configurations like a 32-bit RISC CPU, ROM, RAM,
and I/O port.
This also provides the idle/sleep/stop functions that
enable lower power consumption.
176 pin LFLGA (Plastic)
Features
• CPU
• Minimum instruction cycle
•
•
•
•
•
SR11 series 32-bit RISC CPU core
54.3ns (fSRC: 18.432MHz)
30.5µs (fTEX: 32.768kHz)
Incorporated FLASH EEPROM
256K bytes
Incorporated RAM
16K bytes
Peripheral functions
— Bus interface unit
— DMA controller
4 channels
— A/D converter
8-bit 4-analog input, successive approximation system
— Serial interface
Clock synchronization, 2 channels
Clock synchronization, 1 channel (Incorporated 64-byte buffer RAM)
Asynchronization, 2 channels
— Timers
8-bit timer, 8 channels
16-bit capture timer, 3 channels
8-bit time-base timer
Clock prescaler
16-bit watchdog timer
— Memory stick interface
— Beep output circuit
— External interruption
11 channels (polarity selection and both edge detection possible)
Standby mode
Idle/sleep/stop
Package
176-pin plastic LFLGA
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01739
AVDD
–2–
UART (CH1)
TxD1
RxD1
8-BIT TIMER (CH7)
8-BIT TIMER (CH6)
8-BIT TIMER (CH5)
8-BIT TIMER (CH4)
8-BIT TIMER (CH3)
8-BIT TIMER/COUNTER (CH2)
8-BIT TIMER (CH1)
3∗1
RAM
16K BYTES
TOKEI PRESCALER
WATCHDOG TIMER
6
FLASH EEPROM
256K BYTES
6
8
6
4
8
6
6
4
8
PORT A PORT B PORT C PORT D PORT E PORT F PORT G PORT H PORT I
8∗1
∗2
2∗2
2∗2
BUS INTERFACE UNIT
2
8
19
8
16
24
8
8
7
3
8
4
PORT J PORT K PORT L PORT M PORT N PORT O
16-BIT CAPTURE TIMER (CH2)
16-BIT CAPTURE TIMER (CH1)
16-BIT CAPTURE TIMER (CH0)
DMAC (CH3)
DMAC (CH2)
DMAC (CH1)
DMAC (CH0)
EXTERNAL BUS
∗1 The number of causes of interrupts generated from the module is as shown. But the number of causes input to the interrupt controller differs from the shown becauses of OR.
∗2 A part of the interrupt signals generated from UART, MEMORY STICK INTERFACE is input to the interrupt controller via DMA depending on applications.
BEEP
T3
T1
EC2
8-BIT TIMER/COUNTER (CH0)
MEMORY STICK INTERFACE
UART (CH0)
TxD0
RxD0
MSBS
MSDIO
MSIDR
MSSCLK
EC0
SERIAL INTERFACE
UNIT (CH2)
RAM
SCS2
SI2
SO2
SCK2
SERIAL INTERFACE
UNIT (CH0)
A/D CONVERTER
AVREF
SERIAL INTERFACE
UNIT (CH1)
4
AVSS
SCS1
SI1
SO1
SCK1
SCS0
SI0
SO0
SCK0
AN0
to AN3
10 ∗1
TDO
TRST
RTCK
TCK
TMS
TDI
ARM7TDMI
CPU CORE
MSINS
INT0
to INT9
INTERRUPT CONTROLLER
TXOUT
TX
TEX
XOUT
XTAL
EXTAL
RST
VDD
VSS
CLOCK GENERATOR/
SYSTEM CONTROLLER
Block Diagram
CT0ED0
CT0ED1
CT1ED0
CT1ED1
CT2ED0
CT2ED1
DACK0
DREQ0
DACK1
DREQ1
A0
to A23
D0
to D15
CS0
to CS7
RD
WE
LWR/LB
UWR/UB
WAIT
MA0
to MA18
MD0
to MD7
MCS0,
MCS1
MRD
MWE
CXR702F080
CXR702F080
Pin Assignment (Top View) 176-pin LFLGA package
• Pin Assignment
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R
88
87
86
83
80
77
73
69
65
61
57
53
49
45
44
R
P
89
90
82
81
78
72
68
64
60
56
52
48
47
46
43
P
N
93
91
85
84
79
76
71
67
63
59
55
51
41
38
42
N
M
97
92
95
94
75
74
70
66
62
58
54
50
40
37
39
M
L
101
96
99
98
34
35
32
36
L
K
105
100
103
102
30
31
28
33
K
J
109
104
107
106
26
27
24
29
J
H
113
108
111
110
22
23
20
25
H
G
117
112
115
114
18
19
16
21
G
F
121
116
119
118
14
15
12
17
F
E
124
120
123
122
10
11
8
13
E
D
127
125
128
138
142
146
150
154
158
162
166
6
7
4
9
D
C
130
126
129
139
143
147
151
155
159
163
167
172
173
3
5
C
B
131
134
135
136
140
144
148
152
156
160
164
169
170
2
1
B
A
132
133
137
141
145
149
153
157
161
165
168
171
174
175
176
A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
–3–
CXR702F080
• Pin Assignment Table
Pin
No.
Pin
position
Symbol
Pin
No.
Pin
position
Symbol
Pin
No.
Pin
position
Symbol
1
B1
PB3
38
N2
PG2/CT1ED0
75
M11
PK7/D15
2
B2
PB4
39
M1
PG3/CT1ED1
76
N10
VDD
3
C2
PB5
40
M3
PG4/CT2ED0
77
R10
TEX
4
D2
PB6
41
N3
PG5/CT2ED1
78
P11
TX
5
C1
PB7
42
N1
PH0/TxD0
79
N11
VSS
6
D4
VDD
43
P1
PH1/RxD0
80
R11
CS0
7
D3
VSS
44
R1
PH2/TxD1
81
P12
CS1
8
E2
PC0
45
R2
PH3/RxD1
82
P13
RD
9
D1
PC1
46
P2
VDD
83
R12
LWR/LB
10
E4
PC2
47
P3
VSS
84
N12
UWR/UB
11
E3
PC3
48
P4
PI0/MD0
85
N13
MRD
12
F2
PC4
49
R3
PI1/MD1
86
R13
MWE/WE
13
E1
PC5
50
M4
PI2/MD2
87
R14
MCS0
14
F4
PD0
51
N4
PI3/MD3
88
R15
VDD
15
F3
PD1
52
P5
PI4/MD4
89
P15
VSS
16
G2
PD2
53
R4
PI5/MD5
90
P14
MA0
17
F1
PD3
54
M5
PI6/MD6
91
N14
MA1/A9
18
G4
VDD
55
N5
PI7/MD7
92
M14
MA2/A10
19
G3
VSS
56
P6
VDD
93
N15
MA3/A11
20
H2
PE0/INT0
57
R5
VSS
94
M12
MA4/A12
21
G1
PE1/INT1
58
M6
PJ0/D0
95
M13
MA5/A13
22
H4
PE2/INT2
59
N6
PJ1/D1
96
L14
MA6/A14
23
H3
PE3/INT3
60
P7
PJ2/D2
97
M15
MA7/A15
24
J2
PE4/INT4
61
R6
PJ3/D3
98
L12
MA8/A16
25
H1
PE5/INT5
62
M7
PJ4/D4
99
L13
PL0/MA9/A17
26
J4
PE6/INT6
63
N7
PJ5/D5
100
K14
PL1/MA10/A18
27
J3
PE7/INT7
64
P8
PJ6/D6
101
L15
PL2/MA11/A19
28
K2
PF0/EC0
65
R7
PJ7/D7
102
K12
PL3/MA12/A20
29
J1
PF1/T1
66
M8
VDD
103
K13
PL4/MA13/A21
30
K4
PF2/EC2
67
N8
VSS
104
J14
PL5/MA14/A22
31
K3
PF3/T3
68
P9
PK0/D8
105
K15
PL6/MA15/A23
32
L2
PF4/BEEP
69
R8
PK1/D9
106
J12
VDD
33
K1
PF5/TXOUT
70
M9
PK2/D10
107
J13
VSS
34
L4
VDD
71
N9
PK3/D11
108
H14
MA16
35
L3
VSS
72
P10
PK4/D12
109
J15
MA17
36
L1
PG0/CT0ED0
73
R9
PK5/D13
110
H12
MA18/A0
37
M2
PG1/CT0ED1
74
M10
PK6/D14
–4–
111
H13
A1
CXR702F080
Pin
No.
Pin
position
112
G14
113
Pin
No.
Pin
position
Pin
No.
Pin
position
A2
134
B14
TEST1
156
B7
PN5/SO1
H15
A3
135
B13
AN0
157
A8
PN6/SI1
114
G12
A4
136
B12
PM0/AN1
158
D7
PN7/SCS1/INT9
115
G13
A5
137
A13
PM1/AN2
159
C7
PO0/SCK2
116
F14
A6
138
D12
PM2/AN3
160
B6
PO1/SO2
117
G15
A7
139
C12
AVSS
161
A7
PO2/SI2
118
F12
A8
140
B11
AVREF
162
D6
PO3/SCS2
119
F13
VDD
141
A12
AVDD
163
C6
XOUT/CKO
120
E14
EXTAL
142
D11
TDI
164
B5
VDD
121
F15
XTAL
143
C11
TMS
165
A6
VSS
122
E12
VSS
144
B10
TRST
166
D5
PWE
123
E13
MSDIO
145
A11
TCK
167
C5
NC
124
E15
MSBS
146
D10
RTCK
168
A5
PA0/WAIT
125
D14
MSSCLK
147
C10
TDO
169
B4
PA1/CS2
126
C14
MSDIR
148
B9
RST
170
B3
PA2/CS3
127
D15
MSINS
149
A10
VDD
171
A4
PA3/CS4
128
D13
DACK0
150
D9
VSS
172
C4
PA4/CS5
129
C13
DACK1
151
C9
PN0/SCK0
173
C3
PA5/MCS1
130
C15
DREQ0
152
B8
PN1/SO0
174
A3
PB0
131
B15
DREQ1
153
A9
PN2/SI0
175
A2
PB1
132
A15
TEST2
154
D8
PN3/SCS0/INT8
176
A1
PB2
133
A14
TEST0
155
C8
PN4/SCK1
Symbol
Symbol
–5–
Symbol
CXR702F080
Pin Functions
Symbol
Functions
I/O
PA0/WAIT
I/O / Input
PA1/CS2
to PA4/CS5
I/O / Output
PA5/MCS1
I/O / Output
(Port A)
6-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(6 pins)
Wait input for external bus
Chip select output for external S bus
(4 pins)
Chip select output for external M bus.
I/O
(Port B)
8-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor can be incorporated through program in 1-bit units.
(8 pins)
PC0 to PC5
I/O
(Port C)
6-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor can be incorporated through program in 1-bit units.
(6 pins)
PD0, PD1
Output
PD2, PD3
I/O
PB0 to PB7
PE0/INT0
to PE7/INT7
I/O / Input
PF0/EC0
I/O / Input
PF1/T1
I/O / Output
PF2/EC2
I/O / Input
PF3/T3
I/O / Output
PF4/BEEP
I/O / Output
PF5/TXOUT
I/O / Output
PG0/CT0ED0
to PG5/
CT2ED1
I/O / Input
(Port D)
4-bit open drain port. Lower 2 bits are for output; upper 2 bits are for I/O.
(4mA drive)
Upper 2 bits can be specified in 1-bit units.
(4 pins)
(Port E)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
(Port F)
6-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(6 pins)
(Port G)
6-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(6 pins)
–6–
External interruption request input.
(8 pins)
External event input to 8-bit timer (CH0).
8-bit timer (CH1) output.
External event input to 8-bit timer (CH2).
8-bit timer (CH3) output.
Beep output.
Sub oscillation output.
Capture input of 16-bit capture timer.
(6 pins)
CXR702F080
Symbol
PH0/TxD0
I/O / Output
PH1/RxD0
I/O / Input
PH2/TxD1
I/O / Output
PH3/RxD1
I/O / Input
PI0/MD0
to PI7/MD7
PJ0/D0
to PJ7/D7
(Port H)
4-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(4 pins)
I/O / I/O
(Port I)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
I/O / I/O
(Port J)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
PK0/D8
to PK7/D15
I/O / I/O
A1 to A8
Output
MA18/A0
Output / Output
MA1/A9
to MA8/A16
Output / Output
PL0/MA9/A17
to PL6/MA15/
A23
I/O / Output /
Output
MA0
Output
MA16, MA17
Output
AN0
Input
PM0/AN1
to PM2/AN3
Functios
I/O
Input / Input
(Port K)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
(Port L)
7-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(7 pins)
UART (CH0) transmit data output.
UART (CH0) receive data input.
UART (CH1) transmit data output.
UART (CH1) receive data input.
Data bus for external M bus.
(8 pins)
Data bus for external S bus.
(16 pins)
Address bus output for
external M bus
(19 pins)
Address bus output for
external S bus.
(24 pins)
Analog input to A/D converter.
(4 pins)
(Port M)
3-bit input port.
(3-pins)
–7–
CXR702F080
Symbol
I/O
Functios
PN0/SCK0
I/O / I/O
Serial clock (CH0) I/O.
PN1/SO0
I/O / Output
Serial data (CH0) output.
PN2/SI0
I/O / Input
PN3/SCS0/
INT8
I/O / Input /
Input
PN4/SCK1
I/O / I/O
PN5/SO1
I/O / Output
PN6/SI1
I/O / Input
PN7/SCS1/
INT9
I/O / Input /
Input
PO0/SCK2
I/O / I/O
PO1/SO2
I/O / Output
PO2/SI2
I/O / Input
PO3/SCS2
I/O / Input
CS0, CS1
Output
Chip select output for external S bus.
(2 pins)
RD
Output
Read signal output for external S bus.
LWR/LB
Output / Output
Write strobe signal output for D0 to
D7.
Strobe signal output indicates
access to D0 to D7.
UWR/UB
Output / Output
Write strobe signal output for D8 to
D15.
Strobe signal output indicates
access to D8 to D15.
MRD
Output
Read signal output for external M bus.
MWE/WE
Output / Output Write signal output for external M bus. Write signal output for external S bus.
MCS0
Output
Chip select output for external M bus.
DACK0
Output
Transfer request acknowledge signal output from DMA controller (CH0).
DREQ0
Input
Transfer request input to DMA controller (CH0).
DACK1
Output
Transfer request acknowledge signal output from DMA controller (CH1).
DREQ1
Input
Transfer request input to DMA controller (CH1).
MSDIR
Output
Memory stick interface data I/O direction monitor.
MSBS
Output
Memory stick interface bus state output.
MSSCLK
Output
Memory stick interface clock output.
MSDIO
I/O
Memory stick interface data I/O direction monitor.
MSINS
Input
Memory stick interface card detection.
TEST0
Input
TEST1
Input
TEST2
Input
TDI
Input
(Port N)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(8 pins)
Serial data (CH0) input.
Serial chip select (CH0)
input.
Serial clock (CH1) I/O.
Serial data (CH1) output.
Serial data (CH1) input.
Serial chip select (CH1)
input.
(Port O)
4-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor can be
incorporated through
program in 1-bit units.
(4 pins)
External interruption
request input.
Serial clock (CH2) I/O.
Serial data (CH2) output.
Serial data (CH2) input.
Serial chip select (CH2) input.
Test. (Connect to Vss.)
Data input for JTAG boundary scanning test.
–8–
External interruption
request input.
CXR702F080
Symbol
I/O
Functions
TMS
Input
Test mode control input for JTAG boundary scanning test.
TRST
Input
Reset input for JTAG boundary scanning test.
TCK
Input
Clock input for JTAG boundary scanning test.
RTCK
Output
Clock output for JTAG boundary scanning test.
TDO
Output
Data output for JTAG boundary scanning test.
EXTAL
Input
XTAL
Output
Oscillation connector of main oscillation.
(When a clock is supplied externally, input it to EXTAL; opposite phase
clock should be input to XTAL.)
XOUT/CKO
Output / Output Main oscillation output.
TEX
Input
TX
Output
Oscillation connector of main oscillation.
(When a clock is supplied externally, input it to TEX; opposite phase
clock should be input to TX.)
RST
I/O
System reset.
PWE
Input
FLASH EEPROM miswriting protection signal input.
System clock output.
NC
NC. (Leave this pin open or connect to Vss.)
AVDD
Positive power supply for A/D converter.
AVREF
Input
Reference voltage input for A/D converter.
AVSS
GND for A/D converter.
VDD
Positive power supply (Connect all twelve VDD pins to positive power supply.)
VSS
GND (Connect all twelve Vss pins to GND)
–9–
CXR702F080
I/O Circuit Format for Pins
Pin
Circuit format
After a reset
Port A data
Port A direction
"0" after a reset
PA0/WAIT
Pull-up resistor
Hi-Z
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
WAIT
CS2 to CS5
MPX
Port A data
Port A
function select
"0" after a reset
S bus pin active
PA1/CS2
to
PA4/CS5
MPX
Port A direction
Hi-Z
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
MCS1
(M bus unused: CS7)
MPX
Port A data
Port A
function select
"0" after a reset
PA5/MCS1
Port A direction
Hi-Z
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
– 10 –
IP
CXR702F080
Pin
Circuit format
After a reset
Port B data
Port B direction
"0" after a reset
PB0 to PB7
Hi-Z
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
Port C data
Port C direction
"0" after a reset
PC0 to PC5
Hi-Z
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
Port D data
PD0
PD1
Hi-Z
Internal data bus
RD
Port D data
PD2
PD3
Port D
read select
Hi-Z
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
– 11 –
IP
CXR702F080
Pin
Circuit format
After a reset
Port E data
Port E direction
"0" after a reset
PE0/INT0
to
PE7/INT7
Pull-up resistor
Hi-Z
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
INT0 to INT7
Port F data
Port F direction
"0" after a reset
PF0/EC0
PF2/EC2
Hi-Z
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
EC0, EC2
T1, T3, BEEP, TXOUT
MPX
Port F data
Port F
function select
"0" after a reset
PF1/T1
PF3/T3
PF4/BEEP
PF5/TXOUT
Port F direction
Hi-Z
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
– 12 –
IP
CXR702F080
Pin
Circuit format
After a reset
Port G data
Port G direction
PG0/CT0ED0
PG1/CT0ED1
PG2/CT1ED0
PG3/CT1ED1
PG4/CT2ED0
PG5/CT2ED1
"0" after a reset
Pull-up resistor
Hi-Z
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
CT0ED0, CT0ED1
CT1ED0, CT1ED1
CT2ED0, CT2ED1
TxD0, TxD1
MPX
Port H data
Port H
function select
"0" after a reset
PH0/TxD0
PH2/TxD1
Port H direction
Hi-Z
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
Port H data
Port H direction
"0" after a reset
PH1/RxD0
PH3/RxD1
Pull-up resistor
Hi-Z
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
RxD0, RxD1
– 13 –
IP
CMOS
Schmitt input
CXR702F080
Pin
Circuit format
After a reset
MD0 to MD7
MPX
Port I data
Port I
function select
"1" after a reset
M bus output enable
MPX
PI0/MD0
to
PI7/MD7
Port I direction
Hi-Z
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
MD0 to MD7
D0 to D7
MPX
Port J data
Port J
function select
"1" after a reset
S bus output enable
MPX
PJ0/D0
to
PJ7/D7
Port J direction
Hi-Z
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
D0 to D7
D8 to D15
MPX
Port K data
Port K
function select
"1" after a reset
S bus output enable
MPX
PK0/D8
to
PK7/D15
Port K direction
"0" after a reset
Hi-Z
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
D8 to D15
– 14 –
IP
CXR702F080
Pin
Circuit format
After a reset
A1 to A8
Low
A1 to A8
S bus pin active
MA18
MA18/A0
MPX
A0
Low
S bus/M bus select
MA1 to MA8
MA1/A9
to
MA8/A16
MPX
A9 to A16
Low
S bus/M bus select
MA9 to MA15
A17 to A23
MPX
Port L data
S bus/M bus select
Port L
function select
PL0/MA9/A17
to
PL6/MA15/A23
"1" after a reset
S bus pin high impedance
Low
Port L direction
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
Input data
latch
MPX
IP
RD
MA0
MA16
MA17
MA0
Low
MA16, MA17
Low
– 15 –
CXR702F080
Pin
Circuit format
After a reset
Analog input select
("1" after a reset)
AN0
AN0
IP
Input data
latch
Internal data bus
RD
PM0/AN1
to
PM2/AN3
Hi-Z
IP
Port M
function select
"1" after a reset
Hi-Z
Analog input select
("0" after a reset)
AN1, AN2, AN3
SCK0, SCK1
MPX
Port N data
Port N
function select
"0" after a reset
SCKEN0, SCKEN1
MPX
Port N direction
PN0/SCK0
PN4/SCK1
"0" after a reset
Hi-Z
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
CMOS
Scmitt input
SCK0, SCK1
SO0, SO1
MPX
Port N data
Port N
function select
"0" after a reset
SOEN0, SOEN1
MPX
PN1/SO0
PN5/SO1
Port N direction
Hi-Z
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
– 16 –
IP
CXR702F080
Pin
Circuit format
After a reset
Port N data
Port N direction
"0" after a reset
PN2/SI0
PN6/SI1
Hi-Z
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
SI0, SI1
Port N data
Port N direction
"0" after a reset
PN3/SCS0/INT8
PN7/SCS1/INT9
Pull-up resistor
Hi-Z
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
CMOS
Schmitt input
SCS0, SCS1
INT8, INT9
SCK2
MPX
Port O data
Port O
function select
"0" after a reset
SCKEN2
MPX
Port O direction
PO0/SCK2
Hi-Z
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
SCK2
– 17 –
IP
CMOS
Schmitt input
CXR702F080
Pin
Circuit format
After a reset
SO2
MPX
Port O data
Port O
functon select
"0" after a reset
SOEN2
MPX
PO1/SO2
Port O direction
Hi-Z
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
Port O data
Port O direction
"0" after a reset
PO2/SI2
Hi-Z
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
IP
SI2
Port O data
Port O direction
"0" after a reset
PO3/SCS2
Hi-Z
Pull-up resistor
"0" after a reset
Internal data bus
MPX
Input data
latch
RD
SCS2
– 18 –
IP
CMOS
Schmitt input
CXR702F080
Pin
Circuit format
After a reset
CS0, CS1
CS0
CS1
High
S bus pin active
RD
RD
High
S bus pin active
LWR, UWR
LWR/LB
UWR/UB
MPX
LB, UB
High
16-bit SRAM
access method select
S bus pin active
MRD
MRD
High
MWE
MWE/WE
MPX
WE
High
16-bit SRAM
access method select
MCS0
MCS0
(M bus unused: CS6)
High
DACK0
DACK1
DACK0, DACK1
High
DREQ0
DREQ1
IP
DREQ0, DREQ1
– 19 –
Hi-Z
CXR702F080
Pin
Circuit format
MSDIR
MSBS
MSSCLK
After a reset
MSDIR, MSBS, MSSCLK
Low
MSDIO (output data)
MSDIO output enable
MSDIO
Hi-Z
IP
MSDIO (input data)
IP
MSINS
MSINS
CMOS
Schmitt input
Hi-Z
System clock
MPX
XTAL
XOUT/CKO
Oscillation
output
Clock output enable
Output clock select
EXTAL
• Diagram shows circuit
configuration during oscillation.
IP
EXTAL
XTAL
• Feedback resistor is removed
during stop mode, and XTAL is
driven at “H” level.
Oscillation
XTAL
TEX
• Diagram shows circuit
configuration during oscillation.
IP
TEX
TX
• Feedback resistor is removed
during stop mode, and TEX is
driven at “L” level; TX at “H” level.
TX
– 20 –
Oscillation
CXR702F080
Pin
Circuit format
After a reset
CMOS
Schmitt input
RST
IP
Internal reset signal
Pull-up
RSTWD
(from watchdog timer)
PWE
TDI
TMS
TCK
IP
PWE
IP
TDI, TMS, TCK
(to CPU core)
IP
TRST
(to CPU core)
Pull-up
TRST
RTCK
Hi-Z
RTCK
Pull-down
High
TDO
Low
TDO
TDO output enable
TEST0
TEST1
IP
TEST0, TEST1
(to test circuit)
IP
TEST2
(to test circuit)
TEST2
– 21 –
Hi-Z
Pull-down
CXR702F080
Absolute Maximum Ratings
Item
(Vss = 0V reference)
Rating
Unit
V
AVDD
–0.3 to +4.6
AVSS to +4.6∗1
AVSS
–0.3 to +0.3
V
AVREF
V
VIN
AVSS to +4.6
–0.3 to +4.6∗2
Output voltage
VOUT
–0.3 to +4.6∗2
V
High level output current
IOH
–5
mA
Output (value per pin)
High level total output current
ΣIOH
–40
mA
Total for all output pins
Low level output current
IOL
10
mA
Output (value per pin)
Low level total output current
ΣIOL
80
mA
Total for all output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
380
mW
Symbol
VDD
Supply voltage
Input voltage
Remarks
V
V
∗1 AVDD and VDD must be the same voltage.
∗2 VIN and VOUT must not exceed VDD + 0.3V.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation
should be conducted under the recommended operating conditions. Exceeding these conditions may
adversely affect the reliability of the LSI.
Recommended Operating Conditions
Item
Symbol
(Vss = 0V reference)
Min.
Typ.
Max.
Unit
Remarks
Supply voltage
VDD
2.7
3.6
V
Analog voltage
AVDD
2.7
3.6
V
∗1
VIH
0.7VDD
VDD
V
CMOS input∗2
VIHS
0.7VDD
VDD
V
VIHEX
0.9VDD
VDD + 0.3
V
CMOS Schmitt trigger input∗3
EXTAL∗4, TEX∗4
VIL
0
0.2VDD
V
CMOS input∗2
VILS
0
0.2VDD
V
VILEX
–0.3
0.4
V
CMOS Schmitt trigger input∗3
EXTAL∗4, TEX∗4
V
CMOS Schmitt trigger input∗3
High level input voltage
Low level input voltage
Hysteresis width
VIHS – VILS
Operating temperature
Topr
0.5
–20
+75
°C
∗1 AVDD and VDD must be the same voltage.
∗2 Normal input port (PA to PC, PD2, PD3, PE, PF1, PF3 to PF5, PH0, PH2, PI to PM, PN1, PN2, PN5,
PN6, PO1, PO2, DREQ0, DREQ1, MSDIO, TDI, TMS, TRST, TCK, PWE and TEST0 to TEST2).
∗3 Each pin of EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1,
SCK0 to SCK2, SCS0 to SCS2, INT8, INT9, MSINS and RST.
∗4 Specified only during external clock input.
– 22 –
CXR702F080
Electrical Characteristics
DC Characteristics (VDD = 2.7 to 3.6V)
Item
High level
output
voltage
Low level
output
voltage
Symbol
VOH
VOL
IIHE
IILE
IIHT
IILT
IIH
Input
current
IIL
(Topr = –20 to +75°C, Vss = 0V reference)
Pins
Conditions
Min.
Typ.
Max.
Unit
PA to PC, PE to PL, PN, PO,
T1, T3, TxD0, TxD1, MCS0,
MCS1, MA0 to MA18,
MD0 to MD7, MRD, MWE,
CS0 to CS5, A0 to A23,
D0 to D15, RD, LWR, LB,
UWR, UB, WE, RST
IOH = –0.5mA
VDD – 0.4
V
BEEP, TXOUT, SCK0 to SCK2,
SO0 to SO2, DACK0, DACK1,
MSDIR, MSBS, MSSCLK,
MSDIO, RTCK, TDO, XOUT,
CKO
IOH = –4mA
VDD – 0.4
V
PA to PC, PE to PL, PN, PO,
T1, T3, TxD0, TxD1, MCS0,
MCS1, MA0 to MA18,
MD0 to MD7, MRD, MWE,
CS0 to CS5, A0 to A23,
D0 to D15, RD, LWR, LB,
UWR, UB, WE, RST
IOL = 1mA
0.4
V
PD, BEEP, TXOUT,
SCK0 to SCK2, SO0 to SO2,
DACK0, DACK1, MSDIR,
MSBS, MSSCLK, MSDIO,
RTCK, TDO, XOUT, CKO
IOL = 4mA
0.4
V
VIH = 3.6V
0.1
10
µA
VIL = 0.4V
–0.1
–10
µA
VIH = 3.6V
0.1
10
µA
VIL = 0.4V
–0.1
–10
µA
TRST
VIH = 3.6V
20
100
240
µA
PA to PC, PE to PL, PN, PO,
WAIT, INT0 to INT9, EC0,
EC2, CT0ED0, CT0ED1,
CT1ED0, CT1ED1, CT2ED0,
CT2ED1, RxD0, RxD1,
MD0 to MD7, D0 to D15,
SCK0 to SCK2, SI0 to SI2,
SCS0 to SCS2∗1
VIL = Vss
–20
–50
–120
µA
TDI, TMS, TCK
VIL = Vss
–20
–100
–240
µA
EXTAL
TEX
∗1 PA to PC, PE to PL, PN, PO, WAIT, INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1,
CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, SCK0 to SCK2, SI0 to SI2 and SCS0 to
SCS2 pins specify the input current when the pull-up resistor is selected, and specify leakage current
when non-resistor is selected.
– 23 –
CXR702F080
Item
Symbol
Pins
Conditions
Typ.
Max.
Unit
IZH
PD2, PD3, PM, AN0 to AN3,
DREQ0, DREQ1, MSDIO,
MSINS, PA to PC, PE to PL,
PN, PO, WAIT, INT0 to INT9,
EC0, EC2, CT0ED0, CT0ED1,
CT1ED0, CT1ED1, CT2ED0,
CT2ED1, RxD0, RxD1,
MD0 to MD7, D0 to D15,
SCK0 to SCK2, SI0 to SI2,
SCS0 to SCS2
VI = 3.6V
10
µA
IZL
PD2, PD3, PM, AN0 to AN3,
DREQ0, DREQ1, MSDIO,
MSINS, PA to PC, PE to PL,
PN, PO, WAIT, INT0 to INT9,
EC0, EC2, CT0ED0, CT0ED1,
CT1ED0, CT1ED1, CT2ED0,
CT2ED1, RxD0, RxD1,
MD0 to MD7, D0 to D15,
SCK0 to SCK2, SI0 to SI2,
SCS0 to SCS2∗1
VI = 0V
–10
µA
IDD1
Main execution mode
18.432MHz crystal
oscillation (C1 = C2 = 10pF)
60
mA
IDDI1
Main idle mode
18.432MHz crystal
oscillation (C1 = C2 = 10pF)
32
mA
Sub sleep mode
32.768kHz crystal
oscillation (C1 = C2 = 10pF)
500
µA
80
µA
500
µA
50
µA
11
pF
9
pF
I/O leakage
current
Supply
current∗2
VDD
IDDS1
Ta = –20 to +25°C
Stop mode
32.768kHz oscillation stop
IDDS2
Ta = –20 to +25°C
Input
capacity
Min.
CIN
PA to PC, PD2, PD3, PE to PO,
WAIT, INT0 to INT9, EC0,
EC2, CT0ED0, CT0ED1,
CT1ED0, CT1ED1, CT2ED0,
CT2ED1, RxD0, RxD1,
MD0 to MD7, D0 to D15,
AN0 to AN3, SCK0 to SCK2,
SI0 to SI2, SCS0 to SCS2,
MSDIO, EXTAL, TEX, RST,
TEST0
DREQ0, DREQ1, MSINS,
TDI, TMS, TRST, TCK,
TEST1, TEST2, PWE
Clock 1MHz
0V other than the
measured pins
∗1 PA to PC, PE to PL, PN, PO, WAIT, INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1,
CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, SCK0 to SCK2, SI0 to SI2 and SCS0 to
SCS2 pins specify the input current when the pull-up resistor is selected, and specify leakage current
when non-resistor is selected.
∗2 When all output pins are left open and XOUT/CKO = “L” (POSL register SLCKO bit = “00” or “01”).
– 24 –
CXR702F080
AC Characteristics
(Topr = –20 to +75°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
(1) Clock timing
Item
Symbol
Pins
Conditions
Min.
Main oscillation input clock
frequency
fEX
XTAL
EXTAL
Fig. 1, Fig. 2
Main oscillation input clock
pulse width
tXL,
tXH
tCR,
tCF
XTAL
EXTAL
Fig. 1, Fig. 2
External clock drive
XTAL
EXTAL
Fig. 1, Fig. 2
External clock drive
Sub oscillation input clock
frequency
fTEX
TEX
TX
Fig. 2
32kHz clock applied condition
Event count input clock
pulse width
tEH,
tEL
tER,
tEF
EC0
EC2
Fig. 3
EC0
EC2
Fig. 3
Main oscillation input clock
rise time, fall time
Event count input clock
rise time, fall time
Typ.
1
32.768
µs
1
0.4V
tXH
tCF
tXL
tCR
Fig. 1. Clock timing
External clock
32kHz clock applied condition
Crystal oscillation
XTAL
TEX
TX
74HC04
C1
C2
C1
C2
Fig. 2. System clock applied condition
0.7VDD
EC0
EC2
0.2VDD
tEH
tEF
Fig. 3. Event count input timing
– 25 –
tEL
tER
ns
kHz
2/fPS4
0.9VDD
EXTAL
MHz
100/fEX
EXTAL
XTAL
XTAL
20
ns
1/fEX
EXTAL
Unit
22.5
Note) fPS4 is fSRC/16 (MHz) for output fSRC of main oscillation circuit.
Crystal oscillation
Ceramic oscillation
Max.
ms
CXR702F080
(2) Serial transfer (CH0, CH1, CH2)
Item
SCS ↓ → SCK
delay time
Symbol
Pins
tDCSK
SCK0
SCK1
SCK2
SCK0
(Topr = –20 to +75°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Conditions
Max. Unit
Min.
External start transfer mode
Input mode (SCKOE = “1”)
ns
100
Output mode
100
ns
100
ns
External start transfer mode
SCS ↑ → SCK
float delay time
tDCSKF SCK1 (SCK = output mode,
SCS ↓ → SO delay time
tDCSO
SCS ↑ → SO
float delay time
tDCSOF SO1
SCS high level width
tWHCS
SCK2
SCKOE = “1”)
SO0
SO1
SO2
External start transfer mode
(SOEN = “1”)
100
ns
External start transfer mode
(SOEN = “1”)
100
ns
SO0
SO2
SCS0
SCS1
SCS2
External start transfer mode
ns
200
SCK input mode
SCK interval time
tKINT
SCK cycle time
tKCY
SCK high, low
pulse width
tKH
tKL
Input setup time
(for SCK ↑)
tSIK
SI input hold time
(for SCK ↑)
tKSI
SCK ↓ → SO delay time
tKSO
SCK0
SCK0
SCK1
SCK2
SCK0
SCK1
SCK2
SI0
SI1
SI2
SI0
SI1
SI2
SO0
SO1
SO2
Internal start high6000 2000
+
+
speed transfer mode fSYS
fSIO
tKCY
6000 3000
External start high+
+
fSIO
speed transfer mode fSYS
tKCY
ns
2
ns
2
400
ns
1000/fSCK
ns
200
ns
500/fSCK – 50
ns
SCK input mode
50
ns
SCK output mode
75
ns
SCK input mode
100
ns
SCK output mode
50
ns
Input mode
Output mode
Input mode
Output mode
SCK input mode
75
ns
SCK output mode
50
ns
Notes) 1. The load condition for the SCK output mode and SO output delay time is 50pF.
2. fSIO is fSRC/2 (MHz) for output fSRC of main oscillation circuit. As for fSCK and fSYS, see the following.
Serial clock selection
PS3∗1
fSCK (MHz)
Serial clock frequency division ratio
fSCK (MHz)
fSRC/8
No frequency division
No
PS4∗1
fSRC/16
2 frequency division
fSRC/2
PS5
fSRC/32
4 frequency division
fSRC/4
PS6
fSRC/64
16 frequency division
fSRC/16
PS7∗2
fSRC/128
PS8∗2
fSRC/256
∗1 CH1, CH2 only
– 26 –
∗2 CH0 only
CXR702F080
tWHCS
SCS0
SCS1
SCS2
0.7VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.7VDD
SCK0
SCK1
SCK2
0.2VDD
tSIK tKSI
0.7VDD
SI0
SI1
SI2
Input
data
0.2VDD
tDCSO
tKSO
tDCSOF
0.7VDD
SO0
SO1
SO2
0.7VDD
Output data
0.2VDD
0.2VDD
tKINT
SCK0
SCK1
SCK2
n byte
n + 1 byte
Fig. 4. Serial transfer CH0, CH1, CH2 timing
– 27 –
CXR702F080
(3) Serial transfer (memory stick)
Item
Symbol
(Topr = –20 to +75°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Pins
Conditions
Min.
Max.
Unit
MSSCLK
cycle time
tKCY
MSSCLK
1000/fMSCK
ns
MSSCLK
high, low pulse width
tKH
tKL
MSSCLK
500/fMSCK – 5
ns
MSBS
output delay time
tBSD
MSBS
For MSSCLK ↓
10
ns
MSDIO
output delay time
tDIOD
MSDIO
For MSSCLK ↓
10
ns
MSDIO
input setup time
tDIOS
MSDIO
For MSSCLK ↑
18
ns
MSDIO
input hold time
tDIOH
MSDIO
For MSSCLK ↑
5
ns
MSDIR
output delay time
tDIRD
MSDIR
For MSSCLK ↓
Notes) 1. The load condition is 26pF.
2. fMSCK is as follows for output fSRC of main oscillation circuit.
Shift clock frequency division ratio fMSCK (MHz)
No frequency division
fSRC
2 frequency division
fSRC/2
4 frequency division
fSRC/4
8 frequency division
fSRC/8
– 28 –
10
ns
CXR702F080
tKCY
0.7VDD
MSSCLK
0.2VDD
tKL
MSBS
tKH
Bus state output
tBSD
MSDIO (output)
Output data
tDIOD
MSDIO (input)
Input data
tDIOS
MSDIR
tDIOH
Serial data I/O direction output
tDIRD
Fig. 5. Memory stick transfer timing
– 29 –
CXR702F080
(4) A/D converter characteristics
(Topr = –20 to +75°C, VDD = 2.7 to 3.6V, VDD = AVDD, Vss = AVss = 0V reference)
Item
Symbol
Pins
Conditions
Max.
Unit
Resolution
8
Bits
Absolute error
±3
LSB
20/fPS4
µs
Sampling time
tCONV
tSAMP
Reference input voltage
VREF
AVREF
Analog input voltage
VIAN
AN0 to AN3
Conversion time
Min.
Typ.
19/fPS4
µs
5/fPS4
VDD = AVDD = 2.7V AVDD – 0.3
0
AVDD
V
AVREF
V
Note) fPS4 is fSRC/16 (MHz) for output fSRC of main oscillation circuit.
Conversion time indicates the time required from conversion start to ADC interruption request
occurrence when 1 channel is selected. This includes sampling time.
FFh
Digital conversion value
FEh
Absolute error
01h
00h
AVREF
Analog input
Fig. 6. Definition of A/D converter terms
(5) Interruption and reset input
Item
External interruption high,
low level width
Reset input high, low level
width
(Topr = –20 to +75°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Symbol
tIH
tIL
tIH
tIL
Pins
Conditions
INT0 to INT9
Min.
Typ.
100
200
ns
32/fSRC
µs
RST
Note) fSRC is output of main oscillation circuit.
tIH
INT0, INT1,
INT2, INT3,
INT4, INT5,
INT6, INT7,
INT8, INT9,
tIL
0.7VDD
0.2VDD
RST
Fig. 7. Interruption input, RST input timing
– 30 –
Max.
Unit
CXR702F080
Appendix
(ii)∗1
(i)
EXTAL
XTAL
TEX
TX
Rd1
C11
C21
Rd2
C12
C22
Fig. 8. Recommended oscillation circuit
Manufacturer
Model
RIVER EIETEC CO., LTD. FCK-03
fc (MHz)
C11 (pF)
C21 (pF)
Rd1 (Ω)
Circuit example
18.432
12
12
0
(i)
∗1 As for (ii) sub oscillation circuit C12, C22 and Rd2, decide them by seeing matching with oscillator.
– 31 –
CXR702F080
Package Outline
Unit: mm
176PIN LFLGA (PLASTIC)
0.2
S A
X
1.4MAX
PIN 1 INDEX
0.10 S
13.0
S B
0.2 S
13.0
0.1MAX
x4
S
0.2
0.15
0.8
3 – φ0.50
DETAIL X
A
176 – φ0.40 ± 0.05
φ0.08 M S A B
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
0.8
B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0.5
0.55
0.90
0.90
0.55
0.5
0.55
0.55
PACKAGE STRUCTURE
PACKAGE MATERIAL
SONY CODE
EIAJ CODE
JEDEC CODE
LFLGA-176P-01
P-LFLGA176-13X13-0.8
TERMINAL TREATMENT
TERMINAL MATERIAL
PACKAGE MASS
– 32 –
ORGANIC SUBSTRATE
NICKEL & GOLD PLATING
COPPER
0.5g
Sony Corporation