AD ADG5243FBRUZ-RL7 User defined fault protection and detection, 0.8 pc qinj, triple spdt Datasheet

User Defined Fault Protection and
Detection, 0.8 pC QINJ, Triple SPDT
ADG5243F
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
User defined supplies set overvoltage level
Overvoltage protection up to −55 V and +55 V
Power-off protection up to −55 V and +55 V
Overvoltage detection on source pins
Minimum secondary supply level: 4.5 V single-supply
Interrupt flags indicate fault status
Low charge injection (QINJ): 0.8 pC
Low drain/source on capacitance: 10 pF
Latch-up immune under any circumstance
Known state without digital inputs present
VSS to VDD analog signal range
±5 V to ±22 V dual supply operation
8 V to 44 V single-supply operation
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
ADG5243F
S1A
D1
S1B
S3B
D3
S3A
S2B
D2
S2A
FF
NOTES
1. SWITCHES SHOWN FOR INPUT LOGIC 1.
13073-001
SF
IN1
IN2
IN3
EN
POSFV
NEGFV
FAULT
DETECTION
AND SWITCH
DRIVER
Figure 1.
APPLICATIONS
Analog input/output modules
Process control/distributed control systems
Data acquisition
Instrumentation
Avionics
Automatic test equipment
Communication systems
Relay replacement
GENERAL DESCRIPTION
The ADG5243F comprises three independently selectable, singlepole/double-throw (SPDT) switches. All channels exhibit breakbefore-make switching action that prevents momentary shorting
when switching channels. An EN input enables or disables the
device. When disabled, all channels are switched off. Each switch
conducts equally well in both directions when on, and each
switch has an input signal range that extends to the supplies.
The primary supply voltages define the on-resistance profile,
whereas the secondary supply voltages define the voltage level at
which the overvoltage protection engages.
When no power supplies are present, the channel remains in the
off condition, and the switch inputs are high impedance. Under
normal operating conditions, if the analog input signal levels on
any Sx pin exceed the positive fault voltage (POSFV) or the
negative fault voltage (NEGFV) by a threshold voltage (VT), the
channel turns off and that Sx pin becomes high impedance. If
the switch is selected to be on, then the drain pin is pulled to the
secondary supply voltage that was exceeded. Input signal levels up
to −55 V or +55 V relative to ground are blocked, in both the
powered and unpowered conditions.
Rev. 0
The low capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-andhold applications, where low glitch switching and fast settling
times are required.
Note that, throughout this data sheet, multifunction pins, such
as IN1/F1, are referred to either by the entire pin name or by a
single function of the pin, for example, IN1, when only that
function is relevant.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
The source pins are protected against voltages greater than
the secondary supply rails, up to −55 V and +55 V.
The source pins are protected against voltages between
−55 V and +55 V in an unpowered state.
Overvoltage detection with the digital output indicates the
operating state of the switches.
Trench isolation guards against latch-up.
Optimized for low charge injection and on-capacitance.
The ADG5243F can be operated from a dual supply of ±5 V
to ±22 V or a single power supply of 8 V to 44 V.
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADG5243F
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits..................................................................................... 20
Applications ....................................................................................... 1
Terminology .................................................................................... 24
Functional Block Diagram .............................................................. 1
Theory of Operation ...................................................................... 26
General Description ......................................................................... 1
Switch Architecture .................................................................... 26
Product Highlights ........................................................................... 1
User Defined Fault Protection .................................................. 27
Revision History ............................................................................... 2
Applications Information .............................................................. 28
Specifications..................................................................................... 3
Power Supply Rails ..................................................................... 28
±15 V Dual Supply ....................................................................... 3
Power Supply Sequencing Protection ...................................... 28
±20 V Dual Supply ....................................................................... 5
Signal Range ................................................................................ 28
12 V Single Supply ........................................................................ 7
Power Supply Recommendations............................................. 28
36 V Single Supply ........................................................................ 9
High Voltage Surge Suppression .............................................. 28
Continuous Current per Channel, Sx or Dx ........................... 11
Intelligent Fault Detection ........................................................ 28
Absolute Maximum Ratings .......................................................... 12
Large Voltage, High Frequency Signals ................................... 29
ESD Caution ................................................................................ 12
Outline Dimensions ....................................................................... 30
Pin Configurations and Function Descriptions ......................... 13
Ordering Guide .......................................................................... 30
Typical Performance Characteristics ........................................... 15
REVISION HISTORY
10/15—Revision 0: Initial Version
Rev. 0 | Page 2 of 30
Data Sheet
ADG5243F
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
+25°C
−40°C to
+85°C
VDD to VSS
250
270
250
270
1
4
1
4
7
8.5
1.5
3.5
0.7
±0.1
±1
±0.1
±1
±0.3
±1.5
335
395
335
395
5
5
5
5
9.5
9.5
4.5
4.5
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
±5
±2
±5
±5
±10
nA typ
nA max
nA typ
nA max
nA typ
nA max
±66
±78
µA typ
±25
±40
µA typ
±2
nA typ
±8
±5
±15
Power Supplies Floating
±100
±50
±100
±50
Digital Input Capacitance, CIN
Output Voltage
High, VOH
Low, VOL
Unit
±2
Power Supplies Grounded
DIGITAL INPUTS/OUTPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
±0.7
±1.1
5.0
±50
nA max
nA typ
±100
±50
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
2.0
0.4
V min
V max
Rev. 0 | Page 3 of 30
Test Conditions/Comments
VDD = +13.5 V, VSS = −13.5 V, see Figure 34
VS = ±10 V, IS = −1 mA
VS = ±9 V, IS = −1 mA
VS = ±10 V, IS = −1 mA
VS = ±9 V, IS = −1 mA
VDD = +15 V, VSS = −15 V, VS = ±10 V, IS = −1 mA
VDD = +15 V, VSS = −15 V, VS = ±9 V, IS = −1 mA
See Figure 26
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD = ∓10 V, see Figure 32
VS = ±10 V, VD = ∓10 V, see Figure 32
VS = VD = ±10 V, see Figure 33
VDD = +16.5 V, VSS = −16.5 V, GND = 0 V, VS =
±55 V, see Figure 31
VDD = 0 V or floating, VSS = 0 V or floating,
GND = 0 V, INx = 0 V or floating, VS = ±55 V,
see Figure 30
VDD = +16.5 V, VSS = −16.5 V, GND = 0 V, VS =
±55 V, see Figure 31
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V,
INx = 0 V, see Figure 30
VDD = floating, VSS = floating, GND = 0 V,
VS = ±55 V, INx = 0 V, see Figure 30
VIN = GND or VDD
ADG5243F
Parameter
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Data Sheet
+25°C
160
195
165
205
70
90
115
−40°C to
+85°C
−40°C to
+125°C
210
215
220
230
110
110
85
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
VDD/VSS
1
90
115
745
945
90
65
900
−0.8
−74
−83
0.005
130
130
965
970
Unit
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
dB typ
% typ
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 45
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 45
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 44
RL = 1 kΩ, CL = 5 pF, see Figure 39
350
10.5
4
4
10
MHz typ
dB typ
pF typ
pF typ
pF typ
1.3
0.15
2
0.75
1.25
0.65
0.2
0.95
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
2.1
1.4
1.0
RL = 1 kΩ, CL = 5 pF, see Figure 40
CL = 12 pF, see Figure 41
CL = 12 pF, see Figure 42
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 43
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 47
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
RL = 10 kΩ, VS = 15 V p-p, f = 20 Hz to 20 kHz,
see Figure 35
RL = 50 Ω, CL = 5 pF, see Figure 37
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 37
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = POSFV = +16.5 V, VSS = NEGFV = −16.5 V,
GND = 0 V, digital inputs = 0 V, 5 V, or VDD
VS = ±55 V, all channels in fault
1.4
0.2
2.5
0.9
1.8
0.55
0.2
1.0
2.8
1.9
1.1
±5
±22
Guaranteed by design; not subject to production test.
Rev. 0 | Page 4 of 30
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
GND = 0 V
GND = 0 V
Data Sheet
ADG5243F
±20 V DUAL SUPPLY
VDD = 20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
+25°C
−40°C to
+85°C
VDD to VSS
270
290
250
270
1
4
1
4
27
355
410
335
395
5
5
5
5
29.5
5
29.5
6.5
0.7
8.5
±0.1
±1
±0.1
±1
±0.3
±1.5
8.5
±5
±2
±5
±5
±10
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
±66
µA typ
±25
µA typ
±2
nA typ
±8
±5
±15
Power Supplies Floating
±100
±50
±100
±50
Digital Input Capacitance, CIN
Output Voltage
High, VOH
Low, VOL
29.5
±2
Power Supplies Grounded
DIGITAL INPUTS/OUTPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
±0.7
±1.1
5.0
±50
nA max
nA typ
±100
±50
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
2.0
0.4
V min
V max
Rev. 0 | Page 5 of 30
Test Conditions/Comments
VDD = +18 V, VSS = −18 V, see Figure 34
VS = ±15 V, IS = −1 mA
VS = ±13.5 V, IS = −1 mA
VS = ±15 V, IS = −1 mA
VS = ±13.5 V, IS = −1 mA
VDD = +20 V, VSS = −20 V, VS = ±15 V, IS =
−1 mA
VDD = +20 V, VSS = −20 V, VS = ±13.5 V, IS =
−1 mA
See Figure 26
VDD = +22 V, VSS = −22 V
VS = ±15 V, VD = ∓15 V, see Figure 32
VS = ±15 V, VD = ∓15 V, see Figure 32
VS = VD = ±15 V, see Figure 33
VDD = +22 V, VSS = −22 V, GND = 0 V,
VS = ±55 V, see Figure 31
VDD = 0 V or floating, VSS = 0 V or floating,
GND = 0 V, INx = 0 V or floating, VS = ±55 V,
see Figure 30
VDD = +22 V, VSS = −22 V, GND = 0 V,
VS = ±55 V, see Figure 31
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V,
INx = 0 V, see Figure 30
VDD = floating, VSS = floating, GND = 0 V,
VS = ±55 V, INx = 0 V, see Figure 30
VIN = GND or VDD
ADG5243F
Parameter
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Data Sheet
+25°C
165
210
170
215
70
85
120
−40°C to
+85°C
−40°C to
+125°C
230
235
240
250
115
115
85
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
VDD/VSS
1
75
105
820
1100
75
65
1000
−1.2
−74
−82
0.005
105
105
1250
1400
Unit
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
dB typ
% typ
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 45
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 45
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 44
RL = 1 kΩ, CL = 5 pF, see Figure 39
350
10.5
4
4
10
MHz typ
dB typ
pF typ
pF typ
pF typ
1.3
0.15
2
0.75
1.25
0.65
0.2
1.0
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
2.1
1.4
1.0
RL = 1 kΩ, CL = 5 pF, see Figure 40
CL = 12 pF, see Figure 41
CL = 12 pF, see Figure 42
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 43
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 47
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
RL = 10 kΩ, VS = 20 V p-p, f = 20 Hz to
20 kHz, see Figure 35
RL = 50 Ω, CL = 5 pF, see Figure 37
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 37
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = POSFV = +22 V, VSS = NEGFV = −22 V,
GND = 0 V, digital inputs = 0 V, 5 V, or VDD
VS = ±55 V, all channels in fault
1.4
0.2
2.5
0.9
1.8
0.55
0.2
1.0
2.8
1.9
1.1
±5
±22
Guaranteed by design; not subject to production test.
Rev. 0 | Page 6 of 30
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
GND = 0 V
GND = 0 V
Data Sheet
ADG5243F
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
+25°C
−40°C to
+85°C
0 V to VDD
630
690
270
290
6
19
1
5
380
440
25
27
0.7
±0.1
±1
±0.1
±1
±0.3
±1.5
710
730
355
410
19
19
5
5
460
460
28
28
±2
±5
±2
±5
±5
±10
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
µA typ
±25
µA typ
±2
nA typ
±8
±5
±15
Power Supplies Floating
±100
±50
±100
±50
Digital Input Capacitance, CIN
Output Voltage
High, VOH
Low, VOL
Unit
±63
Power Supplies Grounded
DIGITAL INPUTS/OUTPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
±0.7
±1.1
5.0
±50
nA max
nA typ
±100
±50
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
2.0
0.4
V min
V max
Rev. 0 | Page 7 of 30
Test Conditions/Comments
VDD = 10.8 V, VSS = 0 V, see Figure 34
VS = 0 V to 10 V, IS = −1 mA
VS = 3.5 V to 8.5 V, IS = −1 mA
VS = 0 V to 10 V, IS = −1 mA
VS = 3.5 V to 8.5 V, IS = −1 mA
VS = 0 V to 10 V, IS = −1 mA
VS = 3.5 V to 8.5 V, IS = −1 mA
See Figure 26
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
VS = VD = 1 V/10 V, see Figure 33
VDD = 13.2 V, VSS = 0 V, GND = 0 V, VS = ±55 V,
see Figure 31
VDD = 0 V or floating, VSS = 0 V or floating, GND =
0 V, INx = 0 V or floating, VS = ±55 V, see Figure 30
VDD = 13.2 V, VSS = 0 V, GND = 0 V, VS = ±55 V,
see Figure 31
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V,
INx = 0 V, see Figure 30
VDD = floating, VSS = floating, GND = 0 V,VS =
±55 V, INx = 0 V, see Figure 30
VIN = GND or VDD
ADG5243F
Parameter
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Data Sheet
+25°C
140
170
145
170
95
115
80
−40°C to
+85°C
−40°C to
+125°C
185
195
185
200
125
125
60
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
VDD/VSS
1
110
145
500
655
95
65
900
0.8
−74
−82
0.044
145
145
720
765
Unit
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
dB typ
% typ
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 45
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 45
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 44
RL = 1 kΩ, CL = 5 pF, see Figure 39
320
10.5
4
5
10
MHz typ
dB typ
pF typ
pF typ
pF typ
1.3
0.15
2
0.75
1.4
0.55
0.2
0.95
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
2.1
1.5
1.0
RL = 1 kΩ, CL = 5 pF, see Figure 40
CL = 12 pF, see Figure 41
CL = 12 pF, see Figure 42
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 43
VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 47
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
RL = 10 kΩ, VS = 6 V p-p, f = 20 Hz to 20 kHz,
see Figure 35
RL = 50 Ω, CL = 5 pF, see Figure 37
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 37
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = POSFV = 13.2 V, VSS = NEGFV = 0 V, GND =
0 V, digital inputs = 0 V, 5 V, or VDD
VS = ±55 V, all channels in fault
1.4
0.2
2.5
0.9
1.8
0.55
0.2
1.0
2.8
1.9
1.1
8
44
Guaranteed by design; not subject to production test.
Rev. 0 | Page 8 of 30
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
Digital inputs = 5 V
VS = ±55 V, VD = 0 V
GND = 0 V
GND = 0 V
Data Sheet
ADG5243F
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
+25°C
−40°C to
+85°C
0 V to VDD
310
335
250
270
3
7
3
6.5
62
70
1.5
3.5
0.7
±0.1
±1
±0.1
±1
±0.3
±1.5
415
480
335
395
16
18
11
12
85
100
4
4
±2
±5
±2
±5
±5
±10
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
µA typ
±25
µA typ
±2
nA typ
±8
±5
±15
Power Supplies Floating
±100
±50
±100
±50
Digital Input Capacitance, CIN
Output Voltage
High, VOH
Low, VOL
Unit
±58
Power Supplies Grounded
DIGITAL INPUTS/OUTPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
±0.7
±1.1
5.0
±50
nA max
nA typ
±100
±50
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
2.0
0.4
V min
V max
Rev. 0 | Page 9 of 30
Test Conditions/Comments
VDD = 32.4 V, VSS = 0 V, see Figure 34
VS = 0 V to 30 V, IS = −1 mA
VS = 4.5 V to 28 V, IS = −1 mA
VS = 0 V to 30 V, IS = −1 mA
VS = 4.5 V to 28 V, IS = −1 mA
VS = 0 V to 30 V, IS = −1 mA
VS = 4.5 V to 28 V, IS = −1 mA
See Figure 26
VDD =39.6 V, VSS = 0 V
VS = 1 V/30 V, VD = 30 V/1 V, see Figure 32
VS = 1 V/30 V, VD = 30 V/1 V, see Figure 32
VS = VD = 1 V/30 V, see Figure 33
VDD = 39.6 V, VSS = 0 V, GND = 0 V, VS = +55 V,
−40 V, see Figure 31
VDD = 0 V or floating, VSS = 0 V or floating, GND =
0 V, INx = 0 V or floating, VS = +55 V, −40 V, see
Figure 30
VDD = 39.6 V, VSS = 0 V, GND = 0 V, VS = +55 V,
−40 V, see Figure 31
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = +55 V, −40 V,
INx = 0 V, see Figure 30
VDD = floating, VSS = floating, GND = 0 V, VS =
+55 V, −40 V, INx = 0 V, see Figure 30
VIN = VGND or VDD
ADG5243F
Parameter
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Data Sheet
+25°C
155
190
160
195
95
115
100
−40°C to
+85°C
−40°C to
+125°C
205
210
210
220
125
130
70
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
VDD/VSS
1
60
80
1400
1900
85
65
1600
−1.4
−74
−85
0.007
85
85
2100
2200
Unit
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
dB typ
% typ
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 45
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 45
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 44
RL = 1 kΩ, CL = 5 pF, see Figure 39
355
10.5
4
4
9
MHz typ
dB typ
pF typ
pF typ
pF typ
1.3
0.15
2
0.75
1.4
0.55
0.2
0.95
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
2.1
1.5
1.0
RL = 1 kΩ, CL = 5 pF, see Figure 40
CL = 12 pF, see Figure 41
CL = 12 pF, see Figure 42
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 43
VS = 18 V, RS = 0 Ω, CL = 1 nF, see Figure 47
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
RL = 10 kΩ, VS = 18 V p-p, f = 20 Hz to 20 kHz, see
Figure 35
RL = 50 Ω, CL = 5 pF, see Figure 37
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 37
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = POSFV = 39.6 V, VSS = NEGFV = 0 V, GND =
0 V, digital inputs = 0 V, 5 V, or VDD
VS = +55 V, −40 V, all channels in fault
1.4
0.2
2.5
0.9
1.8
0.55
0.2
1.0
2.8
1.9
1.1
8
44
Guaranteed by design; not subject to production test.
Rev. 0 | Page 10 of 30
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
GND = 0 V
GND = 0 V
Data Sheet
ADG5243F
CONTINUOUS CURRENT PER CHANNEL, Sx 1 OR Dx
Table 5.
Parameter
θJA = 112.6°C/W
1
25°C
17
10
85°C
11
7
125°C
7
5
Unit
mA max
mA max
Sx is the S1A to S3A and S1B to S3B pins.
Rev. 0 | Page 11 of 30
Test Conditions/Comments
VS = VSS to VDD − 4.5 V
VS = VSS to VDD
ADG5243F
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
POSFV to GND
NEGFV to GND
Sx Pins
Sx to VDD or VSS
VS to VD
Dx Pins1
Digital Inputs
Peak Current, Sx or Dx Pins
Continuous Current, Sx or Dx Pins
Digital Outputs
Dx Pins, Overvoltage State, Load
Current
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Thermal Impedance, θJA (4-Layer
Board)
Reflow Soldering Peak
Temperature, Pb-Free
1
2
Rating
48 V
−0.3 V to +48 V
−48 V to +0.3 V
−0.3 V to VDD +0.3 V
VSS − 0.3 V to +0.3 V
−55 V to +55 V
80 V
80 V
NEGFV − 0.7 V to POSFV +
0.7 V or 30 mA, whichever
occurs first
GND − 0.7 V to 48 V or
30 mA, whichever occurs first
44.5 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data2 + 15%
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
1 mA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
112.6°C/W
As per JEDEC J-STD-020
Overvoltages at the Dx pins are clamped by internal diodes. Limit the
current to the maximum ratings given.
See Table 5.
Rev. 0 | Page 12 of 30
Data Sheet
ADG5243F
IN1/F1 1
20
IN3
IN2/F2 2
19
EN/F0
S1A 3
18
GND
D1 4
17
VDD
16
VSS
15
S3B
D2 7
14
D3
S2A 8
13
S3A
NEGFV 9
12
POSFV
SF 10
11
FF
S1B 5
S2B 6
ADG5243F
TOP VIEW
(Not to Scale)
13073-002
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
Mnemonic
IN1/F1
2
IN2/F2
3
4
5
6
7
8
9
S1A
D1
S1B
S2B
D2
S2A
NEGFV
10
SF
11
FF
12
POSFV
13
14
15
16
17
18
19
S3A
D3
S3B
VSS
VDD
GND
EN/F0
20
IN3
Description
Logic Control Input (IN1) (See Table 8.)
Decoder Pin (F1). This pin is used together with the specific fault pin (SF) to indicate which input is in a fault
condition (see Table 9).
Logic Control Input (IN2) (See Table 8).
Decoder Pin (F2). This pin is used together with the specific fault pin (SF) to indicate which input is in a fault
condition (see Table 9).
Overvoltage Protected Source Terminal 1A. This pin can be an input or an output.
Drain Terminal 1. This pin can be an input or an output.
Overvoltage Protected Source Terminal 1B. This pin can be an input or an output.
Overvoltage Protected Source Terminal 2B. This pin can be an input or an output.
Drain Terminal 2. This pin can be an input or an output.
Overvoltage Protected Source Terminal 2A. This pin can be an input or an output.
Negative Fault Voltage. This pin is the negative supply voltage that determines the overvoltage protection level. If
a secondary supply is not used, connect this pin to VSS.
Specific Fault Digital Output. This pin has a high output when the device is in normal operation or a low output
when a fault condition is detected on a specific pin, depending on the state of F0, F1, and F2 as shown in Table 9.
The SF pin has a weak internal pull-up resistor, nominally 3 V output.
Fault Flag Digital Output. This pin has a high output when the device is in normal operation, or a low output when
a fault condition occurs on any of the Sx inputs. The FF pin has a weak internal pull-up resistor that allows multiple
signals to be combined into a single interrupt for larger modules that contain multiple devices.
Positive Fault Voltage. This pin is the positive supply voltage that determines the overvoltage protection level. If a
secondary supply is not used, connect this pin to VDD.
Overvoltage Protected Source Terminal 3A. This pin can be an input or an output.
Drain Terminal 3. This pin can be an input or an output.
Overvoltage Protected Source Terminal 3B. This pin can be an input or an output.
Most Negative Power Supply Potential.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Active Low Digital Input. When this pin is high, the device is disabled and all switches are off. When this pin is low,
the INx logic inputs determine the on switches.
Decoder Pin (F0). This pin is used together with the specific fault pin (SF) to indicate which input is in a fault
condition (see Table 9).
Logic Control Input (See Table 8).
Rev. 0 | Page 13 of 30
ADG5243F
Data Sheet
Table 8. Switch Selection Truth Table
EN
1
0
0
1
INx
X1
0
1
SxA
Off
Off
On
SxB
Off
On
Off
X is don’t care.
Table 9. Fault Diagnostic Output Truth Table
Switch in Fault1
None
S1A
S1B
S2B
S2A
S3B
S3A
1
0, 0, 0
1
0
1
1
1
1
1
State of Specific Flag (SF) with Control Inputs (F2, F1, F0)
0, 1, 0
1, 0, 0
1, 0, 1
1, 1, 0
1, 1, 1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
0
More than one switch can be in fault. See the Applications Information section for more information.
Rev. 0 | Page 14 of 30
State of Fault Flag (FF)
1
0
0
0
0
0
0
Data Sheet
ADG5243F
TYPICAL PERFORMANCE CHARACTERISTICS
1200
1400
TA = 25°C
±22V
±20V
±18V
±16.5V
±15.0V
±13.5V
800
ON RESISTANCE (Ω)
600
400
200
600
400
–10
–5
0
5
10
15
20
25
0
–15
–12
–9
–6
–3
0
3
6
9
12
15
VS, VD (V)
Figure 3. RON as a Function of VS, VD, Dual Supply
13073-108
–15
13073-105
–20
VS, VD (V)
Figure 6. RON as a Function of VS, VD for Different Temperatures,
±15 V Dual Supply
1200
1400
TA = 25°C
13.2V
12.0V
10.8V
VDD = +20V
VSS = –20V
+125°C
+85°C
+25°C
–40°C
1200
ON RESISTANCE (Ω)
1000
800
600
400
200
1000
800
600
400
200
0
2
4
6
8
10
12
14
VS, VD (V)
0
–20
13073-106
0
–15
–10
–5
0
5
10
15
20
VS, VD (V)
13073-109
ON RESISTANCE (Ω)
800
200
0
–25
Figure 7. RON as a Function of VS, VD for Different Temperatures,
±20 V Dual Supply
Figure 4. RON as a Function of VS, VD, 12 V Single Supply
1400
1200
TA = 25°C
39.6V
36.0V
32.4V
VDD = 12V
VSS = 0V
+125°C
+85°C
+25°C
–40°C
1200
ON RESISTANCE (Ω)
1000
800
600
400
200
1000
800
600
400
200
0
0
5
10
15
20
25
30
35
VS, VD (V)
40
13073-107
ON RESISTANCE (Ω)
1000
Figure 5. RON as a Function of VS, VD, 36 V Single Supply
0
0
2
4
6
8
10
12
VS, VD (V)
Figure 8. RON as a Function of VS, VD for Different Temperatures,
12 V Single Supply
Rev. 0 | Page 15 of 30
13073-110
ON RESISTANCE (Ω)
1000
VDD = +15V
VSS = –15V
+125°C
+85°C
+25°C
–40°C
1200
ADG5243F
Data Sheet
2.5
VDD = 36V
VSS = 0V
+125°C
+85°C
+25°C
–40°C
1000
800
600
400
200
4
8
12
16
20
24
28
32
1.0
0.5
0
36
VS, VD (V)
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
–1.0
13073-111
0
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 9. RON as a Function of VS, VD for Different Temperatures,
36 V Single Supply
Figure 12. Leakage Current vs. Temperature, 12 V Single Supply
3
4
LEAKAGE CURRENT (nA)
VDD = 36V
VSS = 0V
3 VBIAS = 1V, 30V
1
0
–1
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
20
40
60
0
–1
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
–2
–3
0
1
80
100
120
TEMPERATURE (°C)
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
–3
0
20
40
60
80
Figure 10. Leakage Current vs. Temperature, ±15 V Dual Supply
0.4
OVERVOLTAGE LEAKAGE CURRENT (nA)
VDD = +20V
VSS = –20V
3 V
BIAS = ±15V
2
1
0
–1
–2
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
–4
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 11. Leakage Current vs. Temperature, ±20 V Dual Supply
VDD = +15V
VSS = –15V
0.2
0
–0.2
–0.4
–0.6
–0.8
VS = –30V
VS = +30V
VS = –55V
VS = +55V
–1.0
–1.2
13073-113
–3
120
Figure 13. Leakage Current vs. Temperature, 36 V Single Supply
4
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
100
TEMPERATURE (°C)
0
20
40
60
80
TEMPERATURE (°C)
100
120
13073-116
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
13073-112
–2
2
13073-115
VDD = +15V
VSS = –15V
VBIAS = ±10V
2
LEAKAGE CURRENT (nA)
1.5
–0.5
0
LEAKAGE CURRENT (nA)
VDD = 12V
VSS = 0V
VBIAS = 1V, 10V
2.0
LEAKAGE CURRENT (nA)
ON RESISTANCE (Ω)
1200
13073-114
1400
Figure 14. Overvoltage Leakage Current vs. Temperature, ±15 V Dual Supply
Rev. 0 | Page 16 of 30
Data Sheet
ADG5243F
0
VDD = +20V
VSS = –20V
OFF ISOLATION (dB)
0
–0.5
–1.0
VS = –30V
VS = +30V
VS = –55V
VS = +55V
0
20
40
60
80
100
120
–80
–100
–140
0.5
0
100k
1M
10M
100M
1G
VDD = +15V
VSS = –15V
TA = 25°C
–20
–0.5
CROSSTALK (dB)
–40
–1.0
–1.5
–2.0
–60
–80
–100
VS = –30V
VS = +30V
VS = –55V
VS = +55V
40
60
80
100
120
TEMPERATURE (°C)
–140
10k
CHARGE INJECTION (pC)
–1.0
–1.5
VS = –30V
VS = +40V
VS = –40V
VS = +55V
2
0
–2
–4
–6
TA = 25°C
–8
60
80
TEMPERATURE (°C)
100
120
13073-119
–10
40
1G
4
–0.5
20
100M
6
0
0
10M
Figure 19. Crosstalk vs. Frequency, ±15 V Dual Supply
VDD = 36V
VSS = 0V
–2.0
1M
FREQUENCY (Hz)
Figure 16. Overvoltage Leakage Current vs. Temperature, 12 V Single Supply
0.5
100k
13073-121
20
Figure 17. Overvoltage Leakage Current vs. Temperature, 36 V Single Supply
Rev. 0 | Page 17 of 30
VDD = 36V, VSS = 0V
VDD = 12V, VSS = 0V
0
5
10
15
20
25
30
35
40
VS (V)
Figure 20. Charge Injection vs. Source Voltage (VS), Single Supply
13073-122
0
–120
13073-118
–2.5
–2.5
10k
Figure 18. Off Isolation vs. Frequency, ±15 V Dual Supply
VDD = 12V
VSS = 0V
0
1k
FREQUENCY (Hz)
Figure 15. Overvoltage Leakage Current vs. Temperature, ±20 V Dual Supply
OVERVOLTAGE LEAKAGE CURRENT (nA)
–60
–120
TEMPERATURE (°C)
–3.0
–40
13073-120
–1.5
–2.0
OVERVOLTAGE LEAKAGE CURRENT (nA)
VDD = +15V
VSS = –15V
TA = 25°C
–20
13073-117
OVERVOLTAGE LEAKAGE CURRENT (nA)
0.5
ADG5243F
Data Sheet
8
–9
6
–10
–12
2
BANDWIDTH (dB)
CHARGE INJECTION (pC)
–11
4
0
–2
–4
–13
–14
–15
–16
–17
–6
–8
VDD = +20V, VSS = –20V
VDD = +15V, VSS = –15V
–15
–10
–5
0
5
10
15
20
VS (V)
VDD = +15V
VSS = –15V
TA = 25°C
–20
10k
13073-123
–10
–20
–19
100k
10M
100M
1G
FREQUENCY (Hz)
Figure 21. Charge Injection vs. Source Voltage (VS), Dual Supply
Figure 24. Bandwidth vs. Frequency
0
220
VDD = POSFV = +15V
VSS = NEGFV = –15V
TA = 25°C
WITH 100nF DECOUPLING CAPACITOR
–20
VDD
VDD
VDD
VDD
210
= +12V,
= +36V,
= +15V,
= +20V,
VSS
VSS
VSS
VSS
= 0V
= 0V
= –15V
= –20V
200
tTRANSITION (ns)
–40
–60
–80
–100
190
180
170
160
–120
150
100k
1M
10M
100M
1G
FREQUENCY (Hz)
140
–40
13073-124
–140
10k
0
20
40
60
80
100
120
100
120
TEMPERATURE (°C)
Figure 22. ACPSRR vs. Frequency, ±15 V Dual Supply
0.06
–20
13073-127
ACPSRR (dB)
1M
13073-126
–18
TA = 25°C
Figure 25. tTRANSITION vs. Temperature
0.9
LOAD = 10kΩ
TA = 25°C
0.8
THRESHOLD VOLTAGE, VT (V)
0.05
0.03
VDD
VDD
VDD
VDD
0.02
= +12V,
= +36V,
= +15V,
= +20V,
VSS
VSS
VSS
VSS
= 0V, VS = +6V p-p
= 0V, VS = +18V p-p
= –15V, VS = +15V p-p
= –20V, VS = +20V p-p
0.6
0.5
0.4
0.3
0.2
0.01
0
0
5
10
15
FREQUENCY (kHz)
20
Figure 23. THD + N vs. Frequency
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 26. Threshold Voltage (VT) vs. Temperature
Rev. 0 | Page 18 of 30
13073-128
0.1
13073-125
THD + N (%)
0.04
0.7
Data Sheet
ADG5243F
T
TA = 25°C
VDD = +10V
VSS = –10V
20
SIGNAL VOLTAGE (V p-p)
VS
POSFV
DRAIN
2
NEGFV
16
12
8
DISTORTIONLESS
OPERATING REGION
CH2 10V
CH4 10V
1µs
T
2.5GS/s A CH1
–10.0ns 100k POINTS
15.2V
0
13073-129
CH1 10V
CH3 10V
Figure 29. Large Signal Voltage Tracking vs. Frequency
T
POSF
DRAIN
NEGFV
CH2 10V
CH4 10V
1µs
T
2.5GS/s A CH1
–10.0ns 100k POINTS
–15.6V
13073-130
VS
CH1 10V
CH3 10V
10
FREQUENCY (MHz)
Figure 27. Drain Output Response to Positive Overvoltage
(RL = 1 kΩ)
2
1
Figure 28. Drain Output Response to Negative Overvoltage
(RL = 1 kΩ)
Rev. 0 | Page 19 of 30
100
13073-131
4
ADG5243F
Data Sheet
TEST CIRCUITS
VDD = VSS = GND = 0V
VDD
IS
Dx
VDD
13073-030
RL
10kΩ
VS
0.1µF
A
NETWORK
ANALYZER
VSS
50Ω
Sx
INx
VS
Figure 30. Switch Unpowered Leakage
Dx
VIN
ID
IS
Dx
A
GND
RL
10kΩ
|VS| > |VDD| OR |VSS|
RL
50Ω
13073-031
Sx
A
OFF ISOLATION = 20 log
Figure 31. Switch Overvoltage Leakage
A
SxA
VD
VS
VDD
Dx
SxB
A
50Ω
INx
VS
Dx
ID (ON)
SxA
NETWORK
ANALYZER
VSS
Sx
Figure 32. Off Leakage
NC
0.1µF
0.1µF
A
SxB
A
VS
VSS
VDD
ID (ON)
Dx
VOUT
Figure 36. Off Isolation
13073-032
IS (OFF)
VOUT
13073-036
Sx
A
VSS
0.1µF
ID
VIN
A
RL
50Ω
GND
VOUT
13073-033
VD
VS
INSERTION LOSS = 20 log
Figure 33. On Leakage
Figure 37. Bandwidth
VDD
V
Sx
VSS
0.1µF
0.1µF
Dx
VDD
VSS
NETWORK
ANALYZER
SxA
13073-034
IDS
VS
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
RON = V/IDS
RL
50Ω
RL
50Ω
VOUT
Dx
SxB
Figure 34. On Resistance
GND
VDD
13073-037
IS (OFF)
VS
VSS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VDD
AUDIO
PRECISION
VSS
Figure 38. Channel-to-Channel Crosstalk
RS
Sx
VS
V p-p
INx
Dx
GND
RL
10kΩ
VOUT
13073-035
VIN
VOUT
VS
Figure 35. THD + N
Rev. 0 | Page 20 of 30
13073-038
0.1µF
0.1µF
Data Sheet
ADG5243F
VDD VSS
POSFV + 0.5V
0.1µF
0.1µF
POSFV
NEGFV
0.1µF
0.1µF
0V
tRESPONSE
NEGFV
VDD VSS
POSFV
SOURCE
VOLTAGE
(VS)
Sx
POSFV
VS
VD
Dx
CL
5pF
ADG5243F
RL
1kΩ
OUTPUT × 0.5
OUTPUT
(VD)
OTHER
SOURCE/DRAIN
PINS
0V
13073-039
GND
Figure 39. Overvoltage Response Time, tRESPONSE
VDD VSS
POSFV + 0.5V
0.1µF
0.1µF
POSFV
NEGFV
0.1µF
0V
VDD VSS
tRECOVERY
Sx
VS
OUTPUT
(VD)
NEGFV
0.1µF
POSFV
SOURCE
VOLTAGE
(VS)
VD
Dx
CL
5pF
ADG5243F
RL
1kΩ
OUTPUT × 0.5
OTHER
SOURCE/DRAIN
PINS
0V
NOTES
1. THE OUTPUT STARTS FROM THE POSFV CLAMP LEVEL WITHOUT A 1kΩ RESISTOR
(INTERNAL 40kΩ PULL-UP RESISTOR TO THE POSFV SUPPLY RAIL DURING A FAULT).
Figure 40. Overvoltage Recovery Time, tRECOVERY
VDD VSS
POSFV + 0.5V
0.1µF
0.1µF
POSFV
NEGFV
0V
VDD VSS
Sx
tDIGRESP
Dx
OTHER
SOURCE/DRAIN
PINS
VS
ADG5243F
OUTPUT
(VxF)
xF
0.1VOUT
CL*
12pF
GND
*INCLUDES TRACK CAPACITANCE
Figure 41. Interrupt Flag Response Time, tDIGRESP
Rev. 0 | Page 21 of 30
13073-041
0V
0.1µF
POSFV
SOURCE
VOLTAGE
(VS)
NEGFV
0.1µF
13073-040
GND
ADG5243F
Data Sheet
VDD VSS
POSFV + 0.5V
0.1µF
0.1µF
POSFV
NEGFV
0.1µF
POSFV
SOURCE
VOLTAGE
(VS)
0V
VDD VSS
NEGFV
0.1µF
Sx
Dx
OTHER
SOURCE/DRAIN
PINS
VS
tDIGREC
0.9VOUT
ADG5243F
OUTPUT
(VxF)
xF
0V
CL*
12pF
13073-042
GND
*INCLUDES TRACK CAPACITANCE
Figure 42. Interrupt Flag Recovery Time, tDIGREC
VDD VSS
0.1µF
0.1µF
POSFV
NEGFV
0.1µF
0.1µF
VDD VSS
POSFV
SOURCE
VOLTAGE
(VS)
0V
NEGFV
POSFV + 0.5V
Sx
Dx
OTHER
SOURCE/DRAIN
PINS
VS
tDIGREC
5V
5V
RPULLUP
1kΩ
ADG5243F
xF
3V
OUTPUT
(VxF)
OUTPUT
C L*
12pF
GND
13073-043
0V
*INCLUDES TRACK CAPACITANCE
Figure 43. Interrupt Flag Recovery Time, tDIGREC, with a 1 kΩ Pull-Up Resistor
VDD
VIN
0V
0.1µF
VDD
VS
VS
VSS
0.1µF
80%
80%
VSS
SxB
Dx
SxA
INx
OUTPUT
VIN
CL
35pF
GND
tD
Figure 44. Break-Before-Make Time Delay, tD
Rev. 0 | Page 22 of 30
VOUT
RL
300Ω
13073-044
3V
Data Sheet
ADG5243F
VDD
VSS
VDD
VSS
INx
SxA
SxB
3V
50%
50%
0V
tOFF (EN)
tON (EN)
ADG5243F
0.9VOUT
OUTPUT
VS
0.1VOUT
EN
VIN
50Ω
OUTPUT
Dx
1kΩ
GND
35pF
13073-045
ENABLE
DRIVE (VIN)
Figure 45. Enable Delay, tON (EN), tOFF (EN)
VIN
50%
50%
tR < 20ns
tF < 20ns
0V
tTRANSITION
tTRANSITION
VSxB
VIN
VSS
VDD
VSS
INx
SxA
SxB
50Ω
VS
ADG5243F
90%
EN
OUTPUT
VSxA
VDD
OUTPUT
Dx
1kΩ
GND
90%
35pF
13073-046
3V
Figure 46.Digital Control Input to Output Switching Time, tTRANSITION
3V
VIN
VDD
VSS
VDD
SxA
VSS
INx
RS
VOUT
QINJ = CL × ∆VOUT
∆VOUT
VS
VIN
Figure 47. Charge Injection, QINJ
Rev. 0 | Page 23 of 30
ADG5243F
SxB
EN
GND
Dx
CL
1nF
VOUT
13073-047
0V
ADG5243F
Data Sheet
TERMINOLOGY
IDD
IDD represents the positive supply current.
tON (EN)
tON (EN represents the delay between applying the digital
control input and the output switching on (see Figure 45).
ISS
ISS represents the negative supply current.
tOFF (EN)
tOFF (EN) represents the delay between applying the digital
control input and the output switching off (see Figure 45).
IPOSFV
IPOSFV represents the positive secondary supply current.
tTRANSITION
tTRANSITION represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one switch state to another.
INEGFV
INEGFV represents the negative secondary supply current.
VD
VD represents the analog voltage on the Dx pins.
VS
VS represents the analog voltage on the Sx pins.
RON
RON represents the ohmic resistance between the Dx pins and
the Sx pins.
∆RON
∆RON represents the difference between the RON of any two
channels.
RFLAT(ON)
RFLAT(ON) is the flatness that is defined as the difference between
the maximum and minimum value of on resistance measured
over the specified analog signal range.
IS (Off)
IS (off) is the source leakage current with the switch off.
ID (Off)
ID (off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (on) and IS (on) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
tDIGRESP
tDIGRESP is the time required for the FF pin to go low (0.3 V),
measured with respect to the voltage on the source pin
exceeding the supply voltage by 0.5 V.
tDIGREC
tDIGREC is the time required for the FF pin to return high,
measured with respect to the voltage on the Sx pin falling below
the supply voltage plus 0.5 V.
tRESPONSE
tRESPONSE represents the delay between the source voltage
exceeding the supply voltage by 0.5 V and the drain voltage
falling to 90% of the supply voltage.
tRESPONSE(EN)
tRESPONSE (EN) represents the delay between the enable pin being
asserted and the drain reaching 90% of POSFV or NEGFV for a
switch that is in fault.
tRECOVERY
tRECOVERY represents the delay between an overvoltage on a Sx pin
falling below the supply voltage plus 0.5 V and the drain voltage
rising from 0 V to 10% of the supply voltage.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (on) and CS (on) represent the on switch capacitances, which
are measured with reference to ground.
CIN
CIN is the digital input capacitance.
tD
tD represents the off time measured between the 80% points of
both switches when switching from one state to another.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Channel to Channel Crosstalk
Channel to channel crosstalk is a measure of unwanted signal
that is coupled through from one channel to another as a result
of parasitic capacitance.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
−3 dB Bandwidth
−3 dB bandwidth is the frequency at which the output is
attenuated by 3 dB.
Rev. 0 | Page 24 of 30
Data Sheet
ADG5243F
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. ACPSRR is a measure of the
ability of the device to avoid coupling noise and spurious signals
that appear on the supply voltage pin to the output of the
switch. The dc voltage on the device is modulated by a sine
wave of 0.62 V p-p.
VT
VT is the voltage threshold at which the overvoltage protection
circuitry engages (see Figure 26).
Total Harmonic Distortion Plus Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
On Response
On response is the frequency response of the on switch.
Rev. 0 | Page 25 of 30
ADG5243F
Data Sheet
THEORY OF OPERATION
SWITCH ARCHITECTURE
Each channel of the ADG5243F consists of a parallel pair of
N-channel diffused metal-oxide semiconductor (NDMOS) and
P-channel DMOS (PDMOS) transistors. This construction
provides excellent performance across the signal range. The
ADG5243F channels operate as standard switches when input
signals with a voltage between POSFV and NEGFV are applied.
For example, the on resistance is 250 Ω typically and opening or
closing the switch is controlled using the appropriate control pins.
Additional internal circuitry enables the switch to detect
overvoltage inputs by comparing the voltage on a source pin
with POSFV and NEGFV. A signal is considered overvoltage if
it exceeds these secondary supply voltages by the voltage threshold,
VT. The threshold voltage is typically 0.7 V, but can range from
0.8 V at −40°C down to 0.6 V at +125°C. See Figure 26 to see the
change in VT with operating temperature.
The maximum voltage that can be applied to any source input is
+55 V or −55 V. When the device is powered using a single supply
of 25 V or greater, the maximum negative signal level is reduced. It
reduces from −55 V at VDD = +25 V to −40 V at VDD = +40 V to
remain within the 80 V maximum rating. Construction of the
process allows the channel to withstand 80 V across the switch
when it is opened. These overvoltage limits apply whether the
power supplies are present or not.
POSFV
ESD
PROTECTION
ESD
Sx
Dx
FAULT
DETECTOR
SWITCH
DRIVER
ESD
INx
LOGIC
BLOCK
13073-048
NEGFV
During overvoltage conditions, the leakage current into and out
of the source pins is limited to tens of microamperes. If the source
pin is unselected, only nanoamperes of leakage appear on the
drain pin. However, if the source is selected, the pin is pulled to
the supply rail. The device that pulls the drain pin to the rail has
an impedance of approximately 40 kΩ; thus, the Dx pin current
is limited to approximately 1 mA during a shorted load condition.
This internal impedance also determines the minimum external
load resistance required to ensure that the drain pin is pulled to
the desired voltage level during a fault.
When an overvoltage event occurs, the channels undisturbed by
the overvoltage input continue to operate normally without
additional crosstalk.
ESD Performance
The drain pins have ESD protection diodes to the secondary
supply rails and the voltage at these pins must not exceed the
secondary supply voltages, POSFV and NEGFV. The source
pins have specialized ESD protection that allows the signal voltage
to reach ±55 V regardless of supply voltage level. Exceeding
±55 V on any source input may damage the ESD protection
circuitry on the device. See Figure 48 for an overview of the
switch channel.
Trench Isolation
In the ADG5243F, an insulating oxide layer (trench) is placed
between the NDMOS and the PDMOS transistors of each switch.
Parasitic junctions, which occur between the transistors in
junction-isolated switches, are eliminated, and the result is a
switch that is latch-up immune under all circumstances. The
device passes a JESD78D latch-up test of ±500 mA for 1 sec,
which is the harshest test in the specification.
NDMOS
PDMOS
P-WELL
N-WELL
Figure 48. Switch Channel and Control Function
Rev. 0 | Page 26 of 30
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 49. Trench Isolation
13073-049
When an overvoltage condition is detected on a source pin (Sx),
the switch automatically opens regardless of the digital logic
state and the source pin becomes high impedance. If a source
pin is selected that is in fault, the drain pin is pulled to the
supply that was exceeded. For example, if the source voltage
exceeds POSFV, the drain output pulls to POSFV. If the source
voltage exceeds NEGFV, the drain output pulls to NEGFV. In
Figure 27, the voltage on the drain pin can be seen to follow the
voltage on the source pin until the switch turns off completely.
The drain pin then pulls to GND due to the 1 kΩ load resistor;
otherwise, it pulls to the POSFV supply. The maximum voltage
on the drain is limited by the internal ESD diodes and the rate
at which the output voltage discharges is dependent on the load
at the pin.
Data Sheet
ADG5243F
POSFV and NEGFV are required secondary power supplies that
set the level at which the overvoltage protection is engaged. POSFV
can be supplied from 4.5 V to VDD, and NEGFV can be supplied
from VSS to 0 V. If a secondary supply is not available, connect
these pins to VDD (POSFV) and VSS (NEGFV). The overvoltage
protection then engages at the primary supply voltages. When
the voltages at the source inputs exceed POSFV or NEGFV by
VT, the switch turns off or, if the device is unpowered, the switch
remains off. The switch input remains high impedance regardless
of the digital input state and if it is selected, the drain pulls to
either POSFV or NEGFV. Signal levels up to +55 V and −55 V
are blocked in both the powered and unpowered condition as
long as the 80 V limitation between the source and supply pins
is met.
Power-On Protection
The following conditions must be satisfied for the switch to be
in the on condition:
•
•
•
•
The primary supply must be VDD to VSS ≥ 8 V.
For POSFV, the secondary supply must be between 4.5 V
and VDD, and for NEGFV, the secondary supply must be
between VSS and 0 V.
The input signal must be between NEGFV − VT and
POSFV + VT.
The digital logic control input has selected the switch.
When the switch is turned on, signal levels up to the secondary
supply rails are passed.
The switch responds to an analog input that exceeds POSFV or
NEGFV by a threshold voltage, VT, by turning off. The absolute
input voltage limits are −55 V and +55 V, while maintaining an
80 V limit between the source pin and the supply rails. The switch
remains off until the voltage at the source pin returns to
between POSFV and NEGFV.
The fault response time (tRESPONSE) when powered by ±15 V dual
supply is typically 90 ns and the fault recovery time (tRECOVERY) is
745 ns. These vary with supply voltages and output load conditions.
The maximum stress across the switch channel is 80 V, therefore,
the user must pay close attention to this limit under a fault
condition.
For example, consider the case where the device is set up in a
multiplexer configuration as shown in Figure 50.
•
•
•
•
VDD/VSS and POSFV/NEGFV = ±22 V, S1A = S2B= +22 V,
S1B = +55 V, and S2A = −55 V.
S1A and S2A are selected.
The voltage between S1B and D1 = +55 V − (22 V) = +33 V.
The voltage between S2B and D2 = +22 V − (−55 V) = +77 V.
These calculations are all within device specifications: a 55 V
maximum fault on the source inputs and a maximum of 80 V
across the off switch channel.
+22V
S1A
POSFV
+22V
VDD
0V
GND
–22V
VSS
ADG5243F
NEGFV
USER DEFINED FAULT PROTECTION
D1
+55V
+22V
S1B
S3B
D3
S2B
S3A
D2
+55V
S2A
+5V
0V
IN1 IN2 IN3 EN
13073-050
FAULT
DETECTION
AND SWITCH
DRIVER
Figure 50. ADG5243F in an Overvoltage Condition
Power-Off Protection
When no power supplies are present, the switch remains in the
off condition, and the switch inputs are high impedance. This
state ensures that no current flows and prevents damage to the
switch or downstream circuitry. The switch output is a virtual
open circuit.
The switch remains off regardless of whether the VDD and VSS
supplies are 0 V or floating. A GND reference must always be
present to ensure proper operation. Signal levels of up to ±55 V
are blocked in the unpowered condition.
Digital Input Protection
The ADG5243F can tolerate digital input signals being present
on the device without power. When the device is unpowered,
the switch is guaranteed to be in the off state, regardless of the
state of the digital logic signals.
The digital inputs are protected against positive faults of up to
44 V. The digital inputs do not offer protection against negative
overvoltages. ESD protection diodes connected to GND are
present on the digital inputs.
Overvoltage Interrupt Flag
The voltages on the source inputs of the ADG5243F are
continuously monitored, and the state of the switches is
indicated by an active low digital output pin, FF.
The voltage on the FF pin indicates if any of the source input pins
are experiencing a fault condition. The output of the FF pin is a
nominal 3 V when all source pins are within normal operating
range. If any source pin voltage exceeds the secondary supply
voltage by VT, the FF output reduces to below 0.4 V.
Use the specific fault digital output pin, SF, to decode which
inputs are experiencing a fault condition. The SF pin reduces to
below 0.4 V when a fault condition is detected on a specific pin,
depending on the state of F0, F1, and F2 (see Table 9).
Rev. 0 | Page 27 of 30
ADG5243F
Data Sheet
The overvoltage protected family of switches and multiplexers
provides robust solutions for instrumentation, industrial,
automotive, aerospace, and other harsh environments where
overvoltage signals can be present and the system must remain
operational both during and after the overvoltage has occurred.
POWER SUPPLY RAILS
+16V
12V
INPUT
ADP7118
+15V
ADP7182
–15V
LDO
ADP5070
–16 V
LDO
13073-051
APPLICATIONS INFORMATION
Figure 51. Bipolar Power Solution
Table 10. Recommended Power Management Devices
To guarantee correct operation of the device, 0.1 μF decoupling
capacitors are required on the primary and secondary supplies.
If they are driven from the same supply, one set of 0.1 μF
decoupling capacitors is sufficient.
The secondary supplies (POSFV and NEGFV) provide the
current required to operate the fault protection and, thus, must
be low impedance supplies. Therefore, they can be derived from
the primary supplies by using a resistor divider and buffer.
The secondary supply rails (POSFV and NEGFV) must not
exceed the primary supply rails (VDD and VSS) because this may
lead to a signal passing through the switch unintentionally.
The ADG5243F can operate with bipolar supplies between ±5 V
and ±22 V. The supplies on VDD and VSS need not be symmetrical,
but the VDD to VSS range must not exceed 44 V. The ADG5243F
can also operate with single supplies between 8 V and 44 V with
VSS connected to GND.
The ADG5243F device is fully specified at ±15 V, ±20 V, +12 V,
and +36 V supply ranges.
POWER SUPPLY SEQUENCING PROTECTION
The switch channel remains open when the device is unpowered
and signals from −55 V to +55 V can be applied without damaging
the device. The switch channel closes only when the supplies are
connected, a suitable digital control signal is placed on the control
pins, and the signal is within normal operating range. Placing the
ADG5243F between external connectors and sensitive components
offers protection in systems where a signal is presented to the
source pins before the supply voltages are available.
SIGNAL RANGE
The primary supplies define the on-resistance profile of the
channel, whereas the secondary supplies define the signal range.
Using voltages on POSFV and NEGFV that are lower than VDD
and VSS, the required signal can benefit from the flat on resistance
in the center of the full signal capabilities of the device.
POWER SUPPLY RECOMMENDATIONS
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
An example of a bipolar power solution is shown in Figure 51.
The ADP7118 and ADP7182 can be used to generate clean positive
and negative rails from the ADP5070 dual switching regulator
output. These rails can be used to power the ADG5243F, an
amplifier, and/or a precision converter in a typical signal chain.
Product
ADP5070
ADP7118
ADP7142
ADP7182
Description
1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
20 V, 200 mA, low noise, CMOS LDO
40 V, 200 mA, low noise, CMOS LDO
−28 V, −200 mA, low noise, linear regulator
HIGH VOLTAGE SURGE SUPPRESSION
The ADG5243F is not intended for use in very high voltage
applications. The maximum operating voltage of the transistor
is 80 V. In applications where the inputs are likely to be subject
to overvoltages exceeding the breakdown voltage, use transient
voltage suppressors (TVSs) or similar.
INTELLIGENT FAULT DETECTION
The ADG5243F digital output pin, FF, can interface with a
microprocessor or control system and can be used as an interrupt
flag. This feature provides real-time diagnostic information on
the state of the device and the system to which it connects.
The control system can use the digital interrupt, FF, to start a
variety of actions, as follows:



Initiating an investigation into the source of an overvoltage
fault.
Shutting down critical systems in response to the overvoltage
condition.
Using data recorders to mark data during these events as
unreliable or out of specification.
For systems that are sensitive during a start-up sequence, the
active low operation of the flag allows the system to ensure that
the ADG5243F is powered on and that all input voltages are
within the normal operating range before initiating operation.
The FF pin has a weak internal pull-up resistor, which allows
the signals to combine into a single interrupt for larger modules
that contain multiple devices.
The recovery time, tDIGREC, can be decreased from a typical 65 μs
to 900 ns by using a 1 kΩ pull-up resistor.
The specific fault digital output, SF decodes which inputs are
experiencing a fault condition. The SF pin reduces to below
0.4 V when a fault condition is detected on a specific pin,
depending on the state of the F0, F1, and F2 pins (see Table 9).
Rev. 0 | Page 28 of 30
Data Sheet
ADG5243F
LARGE VOLTAGE, HIGH FREQUENCY SIGNALS
Figure 29 illustrates the voltage range and frequencies that the
ADG5243F can reliably convey. For signals that extend across
the full signal range from VSS to VDD, keep the frequency below
1 MHz. If the required frequency is greater than 1 MHz, decrease
the signal range appropriately to ensure signal integrity.
Rev. 0 | Page 29 of 30
ADG5243F
Data Sheet
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 52. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG5243FBRUZ
ADG5243FBRUZ-RL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13073-0-10/15(0)
Rev. 0 | Page 30 of 30
Package Option
RU-20
RU-20