AD ADL5592 250 mhz to 2400 mhz rf variable gain amplifier Datasheet

250 MHz to 2400 MHz
RF Variable Gain Amplifier
ADL5592
Output frequency range: 250 MHz to 2400 MHz
Noise figure: 5.7 dB at 1960 MHz
OIP3 at 1960 MHz: 29 dBm at PIN = 0 dBm per tone
2 digital attenuators, each with 31 dB range
1 dB attenuation step size
Single SPI port
Single supply: 4.5 V to 5.5 V
40-lead, 6 mm × 6 mm LFCSP package
APPLICATIONS
GSM/EDGE and cellular communications systems
FUNCTIONAL BLOCK DIAGRAM
RFOUT
RFIN
ATTENUATOR
CONTROL
CIRCUITRY
LOIP
LOOP EN
ADL5592
LOOP OUT
SPI PORT*
*COMPRISES THE DATA, CLK, AND LE PINS.
06662-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
The ADL5592 is a digitally programmable variable gain
amplifier (VGA) designed for use from 250 MHz to 2400 MHz.
Two digitally programmable attenuators are cascaded with a
high linearity fixed-gain amplifier. The device also includes a
mixer, which can be used to mix the transmitted signal into an
adjacent receive band for loopback testing.
The ADL5592 can be used in conjunction with a direct-to-RF
modulator, such as ADL537x and ADL539x, in cellular
communications systems such as GSM/EDGE.
The ADL5592 is available in a 6 mm × 6 mm, 40-lead exposedpaddle LFCSP package. The device operates from the −40°C to
+85°C temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADL5592
TABLE OF CONTENTS
Features .............................................................................................. 1
Fixed-Gain Amplifier................................................................. 11
Applications ....................................................................................... 1
Loopback Mixer.......................................................................... 11
Functional Block Diagram .............................................................. 1
Applications Information .............................................................. 12
General Description ......................................................................... 1
Basic Connections ...................................................................... 12
Revision History ............................................................................... 2
Programming the SPI Port ........................................................ 12
Specifications..................................................................................... 3
GSM/EDGE Transmit Application .......................................... 14
Absolute Maximum Ratings............................................................ 6
Soldering Information ............................................................... 14
ESD Caution .................................................................................. 6
Evaluation Board ............................................................................ 15
Pin Configuration and Function Descriptions ............................. 7
Characterization Setup .............................................................. 15
Typical Performance Characteristics ............................................. 8
Schematic and Layout ................................................................ 16
Theory of Operation ...................................................................... 11
Configuration Options .............................................................. 18
Input Switch ................................................................................ 11
Outline Dimensions ....................................................................... 19
Digital Attenuator....................................................................... 11
Ordering Guide .......................................................................... 19
SPI Interface ................................................................................ 11
REVISION HISTORY
6/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADL5592
SPECIFICATIONS
Measured at VCC = 5.0 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
OPERATING FREQUENCY RANGE
DIGITAL ATTENUATORS—fRF =
460 MHz to 496 MHz
Attenuation Range
Attenuator Step Size
Relative Step Accuracy
Absolute Step Accuracy
Step Size Variation vs. Frequency
Dynamic Range Variation vs.
Temperature
VGA RF Output Power
vs. Frequency
Gain
vs. Temperature
vs. Frequency
OIP3
Noise Figure
Return Loss
Modulation Spectrum
Error Vector Magnitude (EVM)
DIGITAL ATTENUATORS—fRF =
869 MHz to 960 MHz
Attenuation Range
Attenuator Step Size
Relative Step Accuracy
Absolute Step Accuracy
Step Size Variation vs. Frequency
Dynamic Range Variation vs.
Temperature
RFOUT Power
vs. Frequency
Gain
vs. Temperature
vs. Frequency
OIP3
Noise Figure
Return Loss
Modulation Spectrum
Conditions
Min
250
Typ
28
30.5
1
−0.02
0.4
−0.02
0.6
Variation within transmit band
TA = 0°C to 85°C
RFIN = 4 dBm, minimum attenuation
Variation within transmit band
Minimum attenuation, 270 nH choke inductor
Variation within TA = 0°C to 85°C
Variation within transmit band
Two tones with Δ = 1 MHz, 0 dBm per input tone
Minimum attenuation
RFIN at minimum attenuation
RFOUT at minimum attenuation
Relative to carrier in 30 kHz, POUT = 12 dBm, 8 PSK,
270 nH choke inductor
400 kHz carrier offset
600 kHz carrier offset
1.2 MHz carrier offset
POUT = 12 dBm, 8 PSK
RMS
Peak
8
28
Variation within transmit band
TA = 0°C to 85°C
RFIN = 4 dBm, minimum attenuation
Variation within transmit band
Minimum attenuation, 270 nH choke inductor
Variation within TA = 0°C to 85°C
Variation within transmit band
Two tones with Δ = 1 MHz, 0 dBm per input tone
Minimum attenuation
RFIN at minimum attenuation
RFOUT at minimum attenuation
Relative to carrier in 30 kHz, POUT = 12 dBm, 8 PSK
270 nH choke inductor
400 kHz carrier offset
600 kHz carrier offset
1.2 MHz carrier offset
Rev. 0 | Page 3 of 20
8
Max
2400
Unit
MHz
±1.0
±4.0
dB
dB
dB
dB
dB
dB
16.3
0.02
12.3
1
0.02
27.7
4.3
−10
−15
dBm
dB
dB
dB
dB
dBm
dB
dB
dB
−72
−85
−88
dBc
dBc
dBc
0.7
2.1
%
%
30.1
1
−0.03
0.5
−0.03
0.6
dB
dB
dB
dB
dB
dB
±1.0
±4.0
14.8
0.2
10.8
1.3
0.2
28.5
4.8
−9.8
−9.8
dBm
dB
dB
dB
dB
dBm
dB
dB
dB
−72
−84
−88
dBc
dBc
dBc
ADL5592
Parameter
Error Vector Magnitude (EVM)
DIGITAL ATTENUATORS—fRF =
1805 MHz to 1990 MHz
Attenuation Range
Attenuator Step Size
Relative Step Accuracy
Absolute Step Accuracy
Step Size Variation vs. Frequency
Dynamic Range Variation vs.
Temperature
RFOUT Power
vs. Frequency
Gain
vs. Temperature
vs. Frequency
OIP3
Noise Figure
Return Loss
Modulation Spectrum
Error Vector Magnitude (EVM)
LOGIC INPUTS
Clock Speed
Input Logic Low
Input Logic High
RF LOOP MIXER
Input Frequency
Output Frequency
Input Return Loss
Output Return Loss
LOIP Frequency Range
LOIP Power
LOOP OUT Power
Output Power Flatness
vs. Frequency
vs. Temperature
OIP3
Output Noise Density
Loop Enable Control
Conditions
POUT = 12 dBm, 8 PSK
RMS
Peak
Min
28
Variation within transmit band
TA = 0°C to 85°C
RFIN = 4 dBm, minimum attenuation
Variation within transmit band
Minimum attenuation, 33 nH choke inductor
Variation within TA = 0°C to 85°C
Variation within transmit band
Two tones with Δ = 1 MHz, 0 dBm per input tone
Minimum attenuation
RFIN at minimum attenuation
RFOUT at minimum attenuation
Relative to carrier in 30 kHz, POUT = 12 dBm, 8 PSK
33 nH choke inductor
400 kHz carrier offset
600 kHz carrier offset
1.2 MHz carrier offset
POUT = 12 dBm, 8 PSK
RMS
Peak
8
Typ
Max
0.9
2.7
%
%
30.5
1
−0.02
0.24
−0.02
0.7
dB
dB
dB
dB
dB
dB
±1.0
±4.0
12.9
0.2
8.9
1.5
0.2
29
5.7
−16.4
−11.1
dBm
dB
dB
dB
dB
dBm
dB
dB
dB
−71
−86
−88
dBc
dBc
dBc
0.7
1.9
%
%
13
DATA, CLK, LE
0.8
2.5
460
450
RFIN with loop enable active low at 1960 MHz
LOIP at 80 MHz
LOOP OUT at 1880 MHz
1990
1910
−13
−16
−8
10
−6
RFIN = 5 dBm
450 MHz to 486 MHz
824 MHz to 915 MHz
1710 MHz to 1910 MHz
Within a received band
Variation within TA = 0°C to 85°C
Two tones with Δ = 1 MHz, 0 dBm per input tone
450 MHz to 486 MHz
824 MHz to 915 MHz
1710 MHz to 1910 MHz
Carrier offset > 400 kHz
Rev. 0 | Page 4 of 20
Unit
95
0
MHz
V
V
MHz
MHz
dB
dB
dB
MHz
dBm
−13.0
−12.1
−13.1
dBm
dBm
dBm
0.6
1.1
dB
dB
13.8
13
10.1
−132
dBm
dBm
dBm
dBc/Hz
V
ADL5592
Parameter
Input Logic Low
Input Logic High
Switching Time
ISOLATION
LOOP OUT to RFOUT
RFIN to RFOUT
RFOUT to LOOP OUT
RFIN to LOOP OUT
POWER SUPPLIES
Voltage
Supply Current
Conditions
Loopback active
Loopback inactive
Enable/disable
Min
2.4
Typ
0
5
Max
0.8
500
Loopback mode, at loop output frequency, maximum
attenuation set on ATTN 1 and ATTN 2. RFIN = 4 dBm,
RF loop output = −11 dBm
Loopback mode, at RF input frequency, maximum
attenuation set on ATTN 1 and ATTN 2. RFIN = 4 dBm,
RF loop output = −11 dBm
At carrier frequency, transmit mode, minimum
attenuation set on ATTN 1 and ATTN 2, POUT = 15 dBm
Transmit mode, maximum attenuation set on ATTN 1
and ATTN 2, PINATT1 = 4 dBm
VCC pins
4.5
Loopback active at TA = 25°C
TA = −40°C to +85°C
Loopback inactive at TA = 25°C
TA = −40°C to +85°C
Rev. 0 | Page 5 of 20
Unit
V
V
ns
−68
dBm
−50
dBm
−50
dB
−50
dB
5.0
230
255
189
208
5.5
V
mA
mA
mA
mA
ADL5592
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage VCC
RFIN
LOIP
LOOP EN, DATA, CLK, LE
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Rating
5.5 V
15 dBm
10 dBm
5.5 V
1650 mW
47°C/W
150°C
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 20
ADL5592
40
39
38
37
36
35
34
33
32
31
NC
RFIN
GND
GND
NC
GND
NC
NC
GND
NC*
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADL5592
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
GND
NC
NC*
NC
GND
GND
GND
NC
GND
VCC
GND
RFOUT
GND
GND
NC
NC
GND
NC
GND
NC
11
12
13
14
15
16
17
18
19
20
LOIP 1
LOIN 2
VCC 3
LOOP OUT 4
LOOP EN 5
DATA 6
CLK 7
LE 8
DVCC 9
GND 10
NOTES
1. NC = NO CONNECT
2. CONNECT EXPOSED PADDLE TO A LOW IMPEDANCE
GROUND PLANE.
06662-002
*THE PADS FOR PIN 28 AND PIN 31 MUST REMAIN FREE
OF TRACES TO AVOID STRAY CAPACITANCE.
Figure 2. Pin Configuration (Top View)
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
LOIP
2
3, 21
LOIN
VCC
4
5
LOOP OUT
LOOP EN
6
7
8
9
12
39
10, 11, 13, 14, 17,
19, 22, 24 to 26,
30, 32, 35, 37, 38
15, 16, 18, 20, 23,
27 to 29, 31, 33,
34, 36, 40
DATA
CLK
LE
DVCC
RFOUT
RFIN
GND
Description
Loopback Mixer Differential LO Input. Should be ac-coupled to the source of the mixer local
oscillator signal.
Loopback Mixer Differential LO Input. Should be ac-coupled to ground.
Positive Supply. Nominally equal to 5 V. VCC and DVCC must be connected together externally
and be properly bypassed.
Loopback Mixer RF Output. Single-ended 50 Ω output.
Loopback Mixer Enable. Apply logic high for normal transmit mode. Apply logic mode low for
loopback mode.
SPI Data Input. Both attenuators are programmed with a single 10-bit word.
SPI Clock Input. Data is clocked on the rising edge of CLK.
SPI Latch Enable. Data is latched on the falling edge of LE.
Digital Positive Supply. Nominally equal to 5 V.
RF Output. Should be ac-coupled.
RF Input. Should be ac-coupled.
Common. Connect to a low impedance ground plane.
NC
No Connection. The pad for Pin 28 and Pin 31 must remain free of traces to avoid stray capacitances.
EP
Exposed Paddle. Connect to a low impedance ground plane.
Rev. 0 | Page 7 of 20
ADL5592
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5.0 V, unless otherwise noted.
40
10
GAIN (dB)
0
–10
–20
31dB
–30
–40
500
750
1000 1250 1500 1750
FREQUENCY (MHz)
2000
2250
Figure 3. Gain vs. Frequency by Gain Code,
All Input Attenuator (ATTN 1) Code Steps
20
OUTPUT P1dB COMPRESSION (dBm)
GAIN (dB)
–10
–20
31dB
–40
750
1000 1250 1500 1750
FREQUENCY (MHz)
2000
2250
750
1000 1250 1500 1750
FREQUENCY (MHz)
2000
2250
Figure 4. Gain vs. Frequency by Gain Code,
All Output Attenuator (ATTN 2) Code Steps
–40°C
–25°C
0°C
+25°C
+85°C
25
20
15
10
250
06662-004
500
500
30
0dB
0
–50
250
25
Figure 6. Output Third-Order Intercept vs. Frequency Across Temperature,
Maximum Gain, 0 dBm per Input Tones with 1 MHz Spacing
10
–30
30
20
250
06662-003
–50
250
35
–40°C
–25°C
0°C
+25°C
+85°C
06662-006
OUTPUT THIRD-ORDER INTERCEPT (dBm)
0dB
500
750
1000 1250 1500 1750
FREQUENCY (MHz)
2000
06662-007
20
2250
Figure 7. Output P1dB Compression vs. Frequency Across Temperature,
Maximum Gain
0
10
20
8
16
–5
–25
–30
RFIN 0dB ATTENUATION
RFIN 31dB ATTENUATION
RFOUT 0dB ATTENUATION
RFOUT 31dB ATTENUATION
LOOP OUT
–35
–40
–45
–50
250
500
750
1000 1250 1500 1750
FREQUENCY (MHz)
2000
2250
NOISE FIGURE
6
12
4
8
GAIN
2
0
250
Figure 5. Return Loss vs. Frequency, RFIN, RFOUT, and LOOP OUT
4
500
750
1000 1250 1500 1750
FREQUENCY (MHz)
2000
2250
Figure 8. Noise Figure and Gain vs. Frequency,
at Maximum Gain
Rev. 0 | Page 8 of 20
GAIN (dB)
–20
0
06662-008
NOISE FIGURE (dB)
–15
06662-005
RETURN LOSS (dB)
–10
ADL5592
0
–0.1
–0.2
–0.3
0
8
16
24
GAIN CODE
32 0
8
16
24
GAIN CODE
32
Figure 9. Gain Step Error Across Temperature, Frequency = 492 MHz
(Each Attenuator Is Swept Independently from 0 to 31)
0.4
0
–0.1
–0.2
–0.3
8
16
24
GAIN CODE
32 0
8
16
24
GAIN CODE
32
0
–0.1
–0.2
–0.3
8
16
24
GAIN CODE
32 0
8
16
24
GAIN CODE
32
0.75
0.50
0.25
ATTENUATOR 1
0
8
16
24
GAIN CODE
ATTENUATOR 2
32 0
8
16
24
GAIN CODE
32
Figure 13. Absolute Gain Error Across Temperature, Frequency = 925 MHz
(Each Attenuator Is Swept Independently from 0 to 31)
–40°C
–25°C
0°C
+25°C
+85°C
32 0
8
16
24
GAIN CODE
1.50
1.25
1.00
0.75
0.50
0.25
0
–0.25
ATTENUATOR 2
32
–0.50
06662-011
ATTENUATOR 1
0
16
24
GAIN CODE
1.00
1.75
0.1
–0.4
8
–40°C
–25°C
0°C
+25°C
+85°C
1.25
–0.25
ABSOLUTE STEP ACCURACY (dB)
RELATIVE STEP ACCURACY (dB)
0.2
0
ATTENUATOR 2
2.00
–40°C
–25°C
0°C
+25°C
+85°C
0.3
ATTENUATOR 1
0
ATTENUATOR 2
Figure 10. Gain Step Error Across Temperature, Frequency = 925 MHz
(Each Attenuator Is Swept Independently from 0 to 31)
0.4
0
Figure 12. Absolute Gain Error Across Temperature, Frequency = 492 MHz
(Each Attenuator Is Swept Independently from 0 to 31)
06662-010
ATTENUATOR 1
0
0.25
1.50
0.1
–0.4
0.50
–0.50
ABSOLUTE STEP ACCURACY (dB)
RELATIVE STEP ACCURACY (dB)
0.2
0.75
1.75
–40°C
–25°C
0°C
+25°C
+85°C
0.3
1.00
–0.25
ATTENUATOR 2
06662-009
ATTENUATOR 1
–0.4
1.25
06662-012
0.1
1.50
06662-013
0.2
–40°C
–25°C
0°C
+25°C
+85°C
1.75
ABSOLUTE STEP ACCURACY (dB)
0.3
RELATIVE STEP ACCURACY (dB)
2.00
–40°C
–25°C
0°C
+25°C
+85°C
Figure 11. Gain Step Error Across Temperature, Frequency = 1960 MHz
(Each Attenuator Is Swept Independently from 0 to 31)
ATTENUATOR 1
0
8
16
24
GAIN CODE
ATTENUATOR 2
32 0
8
16
24
GAIN CODE
32
06662-014
0.4
Figure 14. Absolute Gain Error Across Temperature, Frequency = 1960 MHz
(Each Attenuator Is Swept Independently from 0 to 31)
Rev. 0 | Page 9 of 20
ADL5592
14
492.4MHz
12
925.2MHz
10
6
4
2
0
4.50
4.75
5.00
SUPPLY VOLTAGE (V)
5.25
5.50
06662-015
GAIN (dB)
1960MHz
8
Figure 15. Gain vs. Supply Voltage at Maximum Gain
Rev. 0 | Page 10 of 20
ADL5592
THEORY OF OPERATION
Figure 16 shows a simplified schematic of the ADL5592.
state (n dB). The various combinations of the five blocks
provide the attenuation states from 0 dB to 31 dB, in 1 dB
increments.
RFOUT
RFIN
SPI INTERFACE
The ADL5592 includes a SPI-compatible, 3-wire serial interface.
The Si CMOS interface internally level-shifts the SPI signals,
which are used to program a 10-bit shift register and to control
the loading of a 10-bit parallel latch. The outputs of the latch are
fed into drivers, which convert the logic-level outputs of the
latches to signals appropriate for driving the attenuators.
ATTENUATOR
CONTROL
CIRCUITRY
LOIP
LOOP EN
LOOP OUT
SPI PORT*
*COMPRISES THE DATA, CLK, AND LE PINS.
06662-016
ADL5592
FIXED-GAIN AMPLIFIER
Figure 16. Simplified Schematic
The high performance single-pole, double throw (SPDT) GaAs
pHEMT switch is connected to the RF input pin of the ADL5592
to switch the input signal between the VGA and the mixer. To
diminish the impact of the switch on the performance of the VGA
and the mixer, this SPDT switch exhibits low insertion loss and
high isolation in the operating frequency range. The switch-state
control signal is provided by a Si CMOS control circuit.
The output of the input attenuator (ATTN 1) is connected to a
fixed-gain amplifier that drives the output attenuator (ATTN 2).
Because the passive attenuators are linear and contribute minimal
noise, the fixed-gain amplifier is the major source of nonlinear
distortion and noise. This results in a constant OIP3 and noise
figure throughout the different attenuation stages. The fixed-gain
amplifier provides 14 dB of gain and broadband, 50 Ω, singleended input and output impedances.
DIGITAL ATTENUATOR
LOOPBACK MIXER
The digital attenuator consists of five attenuation blocks—1 dB,
2 dB, 4 dB, 8 dB, and 16 dB—each separately controlled by a Si
CMOS control circuit. Each attenuation block consists of field
effect transistor (FET) switches and resistors that form either a
pi- or a T- shaped attenuator. By controlling the states of the
FET switches through the Si CMOS control lines, each attenuation
block can be set to be in the pass state (0 dB) or the attenuation
The loopback mixer is a Si CMOS Gilbert-cell mixer designed to
provide 10 MHz to 100 MHz of frequency translation from the
RF input to the mixer output. The mixer has 50 Ω loads at the
output for a broadband, single-ended output. The input is fed
from the SPDT GaAs pHEMT switch. The overall mixer gain is
typically −17 dB. The mixer LO input is designed to operate from
10 MHz to greater than 100 MHz.
INPUT SWITCH
Rev. 0 | Page 11 of 20
ADL5592
APPLICATIONS INFORMATION
RF INPUT
1000pF
0.1µF
NC
GND
NC
NC
NC
GND
GND
GND
NC
0.1µF
RFIN
LO INPUT
VPOS
0.1µF
100pF
1000pF
LOOP OUT
LOIP
GND
LOIN
NC
VCC
NC
LOOP OUT
MIXER ENABLE
NC
LOOP EN
GND
ADL5592
DATA
GND
SPI CLOCK
CLK
GND
SPI LATCH
LE
DVCC
GND
GND
VCC
CHOKE INDUCTOR (COILCRAFT 0603CS)
33nH FOR 1800MHz, 1900MHz BANDS
270nH FOR 450MHz, 850MHz, 900MHz BANDS
VPOS
GND
10µF
NC
GND
NC
NC
NC
100pF
GND
100pF
GND
0.1µF
GND
VPOS
NC
RFOUT
SPI DATA
06662-017
1000pF
RF OUTPUT
Figure 17. Basic Connections
BASIC CONNECTIONS
PROGRAMMING THE SPI PORT
Figure 17 shows the basic connections for the ADL5592. A
single power supply between 4.75 V and 5.25 V is applied to
the VCC pins. All the VCC pins must be connected to the same
potential. Each power supply pin should be decoupled using a
100 pF capacitor in addition to either a 0.1 μF or 10 μF capacitor.
These capacitors should be located as close as possible to the
device. One of the supply pins (Pin 21) also requires biasing of
an open-collector using an RF choke (Coilcraft 0603CS). The
value of the inductor is dictated by the frequency band of
operation: 270 nH for the 450 MHz, 850 MHz, and 900 MHz
bands and 33 nH for the 1800 MHz and 1900 MHz bands. The
RFIN, RFOUT, and LOOP OUT pins have 50 Ω impedances
and must be ac-coupled.
Both attenuators are programmed with a single 10-bit word.
Figure 18 shows the input and output attenuators, ATTN 1 and
ATTN 2, respectively. Table 4 lists the 10-bit words corresponding
to the various gain levels. The five least significant bits (LSBs)
set the input attenuator, ATTN 1. The five most significant bits
(MSBs) set the output attenuator, ATTN 2.
ATTN 1
AMP
ATTN 2
RFOUT
06662-018
RFIN
Figure 18. Block Diagram of Attenuator Chain
Figure 19 shows the timing diagram of the SPI port transmission.
DATA is clocked on the rising edge of CLK. The data is latched
and the attenuation is updated on the falling edge of LE (the latch
enable pin). The timing requirements indicated in Figure 19 are
described in Table 5.
Rev. 0 | Page 12 of 20
ADL5592
1
LE
t0
0
t2
t1
1
t3
CLK
0
1
D0
DATA
D9
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL LATCHES
ON LE FALLING EDGE.
LOAD DATA INTO
SERIAL REGISTER
ON RISING EDGE.
06662-019
0
Figure 19. Timing Diagram of SPI Port Transmission
Table 4. 10-Bit Gain Words for SPI Port
ATTN 2
ATTN 1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
1
1
ATTN 1 (dB)
0
0
0
0
0
0
0
1
2
4
8
16
31
31
Resulting Attenuation
ATTN 2 (dB)
Total Attenuation (dB)
0
0
1
1
2
2
4
4
8
8
16
16
31
31
0
1
0
2
0
4
0
8
0
16
0
31
31
62
Table 5. Timing Requirements for the SPI Port
Mnemonic
t0
t1
t2
t3
fCLK
Description
Latch enable setup time. Time between latch enable active (high) and first rising edge of serial clock.
Serial data setup time. Time between valid serial data and rising clock edge. Note that this time applies
to all bits in the serial data stream
Serial data hold time. Time after rising clock edge during which the serial data line cannot change in
value. Note that this time applies to all bits in the serial data stream
Latch enable hold time. Time after final falling clock edge during which the latch enable must remain
active (high).
Clock period.
Rev. 0 | Page 13 of 20
Min
15
15
Max
Unit
ns
ns
15
ns
15
ns
15
MHz
ADL5592
10
0
SOLDERING INFORMATION
On the underside of the chip scale package, there is an exposed
compressed paddle. This paddle is internally connected to the
chip’s ground. Solder the paddle to the low impedance ground
plane on the printed circuit board to ensure specified electrical
performance and to provide thermal relief. It is also recommended
that the ground planes on all layers under the paddle be stitched
together with vias to reduce thermal impedance.
8
7
PEAK EVM
–40
6
–50
5
–60
4
400kHz OFFSET
3
–70
RMS EVM
600kHz OFFSET
2
1
–90
–100
7.5
EVM (%)
–30
–80
1.2MHz OFFSET
10.0
12.5
OUTPUT (dBm)
15.0
0
17.5
Figure 20. EVM and Spectral Mask vs. Output Power,
488.8 MHz EDGE Signal, 270 nH RF Choke, Minimum Attenuation
10
0
SPECTRAL MASK (dB)
Note that the minimum attenuation setting results in the highest
spectral mask and EVM values (excluding noise floor limitations).
Increasing the input attenuation of ATTN 1 causes less power to
be presented to the amplifier stage. Therefore, the levels of the
spectral mask and EVM decrease as the input attenuation of
ATTN 1 is increased. As the output attenuation of ATTN 2 is
increased, the levels of the spectral mask and EVM remain flat.
–20
06662-020
At an output of 12 dBm at 925.5 MHz, the peak and rms EVM
are 0.56% and 1.51%, respectively. The spectral mask offsets at
400 kHz, 600 kHz, and 1.2 MHz sit at −72.2 dBc, −84.8 dBc,
and −88.01 dBc, respectively.
9
–10
9
–20
8
7
–30
PEAK EVM
–40
6
5
–50
–60
4
400kHz OFFSET
3
–70
–80
600kHz OFFSET
RMS EVM
2
1
–90
–100
7.5
EVM (%)
At low output power levels, both the spectral mask and EVM
remain flat. At higher output power levels, however, the spectral
mask expands and the EVM increases.
–10
1.2MHz OFFSET
10.0
12.5
OUTPUT (dBm)
15.0
0
17.5
06662-021
Figure 20, Figure 21, and Figure 22 show effects of different input
power levels on the spectral mask and EVM. The gain code is held
constant at the minimum attenuation (corresponding to Code 0
for both attenuators).
SPECTRAL MASK (dB)
GSM/EDGE TRANSMIT APPLICATION
Figure 21. EVM and Spectral Mask vs. Output Power,
925.5 MHz EDGE Signal, 270 nH RF Choke, Minimum Attenuation
–20
8
–30
7
–40
6
5
–50
PEAK EVM
–60
4
400kHz OFFSET
3
–70
–80
600kHz OFFSET
RMS EVM
2
1
–90
–100
7.5
1.2MHz OFFSET
10.0
12.5
OUTPUT (dBm)
15.0
0
17.5
Figure 22. EVM and Spectral Mask vs. Output Power,
1960 MHz EDGE Signal, 33 nH RF Choke, Minimum Attenuation
Rev. 0 | Page 14 of 20
06662-022
SPECTRAL MASK (dB)
9
EVM (%)
10
0
–10
ADL5592
EVALUATION BOARD
and mixer characterization.) The gain control data was generated
by a Tektronix DG2020A data generator. The DG2020A generated
all three of the SPI input signals: CLK, DATA, and LE. A separate
SMT 03 was used to generate the mixer local oscillator signal
(LO input signal) when the loopback mixer was enabled. An
Agilent Visual Engineering Environment (VEE) program
controlled the test instruments through the general-purpose
interface bus (GPIB) interface.
CHARACTERIZATION SETUP
The primary setup used to characterize the ADL5592 is shown
in Figure 23. This setup was used to measure the frequency
response, linearity, and output compression of the amplifier. A
Rohde & Schwarz SMT 03 signal generator was used to drive
the amplifier with a 4 dBm input. The output of the ADL5592
was connected to a Rohde & Schwarz FSIQ7 spectrum analyzer
through an RF switch matrix unit. For the linearity measurement,
two SMT 03 signal generators were used to generate the two-tone
RF input signal. (The same SMT 03 is used for both amplifier
R&S SMT 03
SIGNAL GENERATOR
R&S FSIQ7
SPECTRUM ANALYZER
ADL5592
RFIN
RFOUT
LOIP
LOOP OUT
DATA CLK LE
TEKTRONIX DG2020A
DATA GENERATOR
RF
SWITCH
VCC
AGILENT 6624A
DC POWER SUPPLY
Figure 23. Characterization Bench Setup
Rev. 0 | Page 15 of 20
GPIB INTERFACE
INSTRUMENT CONTROLLER
06662-026
R&S SMT 03
SIGNAL GENERATOR
ADL5592
The RFIN, RFOUT, and LOOP OUT pins have 50 Ω impedances
and must be ac-coupled. One of the supply pins (Pin 21) requires
supply biasing using an RF choke (Coilcraft 0603CS). The value
of the inductor is dictated by the frequency band of operation:
270 nH for the 450 MHz, 850 MHz, and 900 MHz bands and
33 nH for the 1800 MHz and 1900 MHz bands.
SCHEMATIC AND LAYOUT
Figure 24 shows the schematic and Figure 25 and Figure 26 show
the layout of the ADL5592 evaluation board. The board is powered
by a single supply in the 4.75 V to 5.25 V range. Each power supply
pin should be decoupled using a 100 pF capacitor in addition to
either a 0.1 μF or 10 μF capacitor. Table 6 details the various
configuration options of the evaluation board.
C2A
0.1µF
IN_ATTA
LOPA
C17A
1000pF
LBENBA
VPOS
SW1A
R12A
10kΩ
R8A
0Ω
0
NC
NC
NC
NC
GND
LOIN
NC
VCC
NC
0
GND
ADL5592
DATA
GND
GND
CLK
TO
HEADER
GND
VCC
C10A
100pF
NC
GND
NC
GND
NC
R1A
OPEN
NC
R2A
OPEN
GND
R3A
OPEN
GND
GND
R11A
0Ω
RFOUT
R10A
0Ω
GND
R9A
0Ω
L2A
33nH OR 270nH
(COILCRAFT 0603CS)
NC
LE
DVCC
SPI_DATA-A
C8A
OPEN
NC
LOOP OUT
LOOP EN
SW2A
GND
LOIP
C1A
1000pF
GND
MX_OUTA
GND
C6A
100pF
R5A
0Ω
GND
C7A
0.1µF
NC
VPOS
C9A
OPEN
RFIN
C3A
0.1µF
C11A
10µF
VPOS
SPI_CLK-A
TP1A
VPOS
C5A R4A
0.1µF 0Ω
TP1A
C14A
1000pF
C4A
100pF
TP2A
VPOS
RF_OUTA
Figure 24. Evaluation Board Schematic
Rev. 0 | Page 16 of 20
06662-023
SPI_SEL-A
06662-024
ADL5592
06662-025
Figure 25. Evaluation Board Layout, Component Side
Figure 26. Evaluation Board Layout, Circuit Side
Rev. 0 | Page 17 of 20
ADL5592
CONFIGURATION OPTIONS
Table 6. Evaluation Board Configuration Options
Component
Designator
TP1A, TP2A
L1A, L2A, C4A to
C11A, R4A, R5A
Component Name
Supply and ground vector pins
Power supply decoupling
C14A, C17A
Input and output interfaces
C1A to C3A
Mixer input and output interfaces
SW1A, SW2A,
R8A, R12A
Loopback enable interface
R1A to R3A, R9A
to R11A
Serial control interface
Description
The nominal power supply decoupling is accomplished by using
a 100 pF (C4A, C6A, and C10A) in addition to either a 0.1 μF (C5A
and C7A) or a 10 μF (C11A) capacitor at each power supply pin. A
series inductor, L2A, is used to bias the open collector at Pin 21. To
tune the ADL5592 for the low bands (450 MHz, 850 MHz, and 900
MHz), the value should be 270 nH. For the high bands (1800 MHz
and 1900 MHz), the inductor should be changed to 33 nH.
C14A and C17A are dc blocks. The SMA labeled IN_ATTA is used to
drive the RF input. The SMA labeled RF_OUTA corresponds to the RF
output.
C1A to C3A are dc blocks. The SMA labeled LOPA drives the
balanced differential mixer input with a single-ended LO source.
The unused differential input is ac-coupled to ground. The SMA
labeled MX_OUTA corresponds to the mixer output. To use this
function, the loopback mode must be enabled.
Normal transmit mode is exercised by applying a logic high voltage
to the LOOP EN pin, setting Switch SW1A to the position opposite
Label O. For loopback mode, a logic low voltage must be applied to
the LOOP EN pin by setting both Switch SW1A and Switch SW2A to
the positions closest to the O labels. To exercise the control function
from an external source, Switch SW1A must be set to the position
closest to the O label and Switch SW2A must be set to the opposite
position. The signal is driven from the LBENBA SMA.
The evaluation board can be controlled using most PCs. Windows®based control software is shipped with the evaluation kit. A 25-pin
D-subadapter and cable are required to connect the PC to the SPI
port test points on the evaluation board. In some cases, the quality
of the PC port signals can be improved by adding capacitance to
R1A to R3A. The addition of 50 Ω values for R1A to R3A allow for SPI
port control from digital generators driven from the SMAs
connectors, SPI_DATA-A, SPI_CLK-A, and SPI_SEL-A.
Rev. 0 | Page 18 of 20
Default
Conditions
Not applicable
L2A = 270 nH or
33 nH (Size 0603)
(Coilcraft 0603CS);
C4A, C6A, C10A =
100 pF (Size 0402);
C5A, C7A = 0.1 μF
(Size 0402); C11A =
10 μF (Size 0402);
R4A, R5A = 0 Ω
(Size 0402); C8A,
C9A = open (Size
0402)
C14A, C17A =
1000 pF (Size 0402)
C1A = 1000 pF (Size
0402); C2A, C3A =
0.1 μF (Size 0402)
SW1A, SW2A =
installed; R8A = 0 Ω
(Size 0402); R12A =
10 kΩ (Size 0402)
R1A, R2A, R3A =
open (Size 0402);
R9A, R10A, R11A =
0 Ω (Size 0402)
ADL5592
OUTLINE DIMENSIONS
6.00
BSC SQ
PIN 1
INDICATOR
40
1
31
30
0.50
BSC
TOP VIEW
0.80
0.75
0.70
SEATING
PLANE
0.50
0.40
0.30
21
20
0.05 MAX
0.02 NOM
0.30
0.25
0.18
0.20 REF
4.25
4.15 SQ
4.00
EXPOSED
PAD
10
11
BOTTOM VIEW
0.20 MIN
THE EXPOSED METAL PADDLE ON THE
BOTTOM OF THE LFCSP PACKAGE
MUST BE SOLDERED TO PCB GROUND
FOR PROPER HEAT DISSIPATION AND
ALSO FOR NOISE AND MECHANICAL
STRENGTH BENEFITS.
061108-A
INDEX
AREA
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-2
Figure 27. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADL5592ACPZ-R7 1
ADL5592-EVALZ1
1
Temperature Range
−40°C to +85°C
Package Description
40-Lead LFCSP_WQ, 7" Tape and Reel
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
Package Option
CP-40-2
Ordering Quantity
3,000
ADL5592
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06662-0-6/08(0)
Rev. 0 | Page 20 of 20